2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 struct dma_async_tx_descriptor *desc_tx;
108 struct dma_async_tx_descriptor *desc_rx[2];
109 dma_cookie_t cookie_tx;
110 dma_cookie_t cookie_rx[2];
111 dma_cookie_t active_rx;
112 struct scatterlist sg_tx;
113 unsigned int sg_len_tx;
114 struct scatterlist sg_rx[2];
116 struct sh_dmae_slave param_tx;
117 struct sh_dmae_slave param_rx;
118 struct work_struct work_tx;
119 struct work_struct work_rx;
120 struct timer_list rx_timer;
121 unsigned int rx_timeout;
124 struct notifier_block freq_transition;
127 /* Function prototypes */
128 static void sci_start_tx(struct uart_port *port);
129 static void sci_stop_tx(struct uart_port *port);
130 static void sci_start_rx(struct uart_port *port);
132 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
134 static struct sci_port sci_ports[SCI_NPORTS];
135 static struct uart_driver sci_uart_driver;
137 static inline struct sci_port *
138 to_sci_port(struct uart_port *uart)
140 return container_of(uart, struct sci_port, port);
143 struct plat_sci_reg {
147 /* Helper for invalidating specific entries of an inherited map. */
148 #define sci_reg_invalid { .offset = 0, .size = 0 }
150 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
151 [SCIx_PROBE_REGTYPE] = {
152 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
156 * Common SCI definitions, dependent on the port's regshift
159 [SCIx_SCI_REGTYPE] = {
160 [SCSMR] = { 0x00, 8 },
161 [SCBRR] = { 0x01, 8 },
162 [SCSCR] = { 0x02, 8 },
163 [SCxTDR] = { 0x03, 8 },
164 [SCxSR] = { 0x04, 8 },
165 [SCxRDR] = { 0x05, 8 },
166 [SCFCR] = sci_reg_invalid,
167 [SCFDR] = sci_reg_invalid,
168 [SCTFDR] = sci_reg_invalid,
169 [SCRFDR] = sci_reg_invalid,
170 [SCSPTR] = sci_reg_invalid,
171 [SCLSR] = sci_reg_invalid,
172 [HSSRR] = sci_reg_invalid,
173 [SCPCR] = sci_reg_invalid,
174 [SCPDR] = sci_reg_invalid,
178 * Common definitions for legacy IrDA ports, dependent on
181 [SCIx_IRDA_REGTYPE] = {
182 [SCSMR] = { 0x00, 8 },
183 [SCBRR] = { 0x01, 8 },
184 [SCSCR] = { 0x02, 8 },
185 [SCxTDR] = { 0x03, 8 },
186 [SCxSR] = { 0x04, 8 },
187 [SCxRDR] = { 0x05, 8 },
188 [SCFCR] = { 0x06, 8 },
189 [SCFDR] = { 0x07, 16 },
190 [SCTFDR] = sci_reg_invalid,
191 [SCRFDR] = sci_reg_invalid,
192 [SCSPTR] = sci_reg_invalid,
193 [SCLSR] = sci_reg_invalid,
194 [HSSRR] = sci_reg_invalid,
195 [SCPCR] = sci_reg_invalid,
196 [SCPDR] = sci_reg_invalid,
200 * Common SCIFA definitions.
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
215 [HSSRR] = sci_reg_invalid,
216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
221 * Common SCIFB definitions.
223 [SCIx_SCIFB_REGTYPE] = {
224 [SCSMR] = { 0x00, 16 },
225 [SCBRR] = { 0x04, 8 },
226 [SCSCR] = { 0x08, 16 },
227 [SCxTDR] = { 0x40, 8 },
228 [SCxSR] = { 0x14, 16 },
229 [SCxRDR] = { 0x60, 8 },
230 [SCFCR] = { 0x18, 16 },
231 [SCFDR] = sci_reg_invalid,
232 [SCTFDR] = { 0x38, 16 },
233 [SCRFDR] = { 0x3c, 16 },
234 [SCSPTR] = sci_reg_invalid,
235 [SCLSR] = sci_reg_invalid,
236 [HSSRR] = sci_reg_invalid,
237 [SCPCR] = { 0x30, 16 },
238 [SCPDR] = { 0x34, 16 },
242 * Common SH-2(A) SCIF definitions for ports with FIFO data
245 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x0c, 8 },
250 [SCxSR] = { 0x10, 16 },
251 [SCxRDR] = { 0x14, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCFDR] = { 0x1c, 16 },
254 [SCTFDR] = sci_reg_invalid,
255 [SCRFDR] = sci_reg_invalid,
256 [SCSPTR] = { 0x20, 16 },
257 [SCLSR] = { 0x24, 16 },
258 [HSSRR] = sci_reg_invalid,
259 [SCPCR] = sci_reg_invalid,
260 [SCPDR] = sci_reg_invalid,
264 * Common SH-3 SCIF definitions.
266 [SCIx_SH3_SCIF_REGTYPE] = {
267 [SCSMR] = { 0x00, 8 },
268 [SCBRR] = { 0x02, 8 },
269 [SCSCR] = { 0x04, 8 },
270 [SCxTDR] = { 0x06, 8 },
271 [SCxSR] = { 0x08, 16 },
272 [SCxRDR] = { 0x0a, 8 },
273 [SCFCR] = { 0x0c, 8 },
274 [SCFDR] = { 0x0e, 16 },
275 [SCTFDR] = sci_reg_invalid,
276 [SCRFDR] = sci_reg_invalid,
277 [SCSPTR] = sci_reg_invalid,
278 [SCLSR] = sci_reg_invalid,
279 [HSSRR] = sci_reg_invalid,
280 [SCPCR] = sci_reg_invalid,
281 [SCPDR] = sci_reg_invalid,
285 * Common SH-4(A) SCIF(B) definitions.
287 [SCIx_SH4_SCIF_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x0c, 8 },
292 [SCxSR] = { 0x10, 16 },
293 [SCxRDR] = { 0x14, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = sci_reg_invalid,
297 [SCRFDR] = sci_reg_invalid,
298 [SCSPTR] = { 0x20, 16 },
299 [SCLSR] = { 0x24, 16 },
300 [HSSRR] = sci_reg_invalid,
301 [SCPCR] = sci_reg_invalid,
302 [SCPDR] = sci_reg_invalid,
306 * Common HSCIF definitions.
308 [SCIx_HSCIF_REGTYPE] = {
309 [SCSMR] = { 0x00, 16 },
310 [SCBRR] = { 0x04, 8 },
311 [SCSCR] = { 0x08, 16 },
312 [SCxTDR] = { 0x0c, 8 },
313 [SCxSR] = { 0x10, 16 },
314 [SCxRDR] = { 0x14, 8 },
315 [SCFCR] = { 0x18, 16 },
316 [SCFDR] = { 0x1c, 16 },
317 [SCTFDR] = sci_reg_invalid,
318 [SCRFDR] = sci_reg_invalid,
319 [SCSPTR] = { 0x20, 16 },
320 [SCLSR] = { 0x24, 16 },
321 [HSSRR] = { 0x40, 16 },
322 [SCPCR] = sci_reg_invalid,
323 [SCPDR] = sci_reg_invalid,
327 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
330 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
331 [SCSMR] = { 0x00, 16 },
332 [SCBRR] = { 0x04, 8 },
333 [SCSCR] = { 0x08, 16 },
334 [SCxTDR] = { 0x0c, 8 },
335 [SCxSR] = { 0x10, 16 },
336 [SCxRDR] = { 0x14, 8 },
337 [SCFCR] = { 0x18, 16 },
338 [SCFDR] = { 0x1c, 16 },
339 [SCTFDR] = sci_reg_invalid,
340 [SCRFDR] = sci_reg_invalid,
341 [SCSPTR] = sci_reg_invalid,
342 [SCLSR] = { 0x24, 16 },
343 [HSSRR] = sci_reg_invalid,
344 [SCPCR] = sci_reg_invalid,
345 [SCPDR] = sci_reg_invalid,
349 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
352 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x0c, 8 },
357 [SCxSR] = { 0x10, 16 },
358 [SCxRDR] = { 0x14, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
362 [SCRFDR] = { 0x20, 16 },
363 [SCSPTR] = { 0x24, 16 },
364 [SCLSR] = { 0x28, 16 },
365 [HSSRR] = sci_reg_invalid,
366 [SCPCR] = sci_reg_invalid,
367 [SCPDR] = sci_reg_invalid,
371 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
374 [SCIx_SH7705_SCIF_REGTYPE] = {
375 [SCSMR] = { 0x00, 16 },
376 [SCBRR] = { 0x04, 8 },
377 [SCSCR] = { 0x08, 16 },
378 [SCxTDR] = { 0x20, 8 },
379 [SCxSR] = { 0x14, 16 },
380 [SCxRDR] = { 0x24, 8 },
381 [SCFCR] = { 0x18, 16 },
382 [SCFDR] = { 0x1c, 16 },
383 [SCTFDR] = sci_reg_invalid,
384 [SCRFDR] = sci_reg_invalid,
385 [SCSPTR] = sci_reg_invalid,
386 [SCLSR] = sci_reg_invalid,
387 [HSSRR] = sci_reg_invalid,
388 [SCPCR] = sci_reg_invalid,
389 [SCPDR] = sci_reg_invalid,
393 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
396 * The "offset" here is rather misleading, in that it refers to an enum
397 * value relative to the port mapping rather than the fixed offset
398 * itself, which needs to be manually retrieved from the platform's
399 * register map for the given port.
401 static unsigned int sci_serial_in(struct uart_port *p, int offset)
403 const struct plat_sci_reg *reg = sci_getreg(p, offset);
406 return ioread8(p->membase + (reg->offset << p->regshift));
407 else if (reg->size == 16)
408 return ioread16(p->membase + (reg->offset << p->regshift));
410 WARN(1, "Invalid register access\n");
415 static void sci_serial_out(struct uart_port *p, int offset, int value)
417 const struct plat_sci_reg *reg = sci_getreg(p, offset);
420 iowrite8(value, p->membase + (reg->offset << p->regshift));
421 else if (reg->size == 16)
422 iowrite16(value, p->membase + (reg->offset << p->regshift));
424 WARN(1, "Invalid register access\n");
427 static int sci_probe_regmap(struct plat_sci_port *cfg)
431 cfg->regtype = SCIx_SCI_REGTYPE;
434 cfg->regtype = SCIx_IRDA_REGTYPE;
437 cfg->regtype = SCIx_SCIFA_REGTYPE;
440 cfg->regtype = SCIx_SCIFB_REGTYPE;
444 * The SH-4 is a bit of a misnomer here, although that's
445 * where this particular port layout originated. This
446 * configuration (or some slight variation thereof)
447 * remains the dominant model for all SCIFs.
449 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
452 cfg->regtype = SCIx_HSCIF_REGTYPE;
455 pr_err("Can't probe register map for given port\n");
462 static void sci_port_enable(struct sci_port *sci_port)
464 if (!sci_port->port.dev)
467 pm_runtime_get_sync(sci_port->port.dev);
469 clk_prepare_enable(sci_port->iclk);
470 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
471 clk_prepare_enable(sci_port->fclk);
474 static void sci_port_disable(struct sci_port *sci_port)
476 if (!sci_port->port.dev)
479 /* Cancel the break timer to ensure that the timer handler will not try
480 * to access the hardware with clocks and power disabled. Reset the
481 * break flag to make the break debouncing state machine ready for the
484 del_timer_sync(&sci_port->break_timer);
485 sci_port->break_flag = 0;
487 clk_disable_unprepare(sci_port->fclk);
488 clk_disable_unprepare(sci_port->iclk);
490 pm_runtime_put_sync(sci_port->port.dev);
493 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
495 if (port->type == PORT_SCI) {
496 /* Just store the mask */
497 serial_port_out(port, SCxSR, mask);
498 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
499 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
500 /* Only clear the status bits we want to clear */
501 serial_port_out(port, SCxSR,
502 serial_port_in(port, SCxSR) & mask);
504 /* Store the mask, clear parity/framing errors */
505 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
509 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
511 #ifdef CONFIG_CONSOLE_POLL
512 static int sci_poll_get_char(struct uart_port *port)
514 unsigned short status;
518 status = serial_port_in(port, SCxSR);
519 if (status & SCxSR_ERRORS(port)) {
520 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
526 if (!(status & SCxSR_RDxF(port)))
529 c = serial_port_in(port, SCxRDR);
532 serial_port_in(port, SCxSR);
533 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
539 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
541 unsigned short status;
544 status = serial_port_in(port, SCxSR);
545 } while (!(status & SCxSR_TDxE(port)));
547 serial_port_out(port, SCxTDR, c);
548 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
550 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
552 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
554 struct sci_port *s = to_sci_port(port);
555 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
558 * Use port-specific handler if provided.
560 if (s->cfg->ops && s->cfg->ops->init_pins) {
561 s->cfg->ops->init_pins(port, cflag);
566 * For the generic path SCSPTR is necessary. Bail out if that's
572 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
573 ((!(cflag & CRTSCTS)))) {
574 unsigned short status;
576 status = serial_port_in(port, SCSPTR);
577 status &= ~SCSPTR_CTSIO;
578 status |= SCSPTR_RTSIO;
579 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
583 static int sci_txfill(struct uart_port *port)
585 const struct plat_sci_reg *reg;
587 reg = sci_getreg(port, SCTFDR);
589 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
591 reg = sci_getreg(port, SCFDR);
593 return serial_port_in(port, SCFDR) >> 8;
595 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
598 static int sci_txroom(struct uart_port *port)
600 return port->fifosize - sci_txfill(port);
603 static int sci_rxfill(struct uart_port *port)
605 const struct plat_sci_reg *reg;
607 reg = sci_getreg(port, SCRFDR);
609 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
611 reg = sci_getreg(port, SCFDR);
613 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
615 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
619 * SCI helper for checking the state of the muxed port/RXD pins.
621 static inline int sci_rxd_in(struct uart_port *port)
623 struct sci_port *s = to_sci_port(port);
625 if (s->cfg->port_reg <= 0)
628 /* Cast for ARM damage */
629 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
632 /* ********************************************************************** *
633 * the interrupt related routines *
634 * ********************************************************************** */
636 static void sci_transmit_chars(struct uart_port *port)
638 struct circ_buf *xmit = &port->state->xmit;
639 unsigned int stopped = uart_tx_stopped(port);
640 unsigned short status;
644 status = serial_port_in(port, SCxSR);
645 if (!(status & SCxSR_TDxE(port))) {
646 ctrl = serial_port_in(port, SCSCR);
647 if (uart_circ_empty(xmit))
651 serial_port_out(port, SCSCR, ctrl);
655 count = sci_txroom(port);
663 } else if (!uart_circ_empty(xmit) && !stopped) {
664 c = xmit->buf[xmit->tail];
665 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
670 serial_port_out(port, SCxTDR, c);
673 } while (--count > 0);
675 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
677 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
678 uart_write_wakeup(port);
679 if (uart_circ_empty(xmit)) {
682 ctrl = serial_port_in(port, SCSCR);
684 if (port->type != PORT_SCI) {
685 serial_port_in(port, SCxSR); /* Dummy read */
686 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
690 serial_port_out(port, SCSCR, ctrl);
694 /* On SH3, SCIF may read end-of-break as a space->mark char */
695 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
697 static void sci_receive_chars(struct uart_port *port)
699 struct sci_port *sci_port = to_sci_port(port);
700 struct tty_port *tport = &port->state->port;
701 int i, count, copied = 0;
702 unsigned short status;
705 status = serial_port_in(port, SCxSR);
706 if (!(status & SCxSR_RDxF(port)))
710 /* Don't copy more bytes than there is room for in the buffer */
711 count = tty_buffer_request_room(tport, sci_rxfill(port));
713 /* If for any reason we can't copy more data, we're done! */
717 if (port->type == PORT_SCI) {
718 char c = serial_port_in(port, SCxRDR);
719 if (uart_handle_sysrq_char(port, c) ||
720 sci_port->break_flag)
723 tty_insert_flip_char(tport, c, TTY_NORMAL);
725 for (i = 0; i < count; i++) {
726 char c = serial_port_in(port, SCxRDR);
728 status = serial_port_in(port, SCxSR);
729 #if defined(CONFIG_CPU_SH3)
730 /* Skip "chars" during break */
731 if (sci_port->break_flag) {
733 (status & SCxSR_FER(port))) {
738 /* Nonzero => end-of-break */
739 dev_dbg(port->dev, "debounce<%02x>\n", c);
740 sci_port->break_flag = 0;
747 #endif /* CONFIG_CPU_SH3 */
748 if (uart_handle_sysrq_char(port, c)) {
753 /* Store data and status */
754 if (status & SCxSR_FER(port)) {
756 port->icount.frame++;
757 dev_notice(port->dev, "frame error\n");
758 } else if (status & SCxSR_PER(port)) {
760 port->icount.parity++;
761 dev_notice(port->dev, "parity error\n");
765 tty_insert_flip_char(tport, c, flag);
769 serial_port_in(port, SCxSR); /* dummy read */
770 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
773 port->icount.rx += count;
777 /* Tell the rest of the system the news. New characters! */
778 tty_flip_buffer_push(tport);
780 serial_port_in(port, SCxSR); /* dummy read */
781 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
785 #define SCI_BREAK_JIFFIES (HZ/20)
788 * The sci generates interrupts during the break,
789 * 1 per millisecond or so during the break period, for 9600 baud.
790 * So dont bother disabling interrupts.
791 * But dont want more than 1 break event.
792 * Use a kernel timer to periodically poll the rx line until
793 * the break is finished.
795 static inline void sci_schedule_break_timer(struct sci_port *port)
797 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
800 /* Ensure that two consecutive samples find the break over. */
801 static void sci_break_timer(unsigned long data)
803 struct sci_port *port = (struct sci_port *)data;
805 if (sci_rxd_in(&port->port) == 0) {
806 port->break_flag = 1;
807 sci_schedule_break_timer(port);
808 } else if (port->break_flag == 1) {
810 port->break_flag = 2;
811 sci_schedule_break_timer(port);
813 port->break_flag = 0;
816 static int sci_handle_errors(struct uart_port *port)
819 unsigned short status = serial_port_in(port, SCxSR);
820 struct tty_port *tport = &port->state->port;
821 struct sci_port *s = to_sci_port(port);
823 /* Handle overruns */
824 if (status & s->overrun_mask) {
825 port->icount.overrun++;
828 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
831 dev_notice(port->dev, "overrun error\n");
834 if (status & SCxSR_FER(port)) {
835 if (sci_rxd_in(port) == 0) {
836 /* Notify of BREAK */
837 struct sci_port *sci_port = to_sci_port(port);
839 if (!sci_port->break_flag) {
842 sci_port->break_flag = 1;
843 sci_schedule_break_timer(sci_port);
845 /* Do sysrq handling. */
846 if (uart_handle_break(port))
849 dev_dbg(port->dev, "BREAK detected\n");
851 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
857 port->icount.frame++;
859 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
862 dev_notice(port->dev, "frame error\n");
866 if (status & SCxSR_PER(port)) {
868 port->icount.parity++;
870 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
873 dev_notice(port->dev, "parity error\n");
877 tty_flip_buffer_push(tport);
882 static int sci_handle_fifo_overrun(struct uart_port *port)
884 struct tty_port *tport = &port->state->port;
885 struct sci_port *s = to_sci_port(port);
886 const struct plat_sci_reg *reg;
890 reg = sci_getreg(port, s->overrun_reg);
894 status = serial_port_in(port, s->overrun_reg);
895 if (status & s->overrun_mask) {
896 status &= ~s->overrun_mask;
897 serial_port_out(port, s->overrun_reg, status);
899 port->icount.overrun++;
901 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
902 tty_flip_buffer_push(tport);
904 dev_dbg(port->dev, "overrun error\n");
911 static int sci_handle_breaks(struct uart_port *port)
914 unsigned short status = serial_port_in(port, SCxSR);
915 struct tty_port *tport = &port->state->port;
916 struct sci_port *s = to_sci_port(port);
918 if (uart_handle_break(port))
921 if (!s->break_flag && status & SCxSR_BRK(port)) {
922 #if defined(CONFIG_CPU_SH3)
929 /* Notify of BREAK */
930 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
933 dev_dbg(port->dev, "BREAK detected\n");
937 tty_flip_buffer_push(tport);
939 copied += sci_handle_fifo_overrun(port);
944 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
946 #ifdef CONFIG_SERIAL_SH_SCI_DMA
947 struct uart_port *port = ptr;
948 struct sci_port *s = to_sci_port(port);
951 u16 scr = serial_port_in(port, SCSCR);
952 u16 ssr = serial_port_in(port, SCxSR);
954 /* Disable future Rx interrupts */
955 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
956 disable_irq_nosync(irq);
961 serial_port_out(port, SCSCR, scr);
962 /* Clear current interrupt */
963 serial_port_out(port, SCxSR,
964 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
965 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
966 jiffies, s->rx_timeout);
967 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
973 /* I think sci_receive_chars has to be called irrespective
974 * of whether the I_IXOFF is set, otherwise, how is the interrupt
977 sci_receive_chars(ptr);
982 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
984 struct uart_port *port = ptr;
987 spin_lock_irqsave(&port->lock, flags);
988 sci_transmit_chars(port);
989 spin_unlock_irqrestore(&port->lock, flags);
994 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
996 struct uart_port *port = ptr;
999 if (port->type == PORT_SCI) {
1000 if (sci_handle_errors(port)) {
1001 /* discard character in rx buffer */
1002 serial_port_in(port, SCxSR);
1003 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1006 sci_handle_fifo_overrun(port);
1007 sci_rx_interrupt(irq, ptr);
1010 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1012 /* Kick the transmission */
1013 sci_tx_interrupt(irq, ptr);
1018 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1020 struct uart_port *port = ptr;
1023 sci_handle_breaks(port);
1024 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1029 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1032 * Not all ports (such as SCIFA) will support REIE. Rather than
1033 * special-casing the port type, we check the port initialization
1034 * IRQ enable mask to see whether the IRQ is desired at all. If
1035 * it's unset, it's logically inferred that there's no point in
1038 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1041 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1043 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1044 struct uart_port *port = ptr;
1045 struct sci_port *s = to_sci_port(port);
1046 irqreturn_t ret = IRQ_NONE;
1048 ssr_status = serial_port_in(port, SCxSR);
1049 scr_status = serial_port_in(port, SCSCR);
1050 if (s->overrun_reg == SCxSR)
1051 orer_status = ssr_status;
1053 if (sci_getreg(port, s->overrun_reg)->size)
1054 orer_status = serial_port_in(port, s->overrun_reg);
1057 err_enabled = scr_status & port_rx_irq_mask(port);
1060 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1062 ret = sci_tx_interrupt(irq, ptr);
1065 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1068 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1069 (scr_status & SCSCR_RIE))
1070 ret = sci_rx_interrupt(irq, ptr);
1072 /* Error Interrupt */
1073 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1074 ret = sci_er_interrupt(irq, ptr);
1076 /* Break Interrupt */
1077 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1078 ret = sci_br_interrupt(irq, ptr);
1080 /* Overrun Interrupt */
1081 if (orer_status & s->overrun_mask) {
1082 sci_handle_fifo_overrun(port);
1090 * Here we define a transition notifier so that we can update all of our
1091 * ports' baud rate when the peripheral clock changes.
1093 static int sci_notifier(struct notifier_block *self,
1094 unsigned long phase, void *p)
1096 struct sci_port *sci_port;
1097 unsigned long flags;
1099 sci_port = container_of(self, struct sci_port, freq_transition);
1101 if (phase == CPUFREQ_POSTCHANGE) {
1102 struct uart_port *port = &sci_port->port;
1104 spin_lock_irqsave(&port->lock, flags);
1105 port->uartclk = clk_get_rate(sci_port->iclk);
1106 spin_unlock_irqrestore(&port->lock, flags);
1112 static const struct sci_irq_desc {
1114 irq_handler_t handler;
1115 } sci_irq_desc[] = {
1117 * Split out handlers, the default case.
1121 .handler = sci_er_interrupt,
1126 .handler = sci_rx_interrupt,
1131 .handler = sci_tx_interrupt,
1136 .handler = sci_br_interrupt,
1140 * Special muxed handler.
1144 .handler = sci_mpxed_interrupt,
1148 static int sci_request_irq(struct sci_port *port)
1150 struct uart_port *up = &port->port;
1153 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1154 const struct sci_irq_desc *desc;
1157 if (SCIx_IRQ_IS_MUXED(port)) {
1161 irq = port->irqs[i];
1164 * Certain port types won't support all of the
1165 * available interrupt sources.
1167 if (unlikely(irq < 0))
1171 desc = sci_irq_desc + i;
1172 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1173 dev_name(up->dev), desc->desc);
1174 if (!port->irqstr[j])
1177 ret = request_irq(irq, desc->handler, up->irqflags,
1178 port->irqstr[j], port);
1179 if (unlikely(ret)) {
1180 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1189 free_irq(port->irqs[i], port);
1193 kfree(port->irqstr[j]);
1198 static void sci_free_irq(struct sci_port *port)
1203 * Intentionally in reverse order so we iterate over the muxed
1206 for (i = 0; i < SCIx_NR_IRQS; i++) {
1207 int irq = port->irqs[i];
1210 * Certain port types won't support all of the available
1211 * interrupt sources.
1213 if (unlikely(irq < 0))
1216 free_irq(port->irqs[i], port);
1217 kfree(port->irqstr[i]);
1219 if (SCIx_IRQ_IS_MUXED(port)) {
1220 /* If there's only one IRQ, we're done. */
1226 static unsigned int sci_tx_empty(struct uart_port *port)
1228 unsigned short status = serial_port_in(port, SCxSR);
1229 unsigned short in_tx_fifo = sci_txfill(port);
1231 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1235 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1236 * CTS/RTS is supported in hardware by at least one port and controlled
1237 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1238 * handled via the ->init_pins() op, which is a bit of a one-way street,
1239 * lacking any ability to defer pin control -- this will later be
1240 * converted over to the GPIO framework).
1242 * Other modes (such as loopback) are supported generically on certain
1243 * port types, but not others. For these it's sufficient to test for the
1244 * existence of the support register and simply ignore the port type.
1246 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1248 if (mctrl & TIOCM_LOOP) {
1249 const struct plat_sci_reg *reg;
1252 * Standard loopback mode for SCFCR ports.
1254 reg = sci_getreg(port, SCFCR);
1256 serial_port_out(port, SCFCR,
1257 serial_port_in(port, SCFCR) |
1262 static unsigned int sci_get_mctrl(struct uart_port *port)
1265 * CTS/RTS is handled in hardware when supported, while nothing
1266 * else is wired up. Keep it simple and simply assert DSR/CAR.
1268 return TIOCM_DSR | TIOCM_CAR;
1271 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1272 static void sci_dma_tx_complete(void *arg)
1274 struct sci_port *s = arg;
1275 struct uart_port *port = &s->port;
1276 struct circ_buf *xmit = &port->state->xmit;
1277 unsigned long flags;
1279 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1281 spin_lock_irqsave(&port->lock, flags);
1283 xmit->tail += sg_dma_len(&s->sg_tx);
1284 xmit->tail &= UART_XMIT_SIZE - 1;
1286 port->icount.tx += sg_dma_len(&s->sg_tx);
1288 async_tx_ack(s->desc_tx);
1291 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1292 uart_write_wakeup(port);
1294 if (!uart_circ_empty(xmit)) {
1296 schedule_work(&s->work_tx);
1298 s->cookie_tx = -EINVAL;
1299 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1300 u16 ctrl = serial_port_in(port, SCSCR);
1301 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1305 spin_unlock_irqrestore(&port->lock, flags);
1308 /* Locking: called with port lock held */
1309 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1311 struct uart_port *port = &s->port;
1312 struct tty_port *tport = &port->state->port;
1313 int i, active, room;
1315 room = tty_buffer_request_room(tport, count);
1317 if (s->active_rx == s->cookie_rx[0]) {
1319 } else if (s->active_rx == s->cookie_rx[1]) {
1322 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1328 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1333 for (i = 0; i < room; i++)
1334 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1337 port->icount.rx += room;
1342 static void sci_dma_rx_complete(void *arg)
1344 struct sci_port *s = arg;
1345 struct uart_port *port = &s->port;
1346 unsigned long flags;
1349 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1352 spin_lock_irqsave(&port->lock, flags);
1354 count = sci_dma_rx_push(s, s->buf_len_rx);
1356 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1358 spin_unlock_irqrestore(&port->lock, flags);
1361 tty_flip_buffer_push(&port->state->port);
1363 schedule_work(&s->work_rx);
1366 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1368 struct dma_chan *chan = s->chan_rx;
1369 struct uart_port *port = &s->port;
1372 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1373 dma_release_channel(chan);
1374 if (sg_dma_address(&s->sg_rx[0]))
1375 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1376 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1381 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1383 struct dma_chan *chan = s->chan_tx;
1384 struct uart_port *port = &s->port;
1387 s->cookie_tx = -EINVAL;
1388 dma_release_channel(chan);
1393 static void sci_submit_rx(struct sci_port *s)
1395 struct dma_chan *chan = s->chan_rx;
1398 for (i = 0; i < 2; i++) {
1399 struct scatterlist *sg = &s->sg_rx[i];
1400 struct dma_async_tx_descriptor *desc;
1402 desc = dmaengine_prep_slave_sg(chan,
1403 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1406 s->desc_rx[i] = desc;
1407 desc->callback = sci_dma_rx_complete;
1408 desc->callback_param = s;
1409 s->cookie_rx[i] = desc->tx_submit(desc);
1412 if (!desc || s->cookie_rx[i] < 0) {
1414 async_tx_ack(s->desc_rx[0]);
1415 s->cookie_rx[0] = -EINVAL;
1419 s->cookie_rx[i] = -EINVAL;
1421 dev_warn(s->port.dev,
1422 "Failed to re-start Rx DMA, using PIO\n");
1423 sci_rx_dma_release(s, true);
1426 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1427 s->cookie_rx[i], i);
1430 s->active_rx = s->cookie_rx[0];
1432 dma_async_issue_pending(chan);
1435 static void work_fn_rx(struct work_struct *work)
1437 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1438 struct uart_port *port = &s->port;
1439 struct dma_async_tx_descriptor *desc;
1442 if (s->active_rx == s->cookie_rx[0]) {
1444 } else if (s->active_rx == s->cookie_rx[1]) {
1447 dev_err(port->dev, "%s: Rx cookie %d not found!\n", __func__,
1451 desc = s->desc_rx[new];
1453 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1455 /* Handle incomplete DMA receive */
1456 struct dma_chan *chan = s->chan_rx;
1457 struct shdma_desc *sh_desc = container_of(desc,
1458 struct shdma_desc, async_tx);
1459 unsigned long flags;
1462 dmaengine_terminate_all(chan);
1463 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1464 sh_desc->partial, sh_desc->cookie);
1466 spin_lock_irqsave(&port->lock, flags);
1467 count = sci_dma_rx_push(s, sh_desc->partial);
1468 spin_unlock_irqrestore(&port->lock, flags);
1471 tty_flip_buffer_push(&port->state->port);
1478 s->cookie_rx[new] = desc->tx_submit(desc);
1479 if (s->cookie_rx[new] < 0) {
1480 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1481 sci_rx_dma_release(s, true);
1485 s->active_rx = s->cookie_rx[!new];
1487 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1488 __func__, s->cookie_rx[new], new, s->active_rx);
1491 static void work_fn_tx(struct work_struct *work)
1493 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1494 struct dma_async_tx_descriptor *desc;
1495 struct dma_chan *chan = s->chan_tx;
1496 struct uart_port *port = &s->port;
1497 struct circ_buf *xmit = &port->state->xmit;
1498 struct scatterlist *sg = &s->sg_tx;
1502 * Port xmit buffer is already mapped, and it is one page... Just adjust
1503 * offsets and lengths. Since it is a circular buffer, we have to
1504 * transmit till the end, and then the rest. Take the port lock to get a
1505 * consistent xmit buffer state.
1507 spin_lock_irq(&port->lock);
1508 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1509 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1511 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1512 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1513 spin_unlock_irq(&port->lock);
1515 BUG_ON(!sg_dma_len(sg));
1517 desc = dmaengine_prep_slave_sg(chan,
1518 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1519 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1521 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1523 sci_tx_dma_release(s, true);
1527 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1529 spin_lock_irq(&port->lock);
1531 desc->callback = sci_dma_tx_complete;
1532 desc->callback_param = s;
1533 spin_unlock_irq(&port->lock);
1534 s->cookie_tx = desc->tx_submit(desc);
1535 if (s->cookie_tx < 0) {
1536 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1538 sci_tx_dma_release(s, true);
1542 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1543 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1545 dma_async_issue_pending(chan);
1549 static void sci_start_tx(struct uart_port *port)
1551 struct sci_port *s = to_sci_port(port);
1552 unsigned short ctrl;
1554 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1556 u16 new, scr = serial_port_in(port, SCSCR);
1558 new = scr | SCSCR_TDRQE;
1560 new = scr & ~SCSCR_TDRQE;
1562 serial_port_out(port, SCSCR, new);
1565 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1568 schedule_work(&s->work_tx);
1572 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1573 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1574 ctrl = serial_port_in(port, SCSCR);
1575 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1579 static void sci_stop_tx(struct uart_port *port)
1581 unsigned short ctrl;
1583 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1584 ctrl = serial_port_in(port, SCSCR);
1586 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1587 ctrl &= ~SCSCR_TDRQE;
1591 serial_port_out(port, SCSCR, ctrl);
1594 static void sci_start_rx(struct uart_port *port)
1596 unsigned short ctrl;
1598 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1600 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1601 ctrl &= ~SCSCR_RDRQE;
1603 serial_port_out(port, SCSCR, ctrl);
1606 static void sci_stop_rx(struct uart_port *port)
1608 unsigned short ctrl;
1610 ctrl = serial_port_in(port, SCSCR);
1612 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1613 ctrl &= ~SCSCR_RDRQE;
1615 ctrl &= ~port_rx_irq_mask(port);
1617 serial_port_out(port, SCSCR, ctrl);
1620 static void sci_break_ctl(struct uart_port *port, int break_state)
1622 struct sci_port *s = to_sci_port(port);
1623 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1624 unsigned short scscr, scsptr;
1626 /* check wheter the port has SCSPTR */
1629 * Not supported by hardware. Most parts couple break and rx
1630 * interrupts together, with break detection always enabled.
1635 scsptr = serial_port_in(port, SCSPTR);
1636 scscr = serial_port_in(port, SCSCR);
1638 if (break_state == -1) {
1639 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1642 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1646 serial_port_out(port, SCSPTR, scsptr);
1647 serial_port_out(port, SCSCR, scscr);
1650 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1651 static bool filter(struct dma_chan *chan, void *slave)
1653 struct sh_dmae_slave *param = slave;
1655 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1656 __func__, param->shdma_slave.slave_id);
1658 chan->private = ¶m->shdma_slave;
1662 static void rx_timer_fn(unsigned long arg)
1664 struct sci_port *s = (struct sci_port *)arg;
1665 struct uart_port *port = &s->port;
1666 u16 scr = serial_port_in(port, SCSCR);
1668 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1669 scr &= ~SCSCR_RDRQE;
1670 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1672 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1673 dev_dbg(port->dev, "DMA Rx timed out\n");
1674 schedule_work(&s->work_rx);
1677 static void sci_request_dma(struct uart_port *port)
1679 struct sci_port *s = to_sci_port(port);
1680 struct sh_dmae_slave *param;
1681 struct dma_chan *chan;
1682 dma_cap_mask_t mask;
1685 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1687 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1691 dma_cap_set(DMA_SLAVE, mask);
1693 param = &s->param_tx;
1695 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1696 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1698 s->cookie_tx = -EINVAL;
1699 chan = dma_request_channel(mask, filter, param);
1700 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1703 sg_init_table(&s->sg_tx, 1);
1704 /* UART circular tx buffer is an aligned page. */
1705 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1706 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1708 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1709 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1711 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1712 sci_tx_dma_release(s, false);
1714 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1716 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1717 &sg_dma_address(&s->sg_tx));
1720 s->sg_len_tx = nent;
1722 INIT_WORK(&s->work_tx, work_fn_tx);
1725 param = &s->param_rx;
1727 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1728 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1730 chan = dma_request_channel(mask, filter, param);
1731 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1739 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1740 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1741 &dma[0], GFP_KERNEL);
1745 "Failed to allocate Rx dma buffer, using PIO\n");
1746 sci_rx_dma_release(s, true);
1750 buf[1] = buf[0] + s->buf_len_rx;
1751 dma[1] = dma[0] + s->buf_len_rx;
1753 for (i = 0; i < 2; i++) {
1754 struct scatterlist *sg = &s->sg_rx[i];
1756 sg_init_table(sg, 1);
1757 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1758 (uintptr_t)buf[i] & ~PAGE_MASK);
1759 sg_dma_address(sg) = dma[i];
1762 INIT_WORK(&s->work_rx, work_fn_rx);
1763 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1769 static void sci_free_dma(struct uart_port *port)
1771 struct sci_port *s = to_sci_port(port);
1774 sci_tx_dma_release(s, false);
1776 sci_rx_dma_release(s, false);
1779 static inline void sci_request_dma(struct uart_port *port)
1783 static inline void sci_free_dma(struct uart_port *port)
1788 static int sci_startup(struct uart_port *port)
1790 struct sci_port *s = to_sci_port(port);
1791 unsigned long flags;
1794 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1796 ret = sci_request_irq(s);
1797 if (unlikely(ret < 0))
1800 sci_request_dma(port);
1802 spin_lock_irqsave(&port->lock, flags);
1805 spin_unlock_irqrestore(&port->lock, flags);
1810 static void sci_shutdown(struct uart_port *port)
1812 struct sci_port *s = to_sci_port(port);
1813 unsigned long flags;
1815 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1817 spin_lock_irqsave(&port->lock, flags);
1820 spin_unlock_irqrestore(&port->lock, flags);
1826 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1829 if (s->sampling_rate)
1830 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1832 /* Warn, but use a safe default */
1835 return ((freq + 16 * bps) / (32 * bps) - 1);
1838 /* calculate frame length from SMR */
1839 static int sci_baud_calc_frame_len(unsigned int smr_val)
1843 if (smr_val & SCSMR_CHR)
1845 if (smr_val & SCSMR_PE)
1847 if (smr_val & SCSMR_STOP)
1854 /* calculate sample rate, BRR, and clock select for HSCIF */
1855 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1856 int *brr, unsigned int *srr,
1857 unsigned int *cks, int frame_len)
1859 int sr, c, br, err, recv_margin;
1860 int min_err = 1000; /* 100% */
1861 int recv_max_margin = 0;
1863 /* Find the combination of sample rate and clock select with the
1864 smallest deviation from the desired baud rate. */
1865 for (sr = 8; sr <= 32; sr++) {
1866 for (c = 0; c <= 3; c++) {
1867 /* integerized formulas from HSCIF documentation */
1868 br = DIV_ROUND_CLOSEST(freq, (sr *
1869 (1 << (2 * c + 1)) * bps)) - 1;
1870 br = clamp(br, 0, 255);
1871 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1872 (1 << (2 * c + 1)) / 1000)) -
1875 * M: Receive margin (%)
1876 * N: Ratio of bit rate to clock (N = sampling rate)
1877 * D: Clock duty (D = 0 to 1.0)
1878 * L: Frame length (L = 9 to 12)
1879 * F: Absolute value of clock frequency deviation
1881 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1882 * (|D - 0.5| / N * (1 + F))|
1883 * NOTE: Usually, treat D for 0.5, F is 0 by this
1886 recv_margin = abs((500 -
1887 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1888 if (abs(min_err) > abs(err)) {
1890 recv_max_margin = recv_margin;
1891 } else if ((min_err == err) &&
1892 (recv_margin > recv_max_margin))
1893 recv_max_margin = recv_margin;
1903 if (min_err == 1000) {
1912 static void sci_reset(struct uart_port *port)
1914 const struct plat_sci_reg *reg;
1915 unsigned int status;
1918 status = serial_port_in(port, SCxSR);
1919 } while (!(status & SCxSR_TEND(port)));
1921 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1923 reg = sci_getreg(port, SCFCR);
1925 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1928 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1929 struct ktermios *old)
1931 struct sci_port *s = to_sci_port(port);
1932 const struct plat_sci_reg *reg;
1933 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1935 unsigned int srr = 15;
1937 if ((termios->c_cflag & CSIZE) == CS7)
1938 smr_val |= SCSMR_CHR;
1939 if (termios->c_cflag & PARENB)
1940 smr_val |= SCSMR_PE;
1941 if (termios->c_cflag & PARODD)
1942 smr_val |= SCSMR_PE | SCSMR_ODD;
1943 if (termios->c_cflag & CSTOPB)
1944 smr_val |= SCSMR_STOP;
1947 * earlyprintk comes here early on with port->uartclk set to zero.
1948 * the clock framework is not up and running at this point so here
1949 * we assume that 115200 is the maximum baud rate. please note that
1950 * the baud rate is not programmed during earlyprintk - it is assumed
1951 * that the previous boot loader has enabled required clocks and
1952 * setup the baud rate generator hardware for us already.
1954 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1956 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1957 if (likely(baud && port->uartclk)) {
1958 if (s->cfg->type == PORT_HSCIF) {
1959 int frame_len = sci_baud_calc_frame_len(smr_val);
1960 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1963 t = sci_scbrr_calc(s, baud, port->uartclk);
1964 for (cks = 0; t >= 256 && cks <= 3; cks++)
1973 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1975 uart_update_timeout(port, termios->c_cflag, baud);
1977 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1978 __func__, smr_val, cks, t, s->cfg->scscr);
1981 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1982 serial_port_out(port, SCBRR, t);
1983 reg = sci_getreg(port, HSSRR);
1985 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1986 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1988 serial_port_out(port, SCSMR, smr_val);
1990 sci_init_pins(port, termios->c_cflag);
1992 reg = sci_getreg(port, SCFCR);
1994 unsigned short ctrl = serial_port_in(port, SCFCR);
1996 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1997 if (termios->c_cflag & CRTSCTS)
2004 * As we've done a sci_reset() above, ensure we don't
2005 * interfere with the FIFOs while toggling MCE. As the
2006 * reset values could still be set, simply mask them out.
2008 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2010 serial_port_out(port, SCFCR, ctrl);
2013 serial_port_out(port, SCSCR, s->cfg->scscr);
2015 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2017 * Calculate delay for 2 DMA buffers (4 FIFO).
2018 * See serial_core.c::uart_update_timeout().
2019 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2020 * function calculates 1 jiffie for the data plus 5 jiffies for the
2021 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2022 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2023 * value obtained by this formula is too small. Therefore, if the value
2024 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2029 /* byte size and parity */
2030 switch (termios->c_cflag & CSIZE) {
2045 if (termios->c_cflag & CSTOPB)
2047 if (termios->c_cflag & PARENB)
2049 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2051 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2052 s->rx_timeout * 1000 / HZ, port->timeout);
2053 if (s->rx_timeout < msecs_to_jiffies(20))
2054 s->rx_timeout = msecs_to_jiffies(20);
2058 if ((termios->c_cflag & CREAD) != 0)
2061 sci_port_disable(s);
2064 static void sci_pm(struct uart_port *port, unsigned int state,
2065 unsigned int oldstate)
2067 struct sci_port *sci_port = to_sci_port(port);
2070 case UART_PM_STATE_OFF:
2071 sci_port_disable(sci_port);
2074 sci_port_enable(sci_port);
2079 static const char *sci_type(struct uart_port *port)
2081 switch (port->type) {
2099 static int sci_remap_port(struct uart_port *port)
2101 struct sci_port *sport = to_sci_port(port);
2104 * Nothing to do if there's already an established membase.
2109 if (port->flags & UPF_IOREMAP) {
2110 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2111 if (unlikely(!port->membase)) {
2112 dev_err(port->dev, "can't remap port#%d\n", port->line);
2117 * For the simple (and majority of) cases where we don't
2118 * need to do any remapping, just cast the cookie
2121 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2127 static void sci_release_port(struct uart_port *port)
2129 struct sci_port *sport = to_sci_port(port);
2131 if (port->flags & UPF_IOREMAP) {
2132 iounmap(port->membase);
2133 port->membase = NULL;
2136 release_mem_region(port->mapbase, sport->reg_size);
2139 static int sci_request_port(struct uart_port *port)
2141 struct resource *res;
2142 struct sci_port *sport = to_sci_port(port);
2145 res = request_mem_region(port->mapbase, sport->reg_size,
2146 dev_name(port->dev));
2147 if (unlikely(res == NULL)) {
2148 dev_err(port->dev, "request_mem_region failed.");
2152 ret = sci_remap_port(port);
2153 if (unlikely(ret != 0)) {
2154 release_resource(res);
2161 static void sci_config_port(struct uart_port *port, int flags)
2163 if (flags & UART_CONFIG_TYPE) {
2164 struct sci_port *sport = to_sci_port(port);
2166 port->type = sport->cfg->type;
2167 sci_request_port(port);
2171 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2173 if (ser->baud_base < 2400)
2174 /* No paper tape reader for Mitch.. */
2180 static struct uart_ops sci_uart_ops = {
2181 .tx_empty = sci_tx_empty,
2182 .set_mctrl = sci_set_mctrl,
2183 .get_mctrl = sci_get_mctrl,
2184 .start_tx = sci_start_tx,
2185 .stop_tx = sci_stop_tx,
2186 .stop_rx = sci_stop_rx,
2187 .break_ctl = sci_break_ctl,
2188 .startup = sci_startup,
2189 .shutdown = sci_shutdown,
2190 .set_termios = sci_set_termios,
2193 .release_port = sci_release_port,
2194 .request_port = sci_request_port,
2195 .config_port = sci_config_port,
2196 .verify_port = sci_verify_port,
2197 #ifdef CONFIG_CONSOLE_POLL
2198 .poll_get_char = sci_poll_get_char,
2199 .poll_put_char = sci_poll_put_char,
2203 static int sci_init_single(struct platform_device *dev,
2204 struct sci_port *sci_port, unsigned int index,
2205 struct plat_sci_port *p, bool early)
2207 struct uart_port *port = &sci_port->port;
2208 const struct resource *res;
2214 port->ops = &sci_uart_ops;
2215 port->iotype = UPIO_MEM;
2218 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2222 port->mapbase = res->start;
2223 sci_port->reg_size = resource_size(res);
2225 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2226 sci_port->irqs[i] = platform_get_irq(dev, i);
2228 /* The SCI generates several interrupts. They can be muxed together or
2229 * connected to different interrupt lines. In the muxed case only one
2230 * interrupt resource is specified. In the non-muxed case three or four
2231 * interrupt resources are specified, as the BRI interrupt is optional.
2233 if (sci_port->irqs[0] < 0)
2236 if (sci_port->irqs[1] < 0) {
2237 sci_port->irqs[1] = sci_port->irqs[0];
2238 sci_port->irqs[2] = sci_port->irqs[0];
2239 sci_port->irqs[3] = sci_port->irqs[0];
2242 if (p->regtype == SCIx_PROBE_REGTYPE) {
2243 ret = sci_probe_regmap(p);
2250 port->fifosize = 256;
2251 sci_port->overrun_reg = SCxSR;
2252 sci_port->overrun_mask = SCIFA_ORER;
2253 sci_port->sampling_rate = 16;
2256 port->fifosize = 128;
2257 sci_port->overrun_reg = SCLSR;
2258 sci_port->overrun_mask = SCLSR_ORER;
2259 sci_port->sampling_rate = 0;
2262 port->fifosize = 64;
2263 sci_port->overrun_reg = SCxSR;
2264 sci_port->overrun_mask = SCIFA_ORER;
2265 sci_port->sampling_rate = 16;
2268 port->fifosize = 16;
2269 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2270 sci_port->overrun_reg = SCxSR;
2271 sci_port->overrun_mask = SCIFA_ORER;
2272 sci_port->sampling_rate = 16;
2274 sci_port->overrun_reg = SCLSR;
2275 sci_port->overrun_mask = SCLSR_ORER;
2276 sci_port->sampling_rate = 32;
2281 sci_port->overrun_reg = SCxSR;
2282 sci_port->overrun_mask = SCI_ORER;
2283 sci_port->sampling_rate = 32;
2287 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2288 * match the SoC datasheet, this should be investigated. Let platform
2289 * data override the sampling rate for now.
2291 if (p->sampling_rate)
2292 sci_port->sampling_rate = p->sampling_rate;
2295 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2296 if (IS_ERR(sci_port->iclk)) {
2297 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2298 if (IS_ERR(sci_port->iclk)) {
2299 dev_err(&dev->dev, "can't get iclk\n");
2300 return PTR_ERR(sci_port->iclk);
2305 * The function clock is optional, ignore it if we can't
2308 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2309 if (IS_ERR(sci_port->fclk))
2310 sci_port->fclk = NULL;
2312 port->dev = &dev->dev;
2314 pm_runtime_enable(&dev->dev);
2317 sci_port->break_timer.data = (unsigned long)sci_port;
2318 sci_port->break_timer.function = sci_break_timer;
2319 init_timer(&sci_port->break_timer);
2322 * Establish some sensible defaults for the error detection.
2324 if (p->type == PORT_SCI) {
2325 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2326 sci_port->error_clear = SCI_ERROR_CLEAR;
2328 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2329 sci_port->error_clear = SCIF_ERROR_CLEAR;
2333 * Make the error mask inclusive of overrun detection, if
2336 if (sci_port->overrun_reg == SCxSR) {
2337 sci_port->error_mask |= sci_port->overrun_mask;
2338 sci_port->error_clear &= ~sci_port->overrun_mask;
2341 port->type = p->type;
2342 port->flags = UPF_FIXED_PORT | p->flags;
2343 port->regshift = p->regshift;
2346 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2347 * for the multi-IRQ ports, which is where we are primarily
2348 * concerned with the shutdown path synchronization.
2350 * For the muxed case there's nothing more to do.
2352 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2355 port->serial_in = sci_serial_in;
2356 port->serial_out = sci_serial_out;
2358 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2359 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2360 p->dma_slave_tx, p->dma_slave_rx);
2365 static void sci_cleanup_single(struct sci_port *port)
2367 clk_put(port->iclk);
2368 clk_put(port->fclk);
2370 pm_runtime_disable(port->port.dev);
2373 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2374 static void serial_console_putchar(struct uart_port *port, int ch)
2376 sci_poll_put_char(port, ch);
2380 * Print a string to the serial port trying not to disturb
2381 * any possible real use of the port...
2383 static void serial_console_write(struct console *co, const char *s,
2386 struct sci_port *sci_port = &sci_ports[co->index];
2387 struct uart_port *port = &sci_port->port;
2388 unsigned short bits, ctrl;
2389 unsigned long flags;
2392 local_irq_save(flags);
2395 else if (oops_in_progress)
2396 locked = spin_trylock(&port->lock);
2398 spin_lock(&port->lock);
2400 /* first save the SCSCR then disable the interrupts */
2401 ctrl = serial_port_in(port, SCSCR);
2402 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2404 uart_console_write(port, s, count, serial_console_putchar);
2406 /* wait until fifo is empty and last bit has been transmitted */
2407 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2408 while ((serial_port_in(port, SCxSR) & bits) != bits)
2411 /* restore the SCSCR */
2412 serial_port_out(port, SCSCR, ctrl);
2415 spin_unlock(&port->lock);
2416 local_irq_restore(flags);
2419 static int serial_console_setup(struct console *co, char *options)
2421 struct sci_port *sci_port;
2422 struct uart_port *port;
2430 * Refuse to handle any bogus ports.
2432 if (co->index < 0 || co->index >= SCI_NPORTS)
2435 sci_port = &sci_ports[co->index];
2436 port = &sci_port->port;
2439 * Refuse to handle uninitialized ports.
2444 ret = sci_remap_port(port);
2445 if (unlikely(ret != 0))
2449 uart_parse_options(options, &baud, &parity, &bits, &flow);
2451 return uart_set_options(port, co, baud, parity, bits, flow);
2454 static struct console serial_console = {
2456 .device = uart_console_device,
2457 .write = serial_console_write,
2458 .setup = serial_console_setup,
2459 .flags = CON_PRINTBUFFER,
2461 .data = &sci_uart_driver,
2464 static struct console early_serial_console = {
2465 .name = "early_ttySC",
2466 .write = serial_console_write,
2467 .flags = CON_PRINTBUFFER,
2471 static char early_serial_buf[32];
2473 static int sci_probe_earlyprintk(struct platform_device *pdev)
2475 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2477 if (early_serial_console.data)
2480 early_serial_console.index = pdev->id;
2482 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2484 serial_console_setup(&early_serial_console, early_serial_buf);
2486 if (!strstr(early_serial_buf, "keep"))
2487 early_serial_console.flags |= CON_BOOT;
2489 register_console(&early_serial_console);
2493 #define SCI_CONSOLE (&serial_console)
2496 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2501 #define SCI_CONSOLE NULL
2503 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2505 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2507 static struct uart_driver sci_uart_driver = {
2508 .owner = THIS_MODULE,
2509 .driver_name = "sci",
2510 .dev_name = "ttySC",
2512 .minor = SCI_MINOR_START,
2514 .cons = SCI_CONSOLE,
2517 static int sci_remove(struct platform_device *dev)
2519 struct sci_port *port = platform_get_drvdata(dev);
2521 cpufreq_unregister_notifier(&port->freq_transition,
2522 CPUFREQ_TRANSITION_NOTIFIER);
2524 uart_remove_one_port(&sci_uart_driver, &port->port);
2526 sci_cleanup_single(port);
2531 struct sci_port_info {
2533 unsigned int regtype;
2536 static const struct of_device_id of_sci_match[] = {
2538 .compatible = "renesas,scif",
2539 .data = &(const struct sci_port_info) {
2541 .regtype = SCIx_SH4_SCIF_REGTYPE,
2544 .compatible = "renesas,scifa",
2545 .data = &(const struct sci_port_info) {
2547 .regtype = SCIx_SCIFA_REGTYPE,
2550 .compatible = "renesas,scifb",
2551 .data = &(const struct sci_port_info) {
2553 .regtype = SCIx_SCIFB_REGTYPE,
2556 .compatible = "renesas,hscif",
2557 .data = &(const struct sci_port_info) {
2559 .regtype = SCIx_HSCIF_REGTYPE,
2562 .compatible = "renesas,sci",
2563 .data = &(const struct sci_port_info) {
2565 .regtype = SCIx_SCI_REGTYPE,
2571 MODULE_DEVICE_TABLE(of, of_sci_match);
2573 static struct plat_sci_port *
2574 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2576 struct device_node *np = pdev->dev.of_node;
2577 const struct of_device_id *match;
2578 const struct sci_port_info *info;
2579 struct plat_sci_port *p;
2582 if (!IS_ENABLED(CONFIG_OF) || !np)
2585 match = of_match_node(of_sci_match, pdev->dev.of_node);
2591 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2595 /* Get the line number for the aliases node. */
2596 id = of_alias_get_id(np, "serial");
2598 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2604 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2605 p->type = info->type;
2606 p->regtype = info->regtype;
2607 p->scscr = SCSCR_RE | SCSCR_TE;
2612 static int sci_probe_single(struct platform_device *dev,
2614 struct plat_sci_port *p,
2615 struct sci_port *sciport)
2620 if (unlikely(index >= SCI_NPORTS)) {
2621 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2622 index+1, SCI_NPORTS);
2623 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2627 ret = sci_init_single(dev, sciport, index, p, false);
2631 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2633 sci_cleanup_single(sciport);
2640 static int sci_probe(struct platform_device *dev)
2642 struct plat_sci_port *p;
2643 struct sci_port *sp;
2644 unsigned int dev_id;
2648 * If we've come here via earlyprintk initialization, head off to
2649 * the special early probe. We don't have sufficient device state
2650 * to make it beyond this yet.
2652 if (is_early_platform_device(dev))
2653 return sci_probe_earlyprintk(dev);
2655 if (dev->dev.of_node) {
2656 p = sci_parse_dt(dev, &dev_id);
2660 p = dev->dev.platform_data;
2662 dev_err(&dev->dev, "no platform data supplied\n");
2669 sp = &sci_ports[dev_id];
2670 platform_set_drvdata(dev, sp);
2672 ret = sci_probe_single(dev, dev_id, p, sp);
2676 sp->freq_transition.notifier_call = sci_notifier;
2678 ret = cpufreq_register_notifier(&sp->freq_transition,
2679 CPUFREQ_TRANSITION_NOTIFIER);
2680 if (unlikely(ret < 0)) {
2681 uart_remove_one_port(&sci_uart_driver, &sp->port);
2682 sci_cleanup_single(sp);
2686 #ifdef CONFIG_SH_STANDARD_BIOS
2687 sh_bios_gdb_detach();
2693 static __maybe_unused int sci_suspend(struct device *dev)
2695 struct sci_port *sport = dev_get_drvdata(dev);
2698 uart_suspend_port(&sci_uart_driver, &sport->port);
2703 static __maybe_unused int sci_resume(struct device *dev)
2705 struct sci_port *sport = dev_get_drvdata(dev);
2708 uart_resume_port(&sci_uart_driver, &sport->port);
2713 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2715 static struct platform_driver sci_driver = {
2717 .remove = sci_remove,
2720 .pm = &sci_dev_pm_ops,
2721 .of_match_table = of_match_ptr(of_sci_match),
2725 static int __init sci_init(void)
2729 pr_info("%s\n", banner);
2731 ret = uart_register_driver(&sci_uart_driver);
2732 if (likely(ret == 0)) {
2733 ret = platform_driver_register(&sci_driver);
2735 uart_unregister_driver(&sci_uart_driver);
2741 static void __exit sci_exit(void)
2743 platform_driver_unregister(&sci_driver);
2744 uart_unregister_driver(&sci_uart_driver);
2747 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2748 early_platform_init_buffer("earlyprintk", &sci_driver,
2749 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2751 module_init(sci_init);
2752 module_exit(sci_exit);
2754 MODULE_LICENSE("GPL");
2755 MODULE_ALIAS("platform:sh-sci");
2756 MODULE_AUTHOR("Paul Mundt");
2757 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");