2 * Driver for CSR SiRFprimaII onboard UARTs.
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/module.h>
10 #include <linux/ioport.h>
11 #include <linux/platform_device.h>
12 #include <linux/init.h>
13 #include <linux/sysrq.h>
14 #include <linux/console.h>
15 #include <linux/tty.h>
16 #include <linux/tty_flip.h>
17 #include <linux/serial_core.h>
18 #include <linux/serial.h>
19 #include <linux/clk.h>
21 #include <linux/slab.h>
24 #include <asm/mach/irq.h>
25 #include <linux/pinctrl/consumer.h>
27 #include "sirfsoc_uart.h"
30 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
32 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
33 static struct uart_driver sirfsoc_uart_drv;
35 static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
56 static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
60 .flags = UPF_BOOT_AUTOCONF,
67 .flags = UPF_BOOT_AUTOCONF,
74 .flags = UPF_BOOT_AUTOCONF,
80 static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
82 return container_of(port, struct sirfsoc_uart_port, port);
85 static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
88 reg = rd_regl(port, SIRFUART_TX_FIFO_STATUS);
89 if (reg & SIRFUART_FIFOEMPTY_MASK(port))
95 static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
97 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
98 if (!(sirfport->ms_enabled)) {
100 } else if (sirfport->hw_flow_ctrl) {
101 if (!(rd_regl(port, SIRFUART_AFC_CTRL) &
102 SIRFUART_CTS_IN_STATUS))
108 return TIOCM_CAR | TIOCM_DSR;
110 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
113 static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
115 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
116 unsigned int assert = mctrl & TIOCM_RTS;
117 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
118 unsigned int current_val;
119 if (sirfport->hw_flow_ctrl) {
120 current_val = rd_regl(port, SIRFUART_AFC_CTRL) & ~0xFF;
122 wr_regl(port, SIRFUART_AFC_CTRL, val);
126 static void sirfsoc_uart_stop_tx(struct uart_port *port)
129 regv = rd_regl(port, SIRFUART_INT_EN);
130 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_TX_INT_EN);
133 void sirfsoc_uart_start_tx(struct uart_port *port)
135 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
137 sirfsoc_uart_pio_tx_chars(sirfport, 1);
138 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_START);
139 regv = rd_regl(port, SIRFUART_INT_EN);
140 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_TX_INT_EN);
143 static void sirfsoc_uart_stop_rx(struct uart_port *port)
146 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
147 regv = rd_regl(port, SIRFUART_INT_EN);
148 wr_regl(port, SIRFUART_INT_EN, regv & ~SIRFUART_RX_IO_INT_EN);
151 static void sirfsoc_uart_disable_ms(struct uart_port *port)
153 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
155 sirfport->ms_enabled = 0;
156 if (!sirfport->hw_flow_ctrl)
158 reg = rd_regl(port, SIRFUART_AFC_CTRL);
159 wr_regl(port, SIRFUART_AFC_CTRL, reg & ~0x3FF);
160 reg = rd_regl(port, SIRFUART_INT_EN);
161 wr_regl(port, SIRFUART_INT_EN, reg & ~SIRFUART_CTS_INT_EN);
164 static void sirfsoc_uart_enable_ms(struct uart_port *port)
166 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
169 if (!sirfport->hw_flow_ctrl)
171 flg = SIRFUART_AFC_RX_EN | SIRFUART_AFC_TX_EN;
172 reg = rd_regl(port, SIRFUART_AFC_CTRL);
173 wr_regl(port, SIRFUART_AFC_CTRL, reg | flg);
174 reg = rd_regl(port, SIRFUART_INT_EN);
175 wr_regl(port, SIRFUART_INT_EN, reg | SIRFUART_CTS_INT_EN);
176 uart_handle_cts_change(port,
177 !(rd_regl(port, SIRFUART_AFC_CTRL) & SIRFUART_CTS_IN_STATUS));
178 sirfport->ms_enabled = 1;
181 static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
183 unsigned long ulcon = rd_regl(port, SIRFUART_LINE_CTRL);
185 ulcon |= SIRFUART_SET_BREAK;
187 ulcon &= ~SIRFUART_SET_BREAK;
188 wr_regl(port, SIRFUART_LINE_CTRL, ulcon);
192 sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
194 unsigned int ch, rx_count = 0;
195 struct tty_struct *tty;
197 tty = tty_port_tty_get(&port->state->port);
201 while (!(rd_regl(port, SIRFUART_RX_FIFO_STATUS) &
202 SIRFUART_FIFOEMPTY_MASK(port))) {
203 ch = rd_regl(port, SIRFUART_RX_FIFO_DATA) | SIRFUART_DUMMY_READ;
204 if (unlikely(uart_handle_sysrq_char(port, ch)))
206 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
208 if (rx_count >= max_rx_count)
212 port->icount.rx += rx_count;
213 tty_flip_buffer_push(tty);
220 sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
222 struct uart_port *port = &sirfport->port;
223 struct circ_buf *xmit = &port->state->xmit;
224 unsigned int num_tx = 0;
225 while (!uart_circ_empty(xmit) &&
226 !(rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
227 SIRFUART_FIFOFULL_MASK(port)) &&
229 wr_regl(port, SIRFUART_TX_FIFO_DATA, xmit->buf[xmit->tail]);
230 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
234 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
235 uart_write_wakeup(port);
239 static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
241 unsigned long intr_status;
242 unsigned long cts_status;
243 unsigned long flag = TTY_NORMAL;
244 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
245 struct uart_port *port = &sirfport->port;
246 struct uart_state *state = port->state;
247 struct circ_buf *xmit = &port->state->xmit;
248 intr_status = rd_regl(port, SIRFUART_INT_STATUS);
249 wr_regl(port, SIRFUART_INT_STATUS, intr_status);
250 intr_status &= rd_regl(port, SIRFUART_INT_EN);
251 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT))) {
252 if (intr_status & SIRFUART_RXD_BREAK) {
253 if (uart_handle_break(port))
255 uart_insert_char(port, intr_status,
256 SIRFUART_RX_OFLOW, 0, TTY_BREAK);
259 if (intr_status & SIRFUART_RX_OFLOW)
260 port->icount.overrun++;
261 if (intr_status & SIRFUART_FRM_ERR) {
262 port->icount.frame++;
265 if (intr_status & SIRFUART_PARITY_ERR)
267 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
268 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
269 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
270 intr_status &= port->read_status_mask;
271 uart_insert_char(port, intr_status,
272 SIRFUART_RX_OFLOW_INT, 0, flag);
275 if (intr_status & SIRFUART_CTS_INT_EN) {
276 cts_status = !(rd_regl(port, SIRFUART_AFC_CTRL) &
277 SIRFUART_CTS_IN_STATUS);
278 if (cts_status != 0) {
279 uart_handle_cts_change(port, 1);
281 uart_handle_cts_change(port, 0);
282 wake_up_interruptible(&state->port.delta_msr_wait);
285 if (intr_status & SIRFUART_RX_IO_INT_EN)
286 sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
287 if (intr_status & SIRFUART_TX_INT_EN) {
288 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
291 sirfsoc_uart_pio_tx_chars(sirfport,
292 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
293 if ((uart_circ_empty(xmit)) &&
294 (rd_regl(port, SIRFUART_TX_FIFO_STATUS) &
295 SIRFUART_FIFOEMPTY_MASK(port)))
296 sirfsoc_uart_stop_tx(port);
302 static void sirfsoc_uart_start_rx(struct uart_port *port)
305 regv = rd_regl(port, SIRFUART_INT_EN);
306 wr_regl(port, SIRFUART_INT_EN, regv | SIRFUART_RX_IO_INT_EN);
307 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
308 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
309 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_START);
313 sirfsoc_calc_sample_div(unsigned long baud_rate,
314 unsigned long ioclk_rate, unsigned long *setted_baud)
316 unsigned long min_delta = ~0UL;
317 unsigned short sample_div;
318 unsigned int regv = 0;
319 unsigned long ioclk_div;
320 unsigned long baud_tmp;
323 for (sample_div = SIRF_MIN_SAMPLE_DIV;
324 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
325 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
326 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
328 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
329 temp_delta = baud_tmp - baud_rate;
330 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
331 if (temp_delta < min_delta) {
332 regv = regv & (~SIRF_IOCLK_DIV_MASK);
333 regv = regv | ioclk_div;
334 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
335 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
336 min_delta = temp_delta;
337 *setted_baud = baud_tmp;
343 static void sirfsoc_uart_set_termios(struct uart_port *port,
344 struct ktermios *termios,
345 struct ktermios *old)
347 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
348 unsigned long ioclk_rate;
349 unsigned long config_reg = 0;
350 unsigned long baud_rate;
351 unsigned long setted_baud;
354 unsigned int clk_div_reg = 0;
355 unsigned long temp_reg_val;
356 unsigned long rx_time_out;
360 ioclk_rate = 150000000;
361 switch (termios->c_cflag & CSIZE) {
364 config_reg |= SIRFUART_DATA_BIT_LEN_8;
367 config_reg |= SIRFUART_DATA_BIT_LEN_7;
370 config_reg |= SIRFUART_DATA_BIT_LEN_6;
373 config_reg |= SIRFUART_DATA_BIT_LEN_5;
376 if (termios->c_cflag & CSTOPB)
377 config_reg |= SIRFUART_STOP_BIT_LEN_2;
378 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
379 spin_lock_irqsave(&port->lock, flags);
380 port->read_status_mask = SIRFUART_RX_OFLOW_INT;
381 port->ignore_status_mask = 0;
383 if (termios->c_iflag & INPCK)
384 port->read_status_mask |=
385 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
386 if (termios->c_iflag & (BRKINT | PARMRK))
387 port->read_status_mask |= SIRFUART_RXD_BREAK_INT;
389 if (termios->c_iflag & IGNPAR)
390 port->ignore_status_mask |=
391 SIRFUART_FRM_ERR_INT | SIRFUART_PARITY_ERR_INT;
392 if ((termios->c_cflag & CREAD) == 0)
393 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
394 /* enable parity if PARENB is set*/
395 if (termios->c_cflag & PARENB) {
396 if (termios->c_cflag & CMSPAR) {
397 if (termios->c_cflag & PARODD)
398 config_reg |= SIRFUART_STICK_BIT_MARK;
400 config_reg |= SIRFUART_STICK_BIT_SPACE;
401 } else if (termios->c_cflag & PARODD) {
402 config_reg |= SIRFUART_STICK_BIT_ODD;
404 config_reg |= SIRFUART_STICK_BIT_EVEN;
407 /* Hardware Flow Control Settings */
408 if (UART_ENABLE_MS(port, termios->c_cflag)) {
409 if (!sirfport->ms_enabled)
410 sirfsoc_uart_enable_ms(port);
412 if (sirfport->ms_enabled)
413 sirfsoc_uart_disable_ms(port);
416 /* common rate: fast calculation */
417 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
418 if (baud_rate == baudrate_to_regv[ic].baud_rate)
419 clk_div_reg = baudrate_to_regv[ic].reg_val;
420 setted_baud = baud_rate;
421 /* arbitary rate setting */
422 if (unlikely(clk_div_reg == 0))
423 clk_div_reg = sirfsoc_calc_sample_div(baud_rate, ioclk_rate,
425 wr_regl(port, SIRFUART_DIVISOR, clk_div_reg);
427 if (tty_termios_baud_rate(termios))
428 tty_termios_encode_baud_rate(termios, setted_baud, setted_baud);
430 /* set receive timeout */
431 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(baud_rate, 20000);
432 rx_time_out = (rx_time_out > 0xFFFF) ? 0xFFFF : rx_time_out;
433 config_reg |= SIRFUART_RECV_TIMEOUT(rx_time_out);
434 temp_reg_val = rd_regl(port, SIRFUART_TX_FIFO_OP);
435 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
436 wr_regl(port, SIRFUART_TX_FIFO_OP,
437 temp_reg_val & ~SIRFUART_TX_FIFO_START);
438 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, SIRFUART_TX_MODE_IO);
439 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, SIRFUART_RX_MODE_IO);
440 wr_regl(port, SIRFUART_LINE_CTRL, config_reg);
442 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
443 if (baud_rate < 1000000)
447 temp = port->line == 1 ? 16 : 64;
448 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp / threshold_div);
449 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp / threshold_div);
450 temp_reg_val |= SIRFUART_TX_FIFO_START;
451 wr_regl(port, SIRFUART_TX_FIFO_OP, temp_reg_val);
452 uart_update_timeout(port, termios->c_cflag, baud_rate);
453 sirfsoc_uart_start_rx(port);
454 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_TX_EN | SIRFUART_RX_EN);
455 spin_unlock_irqrestore(&port->lock, flags);
458 static void startup_uart_controller(struct uart_port *port)
460 unsigned long temp_regv;
462 temp_regv = rd_regl(port, SIRFUART_TX_DMA_IO_CTRL);
463 wr_regl(port, SIRFUART_TX_DMA_IO_CTRL, temp_regv | SIRFUART_TX_MODE_IO);
464 temp_regv = rd_regl(port, SIRFUART_RX_DMA_IO_CTRL);
465 wr_regl(port, SIRFUART_RX_DMA_IO_CTRL, temp_regv | SIRFUART_RX_MODE_IO);
466 wr_regl(port, SIRFUART_TX_DMA_IO_LEN, 0);
467 wr_regl(port, SIRFUART_RX_DMA_IO_LEN, 0);
468 wr_regl(port, SIRFUART_TX_RX_EN, SIRFUART_RX_EN | SIRFUART_TX_EN);
469 wr_regl(port, SIRFUART_TX_FIFO_OP, SIRFUART_TX_FIFO_RESET);
470 wr_regl(port, SIRFUART_TX_FIFO_OP, 0);
471 wr_regl(port, SIRFUART_RX_FIFO_OP, SIRFUART_RX_FIFO_RESET);
472 wr_regl(port, SIRFUART_RX_FIFO_OP, 0);
473 temp = port->line == 1 ? 16 : 64;
474 wr_regl(port, SIRFUART_TX_FIFO_CTRL, temp);
475 wr_regl(port, SIRFUART_RX_FIFO_CTRL, temp);
478 static int sirfsoc_uart_startup(struct uart_port *port)
480 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
481 unsigned int index = port->line;
483 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
484 ret = request_irq(port->irq,
490 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
494 startup_uart_controller(port);
495 enable_irq(port->irq);
500 static void sirfsoc_uart_shutdown(struct uart_port *port)
502 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
503 wr_regl(port, SIRFUART_INT_EN, 0);
504 free_irq(port->irq, sirfport);
505 if (sirfport->ms_enabled) {
506 sirfsoc_uart_disable_ms(port);
507 sirfport->ms_enabled = 0;
511 static const char *sirfsoc_uart_type(struct uart_port *port)
513 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
516 static int sirfsoc_uart_request_port(struct uart_port *port)
519 ret = request_mem_region(port->mapbase,
520 SIRFUART_MAP_SIZE, SIRFUART_PORT_NAME);
521 return ret ? 0 : -EBUSY;
524 static void sirfsoc_uart_release_port(struct uart_port *port)
526 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
529 static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
531 if (flags & UART_CONFIG_TYPE) {
532 port->type = SIRFSOC_PORT_TYPE;
533 sirfsoc_uart_request_port(port);
537 static struct uart_ops sirfsoc_uart_ops = {
538 .tx_empty = sirfsoc_uart_tx_empty,
539 .get_mctrl = sirfsoc_uart_get_mctrl,
540 .set_mctrl = sirfsoc_uart_set_mctrl,
541 .stop_tx = sirfsoc_uart_stop_tx,
542 .start_tx = sirfsoc_uart_start_tx,
543 .stop_rx = sirfsoc_uart_stop_rx,
544 .enable_ms = sirfsoc_uart_enable_ms,
545 .break_ctl = sirfsoc_uart_break_ctl,
546 .startup = sirfsoc_uart_startup,
547 .shutdown = sirfsoc_uart_shutdown,
548 .set_termios = sirfsoc_uart_set_termios,
549 .type = sirfsoc_uart_type,
550 .release_port = sirfsoc_uart_release_port,
551 .request_port = sirfsoc_uart_request_port,
552 .config_port = sirfsoc_uart_config_port,
555 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
556 static int __init sirfsoc_uart_console_setup(struct console *co, char *options)
558 unsigned int baud = 115200;
559 unsigned int bits = 8;
560 unsigned int parity = 'n';
561 unsigned int flow = 'n';
562 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
564 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
571 uart_parse_options(options, &baud, &parity, &bits, &flow);
573 return uart_set_options(port, co, baud, parity, bits, flow);
576 static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
579 SIRFUART_TX_FIFO_STATUS) & SIRFUART_FIFOFULL_MASK(port))
581 wr_regb(port, SIRFUART_TX_FIFO_DATA, ch);
584 static void sirfsoc_uart_console_write(struct console *co, const char *s,
587 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
588 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
591 static struct console sirfsoc_uart_console = {
592 .name = SIRFSOC_UART_NAME,
593 .device = uart_console_device,
594 .flags = CON_PRINTBUFFER,
596 .write = sirfsoc_uart_console_write,
597 .setup = sirfsoc_uart_console_setup,
598 .data = &sirfsoc_uart_drv,
601 static int __init sirfsoc_uart_console_init(void)
603 register_console(&sirfsoc_uart_console);
606 console_initcall(sirfsoc_uart_console_init);
609 static struct uart_driver sirfsoc_uart_drv = {
610 .owner = THIS_MODULE,
611 .driver_name = SIRFUART_PORT_NAME,
612 .nr = SIRFSOC_UART_NR,
613 .dev_name = SIRFSOC_UART_NAME,
614 .major = SIRFSOC_UART_MAJOR,
615 .minor = SIRFSOC_UART_MINOR,
616 #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
617 .cons = &sirfsoc_uart_console,
623 int sirfsoc_uart_probe(struct platform_device *pdev)
625 struct sirfsoc_uart_port *sirfport;
626 struct uart_port *port;
627 struct resource *res;
630 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
632 "Unable to find cell-index in uart node.\n");
637 sirfport = &sirfsoc_uart_ports[pdev->id];
638 port = &sirfport->port;
639 port->dev = &pdev->dev;
640 port->private_data = sirfport;
642 if (of_find_property(pdev->dev.of_node, "hw_flow_ctrl", NULL))
643 sirfport->hw_flow_ctrl = 1;
645 if (of_property_read_u32(pdev->dev.of_node,
649 "Unable to find fifosize in uart node.\n");
654 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
656 dev_err(&pdev->dev, "Insufficient resources.\n");
660 port->mapbase = res->start;
661 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
662 if (!port->membase) {
663 dev_err(&pdev->dev, "Cannot remap resource.\n");
667 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
669 dev_err(&pdev->dev, "Insufficient resources.\n");
673 port->irq = res->start;
675 if (sirfport->hw_flow_ctrl) {
676 sirfport->p = pinctrl_get_select_default(&pdev->dev);
677 ret = IS_ERR(sirfport->p);
682 port->ops = &sirfsoc_uart_ops;
683 spin_lock_init(&port->lock);
685 platform_set_drvdata(pdev, sirfport);
686 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
688 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
695 platform_set_drvdata(pdev, NULL);
696 if (sirfport->hw_flow_ctrl)
697 pinctrl_put(sirfport->p);
702 static int sirfsoc_uart_remove(struct platform_device *pdev)
704 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
705 struct uart_port *port = &sirfport->port;
706 platform_set_drvdata(pdev, NULL);
707 if (sirfport->hw_flow_ctrl)
708 pinctrl_put(sirfport->p);
709 uart_remove_one_port(&sirfsoc_uart_drv, port);
714 sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
716 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
717 struct uart_port *port = &sirfport->port;
718 uart_suspend_port(&sirfsoc_uart_drv, port);
722 static int sirfsoc_uart_resume(struct platform_device *pdev)
724 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
725 struct uart_port *port = &sirfport->port;
726 uart_resume_port(&sirfsoc_uart_drv, port);
730 static struct of_device_id sirfsoc_uart_ids[] = {
731 { .compatible = "sirf,prima2-uart", },
734 MODULE_DEVICE_TABLE(of, sirfsoc_serial_of_match);
736 static struct platform_driver sirfsoc_uart_driver = {
737 .probe = sirfsoc_uart_probe,
738 .remove = sirfsoc_uart_remove,
739 .suspend = sirfsoc_uart_suspend,
740 .resume = sirfsoc_uart_resume,
742 .name = SIRFUART_PORT_NAME,
743 .owner = THIS_MODULE,
744 .of_match_table = sirfsoc_uart_ids,
748 static int __init sirfsoc_uart_init(void)
752 ret = uart_register_driver(&sirfsoc_uart_drv);
756 ret = platform_driver_register(&sirfsoc_uart_driver);
758 uart_unregister_driver(&sirfsoc_uart_drv);
762 module_init(sirfsoc_uart_init);
764 static void __exit sirfsoc_uart_exit(void)
766 platform_driver_unregister(&sirfsoc_uart_driver);
767 uart_unregister_driver(&sirfsoc_uart_drv);
769 module_exit(sirfsoc_uart_exit);
771 MODULE_LICENSE("GPL v2");
772 MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
773 MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");