1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/major.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/ioport.h>
27 #include <linux/circ_buf.h>
28 #include <linux/serial.h>
29 #include <linux/sysrq.h>
30 #include <linux/console.h>
31 #include <linux/spinlock.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/init.h>
35 #include <linux/of_device.h>
40 #include <asm/setup.h>
42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
46 #include <linux/serial_core.h>
47 #include <linux/sunserialcore.h>
51 struct uart_sunsab_port {
52 struct uart_port port; /* Generic UART port */
53 union sab82532_async_regs __iomem *regs; /* Chip registers */
54 unsigned long irqflags; /* IRQ state flags */
55 int dsr; /* Current DSR state */
56 unsigned int cec_timeout; /* Chip poll timeout... */
57 unsigned int tec_timeout; /* likewise */
58 unsigned char interrupt_mask0;/* ISR0 masking */
59 unsigned char interrupt_mask1;/* ISR1 masking */
60 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
61 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
62 unsigned int gis_shift;
63 int type; /* SAB82532 version */
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
77 * This assumes you have a 29.4912 MHz clock for your UART.
79 #define SAB_BASE_BAUD ( 29491200 / 16 )
81 static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89 #define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
91 #define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92 #define SAB82532_XMIT_FIFO_SIZE 32
94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
96 int timeout = up->tec_timeout;
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
104 int timeout = up->cec_timeout;
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
110 static struct tty_port *
111 receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat)
114 struct tty_port *port = NULL;
115 unsigned char buf[32];
116 int saw_console_brk = 0;
121 if (up->port.state != NULL) /* Unopened serial console */
122 port = &up->port.state->port;
124 /* Read number of BYTES (Character + Status) available. */
125 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126 count = SAB82532_RECV_FIFO_SIZE;
130 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
135 /* Issue a FIFO read command in case we where idle. */
136 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
138 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
142 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
146 for (i = 0; i < count; i++)
147 buf[i] = readb(&up->regs->r.rfifo[i]);
149 /* Issue Receive Message Complete command. */
152 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
155 /* Count may be zero for BRK, so we check for it here */
156 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157 (up->port.line == up->port.cons->index))
160 for (i = 0; i < count; i++) {
161 unsigned char ch = buf[i], flag;
164 up->port.icount.rx++;
166 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
168 SAB82532_ISR0_RFO)) ||
169 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
171 * For statistics only
173 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
174 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
176 up->port.icount.brk++;
178 * We do the SysRQ and SAK checking
179 * here because otherwise the break
180 * may get masked by ignore_status_mask
181 * or read_status_mask.
183 if (uart_handle_break(&up->port))
185 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
186 up->port.icount.parity++;
187 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
188 up->port.icount.frame++;
189 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
190 up->port.icount.overrun++;
193 * Mask off conditions which should be ingored.
195 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
196 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
198 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
200 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
202 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
206 if (uart_handle_sysrq_char(&up->port, ch) || !port)
209 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
210 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
211 tty_insert_flip_char(port, ch, flag);
212 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
213 tty_insert_flip_char(port, 0, TTY_OVERRUN);
222 static void sunsab_stop_tx(struct uart_port *);
223 static void sunsab_tx_idle(struct uart_sunsab_port *);
225 static void transmit_chars(struct uart_sunsab_port *up,
226 union sab82532_irq_status *stat)
228 struct circ_buf *xmit = &up->port.state->xmit;
231 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
232 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
233 writeb(up->interrupt_mask1, &up->regs->w.imr1);
234 set_bit(SAB82532_ALLS, &up->irqflags);
237 #if 0 /* bde@nwlink.com says this check causes problems */
238 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
242 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
245 set_bit(SAB82532_XPR, &up->irqflags);
248 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
249 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
250 writeb(up->interrupt_mask1, &up->regs->w.imr1);
254 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
255 writeb(up->interrupt_mask1, &up->regs->w.imr1);
256 clear_bit(SAB82532_ALLS, &up->irqflags);
258 /* Stuff 32 bytes into Transmit FIFO. */
259 clear_bit(SAB82532_XPR, &up->irqflags);
260 for (i = 0; i < up->port.fifosize; i++) {
261 writeb(xmit->buf[xmit->tail],
262 &up->regs->w.xfifo[i]);
263 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
264 up->port.icount.tx++;
265 if (uart_circ_empty(xmit))
269 /* Issue a Transmit Frame command. */
271 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
273 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(&up->port);
276 if (uart_circ_empty(xmit))
277 sunsab_stop_tx(&up->port);
280 static void check_status(struct uart_sunsab_port *up,
281 union sab82532_irq_status *stat)
283 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
284 uart_handle_dcd_change(&up->port,
285 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
287 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
288 uart_handle_cts_change(&up->port,
289 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
291 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
292 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
293 up->port.icount.dsr++;
296 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
299 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
301 struct uart_sunsab_port *up = dev_id;
302 struct tty_port *port = NULL;
303 union sab82532_irq_status status;
307 spin_lock_irqsave(&up->port.lock, flags);
310 gis = readb(&up->regs->r.gis) >> up->gis_shift;
312 status.sreg.isr0 = readb(&up->regs->r.isr0);
314 status.sreg.isr1 = readb(&up->regs->r.isr1);
317 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
318 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
319 (status.sreg.isr1 & SAB82532_ISR1_BRK))
320 port = receive_chars(up, &status);
321 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
322 (status.sreg.isr1 & SAB82532_ISR1_CSC))
323 check_status(up, &status);
324 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
325 transmit_chars(up, &status);
328 spin_unlock_irqrestore(&up->port.lock, flags);
331 tty_flip_buffer_push(port);
336 /* port->lock is not held. */
337 static unsigned int sunsab_tx_empty(struct uart_port *port)
339 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
342 /* Do not need a lock for a state test like this. */
343 if (test_bit(SAB82532_ALLS, &up->irqflags))
351 /* port->lock held by caller. */
352 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
354 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
356 if (mctrl & TIOCM_RTS) {
357 up->cached_mode &= ~SAB82532_MODE_FRTS;
358 up->cached_mode |= SAB82532_MODE_RTS;
360 up->cached_mode |= (SAB82532_MODE_FRTS |
363 if (mctrl & TIOCM_DTR) {
364 up->cached_pvr &= ~(up->pvr_dtr_bit);
366 up->cached_pvr |= up->pvr_dtr_bit;
369 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
370 if (test_bit(SAB82532_XPR, &up->irqflags))
374 /* port->lock is held by caller and interrupts are disabled. */
375 static unsigned int sunsab_get_mctrl(struct uart_port *port)
377 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
383 val = readb(&up->regs->r.pvr);
384 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
386 val = readb(&up->regs->r.vstr);
387 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
389 val = readb(&up->regs->r.star);
390 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
395 /* port->lock held by caller. */
396 static void sunsab_stop_tx(struct uart_port *port)
398 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
400 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
401 writeb(up->interrupt_mask1, &up->regs->w.imr1);
404 /* port->lock held by caller. */
405 static void sunsab_tx_idle(struct uart_sunsab_port *up)
407 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
410 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
411 writeb(up->cached_mode, &up->regs->rw.mode);
412 writeb(up->cached_pvr, &up->regs->rw.pvr);
413 writeb(up->cached_dafo, &up->regs->w.dafo);
415 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
416 tmp = readb(&up->regs->rw.ccr2);
418 tmp |= (up->cached_ebrg >> 2) & 0xc0;
419 writeb(tmp, &up->regs->rw.ccr2);
423 /* port->lock held by caller. */
424 static void sunsab_start_tx(struct uart_port *port)
426 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
427 struct circ_buf *xmit = &up->port.state->xmit;
430 if (uart_circ_empty(xmit))
433 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
434 writeb(up->interrupt_mask1, &up->regs->w.imr1);
436 if (!test_bit(SAB82532_XPR, &up->irqflags))
439 clear_bit(SAB82532_ALLS, &up->irqflags);
440 clear_bit(SAB82532_XPR, &up->irqflags);
442 for (i = 0; i < up->port.fifosize; i++) {
443 writeb(xmit->buf[xmit->tail],
444 &up->regs->w.xfifo[i]);
445 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
446 up->port.icount.tx++;
447 if (uart_circ_empty(xmit))
451 /* Issue a Transmit Frame command. */
453 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
456 /* port->lock is not held. */
457 static void sunsab_send_xchar(struct uart_port *port, char ch)
459 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
462 spin_lock_irqsave(&up->port.lock, flags);
465 writeb(ch, &up->regs->w.tic);
467 spin_unlock_irqrestore(&up->port.lock, flags);
470 /* port->lock held by caller. */
471 static void sunsab_stop_rx(struct uart_port *port)
473 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
475 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
476 writeb(up->interrupt_mask1, &up->regs->w.imr0);
479 /* port->lock held by caller. */
480 static void sunsab_enable_ms(struct uart_port *port)
482 /* For now we always receive these interrupts. */
485 /* port->lock is not held. */
486 static void sunsab_break_ctl(struct uart_port *port, int break_state)
488 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
492 spin_lock_irqsave(&up->port.lock, flags);
494 val = up->cached_dafo;
496 val |= SAB82532_DAFO_XBRK;
498 val &= ~SAB82532_DAFO_XBRK;
499 up->cached_dafo = val;
501 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
502 if (test_bit(SAB82532_XPR, &up->irqflags))
505 spin_unlock_irqrestore(&up->port.lock, flags);
508 /* port->lock is not held. */
509 static int sunsab_startup(struct uart_port *port)
511 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
514 int err = request_irq(up->port.irq, sunsab_interrupt,
515 IRQF_SHARED, "sab", up);
519 spin_lock_irqsave(&up->port.lock, flags);
522 * Wait for any commands or immediate characters
528 * Clear the FIFO buffers.
530 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
532 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
535 * Clear the interrupt registers.
537 (void) readb(&up->regs->r.isr0);
538 (void) readb(&up->regs->r.isr1);
541 * Now, initialize the UART
543 writeb(0, &up->regs->w.ccr0); /* power-down */
544 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
545 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
546 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
547 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
548 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
549 writeb(0, &up->regs->w.ccr3);
550 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
551 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
553 writeb(up->cached_mode, &up->regs->w.mode);
554 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
556 tmp = readb(&up->regs->rw.ccr0);
557 tmp |= SAB82532_CCR0_PU; /* power-up */
558 writeb(tmp, &up->regs->rw.ccr0);
561 * Finally, enable interrupts
563 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
565 writeb(up->interrupt_mask0, &up->regs->w.imr0);
566 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
567 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
568 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
570 writeb(up->interrupt_mask1, &up->regs->w.imr1);
571 set_bit(SAB82532_ALLS, &up->irqflags);
572 set_bit(SAB82532_XPR, &up->irqflags);
574 spin_unlock_irqrestore(&up->port.lock, flags);
579 /* port->lock is not held. */
580 static void sunsab_shutdown(struct uart_port *port)
582 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
585 spin_lock_irqsave(&up->port.lock, flags);
587 /* Disable Interrupts */
588 up->interrupt_mask0 = 0xff;
589 writeb(up->interrupt_mask0, &up->regs->w.imr0);
590 up->interrupt_mask1 = 0xff;
591 writeb(up->interrupt_mask1, &up->regs->w.imr1);
593 /* Disable break condition */
594 up->cached_dafo = readb(&up->regs->rw.dafo);
595 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
596 writeb(up->cached_dafo, &up->regs->rw.dafo);
598 /* Disable Receiver */
599 up->cached_mode &= ~SAB82532_MODE_RAC;
600 writeb(up->cached_mode, &up->regs->rw.mode);
605 * If the chip is powered down here the system hangs/crashes during
606 * reboot or shutdown. This needs to be investigated further,
607 * similar behaviour occurs in 2.4 when the driver is configured
608 * as a module only. One hint may be that data is sometimes
609 * transmitted at 9600 baud during shutdown (regardless of the
610 * speed the chip was configured for when the port was open).
614 tmp = readb(&up->regs->rw.ccr0);
615 tmp &= ~SAB82532_CCR0_PU;
616 writeb(tmp, &up->regs->rw.ccr0);
619 spin_unlock_irqrestore(&up->port.lock, flags);
620 free_irq(up->port.irq, up);
624 * This is used to figure out the divisor speeds.
626 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
628 * with 0 <= N < 64 and 0 <= M < 16
631 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
642 * We scale numbers by 10 so that we get better accuracy
643 * without having to use floating point. Here we increment m
644 * until n is within the valid range.
646 n = (SAB_BASE_BAUD * 10) / baud;
654 * We try very hard to avoid speeds with M == 0 since they may
655 * not work correctly for XTAL frequences above 10 MHz.
657 if ((m == 0) && ((n & 1) == 0)) {
665 /* Internal routine, port->lock is held and local interrupts are disabled. */
666 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
667 unsigned int iflag, unsigned int baud,
673 /* Byte size and parity */
674 switch (cflag & CSIZE) {
675 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
676 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
677 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
678 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
679 /* Never happens, but GCC is too dumb to figure it out */
680 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
683 if (cflag & CSTOPB) {
684 dafo |= SAB82532_DAFO_STOP;
688 if (cflag & PARENB) {
689 dafo |= SAB82532_DAFO_PARE;
693 if (cflag & PARODD) {
694 dafo |= SAB82532_DAFO_PAR_ODD;
696 dafo |= SAB82532_DAFO_PAR_EVEN;
698 up->cached_dafo = dafo;
700 calc_ebrg(baud, &n, &m);
702 up->cached_ebrg = n | (m << 6);
704 up->tec_timeout = (10 * 1000000) / baud;
705 up->cec_timeout = up->tec_timeout >> 2;
707 /* CTS flow control flags */
708 /* We encode read_status_mask and ignore_status_mask like so:
710 * ---------------------
711 * | ... | ISR1 | ISR0 |
712 * ---------------------
716 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
717 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
719 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
721 SAB82532_ISR1_XPR) << 8;
723 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
725 if (iflag & (IGNBRK | BRKINT | PARMRK))
726 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
729 * Characteres to ignore
731 up->port.ignore_status_mask = 0;
733 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
735 if (iflag & IGNBRK) {
736 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
738 * If we're ignoring parity and break indicators,
739 * ignore overruns too (for real raw support).
742 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
746 * ignore all characters if CREAD is not set
748 if ((cflag & CREAD) == 0)
749 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
752 uart_update_timeout(&up->port, cflag,
753 (up->port.uartclk / (16 * quot)));
755 /* Now schedule a register update when the chip's
756 * transmitter is idle.
758 up->cached_mode |= SAB82532_MODE_RAC;
759 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
760 if (test_bit(SAB82532_XPR, &up->irqflags))
764 /* port->lock is not held. */
765 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
766 struct ktermios *old)
768 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
770 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
771 unsigned int quot = uart_get_divisor(port, baud);
773 spin_lock_irqsave(&up->port.lock, flags);
774 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
775 spin_unlock_irqrestore(&up->port.lock, flags);
778 static const char *sunsab_type(struct uart_port *port)
780 struct uart_sunsab_port *up = (void *)port;
783 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
787 static void sunsab_release_port(struct uart_port *port)
791 static int sunsab_request_port(struct uart_port *port)
796 static void sunsab_config_port(struct uart_port *port, int flags)
800 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
805 static struct uart_ops sunsab_pops = {
806 .tx_empty = sunsab_tx_empty,
807 .set_mctrl = sunsab_set_mctrl,
808 .get_mctrl = sunsab_get_mctrl,
809 .stop_tx = sunsab_stop_tx,
810 .start_tx = sunsab_start_tx,
811 .send_xchar = sunsab_send_xchar,
812 .stop_rx = sunsab_stop_rx,
813 .enable_ms = sunsab_enable_ms,
814 .break_ctl = sunsab_break_ctl,
815 .startup = sunsab_startup,
816 .shutdown = sunsab_shutdown,
817 .set_termios = sunsab_set_termios,
819 .release_port = sunsab_release_port,
820 .request_port = sunsab_request_port,
821 .config_port = sunsab_config_port,
822 .verify_port = sunsab_verify_port,
825 static struct uart_driver sunsab_reg = {
826 .owner = THIS_MODULE,
827 .driver_name = "sunsab",
832 static struct uart_sunsab_port *sunsab_ports;
834 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
836 static void sunsab_console_putchar(struct uart_port *port, int c)
838 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
841 writeb(c, &up->regs->w.tic);
844 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
846 struct uart_sunsab_port *up = &sunsab_ports[con->index];
850 if (up->port.sysrq || oops_in_progress)
851 locked = spin_trylock_irqsave(&up->port.lock, flags);
853 spin_lock_irqsave(&up->port.lock, flags);
855 uart_console_write(&up->port, s, n, sunsab_console_putchar);
859 spin_unlock_irqrestore(&up->port.lock, flags);
862 static int sunsab_console_setup(struct console *con, char *options)
864 struct uart_sunsab_port *up = &sunsab_ports[con->index];
866 unsigned int baud, quot;
869 * The console framework calls us for each and every port
870 * registered. Defer the console setup until the requested
871 * port has been properly discovered. A bit of a hack,
874 if (up->port.type != PORT_SUNSAB)
877 printk("Console: ttyS%d (SAB82532)\n",
878 (sunsab_reg.minor - 64) + con->index);
880 sunserial_console_termios(con, up->port.dev->of_node);
882 switch (con->cflag & CBAUD) {
883 case B150: baud = 150; break;
884 case B300: baud = 300; break;
885 case B600: baud = 600; break;
886 case B1200: baud = 1200; break;
887 case B2400: baud = 2400; break;
888 case B4800: baud = 4800; break;
889 default: case B9600: baud = 9600; break;
890 case B19200: baud = 19200; break;
891 case B38400: baud = 38400; break;
892 case B57600: baud = 57600; break;
893 case B115200: baud = 115200; break;
894 case B230400: baud = 230400; break;
895 case B460800: baud = 460800; break;
901 spin_lock_init(&up->port.lock);
904 * Initialize the hardware
906 sunsab_startup(&up->port);
908 spin_lock_irqsave(&up->port.lock, flags);
911 * Finally, enable interrupts
913 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
914 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
915 writeb(up->interrupt_mask0, &up->regs->w.imr0);
916 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
917 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
918 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
920 writeb(up->interrupt_mask1, &up->regs->w.imr1);
922 quot = uart_get_divisor(&up->port, baud);
923 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
924 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
926 spin_unlock_irqrestore(&up->port.lock, flags);
931 static struct console sunsab_console = {
933 .write = sunsab_console_write,
934 .device = uart_console_device,
935 .setup = sunsab_console_setup,
936 .flags = CON_PRINTBUFFER,
941 static inline struct console *SUNSAB_CONSOLE(void)
943 return &sunsab_console;
946 #define SUNSAB_CONSOLE() (NULL)
947 #define sunsab_console_init() do { } while (0)
950 static int sunsab_init_one(struct uart_sunsab_port *up,
951 struct platform_device *op,
952 unsigned long offset,
955 up->port.line = line;
956 up->port.dev = &op->dev;
958 up->port.mapbase = op->resource[0].start + offset;
959 up->port.membase = of_ioremap(&op->resource[0], offset,
960 sizeof(union sab82532_async_regs),
962 if (!up->port.membase)
964 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
966 up->port.irq = op->archdata.irqs[0];
968 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
969 up->port.iotype = UPIO_MEM;
971 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
973 up->port.ops = &sunsab_pops;
974 up->port.type = PORT_SUNSAB;
975 up->port.uartclk = SAB_BASE_BAUD;
977 up->type = readb(&up->regs->r.vstr) & 0x0f;
978 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
979 writeb(0xff, &up->regs->w.pim);
980 if ((up->port.line & 0x1) == 0) {
981 up->pvr_dsr_bit = (1 << 0);
982 up->pvr_dtr_bit = (1 << 1);
985 up->pvr_dsr_bit = (1 << 3);
986 up->pvr_dtr_bit = (1 << 2);
989 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
990 writeb(up->cached_pvr, &up->regs->w.pvr);
991 up->cached_mode = readb(&up->regs->rw.mode);
992 up->cached_mode |= SAB82532_MODE_FRTS;
993 writeb(up->cached_mode, &up->regs->rw.mode);
994 up->cached_mode |= SAB82532_MODE_RTS;
995 writeb(up->cached_mode, &up->regs->rw.mode);
997 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
998 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1003 static int sab_probe(struct platform_device *op)
1006 struct uart_sunsab_port *up;
1009 up = &sunsab_ports[inst * 2];
1011 err = sunsab_init_one(&up[0], op,
1017 err = sunsab_init_one(&up[1], op,
1018 sizeof(union sab82532_async_regs),
1023 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1024 &sunsab_reg, up[0].port.line,
1027 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1028 &sunsab_reg, up[1].port.line,
1031 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1035 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1039 platform_set_drvdata(op, &up[0]);
1046 uart_remove_one_port(&sunsab_reg, &up[0].port);
1048 of_iounmap(&op->resource[0],
1050 sizeof(union sab82532_async_regs));
1052 of_iounmap(&op->resource[0],
1054 sizeof(union sab82532_async_regs));
1059 static int sab_remove(struct platform_device *op)
1061 struct uart_sunsab_port *up = platform_get_drvdata(op);
1063 uart_remove_one_port(&sunsab_reg, &up[1].port);
1064 uart_remove_one_port(&sunsab_reg, &up[0].port);
1065 of_iounmap(&op->resource[0],
1067 sizeof(union sab82532_async_regs));
1068 of_iounmap(&op->resource[0],
1070 sizeof(union sab82532_async_regs));
1075 static const struct of_device_id sab_match[] = {
1081 .compatible = "sab82532",
1085 MODULE_DEVICE_TABLE(of, sab_match);
1087 static struct platform_driver sab_driver = {
1090 .owner = THIS_MODULE,
1091 .of_match_table = sab_match,
1094 .remove = sab_remove,
1097 static int __init sunsab_init(void)
1099 struct device_node *dp;
1101 int num_channels = 0;
1103 for_each_node_by_name(dp, "se")
1105 for_each_node_by_name(dp, "serial") {
1106 if (of_device_is_compatible(dp, "sab82532"))
1111 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1112 num_channels, GFP_KERNEL);
1116 err = sunserial_register_minors(&sunsab_reg, num_channels);
1118 kfree(sunsab_ports);
1119 sunsab_ports = NULL;
1125 return platform_driver_register(&sab_driver);
1128 static void __exit sunsab_exit(void)
1130 platform_driver_unregister(&sab_driver);
1131 if (sunsab_reg.nr) {
1132 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1135 kfree(sunsab_ports);
1136 sunsab_ports = NULL;
1139 module_init(sunsab_init);
1140 module_exit(sunsab_exit);
1142 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1143 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1144 MODULE_LICENSE("GPL");