drivers/tty/serial/sunsab.c

   1 /* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
   2  *
   3  * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
   4  * Copyright (C) 2002, 2006  David S. Miller (davem@davemloft.net)
   5  *
   6  * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
   7  *   Maxim Krasnyanskiy <maxk@qualcomm.com>
   8  *
   9  * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
  10  * rates to be programmed into the UART.  Also eliminated a lot of
  11  * duplicated code in the console setup.
  12  *   Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
  13  *
  14  * Ported to new 2.5.x UART layer.
  15  *   David S. Miller <davem@davemloft.net>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/major.h>
  24 #include <linux/string.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/ioport.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/init.h>
  35 #include <linux/of_device.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/irq.h>
  39 #include <asm/prom.h>
  40 #include <asm/setup.h>
  41
  42 #if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  43 #define SUPPORT_SYSRQ
  44 #endif
  45
  46 #include <linux/serial_core.h>
  47 #include <linux/sunserialcore.h>
  48
  49 #include "sunsab.h"
  50
  51 struct uart_sunsab_port {
  52         struct uart_port                port;           /* Generic UART port    */
  53         union sab82532_async_regs       __iomem *regs;  /* Chip registers       */
  54         unsigned long                   irqflags;       /* IRQ state flags      */
  55         int                             dsr;            /* Current DSR state    */
  56         unsigned int                    cec_timeout;    /* Chip poll timeout... */
  57         unsigned int                    tec_timeout;    /* likewise             */
  58         unsigned char                   interrupt_mask0;/* ISR0 masking         */
  59         unsigned char                   interrupt_mask1;/* ISR1 masking         */
  60         unsigned char                   pvr_dtr_bit;    /* Which PVR bit is DTR */
  61         unsigned char                   pvr_dsr_bit;    /* Which PVR bit is DSR */
  62         unsigned int                    gis_shift;
  63         int                             type;           /* SAB82532 version     */
  64
  65         /* Setting configuration bits while the transmitter is active
  66          * can cause garbage characters to get emitted by the chip.
  67          * Therefore, we cache such writes here and do the real register
  68          * write the next time the transmitter becomes idle.
  69          */
  70         unsigned int                    cached_ebrg;
  71         unsigned char                   cached_mode;
  72         unsigned char                   cached_pvr;
  73         unsigned char                   cached_dafo;
  74 };
  75
  76 /*
  77  * This assumes you have a 29.4912 MHz clock for your UART.
  78  */
  79 #define SAB_BASE_BAUD ( 29491200 / 16 )
  80
  81 static char *sab82532_version[16] = {
  82         "V1.0", "V2.0", "V3.2", "V(0x03)",
  83         "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
  84         "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
  85         "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
  86 };
  87
  88 #define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
  89 #define SAB82532_MAX_CEC_TIMEOUT  50000 /* 2.5 TX CLKs (at 50 baud) */
  90
  91 #define SAB82532_RECV_FIFO_SIZE 32      /* Standard async fifo sizes */
  92 #define SAB82532_XMIT_FIFO_SIZE 32
  93
  94 static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
  95 {
  96         int timeout = up->tec_timeout;
  97
  98         while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
  99                 udelay(1);
 100 }
 101
 102 static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
 103 {
 104         int timeout = up->cec_timeout;
 105
 106         while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
 107                 udelay(1);
 108 }
 109
 110 static struct tty_port *
 111 receive_chars(struct uart_sunsab_port *up,
 112               union sab82532_irq_status *stat)
 113 {
 114         struct tty_port *port = NULL;
 115         unsigned char buf[32];
 116         int saw_console_brk = 0;
 117         int free_fifo = 0;
 118         int count = 0;
 119         int i;
 120
 121         if (up->port.state != NULL)             /* Unopened serial console */
 122                 port = &up->port.state->port;
 123
 124         /* Read number of BYTES (Character + Status) available. */
 125         if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
 126                 count = SAB82532_RECV_FIFO_SIZE;
 127                 free_fifo++;
 128         }
 129
 130         if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
 131                 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
 132                 free_fifo++;
 133         }
 134
 135         /* Issue a FIFO read command in case we where idle. */
 136         if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
 137                 sunsab_cec_wait(up);
 138                 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
 139                 return port;
 140         }
 141
 142         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 143                 free_fifo++;
 144
 145         /* Read the FIFO. */
 146         for (i = 0; i < count; i++)
 147                 buf[i] = readb(&up->regs->r.rfifo[i]);
 148
 149         /* Issue Receive Message Complete command. */
 150         if (free_fifo) {
 151                 sunsab_cec_wait(up);
 152                 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
 153         }
 154
 155         /* Count may be zero for BRK, so we check for it here */
 156         if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
 157             (up->port.line == up->port.cons->index))
 158                 saw_console_brk = 1;
 159
 160         for (i = 0; i < count; i++) {
 161                 unsigned char ch = buf[i], flag;
 162
 163                 flag = TTY_NORMAL;
 164                 up->port.icount.rx++;
 165
 166                 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
 167                                                 SAB82532_ISR0_FERR |
 168                                                 SAB82532_ISR0_RFO)) ||
 169                     unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
 170                         /*
 171                          * For statistics only
 172                          */
 173                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 174                                 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
 175                                                      SAB82532_ISR0_FERR);
 176                                 up->port.icount.brk++;
 177                                 /*
 178                                  * We do the SysRQ and SAK checking
 179                                  * here because otherwise the break
 180                                  * may get masked by ignore_status_mask
 181                                  * or read_status_mask.
 182                                  */
 183                                 if (uart_handle_break(&up->port))
 184                                         continue;
 185                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 186                                 up->port.icount.parity++;
 187                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 188                                 up->port.icount.frame++;
 189                         if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 190                                 up->port.icount.overrun++;
 191
 192                         /*
 193                          * Mask off conditions which should be ingored.
 194                          */
 195                         stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
 196                         stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
 197
 198                         if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
 199                                 flag = TTY_BREAK;
 200                         } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
 201                                 flag = TTY_PARITY;
 202                         else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
 203                                 flag = TTY_FRAME;
 204                 }
 205
 206                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
 207                         continue;
 208
 209                 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
 210                     (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
 211                         tty_insert_flip_char(port, ch, flag);
 212                 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
 213                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
 214         }
 215
 216         if (saw_console_brk)
 217                 sun_do_break();
 218
 219         return port;
 220 }
 221
 222 static void sunsab_stop_tx(struct uart_port *);
 223 static void sunsab_tx_idle(struct uart_sunsab_port *);
 224
 225 static void transmit_chars(struct uart_sunsab_port *up,
 226                            union sab82532_irq_status *stat)
 227 {
 228         struct circ_buf *xmit = &up->port.state->xmit;
 229         int i;
 230
 231         if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
 232                 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
 233                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 234                 set_bit(SAB82532_ALLS, &up->irqflags);
 235         }
 236
 237 #if 0 /* bde@nwlink.com says this check causes problems */
 238         if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
 239                 return;
 240 #endif
 241
 242         if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
 243                 return;
 244
 245         set_bit(SAB82532_XPR, &up->irqflags);
 246         sunsab_tx_idle(up);
 247
 248         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 249                 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 250                 writeb(up->interrupt_mask1, &up->regs->w.imr1);
 251                 return;
 252         }
 253
 254         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 255         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 256         clear_bit(SAB82532_ALLS, &up->irqflags);
 257
 258         /* Stuff 32 bytes into Transmit FIFO. */
 259         clear_bit(SAB82532_XPR, &up->irqflags);
 260         for (i = 0; i < up->port.fifosize; i++) {
 261                 writeb(xmit->buf[xmit->tail],
 262                        &up->regs->w.xfifo[i]);
 263                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 264                 up->port.icount.tx++;
 265                 if (uart_circ_empty(xmit))
 266                         break;
 267         }
 268
 269         /* Issue a Transmit Frame command. */
 270         sunsab_cec_wait(up);
 271         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 272
 273         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 274                 uart_write_wakeup(&up->port);
 275
 276         if (uart_circ_empty(xmit))
 277                 sunsab_stop_tx(&up->port);
 278 }
 279
 280 static void check_status(struct uart_sunsab_port *up,
 281                          union sab82532_irq_status *stat)
 282 {
 283         if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
 284                 uart_handle_dcd_change(&up->port,
 285                                        !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
 286
 287         if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
 288                 uart_handle_cts_change(&up->port,
 289                                        (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
 290
 291         if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
 292                 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
 293                 up->port.icount.dsr++;
 294         }
 295
 296         wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 297 }
 298
 299 static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
 300 {
 301         struct uart_sunsab_port *up = dev_id;
 302         struct tty_port *port = NULL;
 303         union sab82532_irq_status status;
 304         unsigned long flags;
 305         unsigned char gis;
 306
 307         spin_lock_irqsave(&up->port.lock, flags);
 308
 309         status.stat = 0;
 310         gis = readb(&up->regs->r.gis) >> up->gis_shift;
 311         if (gis & 1)
 312                 status.sreg.isr0 = readb(&up->regs->r.isr0);
 313         if (gis & 2)
 314                 status.sreg.isr1 = readb(&up->regs->r.isr1);
 315
 316         if (status.stat) {
 317                 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 318                                          SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
 319                     (status.sreg.isr1 & SAB82532_ISR1_BRK))
 320                         port = receive_chars(up, &status);
 321                 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
 322                     (status.sreg.isr1 & SAB82532_ISR1_CSC))
 323                         check_status(up, &status);
 324                 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
 325                         transmit_chars(up, &status);
 326         }
 327
 328         spin_unlock_irqrestore(&up->port.lock, flags);
 329
 330         if (port)
 331                 tty_flip_buffer_push(port);
 332
 333         return IRQ_HANDLED;
 334 }
 335
 336 /* port->lock is not held.  */
 337 static unsigned int sunsab_tx_empty(struct uart_port *port)
 338 {
 339         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 340         int ret;
 341
 342         /* Do not need a lock for a state test like this.  */
 343         if (test_bit(SAB82532_ALLS, &up->irqflags))
 344                 ret = TIOCSER_TEMT;
 345         else
 346                 ret = 0;
 347
 348         return ret;
 349 }
 350
 351 /* port->lock held by caller.  */
 352 static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
 353 {
 354         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 355
 356         if (mctrl & TIOCM_RTS) {
 357                 up->cached_mode &= ~SAB82532_MODE_FRTS;
 358                 up->cached_mode |= SAB82532_MODE_RTS;
 359         } else {
 360                 up->cached_mode |= (SAB82532_MODE_FRTS |
 361                                     SAB82532_MODE_RTS);
 362         }
 363         if (mctrl & TIOCM_DTR) {
 364                 up->cached_pvr &= ~(up->pvr_dtr_bit);
 365         } else {
 366                 up->cached_pvr |= up->pvr_dtr_bit;
 367         }
 368
 369         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 370         if (test_bit(SAB82532_XPR, &up->irqflags))
 371                 sunsab_tx_idle(up);
 372 }
 373
 374 /* port->lock is held by caller and interrupts are disabled.  */
 375 static unsigned int sunsab_get_mctrl(struct uart_port *port)
 376 {
 377         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 378         unsigned char val;
 379         unsigned int result;
 380
 381         result = 0;
 382
 383         val = readb(&up->regs->r.pvr);
 384         result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
 385
 386         val = readb(&up->regs->r.vstr);
 387         result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
 388
 389         val = readb(&up->regs->r.star);
 390         result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
 391
 392         return result;
 393 }
 394
 395 /* port->lock held by caller.  */
 396 static void sunsab_stop_tx(struct uart_port *port)
 397 {
 398         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 399
 400         up->interrupt_mask1 |= SAB82532_IMR1_XPR;
 401         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 402 }
 403
 404 /* port->lock held by caller.  */
 405 static void sunsab_tx_idle(struct uart_sunsab_port *up)
 406 {
 407         if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
 408                 u8 tmp;
 409
 410                 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
 411                 writeb(up->cached_mode, &up->regs->rw.mode);
 412                 writeb(up->cached_pvr, &up->regs->rw.pvr);
 413                 writeb(up->cached_dafo, &up->regs->w.dafo);
 414
 415                 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
 416                 tmp = readb(&up->regs->rw.ccr2);
 417                 tmp &= ~0xc0;
 418                 tmp |= (up->cached_ebrg >> 2) & 0xc0;
 419                 writeb(tmp, &up->regs->rw.ccr2);
 420         }
 421 }
 422
 423 /* port->lock held by caller.  */
 424 static void sunsab_start_tx(struct uart_port *port)
 425 {
 426         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 427         struct circ_buf *xmit = &up->port.state->xmit;
 428         int i;
 429
 430         if (uart_circ_empty(xmit))
 431                 return;
 432
 433         up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
 434         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 435
 436         if (!test_bit(SAB82532_XPR, &up->irqflags))
 437                 return;
 438
 439         clear_bit(SAB82532_ALLS, &up->irqflags);
 440         clear_bit(SAB82532_XPR, &up->irqflags);
 441
 442         for (i = 0; i < up->port.fifosize; i++) {
 443                 writeb(xmit->buf[xmit->tail],
 444                        &up->regs->w.xfifo[i]);
 445                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 446                 up->port.icount.tx++;
 447                 if (uart_circ_empty(xmit))
 448                         break;
 449         }
 450
 451         /* Issue a Transmit Frame command.  */
 452         sunsab_cec_wait(up);
 453         writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
 454 }
 455
 456 /* port->lock is not held.  */
 457 static void sunsab_send_xchar(struct uart_port *port, char ch)
 458 {
 459         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 460         unsigned long flags;
 461
 462         spin_lock_irqsave(&up->port.lock, flags);
 463
 464         sunsab_tec_wait(up);
 465         writeb(ch, &up->regs->w.tic);
 466
 467         spin_unlock_irqrestore(&up->port.lock, flags);
 468 }
 469
 470 /* port->lock held by caller.  */
 471 static void sunsab_stop_rx(struct uart_port *port)
 472 {
 473         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 474
 475         up->interrupt_mask0 |= SAB82532_IMR0_TCD;
 476         writeb(up->interrupt_mask1, &up->regs->w.imr0);
 477 }
 478
 479 /* port->lock is not held.  */
 480 static void sunsab_break_ctl(struct uart_port *port, int break_state)
 481 {
 482         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 483         unsigned long flags;
 484         unsigned char val;
 485
 486         spin_lock_irqsave(&up->port.lock, flags);
 487
 488         val = up->cached_dafo;
 489         if (break_state)
 490                 val |= SAB82532_DAFO_XBRK;
 491         else
 492                 val &= ~SAB82532_DAFO_XBRK;
 493         up->cached_dafo = val;
 494
 495         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 496         if (test_bit(SAB82532_XPR, &up->irqflags))
 497                 sunsab_tx_idle(up);
 498
 499         spin_unlock_irqrestore(&up->port.lock, flags);
 500 }
 501
 502 /* port->lock is not held.  */
 503 static int sunsab_startup(struct uart_port *port)
 504 {
 505         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 506         unsigned long flags;
 507         unsigned char tmp;
 508         int err = request_irq(up->port.irq, sunsab_interrupt,
 509                               IRQF_SHARED, "sab", up);
 510         if (err)
 511                 return err;
 512
 513         spin_lock_irqsave(&up->port.lock, flags);
 514
 515         /*
 516          * Wait for any commands or immediate characters
 517          */
 518         sunsab_cec_wait(up);
 519         sunsab_tec_wait(up);
 520
 521         /*
 522          * Clear the FIFO buffers.
 523          */
 524         writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
 525         sunsab_cec_wait(up);
 526         writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
 527
 528         /*
 529          * Clear the interrupt registers.
 530          */
 531         (void) readb(&up->regs->r.isr0);
 532         (void) readb(&up->regs->r.isr1);
 533
 534         /*
 535          * Now, initialize the UART
 536          */
 537         writeb(0, &up->regs->w.ccr0);                           /* power-down */
 538         writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
 539                SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
 540         writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
 541         writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
 542                SAB82532_CCR2_TOE, &up->regs->w.ccr2);
 543         writeb(0, &up->regs->w.ccr3);
 544         writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
 545         up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
 546                            SAB82532_MODE_RAC);
 547         writeb(up->cached_mode, &up->regs->w.mode);
 548         writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
 549
 550         tmp = readb(&up->regs->rw.ccr0);
 551         tmp |= SAB82532_CCR0_PU;        /* power-up */
 552         writeb(tmp, &up->regs->rw.ccr0);
 553
 554         /*
 555          * Finally, enable interrupts
 556          */
 557         up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 558                                SAB82532_IMR0_PLLA);
 559         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 560         up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 561                                SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 562                                SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 563                                SAB82532_IMR1_XPR);
 564         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 565         set_bit(SAB82532_ALLS, &up->irqflags);
 566         set_bit(SAB82532_XPR, &up->irqflags);
 567
 568         spin_unlock_irqrestore(&up->port.lock, flags);
 569
 570         return 0;
 571 }
 572
 573 /* port->lock is not held.  */
 574 static void sunsab_shutdown(struct uart_port *port)
 575 {
 576         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 577         unsigned long flags;
 578
 579         spin_lock_irqsave(&up->port.lock, flags);
 580
 581         /* Disable Interrupts */
 582         up->interrupt_mask0 = 0xff;
 583         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 584         up->interrupt_mask1 = 0xff;
 585         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 586
 587         /* Disable break condition */
 588         up->cached_dafo = readb(&up->regs->rw.dafo);
 589         up->cached_dafo &= ~SAB82532_DAFO_XBRK;
 590         writeb(up->cached_dafo, &up->regs->rw.dafo);
 591
 592         /* Disable Receiver */
 593         up->cached_mode &= ~SAB82532_MODE_RAC;
 594         writeb(up->cached_mode, &up->regs->rw.mode);
 595
 596         /*
 597          * XXX FIXME
 598          *
 599          * If the chip is powered down here the system hangs/crashes during
 600          * reboot or shutdown.  This needs to be investigated further,
 601          * similar behaviour occurs in 2.4 when the driver is configured
 602          * as a module only.  One hint may be that data is sometimes
 603          * transmitted at 9600 baud during shutdown (regardless of the
 604          * speed the chip was configured for when the port was open).
 605          */
 606 #if 0
 607         /* Power Down */
 608         tmp = readb(&up->regs->rw.ccr0);
 609         tmp &= ~SAB82532_CCR0_PU;
 610         writeb(tmp, &up->regs->rw.ccr0);
 611 #endif
 612
 613         spin_unlock_irqrestore(&up->port.lock, flags);
 614         free_irq(up->port.irq, up);
 615 }
 616
 617 /*
 618  * This is used to figure out the divisor speeds.
 619  *
 620  * The formula is:    Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
 621  *
 622  * with               0 <= N < 64 and 0 <= M < 16
 623  */
 624
 625 static void calc_ebrg(int baud, int *n_ret, int *m_ret)
 626 {
 627         int     n, m;
 628
 629         if (baud == 0) {
 630                 *n_ret = 0;
 631                 *m_ret = 0;
 632                 return;
 633         }
 634
 635         /*
 636          * We scale numbers by 10 so that we get better accuracy
 637          * without having to use floating point.  Here we increment m
 638          * until n is within the valid range.
 639          */
 640         n = (SAB_BASE_BAUD * 10) / baud;
 641         m = 0;
 642         while (n >= 640) {
 643                 n = n / 2;
 644                 m++;
 645         }
 646         n = (n+5) / 10;
 647         /*
 648          * We try very hard to avoid speeds with M == 0 since they may
 649          * not work correctly for XTAL frequences above 10 MHz.
 650          */
 651         if ((m == 0) && ((n & 1) == 0)) {
 652                 n = n / 2;
 653                 m++;
 654         }
 655         *n_ret = n - 1;
 656         *m_ret = m;
 657 }
 658
 659 /* Internal routine, port->lock is held and local interrupts are disabled.  */
 660 static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
 661                                   unsigned int iflag, unsigned int baud,
 662                                   unsigned int quot)
 663 {
 664         unsigned char dafo;
 665         int bits, n, m;
 666
 667         /* Byte size and parity */
 668         switch (cflag & CSIZE) {
 669               case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 670               case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
 671               case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
 672               case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
 673               /* Never happens, but GCC is too dumb to figure it out */
 674               default:  dafo = SAB82532_DAFO_CHL5; bits = 7; break;
 675         }
 676
 677         if (cflag & CSTOPB) {
 678                 dafo |= SAB82532_DAFO_STOP;
 679                 bits++;
 680         }
 681
 682         if (cflag & PARENB) {
 683                 dafo |= SAB82532_DAFO_PARE;
 684                 bits++;
 685         }
 686
 687         if (cflag & PARODD) {
 688                 dafo |= SAB82532_DAFO_PAR_ODD;
 689         } else {
 690                 dafo |= SAB82532_DAFO_PAR_EVEN;
 691         }
 692         up->cached_dafo = dafo;
 693
 694         calc_ebrg(baud, &n, &m);
 695
 696         up->cached_ebrg = n | (m << 6);
 697
 698         up->tec_timeout = (10 * 1000000) / baud;
 699         up->cec_timeout = up->tec_timeout >> 2;
 700
 701         /* CTS flow control flags */
 702         /* We encode read_status_mask and ignore_status_mask like so:
 703          *
 704          * ---------------------
 705          * | ... | ISR1 | ISR0 |
 706          * ---------------------
 707          *  ..    15   8 7    0
 708          */
 709
 710         up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
 711                                      SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
 712                                      SAB82532_ISR0_CDSC);
 713         up->port.read_status_mask |= (SAB82532_ISR1_CSC |
 714                                       SAB82532_ISR1_ALLS |
 715                                       SAB82532_ISR1_XPR) << 8;
 716         if (iflag & INPCK)
 717                 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
 718                                               SAB82532_ISR0_FERR);
 719         if (iflag & (IGNBRK | BRKINT | PARMRK))
 720                 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
 721
 722         /*
 723          * Characteres to ignore
 724          */
 725         up->port.ignore_status_mask = 0;
 726         if (iflag & IGNPAR)
 727                 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
 728                                                 SAB82532_ISR0_FERR);
 729         if (iflag & IGNBRK) {
 730                 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
 731                 /*
 732                  * If we're ignoring parity and break indicators,
 733                  * ignore overruns too (for real raw support).
 734                  */
 735                 if (iflag & IGNPAR)
 736                         up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
 737         }
 738
 739         /*
 740          * ignore all characters if CREAD is not set
 741          */
 742         if ((cflag & CREAD) == 0)
 743                 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
 744                                                 SAB82532_ISR0_TCD);
 745
 746         uart_update_timeout(&up->port, cflag,
 747                             (up->port.uartclk / (16 * quot)));
 748
 749         /* Now schedule a register update when the chip's
 750          * transmitter is idle.
 751          */
 752         up->cached_mode |= SAB82532_MODE_RAC;
 753         set_bit(SAB82532_REGS_PENDING, &up->irqflags);
 754         if (test_bit(SAB82532_XPR, &up->irqflags))
 755                 sunsab_tx_idle(up);
 756 }
 757
 758 /* port->lock is not held.  */
 759 static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
 760                                struct ktermios *old)
 761 {
 762         struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
 763         unsigned long flags;
 764         unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
 765         unsigned int quot = uart_get_divisor(port, baud);
 766
 767         spin_lock_irqsave(&up->port.lock, flags);
 768         sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
 769         spin_unlock_irqrestore(&up->port.lock, flags);
 770 }
 771
 772 static const char *sunsab_type(struct uart_port *port)
 773 {
 774         struct uart_sunsab_port *up = (void *)port;
 775         static char buf[36];
 776
 777         sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
 778         return buf;
 779 }
 780
 781 static void sunsab_release_port(struct uart_port *port)
 782 {
 783 }
 784
 785 static int sunsab_request_port(struct uart_port *port)
 786 {
 787         return 0;
 788 }
 789
 790 static void sunsab_config_port(struct uart_port *port, int flags)
 791 {
 792 }
 793
 794 static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
 795 {
 796         return -EINVAL;
 797 }
 798
 799 static struct uart_ops sunsab_pops = {
 800         .tx_empty       = sunsab_tx_empty,
 801         .set_mctrl      = sunsab_set_mctrl,
 802         .get_mctrl      = sunsab_get_mctrl,
 803         .stop_tx        = sunsab_stop_tx,
 804         .start_tx       = sunsab_start_tx,
 805         .send_xchar     = sunsab_send_xchar,
 806         .stop_rx        = sunsab_stop_rx,
 807         .break_ctl      = sunsab_break_ctl,
 808         .startup        = sunsab_startup,
 809         .shutdown       = sunsab_shutdown,
 810         .set_termios    = sunsab_set_termios,
 811         .type           = sunsab_type,
 812         .release_port   = sunsab_release_port,
 813         .request_port   = sunsab_request_port,
 814         .config_port    = sunsab_config_port,
 815         .verify_port    = sunsab_verify_port,
 816 };
 817
 818 static struct uart_driver sunsab_reg = {
 819         .owner                  = THIS_MODULE,
 820         .driver_name            = "sunsab",
 821         .dev_name               = "ttyS",
 822         .major                  = TTY_MAJOR,
 823 };
 824
 825 static struct uart_sunsab_port *sunsab_ports;
 826
 827 #ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
 828
 829 static void sunsab_console_putchar(struct uart_port *port, int c)
 830 {
 831         struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
 832
 833         sunsab_tec_wait(up);
 834         writeb(c, &up->regs->w.tic);
 835 }
 836
 837 static void sunsab_console_write(struct console *con, const char *s, unsigned n)
 838 {
 839         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 840         unsigned long flags;
 841         int locked = 1;
 842
 843         if (up->port.sysrq || oops_in_progress)
 844                 locked = spin_trylock_irqsave(&up->port.lock, flags);
 845         else
 846                 spin_lock_irqsave(&up->port.lock, flags);
 847
 848         uart_console_write(&up->port, s, n, sunsab_console_putchar);
 849         sunsab_tec_wait(up);
 850
 851         if (locked)
 852                 spin_unlock_irqrestore(&up->port.lock, flags);
 853 }
 854
 855 static int sunsab_console_setup(struct console *con, char *options)
 856 {
 857         struct uart_sunsab_port *up = &sunsab_ports[con->index];
 858         unsigned long flags;
 859         unsigned int baud, quot;
 860
 861         /*
 862          * The console framework calls us for each and every port
 863          * registered. Defer the console setup until the requested
 864          * port has been properly discovered. A bit of a hack,
 865          * though...
 866          */
 867         if (up->port.type != PORT_SUNSAB)
 868                 return -1;
 869
 870         printk("Console: ttyS%d (SAB82532)\n",
 871                (sunsab_reg.minor - 64) + con->index);
 872
 873         sunserial_console_termios(con, up->port.dev->of_node);
 874
 875         switch (con->cflag & CBAUD) {
 876         case B150: baud = 150; break;
 877         case B300: baud = 300; break;
 878         case B600: baud = 600; break;
 879         case B1200: baud = 1200; break;
 880         case B2400: baud = 2400; break;
 881         case B4800: baud = 4800; break;
 882         default: case B9600: baud = 9600; break;
 883         case B19200: baud = 19200; break;
 884         case B38400: baud = 38400; break;
 885         case B57600: baud = 57600; break;
 886         case B115200: baud = 115200; break;
 887         case B230400: baud = 230400; break;
 888         case B460800: baud = 460800; break;
 889         }
 890
 891         /*
 892          * Temporary fix.
 893          */
 894         spin_lock_init(&up->port.lock);
 895
 896         /*
 897          * Initialize the hardware
 898          */
 899         sunsab_startup(&up->port);
 900
 901         spin_lock_irqsave(&up->port.lock, flags);
 902
 903         /*
 904          * Finally, enable interrupts
 905          */
 906         up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
 907                                 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
 908         writeb(up->interrupt_mask0, &up->regs->w.imr0);
 909         up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
 910                                 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
 911                                 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
 912                                 SAB82532_IMR1_XPR;
 913         writeb(up->interrupt_mask1, &up->regs->w.imr1);
 914
 915         quot = uart_get_divisor(&up->port, baud);
 916         sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
 917         sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
 918
 919         spin_unlock_irqrestore(&up->port.lock, flags);
 920
 921         return 0;
 922 }
 923
 924 static struct console sunsab_console = {
 925         .name   =       "ttyS",
 926         .write  =       sunsab_console_write,
 927         .device =       uart_console_device,
 928         .setup  =       sunsab_console_setup,
 929         .flags  =       CON_PRINTBUFFER,
 930         .index  =       -1,
 931         .data   =       &sunsab_reg,
 932 };
 933
 934 static inline struct console *SUNSAB_CONSOLE(void)
 935 {
 936         return &sunsab_console;
 937 }
 938 #else
 939 #define SUNSAB_CONSOLE()        (NULL)
 940 #define sunsab_console_init()   do { } while (0)
 941 #endif
 942
 943 static int sunsab_init_one(struct uart_sunsab_port *up,
 944                                      struct platform_device *op,
 945                                      unsigned long offset,
 946                                      int line)
 947 {
 948         up->port.line = line;
 949         up->port.dev = &op->dev;
 950
 951         up->port.mapbase = op->resource[0].start + offset;
 952         up->port.membase = of_ioremap(&op->resource[0], offset,
 953                                       sizeof(union sab82532_async_regs),
 954                                       "sab");
 955         if (!up->port.membase)
 956                 return -ENOMEM;
 957         up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
 958
 959         up->port.irq = op->archdata.irqs[0];
 960
 961         up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
 962         up->port.iotype = UPIO_MEM;
 963
 964         writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
 965
 966         up->port.ops = &sunsab_pops;
 967         up->port.type = PORT_SUNSAB;
 968         up->port.uartclk = SAB_BASE_BAUD;
 969
 970         up->type = readb(&up->regs->r.vstr) & 0x0f;
 971         writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
 972         writeb(0xff, &up->regs->w.pim);
 973         if ((up->port.line & 0x1) == 0) {
 974                 up->pvr_dsr_bit = (1 << 0);
 975                 up->pvr_dtr_bit = (1 << 1);
 976                 up->gis_shift = 2;
 977         } else {
 978                 up->pvr_dsr_bit = (1 << 3);
 979                 up->pvr_dtr_bit = (1 << 2);
 980                 up->gis_shift = 0;
 981         }
 982         up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
 983         writeb(up->cached_pvr, &up->regs->w.pvr);
 984         up->cached_mode = readb(&up->regs->rw.mode);
 985         up->cached_mode |= SAB82532_MODE_FRTS;
 986         writeb(up->cached_mode, &up->regs->rw.mode);
 987         up->cached_mode |= SAB82532_MODE_RTS;
 988         writeb(up->cached_mode, &up->regs->rw.mode);
 989
 990         up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
 991         up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
 992
 993         return 0;
 994 }
 995
 996 static int sab_probe(struct platform_device *op)
 997 {
 998         static int inst;
 999         struct uart_sunsab_port *up;
1000         int err;
1001
1002         up = &sunsab_ports[inst * 2];
1003
1004         err = sunsab_init_one(&up[0], op,
1005                               0,
1006                               (inst * 2) + 0);
1007         if (err)
1008                 goto out;
1009
1010         err = sunsab_init_one(&up[1], op,
1011                               sizeof(union sab82532_async_regs),
1012                               (inst * 2) + 1);
1013         if (err)
1014                 goto out1;
1015
1016         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1017                                 &sunsab_reg, up[0].port.line,
1018                                 false);
1019
1020         sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1021                                 &sunsab_reg, up[1].port.line,
1022                                 false);
1023
1024         err = uart_add_one_port(&sunsab_reg, &up[0].port);
1025         if (err)
1026                 goto out2;
1027
1028         err = uart_add_one_port(&sunsab_reg, &up[1].port);
1029         if (err)
1030                 goto out3;
1031
1032         platform_set_drvdata(op, &up[0]);
1033
1034         inst++;
1035
1036         return 0;
1037
1038 out3:
1039         uart_remove_one_port(&sunsab_reg, &up[0].port);
1040 out2:
1041         of_iounmap(&op->resource[0],
1042                    up[1].port.membase,
1043                    sizeof(union sab82532_async_regs));
1044 out1:
1045         of_iounmap(&op->resource[0],
1046                    up[0].port.membase,
1047                    sizeof(union sab82532_async_regs));
1048 out:
1049         return err;
1050 }
1051
1052 static int sab_remove(struct platform_device *op)
1053 {
1054         struct uart_sunsab_port *up = platform_get_drvdata(op);
1055
1056         uart_remove_one_port(&sunsab_reg, &up[1].port);
1057         uart_remove_one_port(&sunsab_reg, &up[0].port);
1058         of_iounmap(&op->resource[0],
1059                    up[1].port.membase,
1060                    sizeof(union sab82532_async_regs));
1061         of_iounmap(&op->resource[0],
1062                    up[0].port.membase,
1063                    sizeof(union sab82532_async_regs));
1064
1065         return 0;
1066 }
1067
1068 static const struct of_device_id sab_match[] = {
1069         {
1070                 .name = "se",
1071         },
1072         {
1073                 .name = "serial",
1074                 .compatible = "sab82532",
1075         },
1076         {},
1077 };
1078 MODULE_DEVICE_TABLE(of, sab_match);
1079
1080 static struct platform_driver sab_driver = {
1081         .driver = {
1082                 .name = "sab",
1083                 .owner = THIS_MODULE,
1084                 .of_match_table = sab_match,
1085         },
1086         .probe          = sab_probe,
1087         .remove         = sab_remove,
1088 };
1089
1090 static int __init sunsab_init(void)
1091 {
1092         struct device_node *dp;
1093         int err;
1094         int num_channels = 0;
1095
1096         for_each_node_by_name(dp, "se")
1097                 num_channels += 2;
1098         for_each_node_by_name(dp, "serial") {
1099                 if (of_device_is_compatible(dp, "sab82532"))
1100                         num_channels += 2;
1101         }
1102
1103         if (num_channels) {
1104                 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1105                                        num_channels, GFP_KERNEL);
1106                 if (!sunsab_ports)
1107                         return -ENOMEM;
1108
1109                 err = sunserial_register_minors(&sunsab_reg, num_channels);
1110                 if (err) {
1111                         kfree(sunsab_ports);
1112                         sunsab_ports = NULL;
1113
1114                         return err;
1115                 }
1116         }
1117
1118         return platform_driver_register(&sab_driver);
1119 }
1120
1121 static void __exit sunsab_exit(void)
1122 {
1123         platform_driver_unregister(&sab_driver);
1124         if (sunsab_reg.nr) {
1125                 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1126         }
1127
1128         kfree(sunsab_ports);
1129         sunsab_ports = NULL;
1130 }
1131
1132 module_init(sunsab_init);
1133 module_exit(sunsab_exit);
1134
1135 MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1136 MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1137 MODULE_LICENSE("GPL");