2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
34 #define CDNS_UART_TTY_NAME "ttyPS"
35 #define CDNS_UART_NAME "xuartps"
36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38 #define CDNS_UART_NR_PORTS 2
39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40 #define CDNS_UART_REGISTER_SPACE 0xFFF
42 #define cdns_uart_readl(offset) ioread32(port->membase + offset)
43 #define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset)
45 /* Rx Trigger level */
46 static int rx_trigger_level = 56;
47 module_param(rx_trigger_level, uint, S_IRUGO);
48 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
51 static int rx_timeout = 10;
52 module_param(rx_timeout, uint, S_IRUGO);
53 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
55 /* Register offsets for the UART. */
56 #define CDNS_UART_CR_OFFSET 0x00 /* Control Register */
57 #define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */
58 #define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */
59 #define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */
60 #define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */
61 #define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */
62 #define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
63 #define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */
64 #define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
65 #define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */
66 #define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */
67 #define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */
68 #define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */
69 #define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
70 #define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */
71 #define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */
72 #define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
73 #define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
75 /* Control Register Bit Definitions */
76 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
77 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
78 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
79 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
80 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
81 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
82 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
83 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
84 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
88 * The mode register (MR) defines the mode of transfer as well as the data
89 * format. If this register is modified during transmission or reception,
90 * data validity cannot be guaranteed.
92 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
93 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
94 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
96 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
97 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
99 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
100 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
101 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
102 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
103 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
105 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
106 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
107 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
110 * Interrupt Registers:
111 * Interrupt control logic uses the interrupt enable register (IER) and the
112 * interrupt disable register (IDR) to set the value of the bits in the
113 * interrupt mask register (IMR). The IMR determines whether to pass an
114 * interrupt to the interrupt status register (ISR).
115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
116 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
117 * Reading either IER or IDR returns 0x00.
118 * All four registers have the same bit definitions.
120 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
121 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
122 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
123 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
124 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
125 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
126 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
127 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
128 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
129 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
130 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
132 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
133 #define CDNS_UART_IXR_BRK 0x80000000
136 * Modem Control register:
137 * The read/write Modem Control register controls the interface with the modem
138 * or data set, or a peripheral device emulating a modem.
140 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
141 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
142 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
145 * Channel Status Register:
146 * The channel status register (CSR) is provided to enable the control logic
147 * to monitor the status of bits in the channel interrupt status register,
148 * even if these are masked out by the interrupt mask register.
150 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
151 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
152 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
153 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
155 /* baud dividers min/max values */
156 #define CDNS_UART_BDIV_MIN 4
157 #define CDNS_UART_BDIV_MAX 255
158 #define CDNS_UART_CD_MAX 65535
161 * struct cdns_uart - device data
162 * @port: Pointer to the UART port
163 * @uartclk: Reference clock
165 * @baud: Current baud rate
166 * @clk_rate_change_nb: Notifier block for clock changes
169 struct uart_port *port;
173 struct notifier_block clk_rate_change_nb;
175 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
179 * cdns_uart_isr - Interrupt handler
181 * @dev_id: Id of the port
185 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
187 struct uart_port *port = (struct uart_port *)dev_id;
189 unsigned int isrstatus, numbytes;
191 char status = TTY_NORMAL;
193 spin_lock_irqsave(&port->lock, flags);
195 /* Read the interrupt status register to determine which
196 * interrupt(s) is/are active.
198 isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET);
201 * There is no hardware break detection, so we interpret framing
202 * error with all-zeros data as a break sequence. Most of the time,
203 * there's another non-zero byte at the end of the sequence.
205 if (isrstatus & CDNS_UART_IXR_FRAMING) {
206 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
207 CDNS_UART_SR_RXEMPTY)) {
208 if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) {
209 port->read_status_mask |= CDNS_UART_IXR_BRK;
210 isrstatus &= ~CDNS_UART_IXR_FRAMING;
213 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET);
216 /* drop byte with parity error if IGNPAR specified */
217 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
218 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
220 isrstatus &= port->read_status_mask;
221 isrstatus &= ~port->ignore_status_mask;
223 if ((isrstatus & CDNS_UART_IXR_TOUT) ||
224 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
225 /* Receive Timeout Interrupt */
226 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
227 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
228 data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
230 /* Non-NULL byte after BREAK is garbage (99%) */
231 if (data && (port->read_status_mask &
232 CDNS_UART_IXR_BRK)) {
233 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
235 if (uart_handle_break(port))
241 * uart_handle_sysrq_char() doesn't work if
242 * spinlocked, for some reason
245 spin_unlock(&port->lock);
246 if (uart_handle_sysrq_char(port,
247 (unsigned char)data)) {
248 spin_lock(&port->lock);
251 spin_lock(&port->lock);
257 if (isrstatus & CDNS_UART_IXR_PARITY) {
258 port->icount.parity++;
260 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
261 port->icount.frame++;
263 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
264 port->icount.overrun++;
267 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
270 spin_unlock(&port->lock);
271 tty_flip_buffer_push(&port->state->port);
272 spin_lock(&port->lock);
275 /* Dispatch an appropriate handler */
276 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
277 if (uart_circ_empty(&port->state->xmit)) {
278 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY,
279 CDNS_UART_IDR_OFFSET);
281 numbytes = port->fifosize;
282 /* Break if no more data available in the UART buffer */
284 if (uart_circ_empty(&port->state->xmit))
286 /* Get the data from the UART circular buffer
287 * and write it to the cdns_uart's TX_FIFO
291 port->state->xmit.buf[port->state->xmit.
292 tail], CDNS_UART_FIFO_OFFSET);
296 /* Adjust the tail of the UART buffer and wrap
297 * the buffer if it reaches limit.
299 port->state->xmit.tail =
300 (port->state->xmit.tail + 1) &
301 (UART_XMIT_SIZE - 1);
304 if (uart_circ_chars_pending(
305 &port->state->xmit) < WAKEUP_CHARS)
306 uart_write_wakeup(port);
310 cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET);
312 /* be sure to release the lock and tty before leaving */
313 spin_unlock_irqrestore(&port->lock, flags);
319 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
320 * @clk: UART module input clock
321 * @baud: Desired baud rate
322 * @rbdiv: BDIV value (return value)
323 * @rcd: CD value (return value)
324 * @div8: Value for clk_sel bit in mod (return value)
325 * Return: baud rate, requested baud when possible, or actual baud when there
326 * was too much error, zero if no valid divisors are found.
328 * Formula to obtain baud rate is
329 * baud_tx/rx rate = clk/CD * (BDIV + 1)
330 * input_clk = (Uart User Defined Clock or Apb Clock)
331 * depends on UCLKEN in MR Reg
332 * clk = input_clk or input_clk/8;
333 * depends on CLKS in MR reg
334 * CD and BDIV depends on values in
335 * baud rate generate register
336 * baud rate clock divisor register
338 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
339 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
342 unsigned int calc_baud;
343 unsigned int bestbaud = 0;
344 unsigned int bauderror;
345 unsigned int besterror = ~0;
347 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
354 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
355 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
356 if (cd < 1 || cd > CDNS_UART_CD_MAX)
359 calc_baud = clk / (cd * (bdiv + 1));
361 if (baud > calc_baud)
362 bauderror = baud - calc_baud;
364 bauderror = calc_baud - baud;
366 if (besterror > bauderror) {
369 bestbaud = calc_baud;
370 besterror = bauderror;
373 /* use the values when percent error is acceptable */
374 if (((besterror * 100) / baud) < 3)
381 * cdns_uart_set_baud_rate - Calculate and set the baud rate
382 * @port: Handle to the uart port structure
383 * @baud: Baud rate to set
384 * Return: baud rate, requested baud when possible, or actual baud when there
385 * was too much error, zero if no valid divisors are found.
387 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
390 unsigned int calc_baud;
391 u32 cd = 0, bdiv = 0;
394 struct cdns_uart *cdns_uart = port->private_data;
396 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
399 /* Write new divisors to hardware */
400 mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
402 mreg |= CDNS_UART_MR_CLKSEL;
404 mreg &= ~CDNS_UART_MR_CLKSEL;
405 cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET);
406 cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET);
407 cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET);
408 cdns_uart->baud = baud;
413 #ifdef CONFIG_COMMON_CLK
415 * cdns_uart_clk_notitifer_cb - Clock notifier callback
416 * @nb: Notifier block
417 * @event: Notify event
418 * @data: Notifier data
419 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
421 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
422 unsigned long event, void *data)
425 struct uart_port *port;
427 struct clk_notifier_data *ndata = data;
428 unsigned long flags = 0;
429 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
431 port = cdns_uart->port;
436 case PRE_RATE_CHANGE:
442 * Find out if current baud-rate can be achieved with new clock
445 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
446 &bdiv, &cd, &div8)) {
447 dev_warn(port->dev, "clock rate change rejected\n");
451 spin_lock_irqsave(&cdns_uart->port->lock, flags);
453 /* Disable the TX and RX to set baud rate */
454 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
455 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
456 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
458 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
462 case POST_RATE_CHANGE:
464 * Set clk dividers to generate correct baud with new clock
468 spin_lock_irqsave(&cdns_uart->port->lock, flags);
471 port->uartclk = ndata->new_rate;
473 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
476 case ABORT_RATE_CHANGE:
478 spin_lock_irqsave(&cdns_uart->port->lock, flags);
480 /* Set TX/RX Reset */
481 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
482 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
483 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
485 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
486 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
490 * Clear the RX disable and TX disable bits and then set the TX
491 * enable bit and RX enable bit to enable the transmitter and
494 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
495 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
496 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
497 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
498 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
500 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
510 * cdns_uart_start_tx - Start transmitting bytes
511 * @port: Handle to the uart port structure
513 static void cdns_uart_start_tx(struct uart_port *port)
515 unsigned int status, numbytes = port->fifosize;
517 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
520 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
521 /* Set the TX enable bit and clear the TX disable bit to enable the
524 cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
525 CDNS_UART_CR_OFFSET);
527 while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
528 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
529 /* Break if no more data available in the UART buffer */
530 if (uart_circ_empty(&port->state->xmit))
533 /* Get the data from the UART circular buffer and
534 * write it to the cdns_uart's TX_FIFO register.
537 port->state->xmit.buf[port->state->xmit.tail],
538 CDNS_UART_FIFO_OFFSET);
541 /* Adjust the tail of the UART buffer and wrap
542 * the buffer if it reaches limit.
544 port->state->xmit.tail = (port->state->xmit.tail + 1) &
545 (UART_XMIT_SIZE - 1);
547 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET);
548 /* Enable the TX Empty interrupt */
549 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET);
551 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
552 uart_write_wakeup(port);
556 * cdns_uart_stop_tx - Stop TX
557 * @port: Handle to the uart port structure
559 static void cdns_uart_stop_tx(struct uart_port *port)
563 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
564 regval |= CDNS_UART_CR_TX_DIS;
565 /* Disable the transmitter */
566 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
570 * cdns_uart_stop_rx - Stop RX
571 * @port: Handle to the uart port structure
573 static void cdns_uart_stop_rx(struct uart_port *port)
577 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
578 regval |= CDNS_UART_CR_RX_DIS;
579 /* Disable the receiver */
580 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
584 * cdns_uart_tx_empty - Check whether TX is empty
585 * @port: Handle to the uart port structure
587 * Return: TIOCSER_TEMT on success, 0 otherwise
589 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
593 status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY;
594 return status ? TIOCSER_TEMT : 0;
598 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
599 * transmitting char breaks
600 * @port: Handle to the uart port structure
601 * @ctl: Value based on which start or stop decision is taken
603 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
608 spin_lock_irqsave(&port->lock, flags);
610 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
613 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status,
614 CDNS_UART_CR_OFFSET);
616 if ((status & CDNS_UART_CR_STOPBRK) == 0)
617 cdns_uart_writel(CDNS_UART_CR_STOPBRK | status,
618 CDNS_UART_CR_OFFSET);
620 spin_unlock_irqrestore(&port->lock, flags);
624 * cdns_uart_set_termios - termios operations, handling data length, parity,
625 * stop bits, flow control, baud rate
626 * @port: Handle to the uart port structure
627 * @termios: Handle to the input termios structure
628 * @old: Values of the previously saved termios structure
630 static void cdns_uart_set_termios(struct uart_port *port,
631 struct ktermios *termios, struct ktermios *old)
633 unsigned int cval = 0;
634 unsigned int baud, minbaud, maxbaud;
636 unsigned int ctrl_reg, mode_reg;
638 spin_lock_irqsave(&port->lock, flags);
640 /* Empty the receive FIFO 1st before making changes */
641 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
642 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
643 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
646 /* Disable the TX and RX to set baud rate */
647 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
648 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
649 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
652 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
653 * min and max baud should be calculated here based on port->uartclk.
654 * this way we get a valid baud and can safely call set_baud()
656 minbaud = port->uartclk /
657 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
658 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
659 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
660 baud = cdns_uart_set_baud_rate(port, baud);
661 if (tty_termios_baud_rate(termios))
662 tty_termios_encode_baud_rate(termios, baud, baud);
664 /* Update the per-port timeout. */
665 uart_update_timeout(port, termios->c_cflag, baud);
667 /* Set TX/RX Reset */
668 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
669 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
670 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
673 * Clear the RX disable and TX disable bits and then set the TX enable
674 * bit and RX enable bit to enable the transmitter and receiver.
676 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
677 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
678 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
679 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
681 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
683 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
684 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
685 port->ignore_status_mask = 0;
687 if (termios->c_iflag & INPCK)
688 port->read_status_mask |= CDNS_UART_IXR_PARITY |
689 CDNS_UART_IXR_FRAMING;
691 if (termios->c_iflag & IGNPAR)
692 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
693 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
695 /* ignore all characters if CREAD is not set */
696 if ((termios->c_cflag & CREAD) == 0)
697 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
698 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
699 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
701 mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
703 /* Handling Data Size */
704 switch (termios->c_cflag & CSIZE) {
706 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
709 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
713 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
714 termios->c_cflag &= ~CSIZE;
715 termios->c_cflag |= CS8;
719 /* Handling Parity and Stop Bits length */
720 if (termios->c_cflag & CSTOPB)
721 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
723 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
725 if (termios->c_cflag & PARENB) {
726 /* Mark or Space parity */
727 if (termios->c_cflag & CMSPAR) {
728 if (termios->c_cflag & PARODD)
729 cval |= CDNS_UART_MR_PARITY_MARK;
731 cval |= CDNS_UART_MR_PARITY_SPACE;
733 if (termios->c_cflag & PARODD)
734 cval |= CDNS_UART_MR_PARITY_ODD;
736 cval |= CDNS_UART_MR_PARITY_EVEN;
739 cval |= CDNS_UART_MR_PARITY_NONE;
741 cval |= mode_reg & 1;
742 cdns_uart_writel(cval, CDNS_UART_MR_OFFSET);
744 spin_unlock_irqrestore(&port->lock, flags);
748 * cdns_uart_startup - Called when an application opens a cdns_uart port
749 * @port: Handle to the uart port structure
751 * Return: 0 on success, negative errno otherwise
753 static int cdns_uart_startup(struct uart_port *port)
755 unsigned int retval = 0, status = 0;
757 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
762 /* Disable the TX and RX */
763 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
764 CDNS_UART_CR_OFFSET);
766 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
769 cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
770 CDNS_UART_CR_OFFSET);
772 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
774 /* Clear the RX disable and TX disable bits and then set the TX enable
775 * bit and RX enable bit to enable the transmitter and receiver.
777 cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
778 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
779 CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET);
781 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
784 cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
785 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
786 CDNS_UART_MR_OFFSET);
789 * Set the RX FIFO Trigger level to use most of the FIFO, but it
790 * can be tuned with a module parameter
792 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
795 * Receive Timeout register is enabled but it
796 * can be tuned with a module parameter
798 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
800 /* Clear out any pending interrupts before enabling them */
801 cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET),
802 CDNS_UART_ISR_OFFSET);
804 /* Set the Interrupt Registers with desired interrupts */
805 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
806 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
807 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
808 CDNS_UART_IER_OFFSET);
814 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
815 * @port: Handle to the uart port structure
817 static void cdns_uart_shutdown(struct uart_port *port)
821 /* Disable interrupts */
822 status = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
823 cdns_uart_writel(status, CDNS_UART_IDR_OFFSET);
825 /* Disable the TX and RX */
826 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
827 CDNS_UART_CR_OFFSET);
828 free_irq(port->irq, port);
832 * cdns_uart_type - Set UART type to cdns_uart port
833 * @port: Handle to the uart port structure
835 * Return: string on success, NULL otherwise
837 static const char *cdns_uart_type(struct uart_port *port)
839 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
843 * cdns_uart_verify_port - Verify the port params
844 * @port: Handle to the uart port structure
845 * @ser: Handle to the structure whose members are compared
847 * Return: 0 on success, negative errno otherwise.
849 static int cdns_uart_verify_port(struct uart_port *port,
850 struct serial_struct *ser)
852 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
854 if (port->irq != ser->irq)
856 if (ser->io_type != UPIO_MEM)
858 if (port->iobase != ser->port)
866 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
867 * called when the driver adds a cdns_uart port via
868 * uart_add_one_port()
869 * @port: Handle to the uart port structure
871 * Return: 0 on success, negative errno otherwise.
873 static int cdns_uart_request_port(struct uart_port *port)
875 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
880 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
881 if (!port->membase) {
882 dev_err(port->dev, "Unable to map registers\n");
883 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
890 * cdns_uart_release_port - Release UART port
891 * @port: Handle to the uart port structure
893 * Release the memory region attached to a cdns_uart port. Called when the
894 * driver removes a cdns_uart port via uart_remove_one_port().
896 static void cdns_uart_release_port(struct uart_port *port)
898 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
899 iounmap(port->membase);
900 port->membase = NULL;
904 * cdns_uart_config_port - Configure UART port
905 * @port: Handle to the uart port structure
908 static void cdns_uart_config_port(struct uart_port *port, int flags)
910 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
911 port->type = PORT_XUARTPS;
915 * cdns_uart_get_mctrl - Get the modem control state
916 * @port: Handle to the uart port structure
918 * Return: the modem control state
920 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
922 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
925 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
929 val = cdns_uart_readl(CDNS_UART_MODEMCR_OFFSET);
931 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
933 if (mctrl & TIOCM_RTS)
934 val |= CDNS_UART_MODEMCR_RTS;
935 if (mctrl & TIOCM_DTR)
936 val |= CDNS_UART_MODEMCR_DTR;
938 cdns_uart_writel(val, CDNS_UART_MODEMCR_OFFSET);
941 #ifdef CONFIG_CONSOLE_POLL
942 static int cdns_uart_poll_get_char(struct uart_port *port)
947 /* Disable all interrupts */
948 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
949 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
951 /* Check if FIFO is empty */
952 if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
954 else /* Read a character */
955 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
957 /* Enable interrupts */
958 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
963 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
967 /* Disable all interrupts */
968 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
969 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
971 /* Wait until FIFO is empty */
972 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
975 /* Write a character */
976 cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET);
978 /* Wait until FIFO is empty */
979 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
982 /* Enable interrupts */
983 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
989 static struct uart_ops cdns_uart_ops = {
990 .set_mctrl = cdns_uart_set_mctrl,
991 .get_mctrl = cdns_uart_get_mctrl,
992 .start_tx = cdns_uart_start_tx,
993 .stop_tx = cdns_uart_stop_tx,
994 .stop_rx = cdns_uart_stop_rx,
995 .tx_empty = cdns_uart_tx_empty,
996 .break_ctl = cdns_uart_break_ctl,
997 .set_termios = cdns_uart_set_termios,
998 .startup = cdns_uart_startup,
999 .shutdown = cdns_uart_shutdown,
1000 .type = cdns_uart_type,
1001 .verify_port = cdns_uart_verify_port,
1002 .request_port = cdns_uart_request_port,
1003 .release_port = cdns_uart_release_port,
1004 .config_port = cdns_uart_config_port,
1005 #ifdef CONFIG_CONSOLE_POLL
1006 .poll_get_char = cdns_uart_poll_get_char,
1007 .poll_put_char = cdns_uart_poll_put_char,
1011 static struct uart_port cdns_uart_port[2];
1014 * cdns_uart_get_port - Configure the port from platform device resource info
1017 * Return: a pointer to a uart_port or NULL for failure
1019 static struct uart_port *cdns_uart_get_port(int id)
1021 struct uart_port *port;
1023 /* Try the given port id if failed use default method */
1024 if (cdns_uart_port[id].mapbase != 0) {
1025 /* Find the next unused port */
1026 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1027 if (cdns_uart_port[id].mapbase == 0)
1031 if (id >= CDNS_UART_NR_PORTS)
1034 port = &cdns_uart_port[id];
1036 /* At this point, we've got an empty uart_port struct, initialize it */
1037 spin_lock_init(&port->lock);
1038 port->membase = NULL;
1039 port->iobase = 1; /* mark port in use */
1041 port->type = PORT_UNKNOWN;
1042 port->iotype = UPIO_MEM32;
1043 port->flags = UPF_BOOT_AUTOCONF;
1044 port->ops = &cdns_uart_ops;
1045 port->fifosize = CDNS_UART_FIFO_SIZE;
1051 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1053 * cdns_uart_console_wait_tx - Wait for the TX to be full
1054 * @port: Handle to the uart port structure
1056 static void cdns_uart_console_wait_tx(struct uart_port *port)
1058 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)
1059 != CDNS_UART_SR_TXEMPTY)
1064 * cdns_uart_console_putchar - write the character to the FIFO buffer
1065 * @port: Handle to the uart port structure
1066 * @ch: Character to be written
1068 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1070 cdns_uart_console_wait_tx(port);
1071 cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET);
1074 static void cdns_early_write(struct console *con, const char *s, unsigned n)
1076 struct earlycon_device *dev = con->data;
1078 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1081 static int __init cdns_early_console_setup(struct earlycon_device *device,
1084 if (!device->port.membase)
1087 device->con->write = cdns_early_write;
1091 EARLYCON_DECLARE(cdns, cdns_early_console_setup);
1094 * cdns_uart_console_write - perform write operation
1095 * @co: Console handle
1096 * @s: Pointer to character array
1097 * @count: No of characters
1099 static void cdns_uart_console_write(struct console *co, const char *s,
1102 struct uart_port *port = &cdns_uart_port[co->index];
1103 unsigned long flags;
1104 unsigned int imr, ctrl;
1107 if (oops_in_progress)
1108 locked = spin_trylock_irqsave(&port->lock, flags);
1110 spin_lock_irqsave(&port->lock, flags);
1112 /* save and disable interrupt */
1113 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
1114 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
1117 * Make sure that the tx part is enabled. Set the TX enable bit and
1118 * clear the TX disable bit to enable the transmitter.
1120 ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1121 cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
1122 CDNS_UART_CR_OFFSET);
1124 uart_console_write(port, s, count, cdns_uart_console_putchar);
1125 cdns_uart_console_wait_tx(port);
1127 cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET);
1129 /* restore interrupt state */
1130 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
1133 spin_unlock_irqrestore(&port->lock, flags);
1137 * cdns_uart_console_setup - Initialize the uart to default config
1138 * @co: Console handle
1139 * @options: Initial settings of uart
1141 * Return: 0 on success, negative errno otherwise.
1143 static int __init cdns_uart_console_setup(struct console *co, char *options)
1145 struct uart_port *port = &cdns_uart_port[co->index];
1151 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1154 if (!port->mapbase) {
1155 pr_debug("console on ttyPS%i not present\n", co->index);
1160 uart_parse_options(options, &baud, &parity, &bits, &flow);
1162 return uart_set_options(port, co, baud, parity, bits, flow);
1165 static struct uart_driver cdns_uart_uart_driver;
1167 static struct console cdns_uart_console = {
1168 .name = CDNS_UART_TTY_NAME,
1169 .write = cdns_uart_console_write,
1170 .device = uart_console_device,
1171 .setup = cdns_uart_console_setup,
1172 .flags = CON_PRINTBUFFER,
1173 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1174 .data = &cdns_uart_uart_driver,
1178 * cdns_uart_console_init - Initialization call
1180 * Return: 0 on success, negative errno otherwise
1182 static int __init cdns_uart_console_init(void)
1184 register_console(&cdns_uart_console);
1188 console_initcall(cdns_uart_console_init);
1190 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1192 static struct uart_driver cdns_uart_uart_driver = {
1193 .owner = THIS_MODULE,
1194 .driver_name = CDNS_UART_NAME,
1195 .dev_name = CDNS_UART_TTY_NAME,
1196 .major = CDNS_UART_MAJOR,
1197 .minor = CDNS_UART_MINOR,
1198 .nr = CDNS_UART_NR_PORTS,
1199 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1200 .cons = &cdns_uart_console,
1204 #ifdef CONFIG_PM_SLEEP
1206 * cdns_uart_suspend - suspend event
1207 * @device: Pointer to the device structure
1211 static int cdns_uart_suspend(struct device *device)
1213 struct uart_port *port = dev_get_drvdata(device);
1214 struct tty_struct *tty;
1215 struct device *tty_dev;
1218 /* Get the tty which could be NULL so don't assume it's valid */
1219 tty = tty_port_tty_get(&port->state->port);
1222 may_wake = device_may_wakeup(tty_dev);
1227 * Call the API provided in serial_core.c file which handles
1230 uart_suspend_port(&cdns_uart_uart_driver, port);
1231 if (console_suspend_enabled && !may_wake) {
1232 struct cdns_uart *cdns_uart = port->private_data;
1234 clk_disable(cdns_uart->uartclk);
1235 clk_disable(cdns_uart->pclk);
1237 unsigned long flags = 0;
1239 spin_lock_irqsave(&port->lock, flags);
1240 /* Empty the receive FIFO 1st before making changes */
1241 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
1242 CDNS_UART_SR_RXEMPTY))
1243 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
1244 /* set RX trigger level to 1 */
1245 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET);
1246 /* disable RX timeout interrups */
1247 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET);
1248 spin_unlock_irqrestore(&port->lock, flags);
1255 * cdns_uart_resume - Resume after a previous suspend
1256 * @device: Pointer to the device structure
1260 static int cdns_uart_resume(struct device *device)
1262 struct uart_port *port = dev_get_drvdata(device);
1263 unsigned long flags = 0;
1265 struct tty_struct *tty;
1266 struct device *tty_dev;
1269 /* Get the tty which could be NULL so don't assume it's valid */
1270 tty = tty_port_tty_get(&port->state->port);
1273 may_wake = device_may_wakeup(tty_dev);
1277 if (console_suspend_enabled && !may_wake) {
1278 struct cdns_uart *cdns_uart = port->private_data;
1280 clk_enable(cdns_uart->pclk);
1281 clk_enable(cdns_uart->uartclk);
1283 spin_lock_irqsave(&port->lock, flags);
1285 /* Set TX/RX Reset */
1286 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1287 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1288 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1289 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
1290 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1293 /* restore rx timeout value */
1294 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
1296 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1297 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1298 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1299 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1301 spin_unlock_irqrestore(&port->lock, flags);
1303 spin_lock_irqsave(&port->lock, flags);
1304 /* restore original rx trigger level */
1305 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
1306 /* enable RX timeout interrupt */
1307 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
1308 spin_unlock_irqrestore(&port->lock, flags);
1311 return uart_resume_port(&cdns_uart_uart_driver, port);
1313 #endif /* ! CONFIG_PM_SLEEP */
1315 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1319 * cdns_uart_probe - Platform driver probe
1320 * @pdev: Pointer to the platform device structure
1322 * Return: 0 on success, negative errno otherwise
1324 static int cdns_uart_probe(struct platform_device *pdev)
1327 struct uart_port *port;
1328 struct resource *res, *res2;
1329 struct cdns_uart *cdns_uart_data;
1331 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1333 if (!cdns_uart_data)
1336 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1337 if (IS_ERR(cdns_uart_data->pclk)) {
1338 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1339 if (!IS_ERR(cdns_uart_data->pclk))
1340 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1342 if (IS_ERR(cdns_uart_data->pclk)) {
1343 dev_err(&pdev->dev, "pclk clock not found.\n");
1344 return PTR_ERR(cdns_uart_data->pclk);
1347 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1348 if (IS_ERR(cdns_uart_data->uartclk)) {
1349 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1350 if (!IS_ERR(cdns_uart_data->uartclk))
1351 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1353 if (IS_ERR(cdns_uart_data->uartclk)) {
1354 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1355 return PTR_ERR(cdns_uart_data->uartclk);
1358 rc = clk_prepare_enable(cdns_uart_data->pclk);
1360 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1363 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1365 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1366 goto err_out_clk_dis_pclk;
1369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372 goto err_out_clk_disable;
1375 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1378 goto err_out_clk_disable;
1381 #ifdef CONFIG_COMMON_CLK
1382 cdns_uart_data->clk_rate_change_nb.notifier_call =
1383 cdns_uart_clk_notifier_cb;
1384 if (clk_notifier_register(cdns_uart_data->uartclk,
1385 &cdns_uart_data->clk_rate_change_nb))
1386 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1388 /* Look for a serialN alias */
1389 id = of_alias_get_id(pdev->dev.of_node, "serial");
1393 /* Initialize the port structure */
1394 port = cdns_uart_get_port(id);
1397 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1399 goto err_out_notif_unreg;
1401 /* Register the port.
1402 * This function also registers this device with the tty layer
1403 * and triggers invocation of the config_port() entry point.
1405 port->mapbase = res->start;
1406 port->irq = res2->start;
1407 port->dev = &pdev->dev;
1408 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1409 port->private_data = cdns_uart_data;
1410 cdns_uart_data->port = port;
1411 platform_set_drvdata(pdev, port);
1412 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1415 "uart_add_one_port() failed; err=%i\n", rc);
1416 goto err_out_notif_unreg;
1421 err_out_notif_unreg:
1422 #ifdef CONFIG_COMMON_CLK
1423 clk_notifier_unregister(cdns_uart_data->uartclk,
1424 &cdns_uart_data->clk_rate_change_nb);
1426 err_out_clk_disable:
1427 clk_disable_unprepare(cdns_uart_data->uartclk);
1428 err_out_clk_dis_pclk:
1429 clk_disable_unprepare(cdns_uart_data->pclk);
1435 * cdns_uart_remove - called when the platform driver is unregistered
1436 * @pdev: Pointer to the platform device structure
1438 * Return: 0 on success, negative errno otherwise
1440 static int cdns_uart_remove(struct platform_device *pdev)
1442 struct uart_port *port = platform_get_drvdata(pdev);
1443 struct cdns_uart *cdns_uart_data = port->private_data;
1446 /* Remove the cdns_uart port from the serial core */
1447 #ifdef CONFIG_COMMON_CLK
1448 clk_notifier_unregister(cdns_uart_data->uartclk,
1449 &cdns_uart_data->clk_rate_change_nb);
1451 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1453 clk_disable_unprepare(cdns_uart_data->uartclk);
1454 clk_disable_unprepare(cdns_uart_data->pclk);
1458 /* Match table for of_platform binding */
1459 static struct of_device_id cdns_uart_of_match[] = {
1460 { .compatible = "xlnx,xuartps", },
1461 { .compatible = "cdns,uart-r1p8", },
1464 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1466 static struct platform_driver cdns_uart_platform_driver = {
1467 .probe = cdns_uart_probe,
1468 .remove = cdns_uart_remove,
1470 .name = CDNS_UART_NAME,
1471 .of_match_table = cdns_uart_of_match,
1472 .pm = &cdns_uart_dev_pm_ops,
1476 static int __init cdns_uart_init(void)
1480 /* Register the cdns_uart driver with the serial core */
1481 retval = uart_register_driver(&cdns_uart_uart_driver);
1485 /* Register the platform driver */
1486 retval = platform_driver_register(&cdns_uart_platform_driver);
1488 uart_unregister_driver(&cdns_uart_uart_driver);
1493 static void __exit cdns_uart_exit(void)
1495 /* Unregister the platform driver */
1496 platform_driver_unregister(&cdns_uart_platform_driver);
1498 /* Unregister the cdns_uart driver */
1499 uart_unregister_driver(&cdns_uart_uart_driver);
1502 module_init(cdns_uart_init);
1503 module_exit(cdns_uart_exit);
1505 MODULE_DESCRIPTION("Driver for Cadence UART");
1506 MODULE_AUTHOR("Xilinx Inc.");
1507 MODULE_LICENSE("GPL");