drivers/tty/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 /*#define DBGTBUF(info) dump_tbufs(info)*/
  44 /*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/io.h>
  77 #include <asm/irq.h>
  78 #include <asm/dma.h>
  79 #include <asm/types.h>
  80 #include <asm/uaccess.h>
  81
  82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  83 #define SYNCLINK_GENERIC_HDLC 1
  84 #else
  85 #define SYNCLINK_GENERIC_HDLC 0
  86 #endif
  87
  88 /*
  89  * module identification
  90  */
  91 static char *driver_name     = "SyncLink GT";
  92 static char *tty_driver_name = "synclink_gt";
  93 static char *tty_dev_prefix  = "ttySLG";
  94 MODULE_LICENSE("GPL");
  95 #define MGSL_MAGIC 0x5401
  96 #define MAX_DEVICES 32
  97
  98 static struct pci_device_id pci_table[] = {
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {0,}, /* terminate list */
 104 };
 105 MODULE_DEVICE_TABLE(pci, pci_table);
 106
 107 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 108 static void remove_one(struct pci_dev *dev);
 109 static struct pci_driver pci_driver = {
 110         .name           = "synclink_gt",
 111         .id_table       = pci_table,
 112         .probe          = init_one,
 113         .remove         = remove_one,
 114 };
 115
 116 static bool pci_registered;
 117
 118 /*
 119  * module configuration and status
 120  */
 121 static struct slgt_info *slgt_device_list;
 122 static int slgt_device_count;
 123
 124 static int ttymajor;
 125 static int debug_level;
 126 static int maxframe[MAX_DEVICES];
 127
 128 module_param(ttymajor, int, 0);
 129 module_param(debug_level, int, 0);
 130 module_param_array(maxframe, int, NULL, 0);
 131
 132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 135
 136 /*
 137  * tty support and callbacks
 138  */
 139 static struct tty_driver *serial_driver;
 140
 141 static int  open(struct tty_struct *tty, struct file * filp);
 142 static void close(struct tty_struct *tty, struct file * filp);
 143 static void hangup(struct tty_struct *tty);
 144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 145
 146 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 147 static int put_char(struct tty_struct *tty, unsigned char ch);
 148 static void send_xchar(struct tty_struct *tty, char ch);
 149 static void wait_until_sent(struct tty_struct *tty, int timeout);
 150 static int  write_room(struct tty_struct *tty);
 151 static void flush_chars(struct tty_struct *tty);
 152 static void flush_buffer(struct tty_struct *tty);
 153 static void tx_hold(struct tty_struct *tty);
 154 static void tx_release(struct tty_struct *tty);
 155
 156 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 157 static int  chars_in_buffer(struct tty_struct *tty);
 158 static void throttle(struct tty_struct * tty);
 159 static void unthrottle(struct tty_struct * tty);
 160 static int set_break(struct tty_struct *tty, int break_state);
 161
 162 /*
 163  * generic HDLC support and callbacks
 164  */
 165 #if SYNCLINK_GENERIC_HDLC
 166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 167 static void hdlcdev_tx_done(struct slgt_info *info);
 168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 169 static int  hdlcdev_init(struct slgt_info *info);
 170 static void hdlcdev_exit(struct slgt_info *info);
 171 #endif
 172
 173
 174 /*
 175  * device specific structures, macros and functions
 176  */
 177
 178 #define SLGT_MAX_PORTS 4
 179 #define SLGT_REG_SIZE  256
 180
 181 /*
 182  * conditional wait facility
 183  */
 184 struct cond_wait {
 185         struct cond_wait *next;
 186         wait_queue_head_t q;
 187         wait_queue_t wait;
 188         unsigned int data;
 189 };
 190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void flush_cond_wait(struct cond_wait **head);
 194
 195 /*
 196  * DMA buffer descriptor and access macros
 197  */
 198 struct slgt_desc
 199 {
 200         __le16 count;
 201         __le16 status;
 202         __le32 pbuf;  /* physical address of data buffer */
 203         __le32 next;  /* physical address of next descriptor */
 204
 205         /* driver book keeping */
 206         char *buf;          /* virtual  address of data buffer */
 207         unsigned int pdesc; /* physical address of this descriptor */
 208         dma_addr_t buf_dma_addr;
 209         unsigned short buf_count;
 210 };
 211
 212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 213 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 215 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 217 #define desc_count(a)      (le16_to_cpu((a).count))
 218 #define desc_status(a)     (le16_to_cpu((a).status))
 219 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 220 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 221 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 222 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 223 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 224
 225 struct _input_signal_events {
 226         int ri_up;
 227         int ri_down;
 228         int dsr_up;
 229         int dsr_down;
 230         int dcd_up;
 231         int dcd_down;
 232         int cts_up;
 233         int cts_down;
 234 };
 235
 236 /*
 237  * device instance data structure
 238  */
 239 struct slgt_info {
 240         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 241         struct tty_port port;
 242
 243         struct slgt_info *next_device;  /* device list link */
 244
 245         int magic;
 246
 247         char device_name[25];
 248         struct pci_dev *pdev;
 249
 250         int port_count;  /* count of ports on adapter */
 251         int adapter_num; /* adapter instance number */
 252         int port_num;    /* port instance number */
 253
 254         /* array of pointers to port contexts on this adapter */
 255         struct slgt_info *port_array[SLGT_MAX_PORTS];
 256
 257         int                     line;           /* tty line instance number */
 258
 259         struct mgsl_icount      icount;
 260
 261         int                     timeout;
 262         int                     x_char;         /* xon/xoff character */
 263         unsigned int            read_status_mask;
 264         unsigned int            ignore_status_mask;
 265
 266         wait_queue_head_t       status_event_wait_q;
 267         wait_queue_head_t       event_wait_q;
 268         struct timer_list       tx_timer;
 269         struct timer_list       rx_timer;
 270
 271         unsigned int            gpio_present;
 272         struct cond_wait        *gpio_wait_q;
 273
 274         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 275
 276         struct work_struct task;
 277         u32 pending_bh;
 278         bool bh_requested;
 279         bool bh_running;
 280
 281         int isr_overflow;
 282         bool irq_requested;     /* true if IRQ requested */
 283         bool irq_occurred;      /* for diagnostics use */
 284
 285         /* device configuration */
 286
 287         unsigned int bus_type;
 288         unsigned int irq_level;
 289         unsigned long irq_flags;
 290
 291         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 292         u32 phys_reg_addr;
 293         bool reg_addr_requested;
 294
 295         MGSL_PARAMS params;       /* communications parameters */
 296         u32 idle_mode;
 297         u32 max_frame_size;       /* as set by device config */
 298
 299         unsigned int rbuf_fill_level;
 300         unsigned int rx_pio;
 301         unsigned int if_mode;
 302         unsigned int base_clock;
 303         unsigned int xsync;
 304         unsigned int xctrl;
 305
 306         /* device status */
 307
 308         bool rx_enabled;
 309         bool rx_restart;
 310
 311         bool tx_enabled;
 312         bool tx_active;
 313
 314         unsigned char signals;    /* serial signal states */
 315         int init_error;  /* initialization error */
 316
 317         unsigned char *tx_buf;
 318         int tx_count;
 319
 320         char *flag_buf;
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336         unsigned int rbuf_fill_index;
 337         unsigned short rbuf_fill_count;
 338
 339         unsigned int tbuf_count;
 340         struct slgt_desc *tbufs;
 341         unsigned int tbuf_current;
 342         unsigned int tbuf_start;
 343
 344         unsigned char *tmp_rbuf;
 345         unsigned int tmp_rbuf_count;
 346
 347         /* SPPP/Cisco HDLC device parts */
 348
 349         int netcount;
 350         spinlock_t netlock;
 351 #if SYNCLINK_GENERIC_HDLC
 352         struct net_device *netdev;
 353 #endif
 354
 355 };
 356
 357 static MGSL_PARAMS default_params = {
 358         .mode            = MGSL_MODE_HDLC,
 359         .loopback        = 0,
 360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362         .clock_speed     = 0,
 363         .addr_filter     = 0xff,
 364         .crc_type        = HDLC_CRC_16_CCITT,
 365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367         .data_rate       = 9600,
 368         .data_bits       = 8,
 369         .stop_bits       = 1,
 370         .parity          = ASYNC_PARITY_NONE
 371 };
 372
 373
 374 #define BH_RECEIVE  1
 375 #define BH_TRANSMIT 2
 376 #define BH_STATUS   4
 377 #define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379 #define DMABUFSIZE 256
 380 #define DESC_LIST_SIZE 4096
 381
 382 #define MASK_PARITY  BIT1
 383 #define MASK_FRAMING BIT0
 384 #define MASK_BREAK   BIT14
 385 #define MASK_OVERRUN BIT4
 386
 387 #define GSR   0x00 /* global status */
 388 #define JCR   0x04 /* JTAG control */
 389 #define IODR  0x08 /* GPIO direction */
 390 #define IOER  0x0c /* GPIO interrupt enable */
 391 #define IOVR  0x10 /* GPIO value */
 392 #define IOSR  0x14 /* GPIO interrupt status */
 393 #define TDR   0x80 /* tx data */
 394 #define RDR   0x80 /* rx data */
 395 #define TCR   0x82 /* tx control */
 396 #define TIR   0x84 /* tx idle */
 397 #define TPR   0x85 /* tx preamble */
 398 #define RCR   0x86 /* rx control */
 399 #define VCR   0x88 /* V.24 control */
 400 #define CCR   0x89 /* clock control */
 401 #define BDR   0x8a /* baud divisor */
 402 #define SCR   0x8c /* serial control */
 403 #define SSR   0x8e /* serial status */
 404 #define RDCSR 0x90 /* rx DMA control/status */
 405 #define TDCSR 0x94 /* tx DMA control/status */
 406 #define RDDAR 0x98 /* rx DMA descriptor address */
 407 #define TDDAR 0x9c /* tx DMA descriptor address */
 408 #define XSR   0x40 /* extended sync pattern */
 409 #define XCR   0x44 /* extended control */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static unsigned int tbuf_bytes(struct slgt_info *info);
 470 static void reset_tbufs(struct slgt_info *info);
 471 static void tdma_reset(struct slgt_info *info);
 472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty);
 514 static int  tiocmset(struct tty_struct *tty,
 515                                 unsigned int set, unsigned int clear);
 516 static int set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 523 static int  set_xsync(struct slgt_info *info, int if_mode);
 524 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 525 static int  set_xctrl(struct slgt_info *info, int if_mode);
 526
 527 /*
 528  * driver functions
 529  */
 530 static void add_device(struct slgt_info *info);
 531 static void device_init(int adapter_num, struct pci_dev *pdev);
 532 static int  claim_resources(struct slgt_info *info);
 533 static void release_resources(struct slgt_info *info);
 534
 535 /*
 536  * DEBUG OUTPUT CODE
 537  */
 538 #ifndef DBGINFO
 539 #define DBGINFO(fmt)
 540 #endif
 541 #ifndef DBGERR
 542 #define DBGERR(fmt)
 543 #endif
 544 #ifndef DBGBH
 545 #define DBGBH(fmt)
 546 #endif
 547 #ifndef DBGISR
 548 #define DBGISR(fmt)
 549 #endif
 550
 551 #ifdef DBGDATA
 552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 553 {
 554         int i;
 555         int linecount;
 556         printk("%s %s data:\n",info->device_name, label);
 557         while(count) {
 558                 linecount = (count > 16) ? 16 : count;
 559                 for(i=0; i < linecount; i++)
 560                         printk("%02X ",(unsigned char)data[i]);
 561                 for(;i<17;i++)
 562                         printk("   ");
 563                 for(i=0;i<linecount;i++) {
 564                         if (data[i]>=040 && data[i]<=0176)
 565                                 printk("%c",data[i]);
 566                         else
 567                                 printk(".");
 568                 }
 569                 printk("\n");
 570                 data  += linecount;
 571                 count -= linecount;
 572         }
 573 }
 574 #else
 575 #define DBGDATA(info, buf, size, label)
 576 #endif
 577
 578 #ifdef DBGTBUF
 579 static void dump_tbufs(struct slgt_info *info)
 580 {
 581         int i;
 582         printk("tbuf_current=%d\n", info->tbuf_current);
 583         for (i=0 ; i < info->tbuf_count ; i++) {
 584                 printk("%d: count=%04X status=%04X\n",
 585                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 586         }
 587 }
 588 #else
 589 #define DBGTBUF(info)
 590 #endif
 591
 592 #ifdef DBGRBUF
 593 static void dump_rbufs(struct slgt_info *info)
 594 {
 595         int i;
 596         printk("rbuf_current=%d\n", info->rbuf_current);
 597         for (i=0 ; i < info->rbuf_count ; i++) {
 598                 printk("%d: count=%04X status=%04X\n",
 599                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 600         }
 601 }
 602 #else
 603 #define DBGRBUF(info)
 604 #endif
 605
 606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 607 {
 608 #ifdef SANITY_CHECK
 609         if (!info) {
 610                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613         if (info->magic != MGSL_MAGIC) {
 614                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 615                 return 1;
 616         }
 617 #else
 618         if (!info)
 619                 return 1;
 620 #endif
 621         return 0;
 622 }
 623
 624 /**
 625  * line discipline callback wrappers
 626  *
 627  * The wrappers maintain line discipline references
 628  * while calling into the line discipline.
 629  *
 630  * ldisc_receive_buf  - pass receive data to line discipline
 631  */
 632 static void ldisc_receive_buf(struct tty_struct *tty,
 633                               const __u8 *data, char *flags, int count)
 634 {
 635         struct tty_ldisc *ld;
 636         if (!tty)
 637                 return;
 638         ld = tty_ldisc_ref(tty);
 639         if (ld) {
 640                 if (ld->ops->receive_buf)
 641                         ld->ops->receive_buf(tty, data, flags, count);
 642                 tty_ldisc_deref(ld);
 643         }
 644 }
 645
 646 /* tty callbacks */
 647
 648 static int open(struct tty_struct *tty, struct file *filp)
 649 {
 650         struct slgt_info *info;
 651         int retval, line;
 652         unsigned long flags;
 653
 654         line = tty->index;
 655         if (line >= slgt_device_count) {
 656                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 657                 return -ENODEV;
 658         }
 659
 660         info = slgt_device_list;
 661         while(info && info->line != line)
 662                 info = info->next_device;
 663         if (sanity_check(info, tty->name, "open"))
 664                 return -ENODEV;
 665         if (info->init_error) {
 666                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 667                 return -ENODEV;
 668         }
 669
 670         tty->driver_data = info;
 671         info->port.tty = tty;
 672
 673         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 674
 675         /* If port is closing, signal caller to try again */
 676         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 677                 if (info->port.flags & ASYNC_CLOSING)
 678                         interruptible_sleep_on(&info->port.close_wait);
 679                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 680                         -EAGAIN : -ERESTARTSYS);
 681                 goto cleanup;
 682         }
 683
 684         mutex_lock(&info->port.mutex);
 685         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 686
 687         spin_lock_irqsave(&info->netlock, flags);
 688         if (info->netcount) {
 689                 retval = -EBUSY;
 690                 spin_unlock_irqrestore(&info->netlock, flags);
 691                 mutex_unlock(&info->port.mutex);
 692                 goto cleanup;
 693         }
 694         info->port.count++;
 695         spin_unlock_irqrestore(&info->netlock, flags);
 696
 697         if (info->port.count == 1) {
 698                 /* 1st open on this device, init hardware */
 699                 retval = startup(info);
 700                 if (retval < 0) {
 701                         mutex_unlock(&info->port.mutex);
 702                         goto cleanup;
 703                 }
 704         }
 705         mutex_unlock(&info->port.mutex);
 706         retval = block_til_ready(tty, filp, info);
 707         if (retval) {
 708                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 709                 goto cleanup;
 710         }
 711
 712         retval = 0;
 713
 714 cleanup:
 715         if (retval) {
 716                 if (tty->count == 1)
 717                         info->port.tty = NULL; /* tty layer will release tty struct */
 718                 if(info->port.count)
 719                         info->port.count--;
 720         }
 721
 722         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 723         return retval;
 724 }
 725
 726 static void close(struct tty_struct *tty, struct file *filp)
 727 {
 728         struct slgt_info *info = tty->driver_data;
 729
 730         if (sanity_check(info, tty->name, "close"))
 731                 return;
 732         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 733
 734         if (tty_port_close_start(&info->port, tty, filp) == 0)
 735                 goto cleanup;
 736
 737         mutex_lock(&info->port.mutex);
 738         if (info->port.flags & ASYNC_INITIALIZED)
 739                 wait_until_sent(tty, info->timeout);
 740         flush_buffer(tty);
 741         tty_ldisc_flush(tty);
 742
 743         shutdown(info);
 744         mutex_unlock(&info->port.mutex);
 745
 746         tty_port_close_end(&info->port, tty);
 747         info->port.tty = NULL;
 748 cleanup:
 749         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 750 }
 751
 752 static void hangup(struct tty_struct *tty)
 753 {
 754         struct slgt_info *info = tty->driver_data;
 755         unsigned long flags;
 756
 757         if (sanity_check(info, tty->name, "hangup"))
 758                 return;
 759         DBGINFO(("%s hangup\n", info->device_name));
 760
 761         flush_buffer(tty);
 762
 763         mutex_lock(&info->port.mutex);
 764         shutdown(info);
 765
 766         spin_lock_irqsave(&info->port.lock, flags);
 767         info->port.count = 0;
 768         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 769         info->port.tty = NULL;
 770         spin_unlock_irqrestore(&info->port.lock, flags);
 771         mutex_unlock(&info->port.mutex);
 772
 773         wake_up_interruptible(&info->port.open_wait);
 774 }
 775
 776 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 777 {
 778         struct slgt_info *info = tty->driver_data;
 779         unsigned long flags;
 780
 781         DBGINFO(("%s set_termios\n", tty->driver->name));
 782
 783         change_params(info);
 784
 785         /* Handle transition to B0 status */
 786         if (old_termios->c_cflag & CBAUD &&
 787             !(tty->termios.c_cflag & CBAUD)) {
 788                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 789                 spin_lock_irqsave(&info->lock,flags);
 790                 set_signals(info);
 791                 spin_unlock_irqrestore(&info->lock,flags);
 792         }
 793
 794         /* Handle transition away from B0 status */
 795         if (!(old_termios->c_cflag & CBAUD) &&
 796             tty->termios.c_cflag & CBAUD) {
 797                 info->signals |= SerialSignal_DTR;
 798                 if (!(tty->termios.c_cflag & CRTSCTS) ||
 799                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 800                         info->signals |= SerialSignal_RTS;
 801                 }
 802                 spin_lock_irqsave(&info->lock,flags);
 803                 set_signals(info);
 804                 spin_unlock_irqrestore(&info->lock,flags);
 805         }
 806
 807         /* Handle turning off CRTSCTS */
 808         if (old_termios->c_cflag & CRTSCTS &&
 809             !(tty->termios.c_cflag & CRTSCTS)) {
 810                 tty->hw_stopped = 0;
 811                 tx_release(tty);
 812         }
 813 }
 814
 815 static void update_tx_timer(struct slgt_info *info)
 816 {
 817         /*
 818          * use worst case speed of 1200bps to calculate transmit timeout
 819          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 820          */
 821         if (info->params.mode == MGSL_MODE_HDLC) {
 822                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 823                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 824         }
 825 }
 826
 827 static int write(struct tty_struct *tty,
 828                  const unsigned char *buf, int count)
 829 {
 830         int ret = 0;
 831         struct slgt_info *info = tty->driver_data;
 832         unsigned long flags;
 833
 834         if (sanity_check(info, tty->name, "write"))
 835                 return -EIO;
 836
 837         DBGINFO(("%s write count=%d\n", info->device_name, count));
 838
 839         if (!info->tx_buf || (count > info->max_frame_size))
 840                 return -EIO;
 841
 842         if (!count || tty->stopped || tty->hw_stopped)
 843                 return 0;
 844
 845         spin_lock_irqsave(&info->lock, flags);
 846
 847         if (info->tx_count) {
 848                 /* send accumulated data from send_char() */
 849                 if (!tx_load(info, info->tx_buf, info->tx_count))
 850                         goto cleanup;
 851                 info->tx_count = 0;
 852         }
 853
 854         if (tx_load(info, buf, count))
 855                 ret = count;
 856
 857 cleanup:
 858         spin_unlock_irqrestore(&info->lock, flags);
 859         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 860         return ret;
 861 }
 862
 863 static int put_char(struct tty_struct *tty, unsigned char ch)
 864 {
 865         struct slgt_info *info = tty->driver_data;
 866         unsigned long flags;
 867         int ret = 0;
 868
 869         if (sanity_check(info, tty->name, "put_char"))
 870                 return 0;
 871         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 872         if (!info->tx_buf)
 873                 return 0;
 874         spin_lock_irqsave(&info->lock,flags);
 875         if (info->tx_count < info->max_frame_size) {
 876                 info->tx_buf[info->tx_count++] = ch;
 877                 ret = 1;
 878         }
 879         spin_unlock_irqrestore(&info->lock,flags);
 880         return ret;
 881 }
 882
 883 static void send_xchar(struct tty_struct *tty, char ch)
 884 {
 885         struct slgt_info *info = tty->driver_data;
 886         unsigned long flags;
 887
 888         if (sanity_check(info, tty->name, "send_xchar"))
 889                 return;
 890         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 891         info->x_char = ch;
 892         if (ch) {
 893                 spin_lock_irqsave(&info->lock,flags);
 894                 if (!info->tx_enabled)
 895                         tx_start(info);
 896                 spin_unlock_irqrestore(&info->lock,flags);
 897         }
 898 }
 899
 900 static void wait_until_sent(struct tty_struct *tty, int timeout)
 901 {
 902         struct slgt_info *info = tty->driver_data;
 903         unsigned long orig_jiffies, char_time;
 904
 905         if (!info )
 906                 return;
 907         if (sanity_check(info, tty->name, "wait_until_sent"))
 908                 return;
 909         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 910         if (!(info->port.flags & ASYNC_INITIALIZED))
 911                 goto exit;
 912
 913         orig_jiffies = jiffies;
 914
 915         /* Set check interval to 1/5 of estimated time to
 916          * send a character, and make it at least 1. The check
 917          * interval should also be less than the timeout.
 918          * Note: use tight timings here to satisfy the NIST-PCTS.
 919          */
 920
 921         if (info->params.data_rate) {
 922                 char_time = info->timeout/(32 * 5);
 923                 if (!char_time)
 924                         char_time++;
 925         } else
 926                 char_time = 1;
 927
 928         if (timeout)
 929                 char_time = min_t(unsigned long, char_time, timeout);
 930
 931         while (info->tx_active) {
 932                 msleep_interruptible(jiffies_to_msecs(char_time));
 933                 if (signal_pending(current))
 934                         break;
 935                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 936                         break;
 937         }
 938 exit:
 939         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 940 }
 941
 942 static int write_room(struct tty_struct *tty)
 943 {
 944         struct slgt_info *info = tty->driver_data;
 945         int ret;
 946
 947         if (sanity_check(info, tty->name, "write_room"))
 948                 return 0;
 949         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 950         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 951         return ret;
 952 }
 953
 954 static void flush_chars(struct tty_struct *tty)
 955 {
 956         struct slgt_info *info = tty->driver_data;
 957         unsigned long flags;
 958
 959         if (sanity_check(info, tty->name, "flush_chars"))
 960                 return;
 961         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 962
 963         if (info->tx_count <= 0 || tty->stopped ||
 964             tty->hw_stopped || !info->tx_buf)
 965                 return;
 966
 967         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 968
 969         spin_lock_irqsave(&info->lock,flags);
 970         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 971                 info->tx_count = 0;
 972         spin_unlock_irqrestore(&info->lock,flags);
 973 }
 974
 975 static void flush_buffer(struct tty_struct *tty)
 976 {
 977         struct slgt_info *info = tty->driver_data;
 978         unsigned long flags;
 979
 980         if (sanity_check(info, tty->name, "flush_buffer"))
 981                 return;
 982         DBGINFO(("%s flush_buffer\n", info->device_name));
 983
 984         spin_lock_irqsave(&info->lock, flags);
 985         info->tx_count = 0;
 986         spin_unlock_irqrestore(&info->lock, flags);
 987
 988         tty_wakeup(tty);
 989 }
 990
 991 /*
 992  * throttle (stop) transmitter
 993  */
 994 static void tx_hold(struct tty_struct *tty)
 995 {
 996         struct slgt_info *info = tty->driver_data;
 997         unsigned long flags;
 998
 999         if (sanity_check(info, tty->name, "tx_hold"))
1000                 return;
1001         DBGINFO(("%s tx_hold\n", info->device_name));
1002         spin_lock_irqsave(&info->lock,flags);
1003         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1004                 tx_stop(info);
1005         spin_unlock_irqrestore(&info->lock,flags);
1006 }
1007
1008 /*
1009  * release (start) transmitter
1010  */
1011 static void tx_release(struct tty_struct *tty)
1012 {
1013         struct slgt_info *info = tty->driver_data;
1014         unsigned long flags;
1015
1016         if (sanity_check(info, tty->name, "tx_release"))
1017                 return;
1018         DBGINFO(("%s tx_release\n", info->device_name));
1019         spin_lock_irqsave(&info->lock, flags);
1020         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1021                 info->tx_count = 0;
1022         spin_unlock_irqrestore(&info->lock, flags);
1023 }
1024
1025 /*
1026  * Service an IOCTL request
1027  *
1028  * Arguments
1029  *
1030  *      tty     pointer to tty instance data
1031  *      cmd     IOCTL command code
1032  *      arg     command argument/context
1033  *
1034  * Return 0 if success, otherwise error code
1035  */
1036 static int ioctl(struct tty_struct *tty,
1037                  unsigned int cmd, unsigned long arg)
1038 {
1039         struct slgt_info *info = tty->driver_data;
1040         void __user *argp = (void __user *)arg;
1041         int ret;
1042
1043         if (sanity_check(info, tty->name, "ioctl"))
1044                 return -ENODEV;
1045         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1046
1047         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1048             (cmd != TIOCMIWAIT)) {
1049                 if (tty->flags & (1 << TTY_IO_ERROR))
1050                     return -EIO;
1051         }
1052
1053         switch (cmd) {
1054         case MGSL_IOCWAITEVENT:
1055                 return wait_mgsl_event(info, argp);
1056         case TIOCMIWAIT:
1057                 return modem_input_wait(info,(int)arg);
1058         case MGSL_IOCSGPIO:
1059                 return set_gpio(info, argp);
1060         case MGSL_IOCGGPIO:
1061                 return get_gpio(info, argp);
1062         case MGSL_IOCWAITGPIO:
1063                 return wait_gpio(info, argp);
1064         case MGSL_IOCGXSYNC:
1065                 return get_xsync(info, argp);
1066         case MGSL_IOCSXSYNC:
1067                 return set_xsync(info, (int)arg);
1068         case MGSL_IOCGXCTRL:
1069                 return get_xctrl(info, argp);
1070         case MGSL_IOCSXCTRL:
1071                 return set_xctrl(info, (int)arg);
1072         }
1073         mutex_lock(&info->port.mutex);
1074         switch (cmd) {
1075         case MGSL_IOCGPARAMS:
1076                 ret = get_params(info, argp);
1077                 break;
1078         case MGSL_IOCSPARAMS:
1079                 ret = set_params(info, argp);
1080                 break;
1081         case MGSL_IOCGTXIDLE:
1082                 ret = get_txidle(info, argp);
1083                 break;
1084         case MGSL_IOCSTXIDLE:
1085                 ret = set_txidle(info, (int)arg);
1086                 break;
1087         case MGSL_IOCTXENABLE:
1088                 ret = tx_enable(info, (int)arg);
1089                 break;
1090         case MGSL_IOCRXENABLE:
1091                 ret = rx_enable(info, (int)arg);
1092                 break;
1093         case MGSL_IOCTXABORT:
1094                 ret = tx_abort(info);
1095                 break;
1096         case MGSL_IOCGSTATS:
1097                 ret = get_stats(info, argp);
1098                 break;
1099         case MGSL_IOCGIF:
1100                 ret = get_interface(info, argp);
1101                 break;
1102         case MGSL_IOCSIF:
1103                 ret = set_interface(info,(int)arg);
1104                 break;
1105         default:
1106                 ret = -ENOIOCTLCMD;
1107         }
1108         mutex_unlock(&info->port.mutex);
1109         return ret;
1110 }
1111
1112 static int get_icount(struct tty_struct *tty,
1113                                 struct serial_icounter_struct *icount)
1114
1115 {
1116         struct slgt_info *info = tty->driver_data;
1117         struct mgsl_icount cnow;        /* kernel counter temps */
1118         unsigned long flags;
1119
1120         spin_lock_irqsave(&info->lock,flags);
1121         cnow = info->icount;
1122         spin_unlock_irqrestore(&info->lock,flags);
1123
1124         icount->cts = cnow.cts;
1125         icount->dsr = cnow.dsr;
1126         icount->rng = cnow.rng;
1127         icount->dcd = cnow.dcd;
1128         icount->rx = cnow.rx;
1129         icount->tx = cnow.tx;
1130         icount->frame = cnow.frame;
1131         icount->overrun = cnow.overrun;
1132         icount->parity = cnow.parity;
1133         icount->brk = cnow.brk;
1134         icount->buf_overrun = cnow.buf_overrun;
1135
1136         return 0;
1137 }
1138
1139 /*
1140  * support for 32 bit ioctl calls on 64 bit systems
1141  */
1142 #ifdef CONFIG_COMPAT
1143 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1144 {
1145         struct MGSL_PARAMS32 tmp_params;
1146
1147         DBGINFO(("%s get_params32\n", info->device_name));
1148         memset(&tmp_params, 0, sizeof(tmp_params));
1149         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1150         tmp_params.loopback        = info->params.loopback;
1151         tmp_params.flags           = info->params.flags;
1152         tmp_params.encoding        = info->params.encoding;
1153         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1154         tmp_params.addr_filter     = info->params.addr_filter;
1155         tmp_params.crc_type        = info->params.crc_type;
1156         tmp_params.preamble_length = info->params.preamble_length;
1157         tmp_params.preamble        = info->params.preamble;
1158         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1159         tmp_params.data_bits       = info->params.data_bits;
1160         tmp_params.stop_bits       = info->params.stop_bits;
1161         tmp_params.parity          = info->params.parity;
1162         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1163                 return -EFAULT;
1164         return 0;
1165 }
1166
1167 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1168 {
1169         struct MGSL_PARAMS32 tmp_params;
1170
1171         DBGINFO(("%s set_params32\n", info->device_name));
1172         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1173                 return -EFAULT;
1174
1175         spin_lock(&info->lock);
1176         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1177                 info->base_clock = tmp_params.clock_speed;
1178         } else {
1179                 info->params.mode            = tmp_params.mode;
1180                 info->params.loopback        = tmp_params.loopback;
1181                 info->params.flags           = tmp_params.flags;
1182                 info->params.encoding        = tmp_params.encoding;
1183                 info->params.clock_speed     = tmp_params.clock_speed;
1184                 info->params.addr_filter     = tmp_params.addr_filter;
1185                 info->params.crc_type        = tmp_params.crc_type;
1186                 info->params.preamble_length = tmp_params.preamble_length;
1187                 info->params.preamble        = tmp_params.preamble;
1188                 info->params.data_rate       = tmp_params.data_rate;
1189                 info->params.data_bits       = tmp_params.data_bits;
1190                 info->params.stop_bits       = tmp_params.stop_bits;
1191                 info->params.parity          = tmp_params.parity;
1192         }
1193         spin_unlock(&info->lock);
1194
1195         program_hw(info);
1196
1197         return 0;
1198 }
1199
1200 static long slgt_compat_ioctl(struct tty_struct *tty,
1201                          unsigned int cmd, unsigned long arg)
1202 {
1203         struct slgt_info *info = tty->driver_data;
1204         int rc = -ENOIOCTLCMD;
1205
1206         if (sanity_check(info, tty->name, "compat_ioctl"))
1207                 return -ENODEV;
1208         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1209
1210         switch (cmd) {
1211
1212         case MGSL_IOCSPARAMS32:
1213                 rc = set_params32(info, compat_ptr(arg));
1214                 break;
1215
1216         case MGSL_IOCGPARAMS32:
1217                 rc = get_params32(info, compat_ptr(arg));
1218                 break;
1219
1220         case MGSL_IOCGPARAMS:
1221         case MGSL_IOCSPARAMS:
1222         case MGSL_IOCGTXIDLE:
1223         case MGSL_IOCGSTATS:
1224         case MGSL_IOCWAITEVENT:
1225         case MGSL_IOCGIF:
1226         case MGSL_IOCSGPIO:
1227         case MGSL_IOCGGPIO:
1228         case MGSL_IOCWAITGPIO:
1229         case MGSL_IOCGXSYNC:
1230         case MGSL_IOCGXCTRL:
1231         case MGSL_IOCSTXIDLE:
1232         case MGSL_IOCTXENABLE:
1233         case MGSL_IOCRXENABLE:
1234         case MGSL_IOCTXABORT:
1235         case TIOCMIWAIT:
1236         case MGSL_IOCSIF:
1237         case MGSL_IOCSXSYNC:
1238         case MGSL_IOCSXCTRL:
1239                 rc = ioctl(tty, cmd, arg);
1240                 break;
1241         }
1242
1243         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1244         return rc;
1245 }
1246 #else
1247 #define slgt_compat_ioctl NULL
1248 #endif /* ifdef CONFIG_COMPAT */
1249
1250 /*
1251  * proc fs support
1252  */
1253 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1254 {
1255         char stat_buf[30];
1256         unsigned long flags;
1257
1258         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1259                       info->device_name, info->phys_reg_addr,
1260                       info->irq_level, info->max_frame_size);
1261
1262         /* output current serial signal states */
1263         spin_lock_irqsave(&info->lock,flags);
1264         get_signals(info);
1265         spin_unlock_irqrestore(&info->lock,flags);
1266
1267         stat_buf[0] = 0;
1268         stat_buf[1] = 0;
1269         if (info->signals & SerialSignal_RTS)
1270                 strcat(stat_buf, "|RTS");
1271         if (info->signals & SerialSignal_CTS)
1272                 strcat(stat_buf, "|CTS");
1273         if (info->signals & SerialSignal_DTR)
1274                 strcat(stat_buf, "|DTR");
1275         if (info->signals & SerialSignal_DSR)
1276                 strcat(stat_buf, "|DSR");
1277         if (info->signals & SerialSignal_DCD)
1278                 strcat(stat_buf, "|CD");
1279         if (info->signals & SerialSignal_RI)
1280                 strcat(stat_buf, "|RI");
1281
1282         if (info->params.mode != MGSL_MODE_ASYNC) {
1283                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1284                                info->icount.txok, info->icount.rxok);
1285                 if (info->icount.txunder)
1286                         seq_printf(m, " txunder:%d", info->icount.txunder);
1287                 if (info->icount.txabort)
1288                         seq_printf(m, " txabort:%d", info->icount.txabort);
1289                 if (info->icount.rxshort)
1290                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1291                 if (info->icount.rxlong)
1292                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1293                 if (info->icount.rxover)
1294                         seq_printf(m, " rxover:%d", info->icount.rxover);
1295                 if (info->icount.rxcrc)
1296                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1297         } else {
1298                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1299                                info->icount.tx, info->icount.rx);
1300                 if (info->icount.frame)
1301                         seq_printf(m, " fe:%d", info->icount.frame);
1302                 if (info->icount.parity)
1303                         seq_printf(m, " pe:%d", info->icount.parity);
1304                 if (info->icount.brk)
1305                         seq_printf(m, " brk:%d", info->icount.brk);
1306                 if (info->icount.overrun)
1307                         seq_printf(m, " oe:%d", info->icount.overrun);
1308         }
1309
1310         /* Append serial signal status to end */
1311         seq_printf(m, " %s\n", stat_buf+1);
1312
1313         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1314                        info->tx_active,info->bh_requested,info->bh_running,
1315                        info->pending_bh);
1316 }
1317
1318 /* Called to print information about devices
1319  */
1320 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1321 {
1322         struct slgt_info *info;
1323
1324         seq_puts(m, "synclink_gt driver\n");
1325
1326         info = slgt_device_list;
1327         while( info ) {
1328                 line_info(m, info);
1329                 info = info->next_device;
1330         }
1331         return 0;
1332 }
1333
1334 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1335 {
1336         return single_open(file, synclink_gt_proc_show, NULL);
1337 }
1338
1339 static const struct file_operations synclink_gt_proc_fops = {
1340         .owner          = THIS_MODULE,
1341         .open           = synclink_gt_proc_open,
1342         .read           = seq_read,
1343         .llseek         = seq_lseek,
1344         .release        = single_release,
1345 };
1346
1347 /*
1348  * return count of bytes in transmit buffer
1349  */
1350 static int chars_in_buffer(struct tty_struct *tty)
1351 {
1352         struct slgt_info *info = tty->driver_data;
1353         int count;
1354         if (sanity_check(info, tty->name, "chars_in_buffer"))
1355                 return 0;
1356         count = tbuf_bytes(info);
1357         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1358         return count;
1359 }
1360
1361 /*
1362  * signal remote device to throttle send data (our receive data)
1363  */
1364 static void throttle(struct tty_struct * tty)
1365 {
1366         struct slgt_info *info = tty->driver_data;
1367         unsigned long flags;
1368
1369         if (sanity_check(info, tty->name, "throttle"))
1370                 return;
1371         DBGINFO(("%s throttle\n", info->device_name));
1372         if (I_IXOFF(tty))
1373                 send_xchar(tty, STOP_CHAR(tty));
1374         if (tty->termios.c_cflag & CRTSCTS) {
1375                 spin_lock_irqsave(&info->lock,flags);
1376                 info->signals &= ~SerialSignal_RTS;
1377                 set_signals(info);
1378                 spin_unlock_irqrestore(&info->lock,flags);
1379         }
1380 }
1381
1382 /*
1383  * signal remote device to stop throttling send data (our receive data)
1384  */
1385 static void unthrottle(struct tty_struct * tty)
1386 {
1387         struct slgt_info *info = tty->driver_data;
1388         unsigned long flags;
1389
1390         if (sanity_check(info, tty->name, "unthrottle"))
1391                 return;
1392         DBGINFO(("%s unthrottle\n", info->device_name));
1393         if (I_IXOFF(tty)) {
1394                 if (info->x_char)
1395                         info->x_char = 0;
1396                 else
1397                         send_xchar(tty, START_CHAR(tty));
1398         }
1399         if (tty->termios.c_cflag & CRTSCTS) {
1400                 spin_lock_irqsave(&info->lock,flags);
1401                 info->signals |= SerialSignal_RTS;
1402                 set_signals(info);
1403                 spin_unlock_irqrestore(&info->lock,flags);
1404         }
1405 }
1406
1407 /*
1408  * set or clear transmit break condition
1409  * break_state  -1=set break condition, 0=clear
1410  */
1411 static int set_break(struct tty_struct *tty, int break_state)
1412 {
1413         struct slgt_info *info = tty->driver_data;
1414         unsigned short value;
1415         unsigned long flags;
1416
1417         if (sanity_check(info, tty->name, "set_break"))
1418                 return -EINVAL;
1419         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1420
1421         spin_lock_irqsave(&info->lock,flags);
1422         value = rd_reg16(info, TCR);
1423         if (break_state == -1)
1424                 value |= BIT6;
1425         else
1426                 value &= ~BIT6;
1427         wr_reg16(info, TCR, value);
1428         spin_unlock_irqrestore(&info->lock,flags);
1429         return 0;
1430 }
1431
1432 #if SYNCLINK_GENERIC_HDLC
1433
1434 /**
1435  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1436  * set encoding and frame check sequence (FCS) options
1437  *
1438  * dev       pointer to network device structure
1439  * encoding  serial encoding setting
1440  * parity    FCS setting
1441  *
1442  * returns 0 if success, otherwise error code
1443  */
1444 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1445                           unsigned short parity)
1446 {
1447         struct slgt_info *info = dev_to_port(dev);
1448         unsigned char  new_encoding;
1449         unsigned short new_crctype;
1450
1451         /* return error if TTY interface open */
1452         if (info->port.count)
1453                 return -EBUSY;
1454
1455         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1456
1457         switch (encoding)
1458         {
1459         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1460         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1461         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1462         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1463         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1464         default: return -EINVAL;
1465         }
1466
1467         switch (parity)
1468         {
1469         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1470         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1471         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1472         default: return -EINVAL;
1473         }
1474
1475         info->params.encoding = new_encoding;
1476         info->params.crc_type = new_crctype;
1477
1478         /* if network interface up, reprogram hardware */
1479         if (info->netcount)
1480                 program_hw(info);
1481
1482         return 0;
1483 }
1484
1485 /**
1486  * called by generic HDLC layer to send frame
1487  *
1488  * skb  socket buffer containing HDLC frame
1489  * dev  pointer to network device structure
1490  */
1491 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1492                                       struct net_device *dev)
1493 {
1494         struct slgt_info *info = dev_to_port(dev);
1495         unsigned long flags;
1496
1497         DBGINFO(("%s hdlc_xmit\n", dev->name));
1498
1499         if (!skb->len)
1500                 return NETDEV_TX_OK;
1501
1502         /* stop sending until this frame completes */
1503         netif_stop_queue(dev);
1504
1505         /* update network statistics */
1506         dev->stats.tx_packets++;
1507         dev->stats.tx_bytes += skb->len;
1508
1509         /* save start time for transmit timeout detection */
1510         dev->trans_start = jiffies;
1511
1512         spin_lock_irqsave(&info->lock, flags);
1513         tx_load(info, skb->data, skb->len);
1514         spin_unlock_irqrestore(&info->lock, flags);
1515
1516         /* done with socket buffer, so free it */
1517         dev_kfree_skb(skb);
1518
1519         return NETDEV_TX_OK;
1520 }
1521
1522 /**
1523  * called by network layer when interface enabled
1524  * claim resources and initialize hardware
1525  *
1526  * dev  pointer to network device structure
1527  *
1528  * returns 0 if success, otherwise error code
1529  */
1530 static int hdlcdev_open(struct net_device *dev)
1531 {
1532         struct slgt_info *info = dev_to_port(dev);
1533         int rc;
1534         unsigned long flags;
1535
1536         if (!try_module_get(THIS_MODULE))
1537                 return -EBUSY;
1538
1539         DBGINFO(("%s hdlcdev_open\n", dev->name));
1540
1541         /* generic HDLC layer open processing */
1542         if ((rc = hdlc_open(dev)))
1543                 return rc;
1544
1545         /* arbitrate between network and tty opens */
1546         spin_lock_irqsave(&info->netlock, flags);
1547         if (info->port.count != 0 || info->netcount != 0) {
1548                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1549                 spin_unlock_irqrestore(&info->netlock, flags);
1550                 return -EBUSY;
1551         }
1552         info->netcount=1;
1553         spin_unlock_irqrestore(&info->netlock, flags);
1554
1555         /* claim resources and init adapter */
1556         if ((rc = startup(info)) != 0) {
1557                 spin_lock_irqsave(&info->netlock, flags);
1558                 info->netcount=0;
1559                 spin_unlock_irqrestore(&info->netlock, flags);
1560                 return rc;
1561         }
1562
1563         /* assert DTR and RTS, apply hardware settings */
1564         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1565         program_hw(info);
1566
1567         /* enable network layer transmit */
1568         dev->trans_start = jiffies;
1569         netif_start_queue(dev);
1570
1571         /* inform generic HDLC layer of current DCD status */
1572         spin_lock_irqsave(&info->lock, flags);
1573         get_signals(info);
1574         spin_unlock_irqrestore(&info->lock, flags);
1575         if (info->signals & SerialSignal_DCD)
1576                 netif_carrier_on(dev);
1577         else
1578                 netif_carrier_off(dev);
1579         return 0;
1580 }
1581
1582 /**
1583  * called by network layer when interface is disabled
1584  * shutdown hardware and release resources
1585  *
1586  * dev  pointer to network device structure
1587  *
1588  * returns 0 if success, otherwise error code
1589  */
1590 static int hdlcdev_close(struct net_device *dev)
1591 {
1592         struct slgt_info *info = dev_to_port(dev);
1593         unsigned long flags;
1594
1595         DBGINFO(("%s hdlcdev_close\n", dev->name));
1596
1597         netif_stop_queue(dev);
1598
1599         /* shutdown adapter and release resources */
1600         shutdown(info);
1601
1602         hdlc_close(dev);
1603
1604         spin_lock_irqsave(&info->netlock, flags);
1605         info->netcount=0;
1606         spin_unlock_irqrestore(&info->netlock, flags);
1607
1608         module_put(THIS_MODULE);
1609         return 0;
1610 }
1611
1612 /**
1613  * called by network layer to process IOCTL call to network device
1614  *
1615  * dev  pointer to network device structure
1616  * ifr  pointer to network interface request structure
1617  * cmd  IOCTL command code
1618  *
1619  * returns 0 if success, otherwise error code
1620  */
1621 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1622 {
1623         const size_t size = sizeof(sync_serial_settings);
1624         sync_serial_settings new_line;
1625         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1626         struct slgt_info *info = dev_to_port(dev);
1627         unsigned int flags;
1628
1629         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1630
1631         /* return error if TTY interface open */
1632         if (info->port.count)
1633                 return -EBUSY;
1634
1635         if (cmd != SIOCWANDEV)
1636                 return hdlc_ioctl(dev, ifr, cmd);
1637
1638         memset(&new_line, 0, sizeof(new_line));
1639
1640         switch(ifr->ifr_settings.type) {
1641         case IF_GET_IFACE: /* return current sync_serial_settings */
1642
1643                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1644                 if (ifr->ifr_settings.size < size) {
1645                         ifr->ifr_settings.size = size; /* data size wanted */
1646                         return -ENOBUFS;
1647                 }
1648
1649                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1650                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1651                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1652                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1653
1654                 switch (flags){
1655                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1656                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1657                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1658                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1659                 default: new_line.clock_type = CLOCK_DEFAULT;
1660                 }
1661
1662                 new_line.clock_rate = info->params.clock_speed;
1663                 new_line.loopback   = info->params.loopback ? 1:0;
1664
1665                 if (copy_to_user(line, &new_line, size))
1666                         return -EFAULT;
1667                 return 0;
1668
1669         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1670
1671                 if(!capable(CAP_NET_ADMIN))
1672                         return -EPERM;
1673                 if (copy_from_user(&new_line, line, size))
1674                         return -EFAULT;
1675
1676                 switch (new_line.clock_type)
1677                 {
1678                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1679                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1680                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1681                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1682                 case CLOCK_DEFAULT:  flags = info->params.flags &
1683                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1684                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1685                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1686                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1687                 default: return -EINVAL;
1688                 }
1689
1690                 if (new_line.loopback != 0 && new_line.loopback != 1)
1691                         return -EINVAL;
1692
1693                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1694                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1695                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1696                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1697                 info->params.flags |= flags;
1698
1699                 info->params.loopback = new_line.loopback;
1700
1701                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1702                         info->params.clock_speed = new_line.clock_rate;
1703                 else
1704                         info->params.clock_speed = 0;
1705
1706                 /* if network interface up, reprogram hardware */
1707                 if (info->netcount)
1708                         program_hw(info);
1709                 return 0;
1710
1711         default:
1712                 return hdlc_ioctl(dev, ifr, cmd);
1713         }
1714 }
1715
1716 /**
1717  * called by network layer when transmit timeout is detected
1718  *
1719  * dev  pointer to network device structure
1720  */
1721 static void hdlcdev_tx_timeout(struct net_device *dev)
1722 {
1723         struct slgt_info *info = dev_to_port(dev);
1724         unsigned long flags;
1725
1726         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1727
1728         dev->stats.tx_errors++;
1729         dev->stats.tx_aborted_errors++;
1730
1731         spin_lock_irqsave(&info->lock,flags);
1732         tx_stop(info);
1733         spin_unlock_irqrestore(&info->lock,flags);
1734
1735         netif_wake_queue(dev);
1736 }
1737
1738 /**
1739  * called by device driver when transmit completes
1740  * reenable network layer transmit if stopped
1741  *
1742  * info  pointer to device instance information
1743  */
1744 static void hdlcdev_tx_done(struct slgt_info *info)
1745 {
1746         if (netif_queue_stopped(info->netdev))
1747                 netif_wake_queue(info->netdev);
1748 }
1749
1750 /**
1751  * called by device driver when frame received
1752  * pass frame to network layer
1753  *
1754  * info  pointer to device instance information
1755  * buf   pointer to buffer contianing frame data
1756  * size  count of data bytes in buf
1757  */
1758 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1759 {
1760         struct sk_buff *skb = dev_alloc_skb(size);
1761         struct net_device *dev = info->netdev;
1762
1763         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1764
1765         if (skb == NULL) {
1766                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1767                 dev->stats.rx_dropped++;
1768                 return;
1769         }
1770
1771         memcpy(skb_put(skb, size), buf, size);
1772
1773         skb->protocol = hdlc_type_trans(skb, dev);
1774
1775         dev->stats.rx_packets++;
1776         dev->stats.rx_bytes += size;
1777
1778         netif_rx(skb);
1779 }
1780
1781 static const struct net_device_ops hdlcdev_ops = {
1782         .ndo_open       = hdlcdev_open,
1783         .ndo_stop       = hdlcdev_close,
1784         .ndo_change_mtu = hdlc_change_mtu,
1785         .ndo_start_xmit = hdlc_start_xmit,
1786         .ndo_do_ioctl   = hdlcdev_ioctl,
1787         .ndo_tx_timeout = hdlcdev_tx_timeout,
1788 };
1789
1790 /**
1791  * called by device driver when adding device instance
1792  * do generic HDLC initialization
1793  *
1794  * info  pointer to device instance information
1795  *
1796  * returns 0 if success, otherwise error code
1797  */
1798 static int hdlcdev_init(struct slgt_info *info)
1799 {
1800         int rc;
1801         struct net_device *dev;
1802         hdlc_device *hdlc;
1803
1804         /* allocate and initialize network and HDLC layer objects */
1805
1806         if (!(dev = alloc_hdlcdev(info))) {
1807                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1808                 return -ENOMEM;
1809         }
1810
1811         /* for network layer reporting purposes only */
1812         dev->mem_start = info->phys_reg_addr;
1813         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1814         dev->irq       = info->irq_level;
1815
1816         /* network layer callbacks and settings */
1817         dev->netdev_ops     = &hdlcdev_ops;
1818         dev->watchdog_timeo = 10 * HZ;
1819         dev->tx_queue_len   = 50;
1820
1821         /* generic HDLC layer callbacks and settings */
1822         hdlc         = dev_to_hdlc(dev);
1823         hdlc->attach = hdlcdev_attach;
1824         hdlc->xmit   = hdlcdev_xmit;
1825
1826         /* register objects with HDLC layer */
1827         if ((rc = register_hdlc_device(dev))) {
1828                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1829                 free_netdev(dev);
1830                 return rc;
1831         }
1832
1833         info->netdev = dev;
1834         return 0;
1835 }
1836
1837 /**
1838  * called by device driver when removing device instance
1839  * do generic HDLC cleanup
1840  *
1841  * info  pointer to device instance information
1842  */
1843 static void hdlcdev_exit(struct slgt_info *info)
1844 {
1845         unregister_hdlc_device(info->netdev);
1846         free_netdev(info->netdev);
1847         info->netdev = NULL;
1848 }
1849
1850 #endif /* ifdef CONFIG_HDLC */
1851
1852 /*
1853  * get async data from rx DMA buffers
1854  */
1855 static void rx_async(struct slgt_info *info)
1856 {
1857         struct tty_struct *tty = info->port.tty;
1858         struct mgsl_icount *icount = &info->icount;
1859         unsigned int start, end;
1860         unsigned char *p;
1861         unsigned char status;
1862         struct slgt_desc *bufs = info->rbufs;
1863         int i, count;
1864         int chars = 0;
1865         int stat;
1866         unsigned char ch;
1867
1868         start = end = info->rbuf_current;
1869
1870         while(desc_complete(bufs[end])) {
1871                 count = desc_count(bufs[end]) - info->rbuf_index;
1872                 p     = bufs[end].buf + info->rbuf_index;
1873
1874                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1875                 DBGDATA(info, p, count, "rx");
1876
1877                 for(i=0 ; i < count; i+=2, p+=2) {
1878                         ch = *p;
1879                         icount->rx++;
1880
1881                         stat = 0;
1882
1883                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1884                                 if (status & BIT1)
1885                                         icount->parity++;
1886                                 else if (status & BIT0)
1887                                         icount->frame++;
1888                                 /* discard char if tty control flags say so */
1889                                 if (status & info->ignore_status_mask)
1890                                         continue;
1891                                 if (status & BIT1)
1892                                         stat = TTY_PARITY;
1893                                 else if (status & BIT0)
1894                                         stat = TTY_FRAME;
1895                         }
1896                         if (tty) {
1897                                 tty_insert_flip_char(tty, ch, stat);
1898                                 chars++;
1899                         }
1900                 }
1901
1902                 if (i < count) {
1903                         /* receive buffer not completed */
1904                         info->rbuf_index += i;
1905                         mod_timer(&info->rx_timer, jiffies + 1);
1906                         break;
1907                 }
1908
1909                 info->rbuf_index = 0;
1910                 free_rbufs(info, end, end);
1911
1912                 if (++end == info->rbuf_count)
1913                         end = 0;
1914
1915                 /* if entire list searched then no frame available */
1916                 if (end == start)
1917                         break;
1918         }
1919
1920         if (tty && chars)
1921                 tty_flip_buffer_push(tty);
1922 }
1923
1924 /*
1925  * return next bottom half action to perform
1926  */
1927 static int bh_action(struct slgt_info *info)
1928 {
1929         unsigned long flags;
1930         int rc;
1931
1932         spin_lock_irqsave(&info->lock,flags);
1933
1934         if (info->pending_bh & BH_RECEIVE) {
1935                 info->pending_bh &= ~BH_RECEIVE;
1936                 rc = BH_RECEIVE;
1937         } else if (info->pending_bh & BH_TRANSMIT) {
1938                 info->pending_bh &= ~BH_TRANSMIT;
1939                 rc = BH_TRANSMIT;
1940         } else if (info->pending_bh & BH_STATUS) {
1941                 info->pending_bh &= ~BH_STATUS;
1942                 rc = BH_STATUS;
1943         } else {
1944                 /* Mark BH routine as complete */
1945                 info->bh_running = false;
1946                 info->bh_requested = false;
1947                 rc = 0;
1948         }
1949
1950         spin_unlock_irqrestore(&info->lock,flags);
1951
1952         return rc;
1953 }
1954
1955 /*
1956  * perform bottom half processing
1957  */
1958 static void bh_handler(struct work_struct *work)
1959 {
1960         struct slgt_info *info = container_of(work, struct slgt_info, task);
1961         int action;
1962
1963         if (!info)
1964                 return;
1965         info->bh_running = true;
1966
1967         while((action = bh_action(info))) {
1968                 switch (action) {
1969                 case BH_RECEIVE:
1970                         DBGBH(("%s bh receive\n", info->device_name));
1971                         switch(info->params.mode) {
1972                         case MGSL_MODE_ASYNC:
1973                                 rx_async(info);
1974                                 break;
1975                         case MGSL_MODE_HDLC:
1976                                 while(rx_get_frame(info));
1977                                 break;
1978                         case MGSL_MODE_RAW:
1979                         case MGSL_MODE_MONOSYNC:
1980                         case MGSL_MODE_BISYNC:
1981                         case MGSL_MODE_XSYNC:
1982                                 while(rx_get_buf(info));
1983                                 break;
1984                         }
1985                         /* restart receiver if rx DMA buffers exhausted */
1986                         if (info->rx_restart)
1987                                 rx_start(info);
1988                         break;
1989                 case BH_TRANSMIT:
1990                         bh_transmit(info);
1991                         break;
1992                 case BH_STATUS:
1993                         DBGBH(("%s bh status\n", info->device_name));
1994                         info->ri_chkcount = 0;
1995                         info->dsr_chkcount = 0;
1996                         info->dcd_chkcount = 0;
1997                         info->cts_chkcount = 0;
1998                         break;
1999                 default:
2000                         DBGBH(("%s unknown action\n", info->device_name));
2001                         break;
2002                 }
2003         }
2004         DBGBH(("%s bh_handler exit\n", info->device_name));
2005 }
2006
2007 static void bh_transmit(struct slgt_info *info)
2008 {
2009         struct tty_struct *tty = info->port.tty;
2010
2011         DBGBH(("%s bh_transmit\n", info->device_name));
2012         if (tty)
2013                 tty_wakeup(tty);
2014 }
2015
2016 static void dsr_change(struct slgt_info *info, unsigned short status)
2017 {
2018         if (status & BIT3) {
2019                 info->signals |= SerialSignal_DSR;
2020                 info->input_signal_events.dsr_up++;
2021         } else {
2022                 info->signals &= ~SerialSignal_DSR;
2023                 info->input_signal_events.dsr_down++;
2024         }
2025         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2026         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2027                 slgt_irq_off(info, IRQ_DSR);
2028                 return;
2029         }
2030         info->icount.dsr++;
2031         wake_up_interruptible(&info->status_event_wait_q);
2032         wake_up_interruptible(&info->event_wait_q);
2033         info->pending_bh |= BH_STATUS;
2034 }
2035
2036 static void cts_change(struct slgt_info *info, unsigned short status)
2037 {
2038         if (status & BIT2) {
2039                 info->signals |= SerialSignal_CTS;
2040                 info->input_signal_events.cts_up++;
2041         } else {
2042                 info->signals &= ~SerialSignal_CTS;
2043                 info->input_signal_events.cts_down++;
2044         }
2045         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2046         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2047                 slgt_irq_off(info, IRQ_CTS);
2048                 return;
2049         }
2050         info->icount.cts++;
2051         wake_up_interruptible(&info->status_event_wait_q);
2052         wake_up_interruptible(&info->event_wait_q);
2053         info->pending_bh |= BH_STATUS;
2054
2055         if (tty_port_cts_enabled(&info->port)) {
2056                 if (info->port.tty) {
2057                         if (info->port.tty->hw_stopped) {
2058                                 if (info->signals & SerialSignal_CTS) {
2059                                         info->port.tty->hw_stopped = 0;
2060                                         info->pending_bh |= BH_TRANSMIT;
2061                                         return;
2062                                 }
2063                         } else {
2064                                 if (!(info->signals & SerialSignal_CTS))
2065                                         info->port.tty->hw_stopped = 1;
2066                         }
2067                 }
2068         }
2069 }
2070
2071 static void dcd_change(struct slgt_info *info, unsigned short status)
2072 {
2073         if (status & BIT1) {
2074                 info->signals |= SerialSignal_DCD;
2075                 info->input_signal_events.dcd_up++;
2076         } else {
2077                 info->signals &= ~SerialSignal_DCD;
2078                 info->input_signal_events.dcd_down++;
2079         }
2080         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2081         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2082                 slgt_irq_off(info, IRQ_DCD);
2083                 return;
2084         }
2085         info->icount.dcd++;
2086 #if SYNCLINK_GENERIC_HDLC
2087         if (info->netcount) {
2088                 if (info->signals & SerialSignal_DCD)
2089                         netif_carrier_on(info->netdev);
2090                 else
2091                         netif_carrier_off(info->netdev);
2092         }
2093 #endif
2094         wake_up_interruptible(&info->status_event_wait_q);
2095         wake_up_interruptible(&info->event_wait_q);
2096         info->pending_bh |= BH_STATUS;
2097
2098         if (info->port.flags & ASYNC_CHECK_CD) {
2099                 if (info->signals & SerialSignal_DCD)
2100                         wake_up_interruptible(&info->port.open_wait);
2101                 else {
2102                         if (info->port.tty)
2103                                 tty_hangup(info->port.tty);
2104                 }
2105         }
2106 }
2107
2108 static void ri_change(struct slgt_info *info, unsigned short status)
2109 {
2110         if (status & BIT0) {
2111                 info->signals |= SerialSignal_RI;
2112                 info->input_signal_events.ri_up++;
2113         } else {
2114                 info->signals &= ~SerialSignal_RI;
2115                 info->input_signal_events.ri_down++;
2116         }
2117         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2118         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2119                 slgt_irq_off(info, IRQ_RI);
2120                 return;
2121         }
2122         info->icount.rng++;
2123         wake_up_interruptible(&info->status_event_wait_q);
2124         wake_up_interruptible(&info->event_wait_q);
2125         info->pending_bh |= BH_STATUS;
2126 }
2127
2128 static void isr_rxdata(struct slgt_info *info)
2129 {
2130         unsigned int count = info->rbuf_fill_count;
2131         unsigned int i = info->rbuf_fill_index;
2132         unsigned short reg;
2133
2134         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2135                 reg = rd_reg16(info, RDR);
2136                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2137                 if (desc_complete(info->rbufs[i])) {
2138                         /* all buffers full */
2139                         rx_stop(info);
2140                         info->rx_restart = 1;
2141                         continue;
2142                 }
2143                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2144                 /* async mode saves status byte to buffer for each data byte */
2145                 if (info->params.mode == MGSL_MODE_ASYNC)
2146                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2147                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2148                         /* buffer full or end of frame */
2149                         set_desc_count(info->rbufs[i], count);
2150                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2151                         info->rbuf_fill_count = count = 0;
2152                         if (++i == info->rbuf_count)
2153                                 i = 0;
2154                         info->pending_bh |= BH_RECEIVE;
2155                 }
2156         }
2157
2158         info->rbuf_fill_index = i;
2159         info->rbuf_fill_count = count;
2160 }
2161
2162 static void isr_serial(struct slgt_info *info)
2163 {
2164         unsigned short status = rd_reg16(info, SSR);
2165
2166         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2167
2168         wr_reg16(info, SSR, status); /* clear pending */
2169
2170         info->irq_occurred = true;
2171
2172         if (info->params.mode == MGSL_MODE_ASYNC) {
2173                 if (status & IRQ_TXIDLE) {
2174                         if (info->tx_active)
2175                                 isr_txeom(info, status);
2176                 }
2177                 if (info->rx_pio && (status & IRQ_RXDATA))
2178                         isr_rxdata(info);
2179                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2180                         info->icount.brk++;
2181                         /* process break detection if tty control allows */
2182                         if (info->port.tty) {
2183                                 if (!(status & info->ignore_status_mask)) {
2184                                         if (info->read_status_mask & MASK_BREAK) {
2185                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2186                                                 if (info->port.flags & ASYNC_SAK)
2187                                                         do_SAK(info->port.tty);
2188                                         }
2189                                 }
2190                         }
2191                 }
2192         } else {
2193                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2194                         isr_txeom(info, status);
2195                 if (info->rx_pio && (status & IRQ_RXDATA))
2196                         isr_rxdata(info);
2197                 if (status & IRQ_RXIDLE) {
2198                         if (status & RXIDLE)
2199                                 info->icount.rxidle++;
2200                         else
2201                                 info->icount.exithunt++;
2202                         wake_up_interruptible(&info->event_wait_q);
2203                 }
2204
2205                 if (status & IRQ_RXOVER)
2206                         rx_start(info);
2207         }
2208
2209         if (status & IRQ_DSR)
2210                 dsr_change(info, status);
2211         if (status & IRQ_CTS)
2212                 cts_change(info, status);
2213         if (status & IRQ_DCD)
2214                 dcd_change(info, status);
2215         if (status & IRQ_RI)
2216                 ri_change(info, status);
2217 }
2218
2219 static void isr_rdma(struct slgt_info *info)
2220 {
2221         unsigned int status = rd_reg32(info, RDCSR);
2222
2223         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2224
2225         /* RDCSR (rx DMA control/status)
2226          *
2227          * 31..07  reserved
2228          * 06      save status byte to DMA buffer
2229          * 05      error
2230          * 04      eol (end of list)
2231          * 03      eob (end of buffer)
2232          * 02      IRQ enable
2233          * 01      reset
2234          * 00      enable
2235          */
2236         wr_reg32(info, RDCSR, status);  /* clear pending */
2237
2238         if (status & (BIT5 + BIT4)) {
2239                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2240                 info->rx_restart = true;
2241         }
2242         info->pending_bh |= BH_RECEIVE;
2243 }
2244
2245 static void isr_tdma(struct slgt_info *info)
2246 {
2247         unsigned int status = rd_reg32(info, TDCSR);
2248
2249         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2250
2251         /* TDCSR (tx DMA control/status)
2252          *
2253          * 31..06  reserved
2254          * 05      error
2255          * 04      eol (end of list)
2256          * 03      eob (end of buffer)
2257          * 02      IRQ enable
2258          * 01      reset
2259          * 00      enable
2260          */
2261         wr_reg32(info, TDCSR, status);  /* clear pending */
2262
2263         if (status & (BIT5 + BIT4 + BIT3)) {
2264                 // another transmit buffer has completed
2265                 // run bottom half to get more send data from user
2266                 info->pending_bh |= BH_TRANSMIT;
2267         }
2268 }
2269
2270 /*
2271  * return true if there are unsent tx DMA buffers, otherwise false
2272  *
2273  * if there are unsent buffers then info->tbuf_start
2274  * is set to index of first unsent buffer
2275  */
2276 static bool unsent_tbufs(struct slgt_info *info)
2277 {
2278         unsigned int i = info->tbuf_current;
2279         bool rc = false;
2280
2281         /*
2282          * search backwards from last loaded buffer (precedes tbuf_current)
2283          * for first unsent buffer (desc_count > 0)
2284          */
2285
2286         do {
2287                 if (i)
2288                         i--;
2289                 else
2290                         i = info->tbuf_count - 1;
2291                 if (!desc_count(info->tbufs[i]))
2292                         break;
2293                 info->tbuf_start = i;
2294                 rc = true;
2295         } while (i != info->tbuf_current);
2296
2297         return rc;
2298 }
2299
2300 static void isr_txeom(struct slgt_info *info, unsigned short status)
2301 {
2302         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2303
2304         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2305         tdma_reset(info);
2306         if (status & IRQ_TXUNDER) {
2307                 unsigned short val = rd_reg16(info, TCR);
2308                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2309                 wr_reg16(info, TCR, val); /* clear reset bit */
2310         }
2311
2312         if (info->tx_active) {
2313                 if (info->params.mode != MGSL_MODE_ASYNC) {
2314                         if (status & IRQ_TXUNDER)
2315                                 info->icount.txunder++;
2316                         else if (status & IRQ_TXIDLE)
2317                                 info->icount.txok++;
2318                 }
2319
2320                 if (unsent_tbufs(info)) {
2321                         tx_start(info);
2322                         update_tx_timer(info);
2323                         return;
2324                 }
2325                 info->tx_active = false;
2326
2327                 del_timer(&info->tx_timer);
2328
2329                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2330                         info->signals &= ~SerialSignal_RTS;
2331                         info->drop_rts_on_tx_done = false;
2332                         set_signals(info);
2333                 }
2334
2335 #if SYNCLINK_GENERIC_HDLC
2336                 if (info->netcount)
2337                         hdlcdev_tx_done(info);
2338                 else
2339 #endif
2340                 {
2341                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2342                                 tx_stop(info);
2343                                 return;
2344                         }
2345                         info->pending_bh |= BH_TRANSMIT;
2346                 }
2347         }
2348 }
2349
2350 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2351 {
2352         struct cond_wait *w, *prev;
2353
2354         /* wake processes waiting for specific transitions */
2355         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2356                 if (w->data & changed) {
2357                         w->data = state;
2358                         wake_up_interruptible(&w->q);
2359                         if (prev != NULL)
2360                                 prev->next = w->next;
2361                         else
2362                                 info->gpio_wait_q = w->next;
2363                 } else
2364                         prev = w;
2365         }
2366 }
2367
2368 /* interrupt service routine
2369  *
2370  *      irq     interrupt number
2371  *      dev_id  device ID supplied during interrupt registration
2372  */
2373 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2374 {
2375         struct slgt_info *info = dev_id;
2376         unsigned int gsr;
2377         unsigned int i;
2378
2379         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2380
2381         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2382                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2383                 info->irq_occurred = true;
2384                 for(i=0; i < info->port_count ; i++) {
2385                         if (info->port_array[i] == NULL)
2386                                 continue;
2387                         spin_lock(&info->port_array[i]->lock);
2388                         if (gsr & (BIT8 << i))
2389                                 isr_serial(info->port_array[i]);
2390                         if (gsr & (BIT16 << (i*2)))
2391                                 isr_rdma(info->port_array[i]);
2392                         if (gsr & (BIT17 << (i*2)))
2393                                 isr_tdma(info->port_array[i]);
2394                         spin_unlock(&info->port_array[i]->lock);
2395                 }
2396         }
2397
2398         if (info->gpio_present) {
2399                 unsigned int state;
2400                 unsigned int changed;
2401                 spin_lock(&info->lock);
2402                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2403                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2404                         /* read latched state of GPIO signals */
2405                         state = rd_reg32(info, IOVR);
2406                         /* clear pending GPIO interrupt bits */
2407                         wr_reg32(info, IOSR, changed);
2408                         for (i=0 ; i < info->port_count ; i++) {
2409                                 if (info->port_array[i] != NULL)
2410                                         isr_gpio(info->port_array[i], changed, state);
2411                         }
2412                 }
2413                 spin_unlock(&info->lock);
2414         }
2415
2416         for(i=0; i < info->port_count ; i++) {
2417                 struct slgt_info *port = info->port_array[i];
2418                 if (port == NULL)
2419                         continue;
2420                 spin_lock(&port->lock);
2421                 if ((port->port.count || port->netcount) &&
2422                     port->pending_bh && !port->bh_running &&
2423                     !port->bh_requested) {
2424                         DBGISR(("%s bh queued\n", port->device_name));
2425                         schedule_work(&port->task);
2426                         port->bh_requested = true;
2427                 }
2428                 spin_unlock(&port->lock);
2429         }
2430
2431         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2432         return IRQ_HANDLED;
2433 }
2434
2435 static int startup(struct slgt_info *info)
2436 {
2437         DBGINFO(("%s startup\n", info->device_name));
2438
2439         if (info->port.flags & ASYNC_INITIALIZED)
2440                 return 0;
2441
2442         if (!info->tx_buf) {
2443                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2444                 if (!info->tx_buf) {
2445                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2446                         return -ENOMEM;
2447                 }
2448         }
2449
2450         info->pending_bh = 0;
2451
2452         memset(&info->icount, 0, sizeof(info->icount));
2453
2454         /* program hardware for current parameters */
2455         change_params(info);
2456
2457         if (info->port.tty)
2458                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2459
2460         info->port.flags |= ASYNC_INITIALIZED;
2461
2462         return 0;
2463 }
2464
2465 /*
2466  *  called by close() and hangup() to shutdown hardware
2467  */
2468 static void shutdown(struct slgt_info *info)
2469 {
2470         unsigned long flags;
2471
2472         if (!(info->port.flags & ASYNC_INITIALIZED))
2473                 return;
2474
2475         DBGINFO(("%s shutdown\n", info->device_name));
2476
2477         /* clear status wait queue because status changes */
2478         /* can't happen after shutting down the hardware */
2479         wake_up_interruptible(&info->status_event_wait_q);
2480         wake_up_interruptible(&info->event_wait_q);
2481
2482         del_timer_sync(&info->tx_timer);
2483         del_timer_sync(&info->rx_timer);
2484
2485         kfree(info->tx_buf);
2486         info->tx_buf = NULL;
2487
2488         spin_lock_irqsave(&info->lock,flags);
2489
2490         tx_stop(info);
2491         rx_stop(info);
2492
2493         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2494
2495         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2496                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2497                 set_signals(info);
2498         }
2499
2500         flush_cond_wait(&info->gpio_wait_q);
2501
2502         spin_unlock_irqrestore(&info->lock,flags);
2503
2504         if (info->port.tty)
2505                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2506
2507         info->port.flags &= ~ASYNC_INITIALIZED;
2508 }
2509
2510 static void program_hw(struct slgt_info *info)
2511 {
2512         unsigned long flags;
2513
2514         spin_lock_irqsave(&info->lock,flags);
2515
2516         rx_stop(info);
2517         tx_stop(info);
2518
2519         if (info->params.mode != MGSL_MODE_ASYNC ||
2520             info->netcount)
2521                 sync_mode(info);
2522         else
2523                 async_mode(info);
2524
2525         set_signals(info);
2526
2527         info->dcd_chkcount = 0;
2528         info->cts_chkcount = 0;
2529         info->ri_chkcount = 0;
2530         info->dsr_chkcount = 0;
2531
2532         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2533         get_signals(info);
2534
2535         if (info->netcount ||
2536             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2537                 rx_start(info);
2538
2539         spin_unlock_irqrestore(&info->lock,flags);
2540 }
2541
2542 /*
2543  * reconfigure adapter based on new parameters
2544  */
2545 static void change_params(struct slgt_info *info)
2546 {
2547         unsigned cflag;
2548         int bits_per_char;
2549
2550         if (!info->port.tty)
2551                 return;
2552         DBGINFO(("%s change_params\n", info->device_name));
2553
2554         cflag = info->port.tty->termios.c_cflag;
2555
2556         /* if B0 rate (hangup) specified then negate DTR and RTS */
2557         /* otherwise assert DTR and RTS */
2558         if (cflag & CBAUD)
2559                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2560         else
2561                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2562
2563         /* byte size and parity */
2564
2565         switch (cflag & CSIZE) {
2566         case CS5: info->params.data_bits = 5; break;
2567         case CS6: info->params.data_bits = 6; break;
2568         case CS7: info->params.data_bits = 7; break;
2569         case CS8: info->params.data_bits = 8; break;
2570         default:  info->params.data_bits = 7; break;
2571         }
2572
2573         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2574
2575         if (cflag & PARENB)
2576                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2577         else
2578                 info->params.parity = ASYNC_PARITY_NONE;
2579
2580         /* calculate number of jiffies to transmit a full
2581          * FIFO (32 bytes) at specified data rate
2582          */
2583         bits_per_char = info->params.data_bits +
2584                         info->params.stop_bits + 1;
2585
2586         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2587
2588         if (info->params.data_rate) {
2589                 info->timeout = (32*HZ*bits_per_char) /
2590                                 info->params.data_rate;
2591         }
2592         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2593
2594         if (cflag & CRTSCTS)
2595                 info->port.flags |= ASYNC_CTS_FLOW;
2596         else
2597                 info->port.flags &= ~ASYNC_CTS_FLOW;
2598
2599         if (cflag & CLOCAL)
2600                 info->port.flags &= ~ASYNC_CHECK_CD;
2601         else
2602                 info->port.flags |= ASYNC_CHECK_CD;
2603
2604         /* process tty input control flags */
2605
2606         info->read_status_mask = IRQ_RXOVER;
2607         if (I_INPCK(info->port.tty))
2608                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2609         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2610                 info->read_status_mask |= MASK_BREAK;
2611         if (I_IGNPAR(info->port.tty))
2612                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2613         if (I_IGNBRK(info->port.tty)) {
2614                 info->ignore_status_mask |= MASK_BREAK;
2615                 /* If ignoring parity and break indicators, ignore
2616                  * overruns too.  (For real raw support).
2617                  */
2618                 if (I_IGNPAR(info->port.tty))
2619                         info->ignore_status_mask |= MASK_OVERRUN;
2620         }
2621
2622         program_hw(info);
2623 }
2624
2625 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2626 {
2627         DBGINFO(("%s get_stats\n",  info->device_name));
2628         if (!user_icount) {
2629                 memset(&info->icount, 0, sizeof(info->icount));
2630         } else {
2631                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2632                         return -EFAULT;
2633         }
2634         return 0;
2635 }
2636
2637 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2638 {
2639         DBGINFO(("%s get_params\n", info->device_name));
2640         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2641                 return -EFAULT;
2642         return 0;
2643 }
2644
2645 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2646 {
2647         unsigned long flags;
2648         MGSL_PARAMS tmp_params;
2649
2650         DBGINFO(("%s set_params\n", info->device_name));
2651         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2652                 return -EFAULT;
2653
2654         spin_lock_irqsave(&info->lock, flags);
2655         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2656                 info->base_clock = tmp_params.clock_speed;
2657         else
2658                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2659         spin_unlock_irqrestore(&info->lock, flags);
2660
2661         program_hw(info);
2662
2663         return 0;
2664 }
2665
2666 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2667 {
2668         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2669         if (put_user(info->idle_mode, idle_mode))
2670                 return -EFAULT;
2671         return 0;
2672 }
2673
2674 static int set_txidle(struct slgt_info *info, int idle_mode)
2675 {
2676         unsigned long flags;
2677         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2678         spin_lock_irqsave(&info->lock,flags);
2679         info->idle_mode = idle_mode;
2680         if (info->params.mode != MGSL_MODE_ASYNC)
2681                 tx_set_idle(info);
2682         spin_unlock_irqrestore(&info->lock,flags);
2683         return 0;
2684 }
2685
2686 static int tx_enable(struct slgt_info *info, int enable)
2687 {
2688         unsigned long flags;
2689         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2690         spin_lock_irqsave(&info->lock,flags);
2691         if (enable) {
2692                 if (!info->tx_enabled)
2693                         tx_start(info);
2694         } else {
2695                 if (info->tx_enabled)
2696                         tx_stop(info);
2697         }
2698         spin_unlock_irqrestore(&info->lock,flags);
2699         return 0;
2700 }
2701
2702 /*
2703  * abort transmit HDLC frame
2704  */
2705 static int tx_abort(struct slgt_info *info)
2706 {
2707         unsigned long flags;
2708         DBGINFO(("%s tx_abort\n", info->device_name));
2709         spin_lock_irqsave(&info->lock,flags);
2710         tdma_reset(info);
2711         spin_unlock_irqrestore(&info->lock,flags);
2712         return 0;
2713 }
2714
2715 static int rx_enable(struct slgt_info *info, int enable)
2716 {
2717         unsigned long flags;
2718         unsigned int rbuf_fill_level;
2719         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2720         spin_lock_irqsave(&info->lock,flags);
2721         /*
2722          * enable[31..16] = receive DMA buffer fill level
2723          * 0 = noop (leave fill level unchanged)
2724          * fill level must be multiple of 4 and <= buffer size
2725          */
2726         rbuf_fill_level = ((unsigned int)enable) >> 16;
2727         if (rbuf_fill_level) {
2728                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2729                         spin_unlock_irqrestore(&info->lock, flags);
2730                         return -EINVAL;
2731                 }
2732                 info->rbuf_fill_level = rbuf_fill_level;
2733                 if (rbuf_fill_level < 128)
2734                         info->rx_pio = 1; /* PIO mode */
2735                 else
2736                         info->rx_pio = 0; /* DMA mode */
2737                 rx_stop(info); /* restart receiver to use new fill level */
2738         }
2739
2740         /*
2741          * enable[1..0] = receiver enable command
2742          * 0 = disable
2743          * 1 = enable
2744          * 2 = enable or force hunt mode if already enabled
2745          */
2746         enable &= 3;
2747         if (enable) {
2748                 if (!info->rx_enabled)
2749                         rx_start(info);
2750                 else if (enable == 2) {
2751                         /* force hunt mode (write 1 to RCR[3]) */
2752                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2753                 }
2754         } else {
2755                 if (info->rx_enabled)
2756                         rx_stop(info);
2757         }
2758         spin_unlock_irqrestore(&info->lock,flags);
2759         return 0;
2760 }
2761
2762 /*
2763  *  wait for specified event to occur
2764  */
2765 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2766 {
2767         unsigned long flags;
2768         int s;
2769         int rc=0;
2770         struct mgsl_icount cprev, cnow;
2771         int events;
2772         int mask;
2773         struct  _input_signal_events oldsigs, newsigs;
2774         DECLARE_WAITQUEUE(wait, current);
2775
2776         if (get_user(mask, mask_ptr))
2777                 return -EFAULT;
2778
2779         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2780
2781         spin_lock_irqsave(&info->lock,flags);
2782
2783         /* return immediately if state matches requested events */
2784         get_signals(info);
2785         s = info->signals;
2786
2787         events = mask &
2788                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2789                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2790                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2791                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2792         if (events) {
2793                 spin_unlock_irqrestore(&info->lock,flags);
2794                 goto exit;
2795         }
2796
2797         /* save current irq counts */
2798         cprev = info->icount;
2799         oldsigs = info->input_signal_events;
2800
2801         /* enable hunt and idle irqs if needed */
2802         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2803                 unsigned short val = rd_reg16(info, SCR);
2804                 if (!(val & IRQ_RXIDLE))
2805                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2806         }
2807
2808         set_current_state(TASK_INTERRUPTIBLE);
2809         add_wait_queue(&info->event_wait_q, &wait);
2810
2811         spin_unlock_irqrestore(&info->lock,flags);
2812
2813         for(;;) {
2814                 schedule();
2815                 if (signal_pending(current)) {
2816                         rc = -ERESTARTSYS;
2817                         break;
2818                 }
2819
2820                 /* get current irq counts */
2821                 spin_lock_irqsave(&info->lock,flags);
2822                 cnow = info->icount;
2823                 newsigs = info->input_signal_events;
2824                 set_current_state(TASK_INTERRUPTIBLE);
2825                 spin_unlock_irqrestore(&info->lock,flags);
2826
2827                 /* if no change, wait aborted for some reason */
2828                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2829                     newsigs.dsr_down == oldsigs.dsr_down &&
2830                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2831                     newsigs.dcd_down == oldsigs.dcd_down &&
2832                     newsigs.cts_up   == oldsigs.cts_up   &&
2833                     newsigs.cts_down == oldsigs.cts_down &&
2834                     newsigs.ri_up    == oldsigs.ri_up    &&
2835                     newsigs.ri_down  == oldsigs.ri_down  &&
2836                     cnow.exithunt    == cprev.exithunt   &&
2837                     cnow.rxidle      == cprev.rxidle) {
2838                         rc = -EIO;
2839                         break;
2840                 }
2841
2842                 events = mask &
2843                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2844                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2845                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2846                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2847                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2848                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2849                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2850                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2851                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2852                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2853                 if (events)
2854                         break;
2855
2856                 cprev = cnow;
2857                 oldsigs = newsigs;
2858         }
2859
2860         remove_wait_queue(&info->event_wait_q, &wait);
2861         set_current_state(TASK_RUNNING);
2862
2863
2864         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2865                 spin_lock_irqsave(&info->lock,flags);
2866                 if (!waitqueue_active(&info->event_wait_q)) {
2867                         /* disable enable exit hunt mode/idle rcvd IRQs */
2868                         wr_reg16(info, SCR,
2869                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2870                 }
2871                 spin_unlock_irqrestore(&info->lock,flags);
2872         }
2873 exit:
2874         if (rc == 0)
2875                 rc = put_user(events, mask_ptr);
2876         return rc;
2877 }
2878
2879 static int get_interface(struct slgt_info *info, int __user *if_mode)
2880 {
2881         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2882         if (put_user(info->if_mode, if_mode))
2883                 return -EFAULT;
2884         return 0;
2885 }
2886
2887 static int set_interface(struct slgt_info *info, int if_mode)
2888 {
2889         unsigned long flags;
2890         unsigned short val;
2891
2892         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2893         spin_lock_irqsave(&info->lock,flags);
2894         info->if_mode = if_mode;
2895
2896         msc_set_vcr(info);
2897
2898         /* TCR (tx control) 07  1=RTS driver control */
2899         val = rd_reg16(info, TCR);
2900         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2901                 val |= BIT7;
2902         else
2903                 val &= ~BIT7;
2904         wr_reg16(info, TCR, val);
2905
2906         spin_unlock_irqrestore(&info->lock,flags);
2907         return 0;
2908 }
2909
2910 static int get_xsync(struct slgt_info *info, int __user *xsync)
2911 {
2912         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2913         if (put_user(info->xsync, xsync))
2914                 return -EFAULT;
2915         return 0;
2916 }
2917
2918 /*
2919  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2920  *
2921  * sync pattern is contained in least significant bytes of value
2922  * most significant byte of sync pattern is oldest (1st sent/detected)
2923  */
2924 static int set_xsync(struct slgt_info *info, int xsync)
2925 {
2926         unsigned long flags;
2927
2928         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2929         spin_lock_irqsave(&info->lock, flags);
2930         info->xsync = xsync;
2931         wr_reg32(info, XSR, xsync);
2932         spin_unlock_irqrestore(&info->lock, flags);
2933         return 0;
2934 }
2935
2936 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2937 {
2938         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2939         if (put_user(info->xctrl, xctrl))
2940                 return -EFAULT;
2941         return 0;
2942 }
2943
2944 /*
2945  * set extended control options
2946  *
2947  * xctrl[31:19] reserved, must be zero
2948  * xctrl[18:17] extended sync pattern length in bytes
2949  *              00 = 1 byte  in xsr[7:0]
2950  *              01 = 2 bytes in xsr[15:0]
2951  *              10 = 3 bytes in xsr[23:0]
2952  *              11 = 4 bytes in xsr[31:0]
2953  * xctrl[16]    1 = enable terminal count, 0=disabled
2954  * xctrl[15:0]  receive terminal count for fixed length packets
2955  *              value is count minus one (0 = 1 byte packet)
2956  *              when terminal count is reached, receiver
2957  *              automatically returns to hunt mode and receive
2958  *              FIFO contents are flushed to DMA buffers with
2959  *              end of frame (EOF) status
2960  */
2961 static int set_xctrl(struct slgt_info *info, int xctrl)
2962 {
2963         unsigned long flags;
2964
2965         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2966         spin_lock_irqsave(&info->lock, flags);
2967         info->xctrl = xctrl;
2968         wr_reg32(info, XCR, xctrl);
2969         spin_unlock_irqrestore(&info->lock, flags);
2970         return 0;
2971 }
2972
2973 /*
2974  * set general purpose IO pin state and direction
2975  *
2976  * user_gpio fields:
2977  * state   each bit indicates a pin state
2978  * smask   set bit indicates pin state to set
2979  * dir     each bit indicates a pin direction (0=input, 1=output)
2980  * dmask   set bit indicates pin direction to set
2981  */
2982 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2983 {
2984         unsigned long flags;
2985         struct gpio_desc gpio;
2986         __u32 data;
2987
2988         if (!info->gpio_present)
2989                 return -EINVAL;
2990         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2991                 return -EFAULT;
2992         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2993                  info->device_name, gpio.state, gpio.smask,
2994                  gpio.dir, gpio.dmask));
2995
2996         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2997         if (gpio.dmask) {
2998                 data = rd_reg32(info, IODR);
2999                 data |= gpio.dmask & gpio.dir;
3000                 data &= ~(gpio.dmask & ~gpio.dir);
3001                 wr_reg32(info, IODR, data);
3002         }
3003         if (gpio.smask) {
3004                 data = rd_reg32(info, IOVR);
3005                 data |= gpio.smask & gpio.state;
3006                 data &= ~(gpio.smask & ~gpio.state);
3007                 wr_reg32(info, IOVR, data);
3008         }
3009         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3010
3011         return 0;
3012 }
3013
3014 /*
3015  * get general purpose IO pin state and direction
3016  */
3017 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3018 {
3019         struct gpio_desc gpio;
3020         if (!info->gpio_present)
3021                 return -EINVAL;
3022         gpio.state = rd_reg32(info, IOVR);
3023         gpio.smask = 0xffffffff;
3024         gpio.dir   = rd_reg32(info, IODR);
3025         gpio.dmask = 0xffffffff;
3026         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3027                 return -EFAULT;
3028         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3029                  info->device_name, gpio.state, gpio.dir));
3030         return 0;
3031 }
3032
3033 /*
3034  * conditional wait facility
3035  */
3036 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3037 {
3038         init_waitqueue_head(&w->q);
3039         init_waitqueue_entry(&w->wait, current);
3040         w->data = data;
3041 }
3042
3043 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3044 {
3045         set_current_state(TASK_INTERRUPTIBLE);
3046         add_wait_queue(&w->q, &w->wait);
3047         w->next = *head;
3048         *head = w;
3049 }
3050
3051 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3052 {
3053         struct cond_wait *w, *prev;
3054         remove_wait_queue(&cw->q, &cw->wait);
3055         set_current_state(TASK_RUNNING);
3056         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3057                 if (w == cw) {
3058                         if (prev != NULL)
3059                                 prev->next = w->next;
3060                         else
3061                                 *head = w->next;
3062                         break;
3063                 }
3064         }
3065 }
3066
3067 static void flush_cond_wait(struct cond_wait **head)
3068 {
3069         while (*head != NULL) {
3070                 wake_up_interruptible(&(*head)->q);
3071                 *head = (*head)->next;
3072         }
3073 }
3074
3075 /*
3076  * wait for general purpose I/O pin(s) to enter specified state
3077  *
3078  * user_gpio fields:
3079  * state - bit indicates target pin state
3080  * smask - set bit indicates watched pin
3081  *
3082  * The wait ends when at least one watched pin enters the specified
3083  * state. When 0 (no error) is returned, user_gpio->state is set to the
3084  * state of all GPIO pins when the wait ends.
3085  *
3086  * Note: Each pin may be a dedicated input, dedicated output, or
3087  * configurable input/output. The number and configuration of pins
3088  * varies with the specific adapter model. Only input pins (dedicated
3089  * or configured) can be monitored with this function.
3090  */
3091 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3092 {
3093         unsigned long flags;
3094         int rc = 0;
3095         struct gpio_desc gpio;
3096         struct cond_wait wait;
3097         u32 state;
3098
3099         if (!info->gpio_present)
3100                 return -EINVAL;
3101         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3102                 return -EFAULT;
3103         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3104                  info->device_name, gpio.state, gpio.smask));
3105         /* ignore output pins identified by set IODR bit */
3106         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3107                 return -EINVAL;
3108         init_cond_wait(&wait, gpio.smask);
3109
3110         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3111         /* enable interrupts for watched pins */
3112         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3113         /* get current pin states */
3114         state = rd_reg32(info, IOVR);
3115
3116         if (gpio.smask & ~(state ^ gpio.state)) {
3117                 /* already in target state */
3118                 gpio.state = state;
3119         } else {
3120                 /* wait for target state */
3121                 add_cond_wait(&info->gpio_wait_q, &wait);
3122                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3123                 schedule();
3124                 if (signal_pending(current))
3125                         rc = -ERESTARTSYS;
3126                 else
3127                         gpio.state = wait.data;
3128                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3129                 remove_cond_wait(&info->gpio_wait_q, &wait);
3130         }
3131
3132         /* disable all GPIO interrupts if no waiting processes */
3133         if (info->gpio_wait_q == NULL)
3134                 wr_reg32(info, IOER, 0);
3135         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3136
3137         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3138                 rc = -EFAULT;
3139         return rc;
3140 }
3141
3142 static int modem_input_wait(struct slgt_info *info,int arg)
3143 {
3144         unsigned long flags;
3145         int rc;
3146         struct mgsl_icount cprev, cnow;
3147         DECLARE_WAITQUEUE(wait, current);
3148
3149         /* save current irq counts */
3150         spin_lock_irqsave(&info->lock,flags);
3151         cprev = info->icount;
3152         add_wait_queue(&info->status_event_wait_q, &wait);
3153         set_current_state(TASK_INTERRUPTIBLE);
3154         spin_unlock_irqrestore(&info->lock,flags);
3155
3156         for(;;) {
3157                 schedule();
3158                 if (signal_pending(current)) {
3159                         rc = -ERESTARTSYS;
3160                         break;
3161                 }
3162
3163                 /* get new irq counts */
3164                 spin_lock_irqsave(&info->lock,flags);
3165                 cnow = info->icount;
3166                 set_current_state(TASK_INTERRUPTIBLE);
3167                 spin_unlock_irqrestore(&info->lock,flags);
3168
3169                 /* if no change, wait aborted for some reason */
3170                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3171                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3172                         rc = -EIO;
3173                         break;
3174                 }
3175
3176                 /* check for change in caller specified modem input */
3177                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3178                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3179                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3180                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3181                         rc = 0;
3182                         break;
3183                 }
3184
3185                 cprev = cnow;
3186         }
3187         remove_wait_queue(&info->status_event_wait_q, &wait);
3188         set_current_state(TASK_RUNNING);
3189         return rc;
3190 }
3191
3192 /*
3193  *  return state of serial control and status signals
3194  */
3195 static int tiocmget(struct tty_struct *tty)
3196 {
3197         struct slgt_info *info = tty->driver_data;
3198         unsigned int result;
3199         unsigned long flags;
3200
3201         spin_lock_irqsave(&info->lock,flags);
3202         get_signals(info);
3203         spin_unlock_irqrestore(&info->lock,flags);
3204
3205         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3206                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3207                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3208                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3209                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3210                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3211
3212         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3213         return result;
3214 }
3215
3216 /*
3217  * set modem control signals (DTR/RTS)
3218  *
3219  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3220  *              TIOCMSET = set/clear signal values
3221  *      value   bit mask for command
3222  */
3223 static int tiocmset(struct tty_struct *tty,
3224                     unsigned int set, unsigned int clear)
3225 {
3226         struct slgt_info *info = tty->driver_data;
3227         unsigned long flags;
3228
3229         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3230
3231         if (set & TIOCM_RTS)
3232                 info->signals |= SerialSignal_RTS;
3233         if (set & TIOCM_DTR)
3234                 info->signals |= SerialSignal_DTR;
3235         if (clear & TIOCM_RTS)
3236                 info->signals &= ~SerialSignal_RTS;
3237         if (clear & TIOCM_DTR)
3238                 info->signals &= ~SerialSignal_DTR;
3239
3240         spin_lock_irqsave(&info->lock,flags);
3241         set_signals(info);
3242         spin_unlock_irqrestore(&info->lock,flags);
3243         return 0;
3244 }
3245
3246 static int carrier_raised(struct tty_port *port)
3247 {
3248         unsigned long flags;
3249         struct slgt_info *info = container_of(port, struct slgt_info, port);
3250
3251         spin_lock_irqsave(&info->lock,flags);
3252         get_signals(info);
3253         spin_unlock_irqrestore(&info->lock,flags);
3254         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3255 }
3256
3257 static void dtr_rts(struct tty_port *port, int on)
3258 {
3259         unsigned long flags;
3260         struct slgt_info *info = container_of(port, struct slgt_info, port);
3261
3262         spin_lock_irqsave(&info->lock,flags);
3263         if (on)
3264                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3265         else
3266                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3267         set_signals(info);
3268         spin_unlock_irqrestore(&info->lock,flags);
3269 }
3270
3271
3272 /*
3273  *  block current process until the device is ready to open
3274  */
3275 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3276                            struct slgt_info *info)
3277 {
3278         DECLARE_WAITQUEUE(wait, current);
3279         int             retval;
3280         bool            do_clocal = false;
3281         bool            extra_count = false;
3282         unsigned long   flags;
3283         int             cd;
3284         struct tty_port *port = &info->port;
3285
3286         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3287
3288         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3289                 /* nonblock mode is set or port is not enabled */
3290                 port->flags |= ASYNC_NORMAL_ACTIVE;
3291                 return 0;
3292         }
3293
3294         if (tty->termios.c_cflag & CLOCAL)
3295                 do_clocal = true;
3296
3297         /* Wait for carrier detect and the line to become
3298          * free (i.e., not in use by the callout).  While we are in
3299          * this loop, port->count is dropped by one, so that
3300          * close() knows when to free things.  We restore it upon
3301          * exit, either normal or abnormal.
3302          */
3303
3304         retval = 0;
3305         add_wait_queue(&port->open_wait, &wait);
3306
3307         spin_lock_irqsave(&info->lock, flags);
3308         if (!tty_hung_up_p(filp)) {
3309                 extra_count = true;
3310                 port->count--;
3311         }
3312         spin_unlock_irqrestore(&info->lock, flags);
3313         port->blocked_open++;
3314
3315         while (1) {
3316                 if ((tty->termios.c_cflag & CBAUD))
3317                         tty_port_raise_dtr_rts(port);
3318
3319                 set_current_state(TASK_INTERRUPTIBLE);
3320
3321                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3322                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3323                                         -EAGAIN : -ERESTARTSYS;
3324                         break;
3325                 }
3326
3327                 cd = tty_port_carrier_raised(port);
3328
3329                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3330                         break;
3331
3332                 if (signal_pending(current)) {
3333                         retval = -ERESTARTSYS;
3334                         break;
3335                 }
3336
3337                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3338                 tty_unlock(tty);
3339                 schedule();
3340                 tty_lock(tty);
3341         }
3342
3343         set_current_state(TASK_RUNNING);
3344         remove_wait_queue(&port->open_wait, &wait);
3345
3346         if (extra_count)
3347                 port->count++;
3348         port->blocked_open--;
3349
3350         if (!retval)
3351                 port->flags |= ASYNC_NORMAL_ACTIVE;
3352
3353         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3354         return retval;
3355 }
3356
3357 /*
3358  * allocate buffers used for calling line discipline receive_buf
3359  * directly in synchronous mode
3360  * note: add 5 bytes to max frame size to allow appending
3361  * 32-bit CRC and status byte when configured to do so
3362  */
3363 static int alloc_tmp_rbuf(struct slgt_info *info)
3364 {
3365         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3366         if (info->tmp_rbuf == NULL)
3367                 return -ENOMEM;
3368         /* unused flag buffer to satisfy receive_buf calling interface */
3369         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3370         if (!info->flag_buf) {
3371                 kfree(info->tmp_rbuf);
3372                 info->tmp_rbuf = NULL;
3373                 return -ENOMEM;
3374         }
3375         return 0;
3376 }
3377
3378 static void free_tmp_rbuf(struct slgt_info *info)
3379 {
3380         kfree(info->tmp_rbuf);
3381         info->tmp_rbuf = NULL;
3382         kfree(info->flag_buf);
3383         info->flag_buf = NULL;
3384 }
3385
3386 /*
3387  * allocate DMA descriptor lists.
3388  */
3389 static int alloc_desc(struct slgt_info *info)
3390 {
3391         unsigned int i;
3392         unsigned int pbufs;
3393
3394         /* allocate memory to hold descriptor lists */
3395         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3396         if (info->bufs == NULL)
3397                 return -ENOMEM;
3398
3399         memset(info->bufs, 0, DESC_LIST_SIZE);
3400
3401         info->rbufs = (struct slgt_desc*)info->bufs;
3402         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3403
3404         pbufs = (unsigned int)info->bufs_dma_addr;
3405
3406         /*
3407          * Build circular lists of descriptors
3408          */
3409
3410         for (i=0; i < info->rbuf_count; i++) {
3411                 /* physical address of this descriptor */
3412                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3413
3414                 /* physical address of next descriptor */
3415                 if (i == info->rbuf_count - 1)
3416                         info->rbufs[i].next = cpu_to_le32(pbufs);
3417                 else
3418                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3419                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3420         }
3421
3422         for (i=0; i < info->tbuf_count; i++) {
3423                 /* physical address of this descriptor */
3424                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3425
3426                 /* physical address of next descriptor */
3427                 if (i == info->tbuf_count - 1)
3428                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3429                 else
3430                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3431         }
3432
3433         return 0;
3434 }
3435
3436 static void free_desc(struct slgt_info *info)
3437 {
3438         if (info->bufs != NULL) {
3439                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3440                 info->bufs  = NULL;
3441                 info->rbufs = NULL;
3442                 info->tbufs = NULL;
3443         }
3444 }
3445
3446 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3447 {
3448         int i;
3449         for (i=0; i < count; i++) {
3450                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3451                         return -ENOMEM;
3452                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3453         }
3454         return 0;
3455 }
3456
3457 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3458 {
3459         int i;
3460         for (i=0; i < count; i++) {
3461                 if (bufs[i].buf == NULL)
3462                         continue;
3463                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3464                 bufs[i].buf = NULL;
3465         }
3466 }
3467
3468 static int alloc_dma_bufs(struct slgt_info *info)
3469 {
3470         info->rbuf_count = 32;
3471         info->tbuf_count = 32;
3472
3473         if (alloc_desc(info) < 0 ||
3474             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3475             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3476             alloc_tmp_rbuf(info) < 0) {
3477                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3478                 return -ENOMEM;
3479         }
3480         reset_rbufs(info);
3481         return 0;
3482 }
3483
3484 static void free_dma_bufs(struct slgt_info *info)
3485 {
3486         if (info->bufs) {
3487                 free_bufs(info, info->rbufs, info->rbuf_count);
3488                 free_bufs(info, info->tbufs, info->tbuf_count);
3489                 free_desc(info);
3490         }
3491         free_tmp_rbuf(info);
3492 }
3493
3494 static int claim_resources(struct slgt_info *info)
3495 {
3496         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3497                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3498                         info->device_name, info->phys_reg_addr));
3499                 info->init_error = DiagStatus_AddressConflict;
3500                 goto errout;
3501         }
3502         else
3503                 info->reg_addr_requested = true;
3504
3505         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3506         if (!info->reg_addr) {
3507                 DBGERR(("%s can't map device registers, addr=%08X\n",
3508                         info->device_name, info->phys_reg_addr));
3509                 info->init_error = DiagStatus_CantAssignPciResources;
3510                 goto errout;
3511         }
3512         return 0;
3513
3514 errout:
3515         release_resources(info);
3516         return -ENODEV;
3517 }
3518
3519 static void release_resources(struct slgt_info *info)
3520 {
3521         if (info->irq_requested) {
3522                 free_irq(info->irq_level, info);
3523                 info->irq_requested = false;
3524         }
3525
3526         if (info->reg_addr_requested) {
3527                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3528                 info->reg_addr_requested = false;
3529         }
3530
3531         if (info->reg_addr) {
3532                 iounmap(info->reg_addr);
3533                 info->reg_addr = NULL;
3534         }
3535 }
3536
3537 /* Add the specified device instance data structure to the
3538  * global linked list of devices and increment the device count.
3539  */
3540 static void add_device(struct slgt_info *info)
3541 {
3542         char *devstr;
3543
3544         info->next_device = NULL;
3545         info->line = slgt_device_count;
3546         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3547
3548         if (info->line < MAX_DEVICES) {
3549                 if (maxframe[info->line])
3550                         info->max_frame_size = maxframe[info->line];
3551         }
3552
3553         slgt_device_count++;
3554
3555         if (!slgt_device_list)
3556                 slgt_device_list = info;
3557         else {
3558                 struct slgt_info *current_dev = slgt_device_list;
3559                 while(current_dev->next_device)
3560                         current_dev = current_dev->next_device;
3561                 current_dev->next_device = info;
3562         }
3563
3564         if (info->max_frame_size < 4096)
3565                 info->max_frame_size = 4096;
3566         else if (info->max_frame_size > 65535)
3567                 info->max_frame_size = 65535;
3568
3569         switch(info->pdev->device) {
3570         case SYNCLINK_GT_DEVICE_ID:
3571                 devstr = "GT";
3572                 break;
3573         case SYNCLINK_GT2_DEVICE_ID:
3574                 devstr = "GT2";
3575                 break;
3576         case SYNCLINK_GT4_DEVICE_ID:
3577                 devstr = "GT4";
3578                 break;
3579         case SYNCLINK_AC_DEVICE_ID:
3580                 devstr = "AC";
3581                 info->params.mode = MGSL_MODE_ASYNC;
3582                 break;
3583         default:
3584                 devstr = "(unknown model)";
3585         }
3586         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3587                 devstr, info->device_name, info->phys_reg_addr,
3588                 info->irq_level, info->max_frame_size);
3589
3590 #if SYNCLINK_GENERIC_HDLC
3591         hdlcdev_init(info);
3592 #endif
3593 }
3594
3595 static const struct tty_port_operations slgt_port_ops = {
3596         .carrier_raised = carrier_raised,
3597         .dtr_rts = dtr_rts,
3598 };
3599
3600 /*
3601  *  allocate device instance structure, return NULL on failure
3602  */
3603 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3604 {
3605         struct slgt_info *info;
3606
3607         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3608
3609         if (!info) {
3610                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3611                         driver_name, adapter_num, port_num));
3612         } else {
3613                 tty_port_init(&info->port);
3614                 info->port.ops = &slgt_port_ops;
3615                 info->magic = MGSL_MAGIC;
3616                 INIT_WORK(&info->task, bh_handler);
3617                 info->max_frame_size = 4096;
3618                 info->base_clock = 14745600;
3619                 info->rbuf_fill_level = DMABUFSIZE;
3620                 info->port.close_delay = 5*HZ/10;
3621                 info->port.closing_wait = 30*HZ;
3622                 init_waitqueue_head(&info->status_event_wait_q);
3623                 init_waitqueue_head(&info->event_wait_q);
3624                 spin_lock_init(&info->netlock);
3625                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3626                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3627                 info->adapter_num = adapter_num;
3628                 info->port_num = port_num;
3629
3630                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3631                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3632
3633                 /* Copy configuration info to device instance data */
3634                 info->pdev = pdev;
3635                 info->irq_level = pdev->irq;
3636                 info->phys_reg_addr = pci_resource_start(pdev,0);
3637
3638                 info->bus_type = MGSL_BUS_TYPE_PCI;
3639                 info->irq_flags = IRQF_SHARED;
3640
3641                 info->init_error = -1; /* assume error, set to 0 on successful init */
3642         }
3643
3644         return info;
3645 }
3646
3647 static void device_init(int adapter_num, struct pci_dev *pdev)
3648 {
3649         struct slgt_info *port_array[SLGT_MAX_PORTS];
3650         int i;
3651         int port_count = 1;
3652
3653         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3654                 port_count = 2;
3655         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3656                 port_count = 4;
3657
3658         /* allocate device instances for all ports */
3659         for (i=0; i < port_count; ++i) {
3660                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3661                 if (port_array[i] == NULL) {
3662                         for (--i; i >= 0; --i) {
3663                                 tty_port_destroy(&port_array[i]->port);
3664                                 kfree(port_array[i]);
3665                         }
3666                         return;
3667                 }
3668         }
3669
3670         /* give copy of port_array to all ports and add to device list  */
3671         for (i=0; i < port_count; ++i) {
3672                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3673                 add_device(port_array[i]);
3674                 port_array[i]->port_count = port_count;
3675                 spin_lock_init(&port_array[i]->lock);
3676         }
3677
3678         /* Allocate and claim adapter resources */
3679         if (!claim_resources(port_array[0])) {
3680
3681                 alloc_dma_bufs(port_array[0]);
3682
3683                 /* copy resource information from first port to others */
3684                 for (i = 1; i < port_count; ++i) {
3685                         port_array[i]->irq_level = port_array[0]->irq_level;
3686                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3687                         alloc_dma_bufs(port_array[i]);
3688                 }
3689
3690                 if (request_irq(port_array[0]->irq_level,
3691                                         slgt_interrupt,
3692                                         port_array[0]->irq_flags,
3693                                         port_array[0]->device_name,
3694                                         port_array[0]) < 0) {
3695                         DBGERR(("%s request_irq failed IRQ=%d\n",
3696                                 port_array[0]->device_name,
3697                                 port_array[0]->irq_level));
3698                 } else {
3699                         port_array[0]->irq_requested = true;
3700                         adapter_test(port_array[0]);
3701                         for (i=1 ; i < port_count ; i++) {
3702                                 port_array[i]->init_error = port_array[0]->init_error;
3703                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3704                         }
3705                 }
3706         }
3707
3708         for (i = 0; i < port_count; ++i) {
3709                 struct slgt_info *info = port_array[i];
3710                 tty_port_register_device(&info->port, serial_driver, info->line,
3711                                 &info->pdev->dev);
3712         }
3713 }
3714
3715 static int init_one(struct pci_dev *dev,
3716                               const struct pci_device_id *ent)
3717 {
3718         if (pci_enable_device(dev)) {
3719                 printk("error enabling pci device %p\n", dev);
3720                 return -EIO;
3721         }
3722         pci_set_master(dev);
3723         device_init(slgt_device_count, dev);
3724         return 0;
3725 }
3726
3727 static void remove_one(struct pci_dev *dev)
3728 {
3729 }
3730
3731 static const struct tty_operations ops = {
3732         .open = open,
3733         .close = close,
3734         .write = write,
3735         .put_char = put_char,
3736         .flush_chars = flush_chars,
3737         .write_room = write_room,
3738         .chars_in_buffer = chars_in_buffer,
3739         .flush_buffer = flush_buffer,
3740         .ioctl = ioctl,
3741         .compat_ioctl = slgt_compat_ioctl,
3742         .throttle = throttle,
3743         .unthrottle = unthrottle,
3744         .send_xchar = send_xchar,
3745         .break_ctl = set_break,
3746         .wait_until_sent = wait_until_sent,
3747         .set_termios = set_termios,
3748         .stop = tx_hold,
3749         .start = tx_release,
3750         .hangup = hangup,
3751         .tiocmget = tiocmget,
3752         .tiocmset = tiocmset,
3753         .get_icount = get_icount,
3754         .proc_fops = &synclink_gt_proc_fops,
3755 };
3756
3757 static void slgt_cleanup(void)
3758 {
3759         int rc;
3760         struct slgt_info *info;
3761         struct slgt_info *tmp;
3762
3763         printk(KERN_INFO "unload %s\n", driver_name);
3764
3765         if (serial_driver) {
3766                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3767                         tty_unregister_device(serial_driver, info->line);
3768                 if ((rc = tty_unregister_driver(serial_driver)))
3769                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3770                 put_tty_driver(serial_driver);
3771         }
3772
3773         /* reset devices */
3774         info = slgt_device_list;
3775         while(info) {
3776                 reset_port(info);
3777                 info = info->next_device;
3778         }
3779
3780         /* release devices */
3781         info = slgt_device_list;
3782         while(info) {
3783 #if SYNCLINK_GENERIC_HDLC
3784                 hdlcdev_exit(info);
3785 #endif
3786                 free_dma_bufs(info);
3787                 free_tmp_rbuf(info);
3788                 if (info->port_num == 0)
3789                         release_resources(info);
3790                 tmp = info;
3791                 info = info->next_device;
3792                 tty_port_destroy(&tmp->port);
3793                 kfree(tmp);
3794         }
3795
3796         if (pci_registered)
3797                 pci_unregister_driver(&pci_driver);
3798 }
3799
3800 /*
3801  *  Driver initialization entry point.
3802  */
3803 static int __init slgt_init(void)
3804 {
3805         int rc;
3806
3807         printk(KERN_INFO "%s\n", driver_name);
3808
3809         serial_driver = alloc_tty_driver(MAX_DEVICES);
3810         if (!serial_driver) {
3811                 printk("%s can't allocate tty driver\n", driver_name);
3812                 return -ENOMEM;
3813         }
3814
3815         /* Initialize the tty_driver structure */
3816
3817         serial_driver->driver_name = tty_driver_name;
3818         serial_driver->name = tty_dev_prefix;
3819         serial_driver->major = ttymajor;
3820         serial_driver->minor_start = 64;
3821         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3822         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3823         serial_driver->init_termios = tty_std_termios;
3824         serial_driver->init_termios.c_cflag =
3825                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3826         serial_driver->init_termios.c_ispeed = 9600;
3827         serial_driver->init_termios.c_ospeed = 9600;
3828         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3829         tty_set_operations(serial_driver, &ops);
3830         if ((rc = tty_register_driver(serial_driver)) < 0) {
3831                 DBGERR(("%s can't register serial driver\n", driver_name));
3832                 put_tty_driver(serial_driver);
3833                 serial_driver = NULL;
3834                 goto error;
3835         }
3836
3837         printk(KERN_INFO "%s, tty major#%d\n",
3838                driver_name, serial_driver->major);
3839
3840         slgt_device_count = 0;
3841         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3842                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3843                 goto error;
3844         }
3845         pci_registered = true;
3846
3847         if (!slgt_device_list)
3848                 printk("%s no devices found\n",driver_name);
3849
3850         return 0;
3851
3852 error:
3853         slgt_cleanup();
3854         return rc;
3855 }
3856
3857 static void __exit slgt_exit(void)
3858 {
3859         slgt_cleanup();
3860 }
3861
3862 module_init(slgt_init);
3863 module_exit(slgt_exit);
3864
3865 /*
3866  * register access routines
3867  */
3868
3869 #define CALC_REGADDR() \
3870         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3871         if (addr >= 0x80) \
3872                 reg_addr += (info->port_num) * 32; \
3873         else if (addr >= 0x40)  \
3874                 reg_addr += (info->port_num) * 16;
3875
3876 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3877 {
3878         CALC_REGADDR();
3879         return readb((void __iomem *)reg_addr);
3880 }
3881
3882 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3883 {
3884         CALC_REGADDR();
3885         writeb(value, (void __iomem *)reg_addr);
3886 }
3887
3888 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3889 {
3890         CALC_REGADDR();
3891         return readw((void __iomem *)reg_addr);
3892 }
3893
3894 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3895 {
3896         CALC_REGADDR();
3897         writew(value, (void __iomem *)reg_addr);
3898 }
3899
3900 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3901 {
3902         CALC_REGADDR();
3903         return readl((void __iomem *)reg_addr);
3904 }
3905
3906 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3907 {
3908         CALC_REGADDR();
3909         writel(value, (void __iomem *)reg_addr);
3910 }
3911
3912 static void rdma_reset(struct slgt_info *info)
3913 {
3914         unsigned int i;
3915
3916         /* set reset bit */
3917         wr_reg32(info, RDCSR, BIT1);
3918
3919         /* wait for enable bit cleared */
3920         for(i=0 ; i < 1000 ; i++)
3921                 if (!(rd_reg32(info, RDCSR) & BIT0))
3922                         break;
3923 }
3924
3925 static void tdma_reset(struct slgt_info *info)
3926 {
3927         unsigned int i;
3928
3929         /* set reset bit */
3930         wr_reg32(info, TDCSR, BIT1);
3931
3932         /* wait for enable bit cleared */
3933         for(i=0 ; i < 1000 ; i++)
3934                 if (!(rd_reg32(info, TDCSR) & BIT0))
3935                         break;
3936 }
3937
3938 /*
3939  * enable internal loopback
3940  * TxCLK and RxCLK are generated from BRG
3941  * and TxD is looped back to RxD internally.
3942  */
3943 static void enable_loopback(struct slgt_info *info)
3944 {
3945         /* SCR (serial control) BIT2=loopback enable */
3946         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3947
3948         if (info->params.mode != MGSL_MODE_ASYNC) {
3949                 /* CCR (clock control)
3950                  * 07..05  tx clock source (010 = BRG)
3951                  * 04..02  rx clock source (010 = BRG)
3952                  * 01      auxclk enable   (0 = disable)
3953                  * 00      BRG enable      (1 = enable)
3954                  *
3955                  * 0100 1001
3956                  */
3957                 wr_reg8(info, CCR, 0x49);
3958
3959                 /* set speed if available, otherwise use default */
3960                 if (info->params.clock_speed)
3961                         set_rate(info, info->params.clock_speed);
3962                 else
3963                         set_rate(info, 3686400);
3964         }
3965 }
3966
3967 /*
3968  *  set baud rate generator to specified rate
3969  */
3970 static void set_rate(struct slgt_info *info, u32 rate)
3971 {
3972         unsigned int div;
3973         unsigned int osc = info->base_clock;
3974
3975         /* div = osc/rate - 1
3976          *
3977          * Round div up if osc/rate is not integer to
3978          * force to next slowest rate.
3979          */
3980
3981         if (rate) {
3982                 div = osc/rate;
3983                 if (!(osc % rate) && div)
3984                         div--;
3985                 wr_reg16(info, BDR, (unsigned short)div);
3986         }
3987 }
3988
3989 static void rx_stop(struct slgt_info *info)
3990 {
3991         unsigned short val;
3992
3993         /* disable and reset receiver */
3994         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3995         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3996         wr_reg16(info, RCR, val);                  /* clear reset bit */
3997
3998         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3999
4000         /* clear pending rx interrupts */
4001         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
4002
4003         rdma_reset(info);
4004
4005         info->rx_enabled = false;
4006         info->rx_restart = false;
4007 }
4008
4009 static void rx_start(struct slgt_info *info)
4010 {
4011         unsigned short val;
4012
4013         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
4014
4015         /* clear pending rx overrun IRQ */
4016         wr_reg16(info, SSR, IRQ_RXOVER);
4017
4018         /* reset and disable receiver */
4019         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4020         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4021         wr_reg16(info, RCR, val);                  /* clear reset bit */
4022
4023         rdma_reset(info);
4024         reset_rbufs(info);
4025
4026         if (info->rx_pio) {
4027                 /* rx request when rx FIFO not empty */
4028                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4029                 slgt_irq_on(info, IRQ_RXDATA);
4030                 if (info->params.mode == MGSL_MODE_ASYNC) {
4031                         /* enable saving of rx status */
4032                         wr_reg32(info, RDCSR, BIT6);
4033                 }
4034         } else {
4035                 /* rx request when rx FIFO half full */
4036                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4037                 /* set 1st descriptor address */
4038                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4039
4040                 if (info->params.mode != MGSL_MODE_ASYNC) {
4041                         /* enable rx DMA and DMA interrupt */
4042                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4043                 } else {
4044                         /* enable saving of rx status, rx DMA and DMA interrupt */
4045                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4046                 }
4047         }
4048
4049         slgt_irq_on(info, IRQ_RXOVER);
4050
4051         /* enable receiver */
4052         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4053
4054         info->rx_restart = false;
4055         info->rx_enabled = true;
4056 }
4057
4058 static void tx_start(struct slgt_info *info)
4059 {
4060         if (!info->tx_enabled) {
4061                 wr_reg16(info, TCR,
4062                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4063                 info->tx_enabled = true;
4064         }
4065
4066         if (desc_count(info->tbufs[info->tbuf_start])) {
4067                 info->drop_rts_on_tx_done = false;
4068
4069                 if (info->params.mode != MGSL_MODE_ASYNC) {
4070                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4071                                 get_signals(info);
4072                                 if (!(info->signals & SerialSignal_RTS)) {
4073                                         info->signals |= SerialSignal_RTS;
4074                                         set_signals(info);
4075                                         info->drop_rts_on_tx_done = true;
4076                                 }
4077                         }
4078
4079                         slgt_irq_off(info, IRQ_TXDATA);
4080                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4081                         /* clear tx idle and underrun status bits */
4082                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4083                 } else {
4084                         slgt_irq_off(info, IRQ_TXDATA);
4085                         slgt_irq_on(info, IRQ_TXIDLE);
4086                         /* clear tx idle status bit */
4087                         wr_reg16(info, SSR, IRQ_TXIDLE);
4088                 }
4089                 /* set 1st descriptor address and start DMA */
4090                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4091                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4092                 info->tx_active = true;
4093         }
4094 }
4095
4096 static void tx_stop(struct slgt_info *info)
4097 {
4098         unsigned short val;
4099
4100         del_timer(&info->tx_timer);
4101
4102         tdma_reset(info);
4103
4104         /* reset and disable transmitter */
4105         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4106         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4107
4108         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4109
4110         /* clear tx idle and underrun status bit */
4111         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4112
4113         reset_tbufs(info);
4114
4115         info->tx_enabled = false;
4116         info->tx_active = false;
4117 }
4118
4119 static void reset_port(struct slgt_info *info)
4120 {
4121         if (!info->reg_addr)
4122                 return;
4123
4124         tx_stop(info);
4125         rx_stop(info);
4126
4127         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4128         set_signals(info);
4129
4130         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4131 }
4132
4133 static void reset_adapter(struct slgt_info *info)
4134 {
4135         int i;
4136         for (i=0; i < info->port_count; ++i) {
4137                 if (info->port_array[i])
4138                         reset_port(info->port_array[i]);
4139         }
4140 }
4141
4142 static void async_mode(struct slgt_info *info)
4143 {
4144         unsigned short val;
4145
4146         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4147         tx_stop(info);
4148         rx_stop(info);
4149
4150         /* TCR (tx control)
4151          *
4152          * 15..13  mode, 010=async
4153          * 12..10  encoding, 000=NRZ
4154          * 09      parity enable
4155          * 08      1=odd parity, 0=even parity
4156          * 07      1=RTS driver control
4157          * 06      1=break enable
4158          * 05..04  character length
4159          *         00=5 bits
4160          *         01=6 bits
4161          *         10=7 bits
4162          *         11=8 bits
4163          * 03      0=1 stop bit, 1=2 stop bits
4164          * 02      reset
4165          * 01      enable
4166          * 00      auto-CTS enable
4167          */
4168         val = 0x4000;
4169
4170         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4171                 val |= BIT7;
4172
4173         if (info->params.parity != ASYNC_PARITY_NONE) {
4174                 val |= BIT9;
4175                 if (info->params.parity == ASYNC_PARITY_ODD)
4176                         val |= BIT8;
4177         }
4178
4179         switch (info->params.data_bits)
4180         {
4181         case 6: val |= BIT4; break;
4182         case 7: val |= BIT5; break;
4183         case 8: val |= BIT5 + BIT4; break;
4184         }
4185
4186         if (info->params.stop_bits != 1)
4187                 val |= BIT3;
4188
4189         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4190                 val |= BIT0;
4191
4192         wr_reg16(info, TCR, val);
4193
4194         /* RCR (rx control)
4195          *
4196          * 15..13  mode, 010=async
4197          * 12..10  encoding, 000=NRZ
4198          * 09      parity enable
4199          * 08      1=odd parity, 0=even parity
4200          * 07..06  reserved, must be 0
4201          * 05..04  character length
4202          *         00=5 bits
4203          *         01=6 bits
4204          *         10=7 bits
4205          *         11=8 bits
4206          * 03      reserved, must be zero
4207          * 02      reset
4208          * 01      enable
4209          * 00      auto-DCD enable
4210          */
4211         val = 0x4000;
4212
4213         if (info->params.parity != ASYNC_PARITY_NONE) {
4214                 val |= BIT9;
4215                 if (info->params.parity == ASYNC_PARITY_ODD)
4216                         val |= BIT8;
4217         }
4218
4219         switch (info->params.data_bits)
4220         {
4221         case 6: val |= BIT4; break;
4222         case 7: val |= BIT5; break;
4223         case 8: val |= BIT5 + BIT4; break;
4224         }
4225
4226         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4227                 val |= BIT0;
4228
4229         wr_reg16(info, RCR, val);
4230
4231         /* CCR (clock control)
4232          *
4233          * 07..05  011 = tx clock source is BRG/16
4234          * 04..02  010 = rx clock source is BRG
4235          * 01      0 = auxclk disabled
4236          * 00      1 = BRG enabled
4237          *
4238          * 0110 1001
4239          */
4240         wr_reg8(info, CCR, 0x69);
4241
4242         msc_set_vcr(info);
4243
4244         /* SCR (serial control)
4245          *
4246          * 15  1=tx req on FIFO half empty
4247          * 14  1=rx req on FIFO half full
4248          * 13  tx data  IRQ enable
4249          * 12  tx idle  IRQ enable
4250          * 11  rx break on IRQ enable
4251          * 10  rx data  IRQ enable
4252          * 09  rx break off IRQ enable
4253          * 08  overrun  IRQ enable
4254          * 07  DSR      IRQ enable
4255          * 06  CTS      IRQ enable
4256          * 05  DCD      IRQ enable
4257          * 04  RI       IRQ enable
4258          * 03  0=16x sampling, 1=8x sampling
4259          * 02  1=txd->rxd internal loopback enable
4260          * 01  reserved, must be zero
4261          * 00  1=master IRQ enable
4262          */
4263         val = BIT15 + BIT14 + BIT0;
4264         /* JCR[8] : 1 = x8 async mode feature available */
4265         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4266             ((info->base_clock < (info->params.data_rate * 16)) ||
4267              (info->base_clock % (info->params.data_rate * 16)))) {
4268                 /* use 8x sampling */
4269                 val |= BIT3;
4270                 set_rate(info, info->params.data_rate * 8);
4271         } else {
4272                 /* use 16x sampling */
4273                 set_rate(info, info->params.data_rate * 16);
4274         }
4275         wr_reg16(info, SCR, val);
4276
4277         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4278
4279         if (info->params.loopback)
4280                 enable_loopback(info);
4281 }
4282
4283 static void sync_mode(struct slgt_info *info)
4284 {
4285         unsigned short val;
4286
4287         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4288         tx_stop(info);
4289         rx_stop(info);
4290
4291         /* TCR (tx control)
4292          *
4293          * 15..13  mode
4294          *         000=HDLC/SDLC
4295          *         001=raw bit synchronous
4296          *         010=asynchronous/isochronous
4297          *         011=monosync byte synchronous
4298          *         100=bisync byte synchronous
4299          *         101=xsync byte synchronous
4300          * 12..10  encoding
4301          * 09      CRC enable
4302          * 08      CRC32
4303          * 07      1=RTS driver control
4304          * 06      preamble enable
4305          * 05..04  preamble length
4306          * 03      share open/close flag
4307          * 02      reset
4308          * 01      enable
4309          * 00      auto-CTS enable
4310          */
4311         val = BIT2;
4312
4313         switch(info->params.mode) {
4314         case MGSL_MODE_XSYNC:
4315                 val |= BIT15 + BIT13;
4316                 break;
4317         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4318         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4319         case MGSL_MODE_RAW:      val |= BIT13; break;
4320         }
4321         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4322                 val |= BIT7;
4323
4324         switch(info->params.encoding)
4325         {
4326         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4327         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4328         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4329         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4330         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4331         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4332         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4333         }
4334
4335         switch (info->params.crc_type & HDLC_CRC_MASK)
4336         {
4337         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4338         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4339         }
4340
4341         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4342                 val |= BIT6;
4343
4344         switch (info->params.preamble_length)
4345         {
4346         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4347         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4348         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4349         }
4350
4351         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4352                 val |= BIT0;
4353
4354         wr_reg16(info, TCR, val);
4355
4356         /* TPR (transmit preamble) */
4357
4358         switch (info->params.preamble)
4359         {
4360         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4361         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4362         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4363         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4364         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4365         default:                          val = 0x7e; break;
4366         }
4367         wr_reg8(info, TPR, (unsigned char)val);
4368
4369         /* RCR (rx control)
4370          *
4371          * 15..13  mode
4372          *         000=HDLC/SDLC
4373          *         001=raw bit synchronous
4374          *         010=asynchronous/isochronous
4375          *         011=monosync byte synchronous
4376          *         100=bisync byte synchronous
4377          *         101=xsync byte synchronous
4378          * 12..10  encoding
4379          * 09      CRC enable
4380          * 08      CRC32
4381          * 07..03  reserved, must be 0
4382          * 02      reset
4383          * 01      enable
4384          * 00      auto-DCD enable
4385          */
4386         val = 0;
4387
4388         switch(info->params.mode) {
4389         case MGSL_MODE_XSYNC:
4390                 val |= BIT15 + BIT13;
4391                 break;
4392         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4393         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4394         case MGSL_MODE_RAW:      val |= BIT13; break;
4395         }
4396
4397         switch(info->params.encoding)
4398         {
4399         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4400         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4401         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4402         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4403         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4404         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4405         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4406         }
4407
4408         switch (info->params.crc_type & HDLC_CRC_MASK)
4409         {
4410         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4411         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4412         }
4413
4414         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4415                 val |= BIT0;
4416
4417         wr_reg16(info, RCR, val);
4418
4419         /* CCR (clock control)
4420          *
4421          * 07..05  tx clock source
4422          * 04..02  rx clock source
4423          * 01      auxclk enable
4424          * 00      BRG enable
4425          */
4426         val = 0;
4427
4428         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4429         {
4430                 // when RxC source is DPLL, BRG generates 16X DPLL
4431                 // reference clock, so take TxC from BRG/16 to get
4432                 // transmit clock at actual data rate
4433                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4434                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4435                 else
4436                         val |= BIT6;    /* 010, txclk = BRG */
4437         }
4438         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4439                 val |= BIT7;    /* 100, txclk = DPLL Input */
4440         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4441                 val |= BIT5;    /* 001, txclk = RXC Input */
4442
4443         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4444                 val |= BIT3;    /* 010, rxclk = BRG */
4445         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4446                 val |= BIT4;    /* 100, rxclk = DPLL */
4447         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4448                 val |= BIT2;    /* 001, rxclk = TXC Input */
4449
4450         if (info->params.clock_speed)
4451                 val |= BIT1 + BIT0;
4452
4453         wr_reg8(info, CCR, (unsigned char)val);
4454
4455         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4456         {
4457                 // program DPLL mode
4458                 switch(info->params.encoding)
4459                 {
4460                 case HDLC_ENCODING_BIPHASE_MARK:
4461                 case HDLC_ENCODING_BIPHASE_SPACE:
4462                         val = BIT7; break;
4463                 case HDLC_ENCODING_BIPHASE_LEVEL:
4464                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4465                         val = BIT7 + BIT6; break;
4466                 default: val = BIT6;    // NRZ encodings
4467                 }
4468                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4469
4470                 // DPLL requires a 16X reference clock from BRG
4471                 set_rate(info, info->params.clock_speed * 16);
4472         }
4473         else
4474                 set_rate(info, info->params.clock_speed);
4475
4476         tx_set_idle(info);
4477
4478         msc_set_vcr(info);
4479
4480         /* SCR (serial control)
4481          *
4482          * 15  1=tx req on FIFO half empty
4483          * 14  1=rx req on FIFO half full
4484          * 13  tx data  IRQ enable
4485          * 12  tx idle  IRQ enable
4486          * 11  underrun IRQ enable
4487          * 10  rx data  IRQ enable
4488          * 09  rx idle  IRQ enable
4489          * 08  overrun  IRQ enable
4490          * 07  DSR      IRQ enable
4491          * 06  CTS      IRQ enable
4492          * 05  DCD      IRQ enable
4493          * 04  RI       IRQ enable
4494          * 03  reserved, must be zero
4495          * 02  1=txd->rxd internal loopback enable
4496          * 01  reserved, must be zero
4497          * 00  1=master IRQ enable
4498          */
4499         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4500
4501         if (info->params.loopback)
4502                 enable_loopback(info);
4503 }
4504
4505 /*
4506  *  set transmit idle mode
4507  */
4508 static void tx_set_idle(struct slgt_info *info)
4509 {
4510         unsigned char val;
4511         unsigned short tcr;
4512
4513         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4514          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4515          */
4516         tcr = rd_reg16(info, TCR);
4517         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4518                 /* disable preamble, set idle size to 16 bits */
4519                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4520                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4521                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4522         } else if (!(tcr & BIT6)) {
4523                 /* preamble is disabled, set idle size to 8 bits */
4524                 tcr &= ~(BIT5 + BIT4);
4525         }
4526         wr_reg16(info, TCR, tcr);
4527
4528         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4529                 /* LSB of custom tx idle specified in tx idle register */
4530                 val = (unsigned char)(info->idle_mode & 0xff);
4531         } else {
4532                 /* standard 8 bit idle patterns */
4533                 switch(info->idle_mode)
4534                 {
4535                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4536                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4537                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4538                 case HDLC_TXIDLE_ZEROS:
4539                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4540                 default:                         val = 0xff;
4541                 }
4542         }
4543
4544         wr_reg8(info, TIR, val);
4545 }
4546
4547 /*
4548  * get state of V24 status (input) signals
4549  */
4550 static void get_signals(struct slgt_info *info)
4551 {
4552         unsigned short status = rd_reg16(info, SSR);
4553
4554         /* clear all serial signals except DTR and RTS */
4555         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4556
4557         if (status & BIT3)
4558                 info->signals |= SerialSignal_DSR;
4559         if (status & BIT2)
4560                 info->signals |= SerialSignal_CTS;
4561         if (status & BIT1)
4562                 info->signals |= SerialSignal_DCD;
4563         if (status & BIT0)
4564                 info->signals |= SerialSignal_RI;
4565 }
4566
4567 /*
4568  * set V.24 Control Register based on current configuration
4569  */
4570 static void msc_set_vcr(struct slgt_info *info)
4571 {
4572         unsigned char val = 0;
4573
4574         /* VCR (V.24 control)
4575          *
4576          * 07..04  serial IF select
4577          * 03      DTR
4578          * 02      RTS
4579          * 01      LL
4580          * 00      RL
4581          */
4582
4583         switch(info->if_mode & MGSL_INTERFACE_MASK)
4584         {
4585         case MGSL_INTERFACE_RS232:
4586                 val |= BIT5; /* 0010 */
4587                 break;
4588         case MGSL_INTERFACE_V35:
4589                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4590                 break;
4591         case MGSL_INTERFACE_RS422:
4592                 val |= BIT6; /* 0100 */
4593                 break;
4594         }
4595
4596         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4597                 val |= BIT4;
4598         if (info->signals & SerialSignal_DTR)
4599                 val |= BIT3;
4600         if (info->signals & SerialSignal_RTS)
4601                 val |= BIT2;
4602         if (info->if_mode & MGSL_INTERFACE_LL)
4603                 val |= BIT1;
4604         if (info->if_mode & MGSL_INTERFACE_RL)
4605                 val |= BIT0;
4606         wr_reg8(info, VCR, val);
4607 }
4608
4609 /*
4610  * set state of V24 control (output) signals
4611  */
4612 static void set_signals(struct slgt_info *info)
4613 {
4614         unsigned char val = rd_reg8(info, VCR);
4615         if (info->signals & SerialSignal_DTR)
4616                 val |= BIT3;
4617         else
4618                 val &= ~BIT3;
4619         if (info->signals & SerialSignal_RTS)
4620                 val |= BIT2;
4621         else
4622                 val &= ~BIT2;
4623         wr_reg8(info, VCR, val);
4624 }
4625
4626 /*
4627  * free range of receive DMA buffers (i to last)
4628  */
4629 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4630 {
4631         int done = 0;
4632
4633         while(!done) {
4634                 /* reset current buffer for reuse */
4635                 info->rbufs[i].status = 0;
4636                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4637                 if (i == last)
4638                         done = 1;
4639                 if (++i == info->rbuf_count)
4640                         i = 0;
4641         }
4642         info->rbuf_current = i;
4643 }
4644
4645 /*
4646  * mark all receive DMA buffers as free
4647  */
4648 static void reset_rbufs(struct slgt_info *info)
4649 {
4650         free_rbufs(info, 0, info->rbuf_count - 1);
4651         info->rbuf_fill_index = 0;
4652         info->rbuf_fill_count = 0;
4653 }
4654
4655 /*
4656  * pass receive HDLC frame to upper layer
4657  *
4658  * return true if frame available, otherwise false
4659  */
4660 static bool rx_get_frame(struct slgt_info *info)
4661 {
4662         unsigned int start, end;
4663         unsigned short status;
4664         unsigned int framesize = 0;
4665         unsigned long flags;
4666         struct tty_struct *tty = info->port.tty;
4667         unsigned char addr_field = 0xff;
4668         unsigned int crc_size = 0;
4669
4670         switch (info->params.crc_type & HDLC_CRC_MASK) {
4671         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4672         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4673         }
4674
4675 check_again:
4676
4677         framesize = 0;
4678         addr_field = 0xff;
4679         start = end = info->rbuf_current;
4680
4681         for (;;) {
4682                 if (!desc_complete(info->rbufs[end]))
4683                         goto cleanup;
4684
4685                 if (framesize == 0 && info->params.addr_filter != 0xff)
4686                         addr_field = info->rbufs[end].buf[0];
4687
4688                 framesize += desc_count(info->rbufs[end]);
4689
4690                 if (desc_eof(info->rbufs[end]))
4691                         break;
4692
4693                 if (++end == info->rbuf_count)
4694                         end = 0;
4695
4696                 if (end == info->rbuf_current) {
4697                         if (info->rx_enabled){
4698                                 spin_lock_irqsave(&info->lock,flags);
4699                                 rx_start(info);
4700                                 spin_unlock_irqrestore(&info->lock,flags);
4701                         }
4702                         goto cleanup;
4703                 }
4704         }
4705
4706         /* status
4707          *
4708          * 15      buffer complete
4709          * 14..06  reserved
4710          * 05..04  residue
4711          * 02      eof (end of frame)
4712          * 01      CRC error
4713          * 00      abort
4714          */
4715         status = desc_status(info->rbufs[end]);
4716
4717         /* ignore CRC bit if not using CRC (bit is undefined) */
4718         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4719                 status &= ~BIT1;
4720
4721         if (framesize == 0 ||
4722                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4723                 free_rbufs(info, start, end);
4724                 goto check_again;
4725         }
4726
4727         if (framesize < (2 + crc_size) || status & BIT0) {
4728                 info->icount.rxshort++;
4729                 framesize = 0;
4730         } else if (status & BIT1) {
4731                 info->icount.rxcrc++;
4732                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4733                         framesize = 0;
4734         }
4735
4736 #if SYNCLINK_GENERIC_HDLC
4737         if (framesize == 0) {
4738                 info->netdev->stats.rx_errors++;
4739                 info->netdev->stats.rx_frame_errors++;
4740         }
4741 #endif
4742
4743         DBGBH(("%s rx frame status=%04X size=%d\n",
4744                 info->device_name, status, framesize));
4745         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4746
4747         if (framesize) {
4748                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4749                         framesize -= crc_size;
4750                         crc_size = 0;
4751                 }
4752
4753                 if (framesize > info->max_frame_size + crc_size)
4754                         info->icount.rxlong++;
4755                 else {
4756                         /* copy dma buffer(s) to contiguous temp buffer */
4757                         int copy_count = framesize;
4758                         int i = start;
4759                         unsigned char *p = info->tmp_rbuf;
4760                         info->tmp_rbuf_count = framesize;
4761
4762                         info->icount.rxok++;
4763
4764                         while(copy_count) {
4765                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4766                                 memcpy(p, info->rbufs[i].buf, partial_count);
4767                                 p += partial_count;
4768                                 copy_count -= partial_count;
4769                                 if (++i == info->rbuf_count)
4770                                         i = 0;
4771                         }
4772
4773                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4774                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4775                                 framesize++;
4776                         }
4777
4778 #if SYNCLINK_GENERIC_HDLC
4779                         if (info->netcount)
4780                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4781                         else
4782 #endif
4783                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4784                 }
4785         }
4786         free_rbufs(info, start, end);
4787         return true;
4788
4789 cleanup:
4790         return false;
4791 }
4792
4793 /*
4794  * pass receive buffer (RAW synchronous mode) to tty layer
4795  * return true if buffer available, otherwise false
4796  */
4797 static bool rx_get_buf(struct slgt_info *info)
4798 {
4799         unsigned int i = info->rbuf_current;
4800         unsigned int count;
4801
4802         if (!desc_complete(info->rbufs[i]))
4803                 return false;
4804         count = desc_count(info->rbufs[i]);
4805         switch(info->params.mode) {
4806         case MGSL_MODE_MONOSYNC:
4807         case MGSL_MODE_BISYNC:
4808         case MGSL_MODE_XSYNC:
4809                 /* ignore residue in byte synchronous modes */
4810                 if (desc_residue(info->rbufs[i]))
4811                         count--;
4812                 break;
4813         }
4814         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4815         DBGINFO(("rx_get_buf size=%d\n", count));
4816         if (count)
4817                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4818                                   info->flag_buf, count);
4819         free_rbufs(info, i, i);
4820         return true;
4821 }
4822
4823 static void reset_tbufs(struct slgt_info *info)
4824 {
4825         unsigned int i;
4826         info->tbuf_current = 0;
4827         for (i=0 ; i < info->tbuf_count ; i++) {
4828                 info->tbufs[i].status = 0;
4829                 info->tbufs[i].count  = 0;
4830         }
4831 }
4832
4833 /*
4834  * return number of free transmit DMA buffers
4835  */
4836 static unsigned int free_tbuf_count(struct slgt_info *info)
4837 {
4838         unsigned int count = 0;
4839         unsigned int i = info->tbuf_current;
4840
4841         do
4842         {
4843                 if (desc_count(info->tbufs[i]))
4844                         break; /* buffer in use */
4845                 ++count;
4846                 if (++i == info->tbuf_count)
4847                         i=0;
4848         } while (i != info->tbuf_current);
4849
4850         /* if tx DMA active, last zero count buffer is in use */
4851         if (count && (rd_reg32(info, TDCSR) & BIT0))
4852                 --count;
4853
4854         return count;
4855 }
4856
4857 /*
4858  * return number of bytes in unsent transmit DMA buffers
4859  * and the serial controller tx FIFO
4860  */
4861 static unsigned int tbuf_bytes(struct slgt_info *info)
4862 {
4863         unsigned int total_count = 0;
4864         unsigned int i = info->tbuf_current;
4865         unsigned int reg_value;
4866         unsigned int count;
4867         unsigned int active_buf_count = 0;
4868
4869         /*
4870          * Add descriptor counts for all tx DMA buffers.
4871          * If count is zero (cleared by DMA controller after read),
4872          * the buffer is complete or is actively being read from.
4873          *
4874          * Record buf_count of last buffer with zero count starting
4875          * from current ring position. buf_count is mirror
4876          * copy of count and is not cleared by serial controller.
4877          * If DMA controller is active, that buffer is actively
4878          * being read so add to total.
4879          */
4880         do {
4881                 count = desc_count(info->tbufs[i]);
4882                 if (count)
4883                         total_count += count;
4884                 else if (!total_count)
4885                         active_buf_count = info->tbufs[i].buf_count;
4886                 if (++i == info->tbuf_count)
4887                         i = 0;
4888         } while (i != info->tbuf_current);
4889
4890         /* read tx DMA status register */
4891         reg_value = rd_reg32(info, TDCSR);
4892
4893         /* if tx DMA active, last zero count buffer is in use */
4894         if (reg_value & BIT0)
4895                 total_count += active_buf_count;
4896
4897         /* add tx FIFO count = reg_value[15..8] */
4898         total_count += (reg_value >> 8) & 0xff;
4899
4900         /* if transmitter active add one byte for shift register */
4901         if (info->tx_active)
4902                 total_count++;
4903
4904         return total_count;
4905 }
4906
4907 /*
4908  * load data into transmit DMA buffer ring and start transmitter if needed
4909  * return true if data accepted, otherwise false (buffers full)
4910  */
4911 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4912 {
4913         unsigned short count;
4914         unsigned int i;
4915         struct slgt_desc *d;
4916
4917         /* check required buffer space */
4918         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4919                 return false;
4920
4921         DBGDATA(info, buf, size, "tx");
4922
4923         /*
4924          * copy data to one or more DMA buffers in circular ring
4925          * tbuf_start   = first buffer for this data
4926          * tbuf_current = next free buffer
4927          *
4928          * Copy all data before making data visible to DMA controller by
4929          * setting descriptor count of the first buffer.
4930          * This prevents an active DMA controller from reading the first DMA
4931          * buffers of a frame and stopping before the final buffers are filled.
4932          */
4933
4934         info->tbuf_start = i = info->tbuf_current;
4935
4936         while (size) {
4937                 d = &info->tbufs[i];
4938
4939                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4940                 memcpy(d->buf, buf, count);
4941
4942                 size -= count;
4943                 buf  += count;
4944
4945                 /*
4946                  * set EOF bit for last buffer of HDLC frame or
4947                  * for every buffer in raw mode
4948                  */
4949                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4950                     info->params.mode == MGSL_MODE_RAW)
4951                         set_desc_eof(*d, 1);
4952                 else
4953                         set_desc_eof(*d, 0);
4954
4955                 /* set descriptor count for all but first buffer */
4956                 if (i != info->tbuf_start)
4957                         set_desc_count(*d, count);
4958                 d->buf_count = count;
4959
4960                 if (++i == info->tbuf_count)
4961                         i = 0;
4962         }
4963
4964         info->tbuf_current = i;
4965
4966         /* set first buffer count to make new data visible to DMA controller */
4967         d = &info->tbufs[info->tbuf_start];
4968         set_desc_count(*d, d->buf_count);
4969
4970         /* start transmitter if needed and update transmit timeout */
4971         if (!info->tx_active)
4972                 tx_start(info);
4973         update_tx_timer(info);
4974
4975         return true;
4976 }
4977
4978 static int register_test(struct slgt_info *info)
4979 {
4980         static unsigned short patterns[] =
4981                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4982         static unsigned int count = ARRAY_SIZE(patterns);
4983         unsigned int i;
4984         int rc = 0;
4985
4986         for (i=0 ; i < count ; i++) {
4987                 wr_reg16(info, TIR, patterns[i]);
4988                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4989                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4990                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4991                         rc = -ENODEV;
4992                         break;
4993                 }
4994         }
4995         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4996         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4997         return rc;
4998 }
4999
5000 static int irq_test(struct slgt_info *info)
5001 {
5002         unsigned long timeout;
5003         unsigned long flags;
5004         struct tty_struct *oldtty = info->port.tty;
5005         u32 speed = info->params.data_rate;
5006
5007         info->params.data_rate = 921600;
5008         info->port.tty = NULL;
5009
5010         spin_lock_irqsave(&info->lock, flags);
5011         async_mode(info);
5012         slgt_irq_on(info, IRQ_TXIDLE);
5013
5014         /* enable transmitter */
5015         wr_reg16(info, TCR,
5016                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
5017
5018         /* write one byte and wait for tx idle */
5019         wr_reg16(info, TDR, 0);
5020
5021         /* assume failure */
5022         info->init_error = DiagStatus_IrqFailure;
5023         info->irq_occurred = false;
5024
5025         spin_unlock_irqrestore(&info->lock, flags);
5026
5027         timeout=100;
5028         while(timeout-- && !info->irq_occurred)
5029                 msleep_interruptible(10);
5030
5031         spin_lock_irqsave(&info->lock,flags);
5032         reset_port(info);
5033         spin_unlock_irqrestore(&info->lock,flags);
5034
5035         info->params.data_rate = speed;
5036         info->port.tty = oldtty;
5037
5038         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5039         return info->irq_occurred ? 0 : -ENODEV;
5040 }
5041
5042 static int loopback_test_rx(struct slgt_info *info)
5043 {
5044         unsigned char *src, *dest;
5045         int count;
5046
5047         if (desc_complete(info->rbufs[0])) {
5048                 count = desc_count(info->rbufs[0]);
5049                 src   = info->rbufs[0].buf;
5050                 dest  = info->tmp_rbuf;
5051
5052                 for( ; count ; count-=2, src+=2) {
5053                         /* src=data byte (src+1)=status byte */
5054                         if (!(*(src+1) & (BIT9 + BIT8))) {
5055                                 *dest = *src;
5056                                 dest++;
5057                                 info->tmp_rbuf_count++;
5058                         }
5059                 }
5060                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5061                 return 1;
5062         }
5063         return 0;
5064 }
5065
5066 static int loopback_test(struct slgt_info *info)
5067 {
5068 #define TESTFRAMESIZE 20
5069
5070         unsigned long timeout;
5071         u16 count = TESTFRAMESIZE;
5072         unsigned char buf[TESTFRAMESIZE];
5073         int rc = -ENODEV;
5074         unsigned long flags;
5075
5076         struct tty_struct *oldtty = info->port.tty;
5077         MGSL_PARAMS params;
5078
5079         memcpy(&params, &info->params, sizeof(params));
5080
5081         info->params.mode = MGSL_MODE_ASYNC;
5082         info->params.data_rate = 921600;
5083         info->params.loopback = 1;
5084         info->port.tty = NULL;
5085
5086         /* build and send transmit frame */
5087         for (count = 0; count < TESTFRAMESIZE; ++count)
5088                 buf[count] = (unsigned char)count;
5089
5090         info->tmp_rbuf_count = 0;
5091         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5092
5093         /* program hardware for HDLC and enabled receiver */
5094         spin_lock_irqsave(&info->lock,flags);
5095         async_mode(info);
5096         rx_start(info);
5097         tx_load(info, buf, count);
5098         spin_unlock_irqrestore(&info->lock, flags);
5099
5100         /* wait for receive complete */
5101         for (timeout = 100; timeout; --timeout) {
5102                 msleep_interruptible(10);
5103                 if (loopback_test_rx(info)) {
5104                         rc = 0;
5105                         break;
5106                 }
5107         }
5108
5109         /* verify received frame length and contents */
5110         if (!rc && (info->tmp_rbuf_count != count ||
5111                   memcmp(buf, info->tmp_rbuf, count))) {
5112                 rc = -ENODEV;
5113         }
5114
5115         spin_lock_irqsave(&info->lock,flags);
5116         reset_adapter(info);
5117         spin_unlock_irqrestore(&info->lock,flags);
5118
5119         memcpy(&info->params, &params, sizeof(info->params));
5120         info->port.tty = oldtty;
5121
5122         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5123         return rc;
5124 }
5125
5126 static int adapter_test(struct slgt_info *info)
5127 {
5128         DBGINFO(("testing %s\n", info->device_name));
5129         if (register_test(info) < 0) {
5130                 printk("register test failure %s addr=%08X\n",
5131                         info->device_name, info->phys_reg_addr);
5132         } else if (irq_test(info) < 0) {
5133                 printk("IRQ test failure %s IRQ=%d\n",
5134                         info->device_name, info->irq_level);
5135         } else if (loopback_test(info) < 0) {
5136                 printk("loopback test failure %s\n", info->device_name);
5137         }
5138         return info->init_error;
5139 }
5140
5141 /*
5142  * transmit timeout handler
5143  */
5144 static void tx_timeout(unsigned long context)
5145 {
5146         struct slgt_info *info = (struct slgt_info*)context;
5147         unsigned long flags;
5148
5149         DBGINFO(("%s tx_timeout\n", info->device_name));
5150         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5151                 info->icount.txtimeout++;
5152         }
5153         spin_lock_irqsave(&info->lock,flags);
5154         tx_stop(info);
5155         spin_unlock_irqrestore(&info->lock,flags);
5156
5157 #if SYNCLINK_GENERIC_HDLC
5158         if (info->netcount)
5159                 hdlcdev_tx_done(info);
5160         else
5161 #endif
5162                 bh_transmit(info);
5163 }
5164
5165 /*
5166  * receive buffer polling timer
5167  */
5168 static void rx_timeout(unsigned long context)
5169 {
5170         struct slgt_info *info = (struct slgt_info*)context;
5171         unsigned long flags;
5172
5173         DBGINFO(("%s rx_timeout\n", info->device_name));
5174         spin_lock_irqsave(&info->lock, flags);
5175         info->pending_bh |= BH_RECEIVE;
5176         spin_unlock_irqrestore(&info->lock, flags);
5177         bh_handler(&info->task);
5178 }
5179