2 * ci.h - common structures, functions, and macros of the ChipIdea driver
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __DRIVERS_USB_CHIPIDEA_CI_H
14 #define __DRIVERS_USB_CHIPIDEA_CI_H
16 #include <linux/list.h>
17 #include <linux/irqreturn.h>
18 #include <linux/usb.h>
19 #include <linux/usb/gadget.h>
21 /******************************************************************************
23 *****************************************************************************/
24 #define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
27 /******************************************************************************
29 *****************************************************************************/
31 * struct ci13xxx_ep - endpoint representation
32 * @ep: endpoint structure for gadget drivers
33 * @dir: endpoint direction (TX/RX)
34 * @num: endpoint number
35 * @type: endpoint type
36 * @name: string description of the endpoint
37 * @qh: queue head for this endpoint
38 * @wedge: is the endpoint wedged
39 * @ci: pointer to the controller
40 * @lock: pointer to controller's spinlock
41 * @td_pool: pointer to controller's TD pool
50 struct list_head queue;
51 struct ci13xxx_qh *ptr;
56 /* global resources */
59 struct dma_pool *td_pool;
69 * struct ci_role_driver - host/gadget role driver
70 * start: start this role
71 * stop: stop this role
72 * irq: irq handler for this role
73 * name: role name string (host/gadget)
75 struct ci_role_driver {
76 int (*start)(struct ci13xxx *);
77 void (*stop)(struct ci13xxx *);
78 irqreturn_t (*irq)(struct ci13xxx *);
83 * struct hw_bank - hardware register mapping representation
84 * @lpm: set if the device is LPM capable
85 * @phys: physical address of the controller's registers
86 * @abs: absolute address of the beginning of register window
87 * @cap: capability registers
88 * @op: operational registers
89 * @size: size of the register window
90 * @regmap: register lookup table
99 void __iomem **regmap;
103 * struct ci13xxx - chipidea device representation
104 * @dev: pointer to parent device
105 * @lock: access synchronization
106 * @hw_bank: hardware register mapping
108 * @roles: array of supported roles for this controller
109 * @role: current role
110 * @is_otg: if the device is otg-capable
111 * @work: work for role changing
112 * @wq: workqueue thread
113 * @qh_pool: allocation pool for queue heads
114 * @td_pool: allocation pool for transfer descriptors
115 * @gadget: device side representation for peripheral controller
116 * @driver: gadget driver
117 * @hw_ep_max: total number of endpoints supported by hardware
118 * @ci13xxx_ep: array of endpoints
119 * @ep0_dir: ep0 direction
120 * @ep0out: pointer to ep0 OUT endpoint
121 * @ep0in: pointer to ep0 IN endpoint
122 * @status: ep0 status request
123 * @setaddr: if we should set the address on status completion
124 * @address: usb address received from the host
125 * @remote_wakeup: host-enabled remote wakeup
126 * @suspended: suspended by host
127 * @test_mode: the selected test mode
128 * @platdata: platform specific information supplied by parent device
129 * @vbus_active: is VBUS active
130 * @transceiver: pointer to USB PHY, if any
131 * @hcd: pointer to usb_hcd for ehci host driver
136 struct hw_bank hw_bank;
138 struct ci_role_driver *roles[CI_ROLE_END];
141 struct work_struct work;
142 struct work_struct vbus_work;
143 struct workqueue_struct *wq;
145 struct dma_pool *qh_pool;
146 struct dma_pool *td_pool;
148 struct usb_gadget gadget;
149 struct usb_gadget_driver *driver;
151 struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX];
153 struct ci13xxx_ep *ep0out, *ep0in;
155 struct usb_request *status;
162 struct ci13xxx_platform_data *platdata;
164 /* FIXME: some day, we'll not use global phy */
166 struct usb_phy *transceiver;
170 static inline struct ci_role_driver *ci_role(struct ci13xxx *ci)
172 BUG_ON(ci->role >= CI_ROLE_END || !ci->roles[ci->role]);
173 return ci->roles[ci->role];
176 static inline int ci_role_start(struct ci13xxx *ci, enum ci_role role)
180 if (role >= CI_ROLE_END)
183 if (!ci->roles[role])
186 ret = ci->roles[role]->start(ci);
192 static inline void ci_role_stop(struct ci13xxx *ci)
194 enum ci_role role = ci->role;
196 if (role == CI_ROLE_END)
199 ci->role = CI_ROLE_END;
201 ci->roles[role]->stop(ci);
204 /******************************************************************************
206 *****************************************************************************/
208 #define REG_BITS (32)
210 /* register indices */
216 CAP_LAST = CAP_TESTMODE,
232 /* endptctrl1..15 follow */
233 OP_LAST = OP_ENDPTCTRL + ENDPT_MAX / 2,
237 * ffs_nr: find first (least significant) bit set
238 * @x: the word to search
240 * This function returns bit number (instead of position)
242 static inline int ffs_nr(u32 x)
250 * hw_read: reads from a hw register
251 * @reg: register index
252 * @mask: bitfield mask
254 * This function returns register contents
256 static inline u32 hw_read(struct ci13xxx *ci, enum ci13xxx_regs reg, u32 mask)
258 return ioread32(ci->hw_bank.regmap[reg]) & mask;
262 * hw_write: writes to a hw register
263 * @reg: register index
264 * @mask: bitfield mask
267 static inline void hw_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
271 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)
274 iowrite32(data, ci->hw_bank.regmap[reg]);
278 * hw_test_and_clear: tests & clears a hw register
279 * @reg: register index
280 * @mask: bitfield mask
282 * This function returns register contents
284 static inline u32 hw_test_and_clear(struct ci13xxx *ci, enum ci13xxx_regs reg,
287 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;
289 iowrite32(val, ci->hw_bank.regmap[reg]);
294 * hw_test_and_write: tests & writes a hw register
295 * @reg: register index
296 * @mask: bitfield mask
299 * This function returns register contents
301 static inline u32 hw_test_and_write(struct ci13xxx *ci, enum ci13xxx_regs reg,
304 u32 val = hw_read(ci, reg, ~0);
306 hw_write(ci, reg, mask, data);
307 return (val & mask) >> ffs_nr(mask);
310 int hw_device_reset(struct ci13xxx *ci, u32 mode);
312 int hw_port_test_set(struct ci13xxx *ci, u8 mode);
314 u8 hw_port_test_get(struct ci13xxx *ci);
316 #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */