2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
47 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
51 #include <linux/delay.h>
52 #include <linux/device.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
55 #include <linux/module.h>
56 #include <linux/idr.h>
57 #include <linux/interrupt.h>
59 #include <linux/kernel.h>
60 #include <linux/slab.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/usb/ch9.h>
63 #include <linux/usb/gadget.h>
64 #include <linux/usb/otg.h>
65 #include <linux/usb/chipidea.h>
66 #include <linux/usb/of.h>
68 #include <linux/phy.h>
69 #include <linux/regulator/consumer.h>
78 /* Controller register map */
79 static const u8 ci_regs_nolpm[] = {
80 [CAP_CAPLENGTH] = 0x00U,
81 [CAP_HCCPARAMS] = 0x08U,
82 [CAP_DCCPARAMS] = 0x24U,
83 [CAP_TESTMODE] = 0x38U,
87 [OP_DEVICEADDR] = 0x14U,
88 [OP_ENDPTLISTADDR] = 0x18U,
93 [OP_ENDPTSETUPSTAT] = 0x6CU,
94 [OP_ENDPTPRIME] = 0x70U,
95 [OP_ENDPTFLUSH] = 0x74U,
96 [OP_ENDPTSTAT] = 0x78U,
97 [OP_ENDPTCOMPLETE] = 0x7CU,
98 [OP_ENDPTCTRL] = 0x80U,
101 static const u8 ci_regs_lpm[] = {
102 [CAP_CAPLENGTH] = 0x00U,
103 [CAP_HCCPARAMS] = 0x08U,
104 [CAP_DCCPARAMS] = 0x24U,
105 [CAP_TESTMODE] = 0xFCU,
108 [OP_USBINTR] = 0x08U,
109 [OP_DEVICEADDR] = 0x14U,
110 [OP_ENDPTLISTADDR] = 0x18U,
114 [OP_USBMODE] = 0xC8U,
115 [OP_ENDPTSETUPSTAT] = 0xD8U,
116 [OP_ENDPTPRIME] = 0xDCU,
117 [OP_ENDPTFLUSH] = 0xE0U,
118 [OP_ENDPTSTAT] = 0xE4U,
119 [OP_ENDPTCOMPLETE] = 0xE8U,
120 [OP_ENDPTCTRL] = 0xECU,
123 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
127 for (i = 0; i < OP_ENDPTCTRL; i++)
128 ci->hw_bank.regmap[i] =
129 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
130 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132 for (; i <= OP_LAST; i++)
133 ci->hw_bank.regmap[i] = ci->hw_bank.op +
134 4 * (i - OP_ENDPTCTRL) +
136 ? ci_regs_lpm[OP_ENDPTCTRL]
137 : ci_regs_nolpm[OP_ENDPTCTRL]);
143 * hw_port_test_set: writes port test mode (execute without interruption)
146 * This function returns an error code
148 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
150 const u8 TEST_MODE_MAX = 7;
152 if (mode > TEST_MODE_MAX)
155 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
160 * hw_port_test_get: reads port test mode value
162 * This function returns port test mode value
164 u8 hw_port_test_get(struct ci_hdrc *ci)
166 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
169 /* The PHY enters/leaves low power mode */
170 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
172 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
173 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
175 if (enable && !lpm) {
176 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
177 PORTSC_PHCD(ci->hw_bank.lpm));
178 } else if (!enable && lpm) {
179 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
182 * The controller needs at least 1ms to reflect
183 * PHY's status, the PHY also needs some time (less
184 * than 1ms) to leave low power mode.
186 usleep_range(1500, 2000);
190 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
194 /* bank is a module variable */
195 ci->hw_bank.abs = base;
197 ci->hw_bank.cap = ci->hw_bank.abs;
198 ci->hw_bank.cap += ci->platdata->capoffset;
199 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
201 hw_alloc_regmap(ci, false);
202 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
203 __ffs(HCCPARAMS_LEN);
204 ci->hw_bank.lpm = reg;
206 hw_alloc_regmap(ci, !!reg);
207 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
208 ci->hw_bank.size += OP_LAST;
209 ci->hw_bank.size /= sizeof(u32);
211 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
212 __ffs(DCCPARAMS_DEN);
213 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
215 if (ci->hw_ep_max > ENDPT_MAX)
218 ci_hdrc_enter_lpm(ci, false);
220 /* Disable all interrupts bits */
221 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
223 /* Clear all interrupts status bits*/
224 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
226 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
227 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
229 /* setup lock mode ? */
231 /* ENDPTSETUPSTAT is '0' by default */
233 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
238 static void hw_phymode_configure(struct ci_hdrc *ci)
240 u32 portsc, lpm, sts = 0;
242 switch (ci->platdata->phy_mode) {
243 case USBPHY_INTERFACE_MODE_UTMI:
244 portsc = PORTSC_PTS(PTS_UTMI);
245 lpm = DEVLC_PTS(PTS_UTMI);
247 case USBPHY_INTERFACE_MODE_UTMIW:
248 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
249 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
251 case USBPHY_INTERFACE_MODE_ULPI:
252 portsc = PORTSC_PTS(PTS_ULPI);
253 lpm = DEVLC_PTS(PTS_ULPI);
255 case USBPHY_INTERFACE_MODE_SERIAL:
256 portsc = PORTSC_PTS(PTS_SERIAL);
257 lpm = DEVLC_PTS(PTS_SERIAL);
260 case USBPHY_INTERFACE_MODE_HSIC:
261 portsc = PORTSC_PTS(PTS_HSIC);
262 lpm = DEVLC_PTS(PTS_HSIC);
268 if (ci->hw_bank.lpm) {
269 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
271 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
273 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
275 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
280 * ci_usb_phy_init: initialize phy according to different phy type
281 * @ci: the controller
283 * This function returns an error code if usb_phy_init has failed
285 static int ci_usb_phy_init(struct ci_hdrc *ci)
289 switch (ci->platdata->phy_mode) {
290 case USBPHY_INTERFACE_MODE_UTMI:
291 case USBPHY_INTERFACE_MODE_UTMIW:
292 case USBPHY_INTERFACE_MODE_HSIC:
293 ret = usb_phy_init(ci->transceiver);
296 hw_phymode_configure(ci);
298 case USBPHY_INTERFACE_MODE_ULPI:
299 case USBPHY_INTERFACE_MODE_SERIAL:
300 hw_phymode_configure(ci);
301 ret = usb_phy_init(ci->transceiver);
306 ret = usb_phy_init(ci->transceiver);
313 * hw_device_reset: resets chip (execute without interruption)
314 * @ci: the controller
316 * This function returns an error code
318 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
320 /* should flush & stop before reset */
321 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
322 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
324 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
325 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
326 udelay(10); /* not RTOS friendly */
328 if (ci->platdata->notify_event)
329 ci->platdata->notify_event(ci,
330 CI_HDRC_CONTROLLER_RESET_EVENT);
332 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
333 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
335 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
337 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
339 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
342 /* USBMODE should be configured step by step */
343 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
344 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
346 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
348 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
349 pr_err("cannot enter in %s mode", ci_role(ci)->name);
350 pr_err("lpm = %i", ci->hw_bank.lpm);
358 * hw_wait_reg: wait the register value
360 * Sometimes, it needs to wait register value before going on.
361 * Eg, when switch to device mode, the vbus value should be lower
362 * than OTGSC_BSV before connects to host.
364 * @ci: the controller
365 * @reg: register index
367 * @value: the bit value to wait
368 * @timeout_ms: timeout in millisecond
370 * This function returns an error code if timeout
372 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
373 u32 value, unsigned int timeout_ms)
375 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
377 while (hw_read(ci, reg, mask) != value) {
378 if (time_after(jiffies, elapse)) {
379 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
389 static irqreturn_t ci_irq(int irq, void *data)
391 struct ci_hdrc *ci = data;
392 irqreturn_t ret = IRQ_NONE;
396 otgsc = hw_read(ci, OP_OTGSC, ~0);
399 * Handle id change interrupt, it indicates device/host function
402 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
404 ci_clear_otg_interrupt(ci, OTGSC_IDIS);
405 disable_irq_nosync(ci->irq);
406 queue_work(ci->wq, &ci->work);
411 * Handle vbus change interrupt, it indicates device connection
412 * and disconnection events.
414 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
415 ci->b_sess_valid_event = true;
416 ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
417 disable_irq_nosync(ci->irq);
418 queue_work(ci->wq, &ci->work);
422 /* Handle device/host interrupt */
423 if (ci->role != CI_ROLE_END)
424 ret = ci_role(ci)->irq(ci);
429 static int ci_get_platdata(struct device *dev,
430 struct ci_hdrc_platform_data *platdata)
432 if (!platdata->phy_mode)
433 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
435 if (!platdata->dr_mode)
436 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
438 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
439 platdata->dr_mode = USB_DR_MODE_OTG;
441 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
442 /* Get the vbus regulator */
443 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
444 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
445 return -EPROBE_DEFER;
446 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
447 /* no vbus regualator is needed */
448 platdata->reg_vbus = NULL;
449 } else if (IS_ERR(platdata->reg_vbus)) {
450 dev_err(dev, "Getting regulator error: %ld\n",
451 PTR_ERR(platdata->reg_vbus));
452 return PTR_ERR(platdata->reg_vbus);
456 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
457 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
462 static DEFINE_IDA(ci_ida);
464 struct platform_device *ci_hdrc_add_device(struct device *dev,
465 struct resource *res, int nres,
466 struct ci_hdrc_platform_data *platdata)
468 struct platform_device *pdev;
471 ret = ci_get_platdata(dev, platdata);
475 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
479 pdev = platform_device_alloc("ci_hdrc", id);
485 pdev->dev.parent = dev;
486 pdev->dev.dma_mask = dev->dma_mask;
487 pdev->dev.dma_parms = dev->dma_parms;
488 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
490 ret = platform_device_add_resources(pdev, res, nres);
494 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
498 ret = platform_device_add(pdev);
505 platform_device_put(pdev);
507 ida_simple_remove(&ci_ida, id);
510 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
512 void ci_hdrc_remove_device(struct platform_device *pdev)
515 platform_device_unregister(pdev);
516 ida_simple_remove(&ci_ida, id);
518 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
520 static inline void ci_role_destroy(struct ci_hdrc *ci)
522 ci_hdrc_gadget_destroy(ci);
523 ci_hdrc_host_destroy(ci);
525 ci_hdrc_otg_destroy(ci);
528 static void ci_get_otg_capable(struct ci_hdrc *ci)
530 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
533 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
534 DCCPARAMS_DC | DCCPARAMS_HC)
535 == (DCCPARAMS_DC | DCCPARAMS_HC));
537 dev_dbg(ci->dev, "It is OTG capable controller\n");
538 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
539 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
543 static int ci_hdrc_probe(struct platform_device *pdev)
545 struct device *dev = &pdev->dev;
547 struct resource *res;
550 enum usb_dr_mode dr_mode;
552 if (!dev_get_platdata(dev)) {
553 dev_err(dev, "platform data missing\n");
557 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
558 base = devm_ioremap_resource(dev, res);
560 return PTR_ERR(base);
562 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
564 dev_err(dev, "can't allocate device\n");
569 ci->platdata = dev_get_platdata(dev);
570 ci->imx28_write_fix = !!(ci->platdata->flags &
571 CI_HDRC_IMX28_WRITE_FIX);
573 ret = hw_device_init(ci, base);
575 dev_err(dev, "can't initialize hardware\n");
579 if (ci->platdata->phy)
580 ci->transceiver = ci->platdata->phy;
582 ci->transceiver = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
584 if (IS_ERR(ci->transceiver)) {
585 ret = PTR_ERR(ci->transceiver);
587 * if -ENXIO is returned, it means PHY layer wasn't
588 * enabled, so it makes no sense to return -EPROBE_DEFER
589 * in that case, since no PHY driver will ever probe.
594 dev_err(dev, "no usb2 phy configured\n");
595 return -EPROBE_DEFER;
598 ret = ci_usb_phy_init(ci);
600 dev_err(dev, "unable to init phy: %d\n", ret);
604 ci->hw_bank.phys = res->start;
606 ci->irq = platform_get_irq(pdev, 0);
608 dev_err(dev, "missing IRQ\n");
613 ci_get_otg_capable(ci);
615 dr_mode = ci->platdata->dr_mode;
616 /* initialize role(s) before the interrupt is requested */
617 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
618 ret = ci_hdrc_host_init(ci);
620 dev_info(dev, "doesn't support host\n");
623 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
624 ret = ci_hdrc_gadget_init(ci);
626 dev_info(dev, "doesn't support gadget\n");
629 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
630 dev_err(dev, "no supported roles\n");
636 ret = ci_hdrc_otg_init(ci);
638 dev_err(dev, "init otg fails, ret = %d\n", ret);
643 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
646 * ID pin needs 1ms debouce time,
647 * we delay 2ms for safe.
650 ci->role = ci_otg_role(ci);
651 ci_enable_otg_interrupt(ci, OTGSC_IDIE);
654 * If the controller is not OTG capable, but support
655 * role switch, the defalt role is gadget, and the
656 * user can switch it through debugfs.
658 ci->role = CI_ROLE_GADGET;
661 ci->role = ci->roles[CI_ROLE_HOST]
666 /* only update vbus status for peripheral */
667 if (ci->role == CI_ROLE_GADGET)
668 ci_handle_vbus_change(ci);
670 ret = ci_role_start(ci, ci->role);
672 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
676 platform_set_drvdata(pdev, ci);
677 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
682 ret = dbg_create_files(ci);
686 free_irq(ci->irq, ci);
690 usb_phy_shutdown(ci->transceiver);
695 static int ci_hdrc_remove(struct platform_device *pdev)
697 struct ci_hdrc *ci = platform_get_drvdata(pdev);
699 dbg_remove_files(ci);
700 free_irq(ci->irq, ci);
702 ci_hdrc_enter_lpm(ci, true);
703 usb_phy_shutdown(ci->transceiver);
704 kfree(ci->hw_bank.regmap);
709 static struct platform_driver ci_hdrc_driver = {
710 .probe = ci_hdrc_probe,
711 .remove = ci_hdrc_remove,
717 module_platform_driver(ci_hdrc_driver);
719 MODULE_ALIAS("platform:ci_hdrc");
720 MODULE_LICENSE("GPL v2");
721 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
722 MODULE_DESCRIPTION("ChipIdea HDRC Driver");