2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
45 * - Suspend & Remote Wakeup
47 #include <linux/delay.h>
48 #include <linux/device.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/extcon.h>
51 #include <linux/phy/phy.h>
52 #include <linux/platform_device.h>
53 #include <linux/module.h>
54 #include <linux/idr.h>
55 #include <linux/interrupt.h>
57 #include <linux/kernel.h>
58 #include <linux/slab.h>
59 #include <linux/pm_runtime.h>
60 #include <linux/usb/ch9.h>
61 #include <linux/usb/gadget.h>
62 #include <linux/usb/otg.h>
63 #include <linux/usb/chipidea.h>
64 #include <linux/usb/of.h>
66 #include <linux/phy.h>
67 #include <linux/regulator/consumer.h>
68 #include <linux/usb/ehci_def.h>
78 /* Controller register map */
79 static const u8 ci_regs_nolpm[] = {
80 [CAP_CAPLENGTH] = 0x00U,
81 [CAP_HCCPARAMS] = 0x08U,
82 [CAP_DCCPARAMS] = 0x24U,
83 [CAP_TESTMODE] = 0x38U,
87 [OP_DEVICEADDR] = 0x14U,
88 [OP_ENDPTLISTADDR] = 0x18U,
90 [OP_BURSTSIZE] = 0x20U,
95 [OP_ENDPTSETUPSTAT] = 0x6CU,
96 [OP_ENDPTPRIME] = 0x70U,
97 [OP_ENDPTFLUSH] = 0x74U,
98 [OP_ENDPTSTAT] = 0x78U,
99 [OP_ENDPTCOMPLETE] = 0x7CU,
100 [OP_ENDPTCTRL] = 0x80U,
103 static const u8 ci_regs_lpm[] = {
104 [CAP_CAPLENGTH] = 0x00U,
105 [CAP_HCCPARAMS] = 0x08U,
106 [CAP_DCCPARAMS] = 0x24U,
107 [CAP_TESTMODE] = 0xFCU,
110 [OP_USBINTR] = 0x08U,
111 [OP_DEVICEADDR] = 0x14U,
112 [OP_ENDPTLISTADDR] = 0x18U,
114 [OP_BURSTSIZE] = 0x20U,
118 [OP_USBMODE] = 0xC8U,
119 [OP_ENDPTSETUPSTAT] = 0xD8U,
120 [OP_ENDPTPRIME] = 0xDCU,
121 [OP_ENDPTFLUSH] = 0xE0U,
122 [OP_ENDPTSTAT] = 0xE4U,
123 [OP_ENDPTCOMPLETE] = 0xE8U,
124 [OP_ENDPTCTRL] = 0xECU,
127 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
131 for (i = 0; i < OP_ENDPTCTRL; i++)
132 ci->hw_bank.regmap[i] =
133 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
134 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
136 for (; i <= OP_LAST; i++)
137 ci->hw_bank.regmap[i] = ci->hw_bank.op +
138 4 * (i - OP_ENDPTCTRL) +
140 ? ci_regs_lpm[OP_ENDPTCTRL]
141 : ci_regs_nolpm[OP_ENDPTCTRL]);
145 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
147 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
148 enum ci_revision rev = CI_REVISION_UNKNOWN;
151 rev = hw_read_id_reg(ci, ID_ID, REVISION)
153 rev += CI_REVISION_20;
154 } else if (ver == 0x0) {
155 rev = CI_REVISION_1X;
162 * hw_read_intr_enable: returns interrupt enable register
164 * @ci: the controller
166 * This function returns register data
168 u32 hw_read_intr_enable(struct ci_hdrc *ci)
170 return hw_read(ci, OP_USBINTR, ~0);
174 * hw_read_intr_status: returns interrupt status register
176 * @ci: the controller
178 * This function returns register data
180 u32 hw_read_intr_status(struct ci_hdrc *ci)
182 return hw_read(ci, OP_USBSTS, ~0);
186 * hw_port_test_set: writes port test mode (execute without interruption)
189 * This function returns an error code
191 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
193 const u8 TEST_MODE_MAX = 7;
195 if (mode > TEST_MODE_MAX)
198 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
203 * hw_port_test_get: reads port test mode value
205 * @ci: the controller
207 * This function returns port test mode value
209 u8 hw_port_test_get(struct ci_hdrc *ci)
211 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
214 static void hw_wait_phy_stable(void)
217 * The phy needs some delay to output the stable status from low
218 * power mode. And for OTGSC, the status inputs are debounced
219 * using a 1 ms time constant, so, delay 2ms for controller to get
220 * the stable status, like vbus and id when the phy leaves low power.
222 usleep_range(2000, 2500);
225 /* The PHY enters/leaves low power mode */
226 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
228 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
229 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
232 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
233 PORTSC_PHCD(ci->hw_bank.lpm));
234 else if (!enable && lpm)
235 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
239 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
243 /* bank is a module variable */
244 ci->hw_bank.abs = base;
246 ci->hw_bank.cap = ci->hw_bank.abs;
247 ci->hw_bank.cap += ci->platdata->capoffset;
248 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
250 hw_alloc_regmap(ci, false);
251 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
252 __ffs(HCCPARAMS_LEN);
253 ci->hw_bank.lpm = reg;
255 hw_alloc_regmap(ci, !!reg);
256 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
257 ci->hw_bank.size += OP_LAST;
258 ci->hw_bank.size /= sizeof(u32);
260 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
261 __ffs(DCCPARAMS_DEN);
262 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
264 if (ci->hw_ep_max > ENDPT_MAX)
267 ci_hdrc_enter_lpm(ci, false);
269 /* Disable all interrupts bits */
270 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
272 /* Clear all interrupts status bits*/
273 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
275 ci->rev = ci_get_revision(ci);
278 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
279 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
281 /* setup lock mode ? */
283 /* ENDPTSETUPSTAT is '0' by default */
285 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
290 static void hw_phymode_configure(struct ci_hdrc *ci)
292 u32 portsc, lpm, sts = 0;
294 switch (ci->platdata->phy_mode) {
295 case USBPHY_INTERFACE_MODE_UTMI:
296 portsc = PORTSC_PTS(PTS_UTMI);
297 lpm = DEVLC_PTS(PTS_UTMI);
299 case USBPHY_INTERFACE_MODE_UTMIW:
300 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
301 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
303 case USBPHY_INTERFACE_MODE_ULPI:
304 portsc = PORTSC_PTS(PTS_ULPI);
305 lpm = DEVLC_PTS(PTS_ULPI);
307 case USBPHY_INTERFACE_MODE_SERIAL:
308 portsc = PORTSC_PTS(PTS_SERIAL);
309 lpm = DEVLC_PTS(PTS_SERIAL);
312 case USBPHY_INTERFACE_MODE_HSIC:
313 portsc = PORTSC_PTS(PTS_HSIC);
314 lpm = DEVLC_PTS(PTS_HSIC);
320 if (ci->hw_bank.lpm) {
321 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
323 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
325 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
327 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
332 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
334 * @ci: the controller
336 * This function returns an error code if the phy failed to init
338 static int _ci_usb_phy_init(struct ci_hdrc *ci)
343 ret = phy_init(ci->phy);
347 ret = phy_power_on(ci->phy);
353 ret = usb_phy_init(ci->usb_phy);
360 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
362 * @ci: the controller
364 static void ci_usb_phy_exit(struct ci_hdrc *ci)
367 phy_power_off(ci->phy);
370 usb_phy_shutdown(ci->usb_phy);
375 * ci_usb_phy_init: initialize phy according to different phy type
376 * @ci: the controller
378 * This function returns an error code if usb_phy_init has failed
380 static int ci_usb_phy_init(struct ci_hdrc *ci)
384 switch (ci->platdata->phy_mode) {
385 case USBPHY_INTERFACE_MODE_UTMI:
386 case USBPHY_INTERFACE_MODE_UTMIW:
387 case USBPHY_INTERFACE_MODE_HSIC:
388 ret = _ci_usb_phy_init(ci);
390 hw_wait_phy_stable();
393 hw_phymode_configure(ci);
395 case USBPHY_INTERFACE_MODE_ULPI:
396 case USBPHY_INTERFACE_MODE_SERIAL:
397 hw_phymode_configure(ci);
398 ret = _ci_usb_phy_init(ci);
403 ret = _ci_usb_phy_init(ci);
405 hw_wait_phy_stable();
413 * ci_platform_configure: do controller configure
414 * @ci: the controller
417 void ci_platform_configure(struct ci_hdrc *ci)
419 bool is_device_mode, is_host_mode;
421 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
422 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
424 if (is_device_mode &&
425 (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING))
426 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
429 (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING))
430 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
432 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
434 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
436 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
439 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
440 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
442 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
444 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
445 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
446 ci->platdata->ahb_burst_config);
448 /* override burst size, take effect only when ahb_burst_config is 0 */
449 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
450 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
451 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
452 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
454 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
455 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
456 ci->platdata->rx_burst_size);
461 * hw_controller_reset: do controller reset
462 * @ci: the controller
464 * This function returns an error code
466 static int hw_controller_reset(struct ci_hdrc *ci)
470 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
471 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
481 * hw_device_reset: resets chip (execute without interruption)
482 * @ci: the controller
484 * This function returns an error code
486 int hw_device_reset(struct ci_hdrc *ci)
490 /* should flush & stop before reset */
491 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
492 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
494 ret = hw_controller_reset(ci);
496 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
500 if (ci->platdata->notify_event)
501 ci->platdata->notify_event(ci,
502 CI_HDRC_CONTROLLER_RESET_EVENT);
504 /* USBMODE should be configured step by step */
505 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
506 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
508 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
510 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
511 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
512 pr_err("lpm = %i", ci->hw_bank.lpm);
516 ci_platform_configure(ci);
522 * hw_wait_reg: wait the register value
524 * Sometimes, it needs to wait register value before going on.
525 * Eg, when switch to device mode, the vbus value should be lower
526 * than OTGSC_BSV before connects to host.
528 * @ci: the controller
529 * @reg: register index
531 * @value: the bit value to wait
532 * @timeout_ms: timeout in millisecond
534 * This function returns an error code if timeout
536 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
537 u32 value, unsigned int timeout_ms)
539 unsigned long elapse = jiffies + msecs_to_jiffies(timeout_ms);
541 while (hw_read(ci, reg, mask) != value) {
542 if (time_after(jiffies, elapse)) {
543 dev_err(ci->dev, "timeout waiting for %08x in %d\n",
553 static irqreturn_t ci_irq(int irq, void *data)
555 struct ci_hdrc *ci = data;
556 irqreturn_t ret = IRQ_NONE;
560 disable_irq_nosync(irq);
561 ci->wakeup_int = true;
562 pm_runtime_get(ci->dev);
567 otgsc = hw_read_otgsc(ci, ~0);
568 if (ci_otg_is_fsm_mode(ci)) {
569 ret = ci_otg_fsm_irq(ci);
570 if (ret == IRQ_HANDLED)
576 * Handle id change interrupt, it indicates device/host function
579 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
581 /* Clear ID change irq status */
582 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
583 ci_otg_queue_work(ci);
588 * Handle vbus change interrupt, it indicates device connection
589 * and disconnection events.
591 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
592 ci->b_sess_valid_event = true;
594 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
595 ci_otg_queue_work(ci);
599 /* Handle device/host interrupt */
600 if (ci->role != CI_ROLE_END)
601 ret = ci_role(ci)->irq(ci);
606 static int ci_vbus_notifier(struct notifier_block *nb, unsigned long event,
609 struct ci_hdrc_cable *vbus = container_of(nb, struct ci_hdrc_cable, nb);
610 struct ci_hdrc *ci = vbus->ci;
617 vbus->changed = true;
623 static int ci_id_notifier(struct notifier_block *nb, unsigned long event,
626 struct ci_hdrc_cable *id = container_of(nb, struct ci_hdrc_cable, nb);
627 struct ci_hdrc *ci = id->ci;
640 static int ci_get_platdata(struct device *dev,
641 struct ci_hdrc_platform_data *platdata)
643 struct extcon_dev *ext_vbus, *ext_id;
644 struct ci_hdrc_cable *cable;
647 if (!platdata->phy_mode)
648 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
650 if (!platdata->dr_mode)
651 platdata->dr_mode = of_usb_get_dr_mode(dev->of_node);
653 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
654 platdata->dr_mode = USB_DR_MODE_OTG;
656 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
657 /* Get the vbus regulator */
658 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
659 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
660 return -EPROBE_DEFER;
661 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
662 /* no vbus regulator is needed */
663 platdata->reg_vbus = NULL;
664 } else if (IS_ERR(platdata->reg_vbus)) {
665 dev_err(dev, "Getting regulator error: %ld\n",
666 PTR_ERR(platdata->reg_vbus));
667 return PTR_ERR(platdata->reg_vbus);
669 /* Get TPL support */
670 if (!platdata->tpl_support)
671 platdata->tpl_support =
672 of_usb_host_tpl_support(dev->of_node);
675 if (platdata->dr_mode == USB_DR_MODE_OTG) {
676 /* We can support HNP and SRP of OTG 2.0 */
677 platdata->ci_otg_caps.otg_rev = 0x0200;
678 platdata->ci_otg_caps.hnp_support = true;
679 platdata->ci_otg_caps.srp_support = true;
681 /* Update otg capabilities by DT properties */
682 ret = of_usb_update_otg_caps(dev->of_node,
683 &platdata->ci_otg_caps);
688 if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
689 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
691 platdata->itc_setting = 1;
692 if (of_find_property(dev->of_node, "itc-setting", NULL)) {
693 ret = of_property_read_u32(dev->of_node, "itc-setting",
694 &platdata->itc_setting);
697 "failed to get itc-setting\n");
702 if (of_find_property(dev->of_node, "ahb-burst-config", NULL)) {
703 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
704 &platdata->ahb_burst_config);
707 "failed to get ahb-burst-config\n");
710 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
713 if (of_find_property(dev->of_node, "tx-burst-size-dword", NULL)) {
714 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
715 &platdata->tx_burst_size);
718 "failed to get tx-burst-size-dword\n");
721 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
724 if (of_find_property(dev->of_node, "rx-burst-size-dword", NULL)) {
725 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
726 &platdata->rx_burst_size);
729 "failed to get rx-burst-size-dword\n");
732 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
735 ext_id = ERR_PTR(-ENODEV);
736 ext_vbus = ERR_PTR(-ENODEV);
737 if (of_property_read_bool(dev->of_node, "extcon")) {
738 /* Each one of them is not mandatory */
739 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
740 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
741 return PTR_ERR(ext_vbus);
743 ext_id = extcon_get_edev_by_phandle(dev, 1);
744 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
745 return PTR_ERR(ext_id);
748 cable = &platdata->vbus_extcon;
749 cable->nb.notifier_call = ci_vbus_notifier;
750 cable->edev = ext_vbus;
752 if (!IS_ERR(ext_vbus)) {
753 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB);
757 cable->state = false;
760 cable = &platdata->id_extcon;
761 cable->nb.notifier_call = ci_id_notifier;
762 cable->edev = ext_id;
764 if (!IS_ERR(ext_id)) {
765 ret = extcon_get_cable_state_(cable->edev, EXTCON_USB_HOST);
767 cable->state = false;
774 static int ci_extcon_register(struct ci_hdrc *ci)
776 struct ci_hdrc_cable *id, *vbus;
779 id = &ci->platdata->id_extcon;
781 if (!IS_ERR(id->edev)) {
782 ret = extcon_register_notifier(id->edev, EXTCON_USB_HOST,
785 dev_err(ci->dev, "register ID failed\n");
790 vbus = &ci->platdata->vbus_extcon;
792 if (!IS_ERR(vbus->edev)) {
793 ret = extcon_register_notifier(vbus->edev, EXTCON_USB,
796 extcon_unregister_notifier(id->edev, EXTCON_USB_HOST,
798 dev_err(ci->dev, "register VBUS failed\n");
806 static void ci_extcon_unregister(struct ci_hdrc *ci)
808 struct ci_hdrc_cable *cable;
810 cable = &ci->platdata->id_extcon;
811 if (!IS_ERR(cable->edev))
812 extcon_unregister_notifier(cable->edev, EXTCON_USB_HOST,
815 cable = &ci->platdata->vbus_extcon;
816 if (!IS_ERR(cable->edev))
817 extcon_unregister_notifier(cable->edev, EXTCON_USB, &cable->nb);
820 static DEFINE_IDA(ci_ida);
822 struct platform_device *ci_hdrc_add_device(struct device *dev,
823 struct resource *res, int nres,
824 struct ci_hdrc_platform_data *platdata)
826 struct platform_device *pdev;
829 ret = ci_get_platdata(dev, platdata);
833 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
837 pdev = platform_device_alloc("ci_hdrc", id);
843 pdev->dev.parent = dev;
844 pdev->dev.dma_mask = dev->dma_mask;
845 pdev->dev.dma_parms = dev->dma_parms;
846 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
848 ret = platform_device_add_resources(pdev, res, nres);
852 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
856 ret = platform_device_add(pdev);
863 platform_device_put(pdev);
865 ida_simple_remove(&ci_ida, id);
868 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
870 void ci_hdrc_remove_device(struct platform_device *pdev)
873 platform_device_unregister(pdev);
874 ida_simple_remove(&ci_ida, id);
876 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
878 static inline void ci_role_destroy(struct ci_hdrc *ci)
880 ci_hdrc_gadget_destroy(ci);
881 ci_hdrc_host_destroy(ci);
883 ci_hdrc_otg_destroy(ci);
886 static void ci_get_otg_capable(struct ci_hdrc *ci)
888 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
891 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
892 DCCPARAMS_DC | DCCPARAMS_HC)
893 == (DCCPARAMS_DC | DCCPARAMS_HC));
895 dev_dbg(ci->dev, "It is OTG capable controller\n");
896 /* Disable and clear all OTG irq */
897 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
898 OTGSC_INT_STATUS_BITS);
902 static int ci_hdrc_probe(struct platform_device *pdev)
904 struct device *dev = &pdev->dev;
906 struct resource *res;
909 enum usb_dr_mode dr_mode;
911 if (!dev_get_platdata(dev)) {
912 dev_err(dev, "platform data missing\n");
916 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
917 base = devm_ioremap_resource(dev, res);
919 return PTR_ERR(base);
921 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
926 ci->platdata = dev_get_platdata(dev);
927 ci->imx28_write_fix = !!(ci->platdata->flags &
928 CI_HDRC_IMX28_WRITE_FIX);
929 ci->supports_runtime_pm = !!(ci->platdata->flags &
930 CI_HDRC_SUPPORTS_RUNTIME_PM);
932 ret = hw_device_init(ci, base);
934 dev_err(dev, "can't initialize hardware\n");
938 if (ci->platdata->phy) {
939 ci->phy = ci->platdata->phy;
940 } else if (ci->platdata->usb_phy) {
941 ci->usb_phy = ci->platdata->usb_phy;
943 ci->phy = devm_phy_get(dev->parent, "usb-phy");
944 ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
946 /* if both generic PHY and USB PHY layers aren't enabled */
947 if (PTR_ERR(ci->phy) == -ENOSYS &&
948 PTR_ERR(ci->usb_phy) == -ENXIO)
951 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
952 return -EPROBE_DEFER;
956 else if (IS_ERR(ci->usb_phy))
960 ret = ci_usb_phy_init(ci);
962 dev_err(dev, "unable to init phy: %d\n", ret);
966 ci->hw_bank.phys = res->start;
968 ci->irq = platform_get_irq(pdev, 0);
970 dev_err(dev, "missing IRQ\n");
975 ci_get_otg_capable(ci);
977 dr_mode = ci->platdata->dr_mode;
978 /* initialize role(s) before the interrupt is requested */
979 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
980 ret = ci_hdrc_host_init(ci);
982 dev_info(dev, "doesn't support host\n");
985 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
986 ret = ci_hdrc_gadget_init(ci);
988 dev_info(dev, "doesn't support gadget\n");
991 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
992 dev_err(dev, "no supported roles\n");
997 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
998 ret = ci_hdrc_otg_init(ci);
1000 dev_err(dev, "init otg fails, ret = %d\n", ret);
1005 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1007 ci->role = ci_otg_role(ci);
1008 /* Enable ID change irq */
1009 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1012 * If the controller is not OTG capable, but support
1013 * role switch, the defalt role is gadget, and the
1014 * user can switch it through debugfs.
1016 ci->role = CI_ROLE_GADGET;
1019 ci->role = ci->roles[CI_ROLE_HOST]
1024 if (!ci_otg_is_fsm_mode(ci)) {
1025 /* only update vbus status for peripheral */
1026 if (ci->role == CI_ROLE_GADGET)
1027 ci_handle_vbus_change(ci);
1029 ret = ci_role_start(ci, ci->role);
1031 dev_err(dev, "can't start %s role\n",
1037 platform_set_drvdata(pdev, ci);
1038 ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
1039 ci->platdata->name, ci);
1043 ret = ci_extcon_register(ci);
1047 if (ci->supports_runtime_pm) {
1048 pm_runtime_set_active(&pdev->dev);
1049 pm_runtime_enable(&pdev->dev);
1050 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1051 pm_runtime_mark_last_busy(ci->dev);
1052 pm_runtime_use_autosuspend(&pdev->dev);
1055 if (ci_otg_is_fsm_mode(ci))
1056 ci_hdrc_otg_fsm_start(ci);
1058 device_set_wakeup_capable(&pdev->dev, true);
1060 ret = dbg_create_files(ci);
1064 ci_extcon_unregister(ci);
1066 ci_role_destroy(ci);
1068 ci_usb_phy_exit(ci);
1073 static int ci_hdrc_remove(struct platform_device *pdev)
1075 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1077 if (ci->supports_runtime_pm) {
1078 pm_runtime_get_sync(&pdev->dev);
1079 pm_runtime_disable(&pdev->dev);
1080 pm_runtime_put_noidle(&pdev->dev);
1083 dbg_remove_files(ci);
1084 ci_extcon_unregister(ci);
1085 ci_role_destroy(ci);
1086 ci_hdrc_enter_lpm(ci, true);
1087 ci_usb_phy_exit(ci);
1093 /* Prepare wakeup by SRP before suspend */
1094 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1096 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1097 !hw_read_otgsc(ci, OTGSC_ID)) {
1098 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1100 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1105 /* Handle SRP when wakeup by data pulse */
1106 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1108 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1109 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1110 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1111 ci->fsm.a_srp_det = 1;
1112 ci->fsm.a_bus_drop = 0;
1116 ci_otg_queue_work(ci);
1120 static void ci_controller_suspend(struct ci_hdrc *ci)
1122 disable_irq(ci->irq);
1123 ci_hdrc_enter_lpm(ci, true);
1124 usb_phy_set_suspend(ci->usb_phy, 1);
1126 enable_irq(ci->irq);
1129 static int ci_controller_resume(struct device *dev)
1131 struct ci_hdrc *ci = dev_get_drvdata(dev);
1133 dev_dbg(dev, "at %s\n", __func__);
1140 ci_hdrc_enter_lpm(ci, false);
1142 usb_phy_set_suspend(ci->usb_phy, 0);
1143 usb_phy_set_wakeup(ci->usb_phy, false);
1144 hw_wait_phy_stable();
1148 if (ci->wakeup_int) {
1149 ci->wakeup_int = false;
1150 pm_runtime_mark_last_busy(ci->dev);
1151 pm_runtime_put_autosuspend(ci->dev);
1152 enable_irq(ci->irq);
1153 if (ci_otg_is_fsm_mode(ci))
1154 ci_otg_fsm_wakeup_by_srp(ci);
1160 #ifdef CONFIG_PM_SLEEP
1161 static int ci_suspend(struct device *dev)
1163 struct ci_hdrc *ci = dev_get_drvdata(dev);
1166 flush_workqueue(ci->wq);
1168 * Controller needs to be active during suspend, otherwise the core
1169 * may run resume when the parent is at suspend if other driver's
1170 * suspend fails, it occurs before parent's suspend has not started,
1171 * but the core suspend has finished.
1174 pm_runtime_resume(dev);
1181 if (device_may_wakeup(dev)) {
1182 if (ci_otg_is_fsm_mode(ci))
1183 ci_otg_fsm_suspend_for_srp(ci);
1185 usb_phy_set_wakeup(ci->usb_phy, true);
1186 enable_irq_wake(ci->irq);
1189 ci_controller_suspend(ci);
1194 static int ci_resume(struct device *dev)
1196 struct ci_hdrc *ci = dev_get_drvdata(dev);
1199 if (device_may_wakeup(dev))
1200 disable_irq_wake(ci->irq);
1202 ret = ci_controller_resume(dev);
1206 if (ci->supports_runtime_pm) {
1207 pm_runtime_disable(dev);
1208 pm_runtime_set_active(dev);
1209 pm_runtime_enable(dev);
1214 #endif /* CONFIG_PM_SLEEP */
1216 static int ci_runtime_suspend(struct device *dev)
1218 struct ci_hdrc *ci = dev_get_drvdata(dev);
1220 dev_dbg(dev, "at %s\n", __func__);
1227 if (ci_otg_is_fsm_mode(ci))
1228 ci_otg_fsm_suspend_for_srp(ci);
1230 usb_phy_set_wakeup(ci->usb_phy, true);
1231 ci_controller_suspend(ci);
1236 static int ci_runtime_resume(struct device *dev)
1238 return ci_controller_resume(dev);
1241 #endif /* CONFIG_PM */
1242 static const struct dev_pm_ops ci_pm_ops = {
1243 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1244 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1247 static struct platform_driver ci_hdrc_driver = {
1248 .probe = ci_hdrc_probe,
1249 .remove = ci_hdrc_remove,
1256 static int __init ci_hdrc_platform_register(void)
1258 ci_hdrc_host_driver_init();
1259 return platform_driver_register(&ci_hdrc_driver);
1261 module_init(ci_hdrc_platform_register);
1263 static void __exit ci_hdrc_platform_unregister(void)
1265 platform_driver_unregister(&ci_hdrc_driver);
1267 module_exit(ci_hdrc_platform_unregister);
1269 MODULE_ALIAS("platform:ci_hdrc");
1270 MODULE_LICENSE("GPL v2");
1271 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1272 MODULE_DESCRIPTION("ChipIdea HDRC Driver");