2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
47 * - GET_STATUS(device) - always reports 0
48 * - Gadget API (majority of optional features)
49 * - Suspend & Remote Wakeup
51 #include <linux/delay.h>
52 #include <linux/device.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/platform_device.h>
55 #include <linux/module.h>
56 #include <linux/idr.h>
57 #include <linux/interrupt.h>
59 #include <linux/kernel.h>
60 #include <linux/slab.h>
61 #include <linux/pm_runtime.h>
62 #include <linux/usb/ch9.h>
63 #include <linux/usb/gadget.h>
64 #include <linux/usb/otg.h>
65 #include <linux/usb/chipidea.h>
66 #include <linux/usb/of.h>
67 #include <linux/phy.h>
68 #include <linux/regulator/consumer.h>
77 /* Controller register map */
78 static uintptr_t ci_regs_nolpm[] = {
79 [CAP_CAPLENGTH] = 0x000UL,
80 [CAP_HCCPARAMS] = 0x008UL,
81 [CAP_DCCPARAMS] = 0x024UL,
82 [CAP_TESTMODE] = 0x038UL,
83 [OP_USBCMD] = 0x000UL,
84 [OP_USBSTS] = 0x004UL,
85 [OP_USBINTR] = 0x008UL,
86 [OP_DEVICEADDR] = 0x014UL,
87 [OP_ENDPTLISTADDR] = 0x018UL,
88 [OP_PORTSC] = 0x044UL,
91 [OP_USBMODE] = 0x068UL,
92 [OP_ENDPTSETUPSTAT] = 0x06CUL,
93 [OP_ENDPTPRIME] = 0x070UL,
94 [OP_ENDPTFLUSH] = 0x074UL,
95 [OP_ENDPTSTAT] = 0x078UL,
96 [OP_ENDPTCOMPLETE] = 0x07CUL,
97 [OP_ENDPTCTRL] = 0x080UL,
100 static uintptr_t ci_regs_lpm[] = {
101 [CAP_CAPLENGTH] = 0x000UL,
102 [CAP_HCCPARAMS] = 0x008UL,
103 [CAP_DCCPARAMS] = 0x024UL,
104 [CAP_TESTMODE] = 0x0FCUL,
105 [OP_USBCMD] = 0x000UL,
106 [OP_USBSTS] = 0x004UL,
107 [OP_USBINTR] = 0x008UL,
108 [OP_DEVICEADDR] = 0x014UL,
109 [OP_ENDPTLISTADDR] = 0x018UL,
110 [OP_PORTSC] = 0x044UL,
111 [OP_DEVLC] = 0x084UL,
112 [OP_OTGSC] = 0x0C4UL,
113 [OP_USBMODE] = 0x0C8UL,
114 [OP_ENDPTSETUPSTAT] = 0x0D8UL,
115 [OP_ENDPTPRIME] = 0x0DCUL,
116 [OP_ENDPTFLUSH] = 0x0E0UL,
117 [OP_ENDPTSTAT] = 0x0E4UL,
118 [OP_ENDPTCOMPLETE] = 0x0E8UL,
119 [OP_ENDPTCTRL] = 0x0ECUL,
122 static int hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
126 kfree(ci->hw_bank.regmap);
128 ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
130 if (!ci->hw_bank.regmap)
133 for (i = 0; i < OP_ENDPTCTRL; i++)
134 ci->hw_bank.regmap[i] =
135 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
136 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
138 for (; i <= OP_LAST; i++)
139 ci->hw_bank.regmap[i] = ci->hw_bank.op +
140 4 * (i - OP_ENDPTCTRL) +
142 ? ci_regs_lpm[OP_ENDPTCTRL]
143 : ci_regs_nolpm[OP_ENDPTCTRL]);
149 * hw_port_test_set: writes port test mode (execute without interruption)
152 * This function returns an error code
154 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
156 const u8 TEST_MODE_MAX = 7;
158 if (mode > TEST_MODE_MAX)
161 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
166 * hw_port_test_get: reads port test mode value
168 * This function returns port test mode value
170 u8 hw_port_test_get(struct ci_hdrc *ci)
172 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
175 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
179 /* bank is a module variable */
180 ci->hw_bank.abs = base;
182 ci->hw_bank.cap = ci->hw_bank.abs;
183 ci->hw_bank.cap += ci->platdata->capoffset;
184 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
186 hw_alloc_regmap(ci, false);
187 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
188 __ffs(HCCPARAMS_LEN);
189 ci->hw_bank.lpm = reg;
190 hw_alloc_regmap(ci, !!reg);
191 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
192 ci->hw_bank.size += OP_LAST;
193 ci->hw_bank.size /= sizeof(u32);
195 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
196 __ffs(DCCPARAMS_DEN);
197 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
199 if (ci->hw_ep_max > ENDPT_MAX)
202 /* Disable all interrupts bits */
203 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
205 /* Clear all interrupts status bits*/
206 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
208 dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
209 ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
211 /* setup lock mode ? */
213 /* ENDPTSETUPSTAT is '0' by default */
215 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
220 static void hw_phymode_configure(struct ci_hdrc *ci)
222 u32 portsc, lpm, sts;
224 switch (ci->platdata->phy_mode) {
225 case USBPHY_INTERFACE_MODE_UTMI:
226 portsc = PORTSC_PTS(PTS_UTMI);
227 lpm = DEVLC_PTS(PTS_UTMI);
229 case USBPHY_INTERFACE_MODE_UTMIW:
230 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
231 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
233 case USBPHY_INTERFACE_MODE_ULPI:
234 portsc = PORTSC_PTS(PTS_ULPI);
235 lpm = DEVLC_PTS(PTS_ULPI);
237 case USBPHY_INTERFACE_MODE_SERIAL:
238 portsc = PORTSC_PTS(PTS_SERIAL);
239 lpm = DEVLC_PTS(PTS_SERIAL);
242 case USBPHY_INTERFACE_MODE_HSIC:
243 portsc = PORTSC_PTS(PTS_HSIC);
244 lpm = DEVLC_PTS(PTS_HSIC);
250 if (ci->hw_bank.lpm) {
251 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
252 hw_write(ci, OP_DEVLC, DEVLC_STS, sts);
254 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
255 hw_write(ci, OP_PORTSC, PORTSC_STS, sts);
260 * hw_device_reset: resets chip (execute without interruption)
261 * @ci: the controller
263 * This function returns an error code
265 int hw_device_reset(struct ci_hdrc *ci, u32 mode)
267 /* should flush & stop before reset */
268 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
269 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
271 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
272 while (hw_read(ci, OP_USBCMD, USBCMD_RST))
273 udelay(10); /* not RTOS friendly */
275 if (ci->platdata->notify_event)
276 ci->platdata->notify_event(ci,
277 CI_HDRC_CONTROLLER_RESET_EVENT);
279 if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
280 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
282 /* USBMODE should be configured step by step */
283 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
284 hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
286 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
288 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
289 pr_err("cannot enter in %s mode", ci_role(ci)->name);
290 pr_err("lpm = %i", ci->hw_bank.lpm);
297 static irqreturn_t ci_irq(int irq, void *data)
299 struct ci_hdrc *ci = data;
300 irqreturn_t ret = IRQ_NONE;
304 otgsc = hw_read(ci, OP_OTGSC, ~0);
307 * Handle id change interrupt, it indicates device/host function
310 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
312 ci_clear_otg_interrupt(ci, OTGSC_IDIS);
313 disable_irq_nosync(ci->irq);
314 queue_work(ci->wq, &ci->work);
319 * Handle vbus change interrupt, it indicates device connection
320 * and disconnection events.
322 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
323 ci->b_sess_valid_event = true;
324 ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
325 disable_irq_nosync(ci->irq);
326 queue_work(ci->wq, &ci->work);
330 /* Handle device/host interrupt */
331 if (ci->role != CI_ROLE_END)
332 ret = ci_role(ci)->irq(ci);
337 static int ci_get_platdata(struct device *dev,
338 struct ci_hdrc_platform_data *platdata)
340 /* Get the vbus regulator */
341 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
342 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
343 return -EPROBE_DEFER;
344 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
345 platdata->reg_vbus = NULL; /* no vbus regualator is needed */
346 } else if (IS_ERR(platdata->reg_vbus)) {
347 dev_err(dev, "Getting regulator error: %ld\n",
348 PTR_ERR(platdata->reg_vbus));
349 return PTR_ERR(platdata->reg_vbus);
355 static DEFINE_IDA(ci_ida);
357 struct platform_device *ci_hdrc_add_device(struct device *dev,
358 struct resource *res, int nres,
359 struct ci_hdrc_platform_data *platdata)
361 struct platform_device *pdev;
364 ret = ci_get_platdata(dev, platdata);
368 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
372 pdev = platform_device_alloc("ci_hdrc", id);
378 pdev->dev.parent = dev;
379 pdev->dev.dma_mask = dev->dma_mask;
380 pdev->dev.dma_parms = dev->dma_parms;
381 dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
383 ret = platform_device_add_resources(pdev, res, nres);
387 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
391 ret = platform_device_add(pdev);
398 platform_device_put(pdev);
400 ida_simple_remove(&ci_ida, id);
403 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
405 void ci_hdrc_remove_device(struct platform_device *pdev)
408 platform_device_unregister(pdev);
409 ida_simple_remove(&ci_ida, id);
411 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
413 static inline void ci_role_destroy(struct ci_hdrc *ci)
415 ci_hdrc_gadget_destroy(ci);
416 ci_hdrc_host_destroy(ci);
418 ci_hdrc_otg_destroy(ci);
421 static void ci_get_otg_capable(struct ci_hdrc *ci)
423 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
426 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
427 DCCPARAMS_DC | DCCPARAMS_HC)
428 == (DCCPARAMS_DC | DCCPARAMS_HC));
430 dev_dbg(ci->dev, "It is OTG capable controller\n");
431 ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
432 ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
436 static int ci_hdrc_probe(struct platform_device *pdev)
438 struct device *dev = &pdev->dev;
440 struct resource *res;
443 enum usb_dr_mode dr_mode;
444 struct device_node *of_node = dev->of_node ?: dev->parent->of_node;
446 if (!dev->platform_data) {
447 dev_err(dev, "platform data missing\n");
451 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
452 base = devm_ioremap_resource(dev, res);
454 return PTR_ERR(base);
456 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
458 dev_err(dev, "can't allocate device\n");
463 ci->platdata = dev->platform_data;
464 if (ci->platdata->phy)
465 ci->transceiver = ci->platdata->phy;
467 ci->global_phy = true;
469 ret = hw_device_init(ci, base);
471 dev_err(dev, "can't initialize hardware\n");
475 ci->hw_bank.phys = res->start;
477 ci->irq = platform_get_irq(pdev, 0);
479 dev_err(dev, "missing IRQ\n");
483 ci_get_otg_capable(ci);
485 if (!ci->platdata->phy_mode)
486 ci->platdata->phy_mode = of_usb_get_phy_mode(of_node);
488 hw_phymode_configure(ci);
490 if (!ci->platdata->dr_mode)
491 ci->platdata->dr_mode = of_usb_get_dr_mode(of_node);
493 if (ci->platdata->dr_mode == USB_DR_MODE_UNKNOWN)
494 ci->platdata->dr_mode = USB_DR_MODE_OTG;
496 dr_mode = ci->platdata->dr_mode;
497 /* initialize role(s) before the interrupt is requested */
498 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
499 ret = ci_hdrc_host_init(ci);
501 dev_info(dev, "doesn't support host\n");
504 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
505 ret = ci_hdrc_gadget_init(ci);
507 dev_info(dev, "doesn't support gadget\n");
510 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
511 dev_err(dev, "no supported roles\n");
516 ret = ci_hdrc_otg_init(ci);
518 dev_err(dev, "init otg fails, ret = %d\n", ret);
523 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
526 * ID pin needs 1ms debouce time,
527 * we delay 2ms for safe.
530 ci->role = ci_otg_role(ci);
531 ci_enable_otg_interrupt(ci, OTGSC_IDIE);
534 * If the controller is not OTG capable, but support
535 * role switch, the defalt role is gadget, and the
536 * user can switch it through debugfs.
538 ci->role = CI_ROLE_GADGET;
541 ci->role = ci->roles[CI_ROLE_HOST]
546 ret = ci_role_start(ci, ci->role);
548 dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
552 platform_set_drvdata(pdev, ci);
553 ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
558 ret = dbg_create_files(ci);
562 free_irq(ci->irq, ci);
569 static int ci_hdrc_remove(struct platform_device *pdev)
571 struct ci_hdrc *ci = platform_get_drvdata(pdev);
573 dbg_remove_files(ci);
574 free_irq(ci->irq, ci);
580 static struct platform_driver ci_hdrc_driver = {
581 .probe = ci_hdrc_probe,
582 .remove = ci_hdrc_remove,
588 module_platform_driver(ci_hdrc_driver);
590 MODULE_ALIAS("platform:ci_hdrc");
591 MODULE_LICENSE("GPL v2");
592 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
593 MODULE_DESCRIPTION("ChipIdea HDRC Driver");