2 * core.c - DesignWare HS OTG Controller common routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
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11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
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17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/moduleparam.h>
45 #include <linux/spinlock.h>
46 #include <linux/interrupt.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
61 * dwc2_backup_host_registers() - Backup controller host registers.
62 * When suspending usb bus, registers needs to be backuped
63 * if controller power is disabled once suspended.
65 * @hsotg: Programming view of the DWC_otg controller
67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
69 struct dwc2_hregs_backup *hr;
72 dev_dbg(hsotg->dev, "%s\n", __func__);
74 /* Backup Host regs */
75 hr = &hsotg->hr_backup;
76 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
77 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
78 for (i = 0; i < hsotg->core_params->host_channels; ++i)
79 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
81 hr->hprt0 = dwc2_read_hprt0(hsotg);
82 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
89 * dwc2_restore_host_registers() - Restore controller host registers.
90 * When resuming usb bus, device registers needs to be restored
91 * if controller power were disabled.
93 * @hsotg: Programming view of the DWC_otg controller
95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
97 struct dwc2_hregs_backup *hr;
100 dev_dbg(hsotg->dev, "%s\n", __func__);
102 /* Restore host regs */
103 hr = &hsotg->hr_backup;
105 dev_err(hsotg->dev, "%s: no host registers to restore\n",
111 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
112 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
114 for (i = 0; i < hsotg->core_params->host_channels; ++i)
115 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
117 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
118 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
119 hsotg->frame_number = 0;
124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
131 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
132 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
134 * dwc2_backup_device_registers() - Backup controller device registers.
135 * When suspending usb bus, registers needs to be backuped
136 * if controller power is disabled once suspended.
138 * @hsotg: Programming view of the DWC_otg controller
140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
142 struct dwc2_dregs_backup *dr;
145 dev_dbg(hsotg->dev, "%s\n", __func__);
147 /* Backup dev regs */
148 dr = &hsotg->dr_backup;
150 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
151 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
152 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
153 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
154 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
156 for (i = 0; i < hsotg->num_of_eps; i++) {
158 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
160 /* Ensure DATA PID is correctly configured */
161 if (dr->diepctl[i] & DXEPCTL_DPID)
162 dr->diepctl[i] |= DXEPCTL_SETD1PID;
164 dr->diepctl[i] |= DXEPCTL_SETD0PID;
166 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
167 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
170 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
172 /* Ensure DATA PID is correctly configured */
173 if (dr->doepctl[i] & DXEPCTL_DPID)
174 dr->doepctl[i] |= DXEPCTL_SETD1PID;
176 dr->doepctl[i] |= DXEPCTL_SETD0PID;
178 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
179 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
186 * dwc2_restore_device_registers() - Restore controller device registers.
187 * When resuming usb bus, device registers needs to be restored
188 * if controller power were disabled.
190 * @hsotg: Programming view of the DWC_otg controller
192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
194 struct dwc2_dregs_backup *dr;
198 dev_dbg(hsotg->dev, "%s\n", __func__);
200 /* Restore dev regs */
201 dr = &hsotg->dr_backup;
203 dev_err(hsotg->dev, "%s: no device registers to restore\n",
209 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
210 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
211 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
212 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
213 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
215 for (i = 0; i < hsotg->num_of_eps; i++) {
217 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
218 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
219 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
221 /* Restore OUT EPs */
222 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
223 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
224 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
227 /* Set the Power-On Programming done bit */
228 dctl = dwc2_readl(hsotg->regs + DCTL);
229 dctl |= DCTL_PWRONPRGDONE;
230 dwc2_writel(dctl, hsotg->regs + DCTL);
235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
243 * dwc2_backup_global_registers() - Backup global controller registers.
244 * When suspending usb bus, registers needs to be backuped
245 * if controller power is disabled once suspended.
247 * @hsotg: Programming view of the DWC_otg controller
249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
251 struct dwc2_gregs_backup *gr;
254 /* Backup global regs */
255 gr = &hsotg->gr_backup;
257 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
258 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
259 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
260 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
261 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
262 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
263 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
264 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
265 for (i = 0; i < MAX_EPS_CHANNELS; i++)
266 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
273 * dwc2_restore_global_registers() - Restore controller global registers.
274 * When resuming usb bus, device registers needs to be restored
275 * if controller power were disabled.
277 * @hsotg: Programming view of the DWC_otg controller
279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
281 struct dwc2_gregs_backup *gr;
284 dev_dbg(hsotg->dev, "%s\n", __func__);
286 /* Restore global regs */
287 gr = &hsotg->gr_backup;
289 dev_err(hsotg->dev, "%s: no global registers to restore\n",
295 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
296 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
297 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
298 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
299 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
300 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
301 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
302 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
303 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
304 for (i = 0; i < MAX_EPS_CHANNELS; i++)
305 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
311 * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
313 * @hsotg: Programming view of the DWC_otg controller
314 * @restore: Controller registers need to be restored
316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
321 if (!hsotg->core_params->hibernation)
324 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
325 pcgcctl &= ~PCGCTL_STOPPCLK;
326 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
328 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
329 pcgcctl &= ~PCGCTL_PWRCLMP;
330 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
332 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
333 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
334 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
338 ret = dwc2_restore_global_registers(hsotg);
340 dev_err(hsotg->dev, "%s: failed to restore registers\n",
344 if (dwc2_is_host_mode(hsotg)) {
345 ret = dwc2_restore_host_registers(hsotg);
347 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
352 ret = dwc2_restore_device_registers(hsotg);
354 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
365 * dwc2_enter_hibernation() - Put controller in Partial Power Down.
367 * @hsotg: Programming view of the DWC_otg controller
369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
374 if (!hsotg->core_params->hibernation)
377 /* Backup all registers */
378 ret = dwc2_backup_global_registers(hsotg);
380 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
385 if (dwc2_is_host_mode(hsotg)) {
386 ret = dwc2_backup_host_registers(hsotg);
388 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
393 ret = dwc2_backup_device_registers(hsotg);
395 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
402 * Clear any pending interrupts since dwc2 will not be able to
403 * clear them after entering hibernation.
405 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
407 /* Put the controller in low power state */
408 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
410 pcgcctl |= PCGCTL_PWRCLMP;
411 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
414 pcgcctl |= PCGCTL_RSTPDWNMODULE;
415 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
418 pcgcctl |= PCGCTL_STOPPCLK;
419 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
425 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
426 * used in both device and host modes
428 * @hsotg: Programming view of the DWC_otg controller
430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
434 /* Clear any pending OTG Interrupts */
435 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
437 /* Clear any pending interrupts */
438 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
440 /* Enable the interrupts in the GINTMSK */
441 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
443 if (hsotg->core_params->dma_enable <= 0)
444 intmsk |= GINTSTS_RXFLVL;
445 if (hsotg->core_params->external_id_pin_ctl <= 0)
446 intmsk |= GINTSTS_CONIDSTSCHNG;
448 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
451 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
455 * Initializes the FSLSPClkSel field of the HCFG register depending on the
458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
462 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
463 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
464 hsotg->core_params->ulpi_fs_ls > 0) ||
465 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
467 val = HCFG_FSLSPCLKSEL_48_MHZ;
469 /* High speed PHY running at full speed or high speed */
470 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
473 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
474 hcfg = dwc2_readl(hsotg->regs + HCFG);
475 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
476 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
477 dwc2_writel(hcfg, hsotg->regs + HCFG);
481 * Do core a soft reset of the core. Be careful with this because it
482 * resets all the internal state machines of the core.
484 int dwc2_core_reset(struct dwc2_hsotg *hsotg)
490 dev_vdbg(hsotg->dev, "%s()\n", __func__);
492 /* Wait for AHB master IDLE state */
494 usleep_range(20000, 40000);
495 greset = dwc2_readl(hsotg->regs + GRSTCTL);
498 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
502 } while (!(greset & GRSTCTL_AHBIDLE));
504 /* Core Soft Reset */
506 greset |= GRSTCTL_CSFTRST;
507 dwc2_writel(greset, hsotg->regs + GRSTCTL);
509 usleep_range(20000, 40000);
510 greset = dwc2_readl(hsotg->regs + GRSTCTL);
513 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
517 } while (greset & GRSTCTL_CSFTRST);
519 if (hsotg->dr_mode == USB_DR_MODE_HOST) {
520 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
521 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
522 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
523 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
524 } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
525 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
526 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
527 gusbcfg |= GUSBCFG_FORCEDEVMODE;
528 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
529 } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
530 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
531 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
532 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
533 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
537 * NOTE: This long sleep is _very_ important, otherwise the core will
538 * not stay in host mode after a connector ID change!
540 usleep_range(150000, 200000);
545 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
551 * core_init() is now called on every switch so only call the
552 * following for the first time through
555 dev_dbg(hsotg->dev, "FS PHY selected\n");
556 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
557 usbcfg |= GUSBCFG_PHYSEL;
558 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
560 /* Reset after a PHY select */
561 retval = dwc2_core_reset(hsotg);
563 dev_err(hsotg->dev, "%s() Reset failed, aborting",
570 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
571 * do this on HNP Dev/Host mode switches (done in dev_init and
574 if (dwc2_is_host_mode(hsotg))
575 dwc2_init_fs_ls_pclk_sel(hsotg);
577 if (hsotg->core_params->i2c_enable > 0) {
578 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
580 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
581 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
582 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
583 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
585 /* Program GI2CCTL.I2CEn */
586 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
587 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
588 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
589 i2cctl &= ~GI2CCTL_I2CEN;
590 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
591 i2cctl |= GI2CCTL_I2CEN;
592 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
598 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
606 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
609 * HS PHY parameters. These parameters are preserved during soft reset
610 * so only program the first time. Do a soft reset immediately after
613 switch (hsotg->core_params->phy_type) {
614 case DWC2_PHY_TYPE_PARAM_ULPI:
616 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
617 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
618 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
619 if (hsotg->core_params->phy_ulpi_ddr > 0)
620 usbcfg |= GUSBCFG_DDRSEL;
622 case DWC2_PHY_TYPE_PARAM_UTMI:
623 /* UTMI+ interface */
624 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
625 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
626 if (hsotg->core_params->phy_utmi_width == 16)
627 usbcfg |= GUSBCFG_PHYIF16;
630 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
634 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
636 /* Reset after setting the PHY parameters */
637 retval = dwc2_core_reset(hsotg);
639 dev_err(hsotg->dev, "%s() Reset failed, aborting",
647 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
652 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
653 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
654 /* If FS mode with FS PHY */
655 retval = dwc2_fs_phy_init(hsotg, select_phy);
660 retval = dwc2_hs_phy_init(hsotg, select_phy);
665 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
666 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
667 hsotg->core_params->ulpi_fs_ls > 0) {
668 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
669 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
670 usbcfg |= GUSBCFG_ULPI_FS_LS;
671 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
672 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
674 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
675 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
676 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
677 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
683 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
685 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
687 switch (hsotg->hw_params.arch) {
688 case GHWCFG2_EXT_DMA_ARCH:
689 dev_err(hsotg->dev, "External DMA Mode not supported\n");
692 case GHWCFG2_INT_DMA_ARCH:
693 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
694 if (hsotg->core_params->ahbcfg != -1) {
695 ahbcfg &= GAHBCFG_CTRL_MASK;
696 ahbcfg |= hsotg->core_params->ahbcfg &
701 case GHWCFG2_SLAVE_ONLY_ARCH:
703 dev_dbg(hsotg->dev, "Slave Only Mode\n");
707 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
708 hsotg->core_params->dma_enable,
709 hsotg->core_params->dma_desc_enable);
711 if (hsotg->core_params->dma_enable > 0) {
712 if (hsotg->core_params->dma_desc_enable > 0)
713 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
715 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
717 dev_dbg(hsotg->dev, "Using Slave mode\n");
718 hsotg->core_params->dma_desc_enable = 0;
721 if (hsotg->core_params->dma_enable > 0)
722 ahbcfg |= GAHBCFG_DMA_EN;
724 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
729 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
733 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
734 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
736 switch (hsotg->hw_params.op_mode) {
737 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
738 if (hsotg->core_params->otg_cap ==
739 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
740 usbcfg |= GUSBCFG_HNPCAP;
741 if (hsotg->core_params->otg_cap !=
742 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
743 usbcfg |= GUSBCFG_SRPCAP;
746 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
747 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
748 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
749 if (hsotg->core_params->otg_cap !=
750 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
751 usbcfg |= GUSBCFG_SRPCAP;
754 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
755 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
756 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
761 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
765 * dwc2_core_init() - Initializes the DWC_otg controller registers and
766 * prepares the core for device mode or host mode operation
768 * @hsotg: Programming view of the DWC_otg controller
769 * @initial_setup: If true then this is the first init for this instance.
771 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
776 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
778 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
780 /* Set ULPI External VBUS bit if needed */
781 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
782 if (hsotg->core_params->phy_ulpi_ext_vbus ==
783 DWC2_PHY_ULPI_EXTERNAL_VBUS)
784 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
786 /* Set external TS Dline pulsing bit if needed */
787 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
788 if (hsotg->core_params->ts_dline > 0)
789 usbcfg |= GUSBCFG_TERMSELDLPULSE;
791 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
794 * Reset the Controller
796 * We only need to reset the controller if this is a re-init.
797 * For the first init we know for sure that earlier code reset us (it
798 * needed to in order to properly detect various parameters).
800 if (!initial_setup) {
801 retval = dwc2_core_reset(hsotg);
803 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
810 * This needs to happen in FS mode before any other programming occurs
812 retval = dwc2_phy_init(hsotg, initial_setup);
816 /* Program the GAHBCFG Register */
817 retval = dwc2_gahbcfg_init(hsotg);
821 /* Program the GUSBCFG register */
822 dwc2_gusbcfg_init(hsotg);
824 /* Program the GOTGCTL register */
825 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
826 otgctl &= ~GOTGCTL_OTGVER;
827 if (hsotg->core_params->otg_ver > 0)
828 otgctl |= GOTGCTL_OTGVER;
829 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
830 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
832 /* Clear the SRP success bit for FS-I2c */
833 hsotg->srp_success = 0;
835 /* Enable common interrupts */
836 dwc2_enable_common_interrupts(hsotg);
839 * Do device or host initialization based on mode during PCD and
842 if (dwc2_is_host_mode(hsotg)) {
843 dev_dbg(hsotg->dev, "Host Mode\n");
844 hsotg->op_state = OTG_STATE_A_HOST;
846 dev_dbg(hsotg->dev, "Device Mode\n");
847 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
854 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
856 * @hsotg: Programming view of DWC_otg controller
858 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
862 dev_dbg(hsotg->dev, "%s()\n", __func__);
864 /* Disable all interrupts */
865 dwc2_writel(0, hsotg->regs + GINTMSK);
866 dwc2_writel(0, hsotg->regs + HAINTMSK);
868 /* Enable the common interrupts */
869 dwc2_enable_common_interrupts(hsotg);
871 /* Enable host mode interrupts without disturbing common interrupts */
872 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
873 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
874 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
878 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
880 * @hsotg: Programming view of DWC_otg controller
882 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
884 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
886 /* Disable host mode interrupts without disturbing common interrupts */
887 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
888 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
889 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
893 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
894 * For system that have a total fifo depth that is smaller than the default
897 * @hsotg: Programming view of DWC_otg controller
899 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
901 struct dwc2_core_params *params = hsotg->core_params;
902 struct dwc2_hw_params *hw = &hsotg->hw_params;
903 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
905 total_fifo_size = hw->total_fifo_size;
906 rxfsiz = params->host_rx_fifo_size;
907 nptxfsiz = params->host_nperio_tx_fifo_size;
908 ptxfsiz = params->host_perio_tx_fifo_size;
911 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
912 * allocation with support for high bandwidth endpoints. Synopsys
913 * defines MPS(Max Packet size) for a periodic EP=1024, and for
914 * non-periodic as 512.
916 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
918 * For Buffer DMA mode/Scatter Gather DMA mode
919 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
920 * with n = number of host channel.
921 * 2 * ((1024/4) + 2) = 516
923 rxfsiz = 516 + hw->host_channels;
926 * min non-periodic tx fifo depth
927 * 2 * (largest non-periodic USB packet used / 4)
933 * min periodic tx fifo depth
934 * (largest packet size*MC)/4
939 params->host_rx_fifo_size = rxfsiz;
940 params->host_nperio_tx_fifo_size = nptxfsiz;
941 params->host_perio_tx_fifo_size = ptxfsiz;
945 * If the summation of RX, NPTX and PTX fifo sizes is still
946 * bigger than the total_fifo_size, then we have a problem.
948 * We won't be able to allocate as many endpoints. Right now,
949 * we're just printing an error message, but ideally this FIFO
950 * allocation algorithm would be improved in the future.
952 * FIXME improve this FIFO allocation algorithm.
954 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
955 dev_err(hsotg->dev, "invalid fifo sizes\n");
958 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
960 struct dwc2_core_params *params = hsotg->core_params;
961 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
963 if (!params->enable_dynamic_fifo)
966 dwc2_calculate_dynamic_fifo(hsotg);
969 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
970 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
971 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
972 grxfsiz |= params->host_rx_fifo_size <<
973 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
974 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
975 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
976 dwc2_readl(hsotg->regs + GRXFSIZ));
978 /* Non-periodic Tx FIFO */
979 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
980 dwc2_readl(hsotg->regs + GNPTXFSIZ));
981 nptxfsiz = params->host_nperio_tx_fifo_size <<
982 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
983 nptxfsiz |= params->host_rx_fifo_size <<
984 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
985 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
986 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
987 dwc2_readl(hsotg->regs + GNPTXFSIZ));
989 /* Periodic Tx FIFO */
990 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
991 dwc2_readl(hsotg->regs + HPTXFSIZ));
992 hptxfsiz = params->host_perio_tx_fifo_size <<
993 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
994 hptxfsiz |= (params->host_rx_fifo_size +
995 params->host_nperio_tx_fifo_size) <<
996 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
997 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
998 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
999 dwc2_readl(hsotg->regs + HPTXFSIZ));
1001 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
1002 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
1004 * Global DFIFOCFG calculation for Host mode -
1005 * include RxFIFO, NPTXFIFO and HPTXFIFO
1007 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
1008 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
1009 dfifocfg |= (params->host_rx_fifo_size +
1010 params->host_nperio_tx_fifo_size +
1011 params->host_perio_tx_fifo_size) <<
1012 GDFIFOCFG_EPINFOBASE_SHIFT &
1013 GDFIFOCFG_EPINFOBASE_MASK;
1014 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
1019 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
1022 * @hsotg: Programming view of DWC_otg controller
1024 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
1025 * request queues. Host channels are reset to ensure that they are ready for
1026 * performing transfers.
1028 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
1030 u32 hcfg, hfir, otgctl;
1032 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
1034 /* Restart the Phy Clock */
1035 dwc2_writel(0, hsotg->regs + PCGCTL);
1037 /* Initialize Host Configuration Register */
1038 dwc2_init_fs_ls_pclk_sel(hsotg);
1039 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
1040 hcfg = dwc2_readl(hsotg->regs + HCFG);
1041 hcfg |= HCFG_FSLSSUPP;
1042 dwc2_writel(hcfg, hsotg->regs + HCFG);
1046 * This bit allows dynamic reloading of the HFIR register during
1047 * runtime. This bit needs to be programmed during initial configuration
1048 * and its value must not be changed during runtime.
1050 if (hsotg->core_params->reload_ctl > 0) {
1051 hfir = dwc2_readl(hsotg->regs + HFIR);
1052 hfir |= HFIR_RLDCTRL;
1053 dwc2_writel(hfir, hsotg->regs + HFIR);
1056 if (hsotg->core_params->dma_desc_enable > 0) {
1057 u32 op_mode = hsotg->hw_params.op_mode;
1058 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
1059 !hsotg->hw_params.dma_desc_enable ||
1060 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
1061 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
1062 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
1064 "Hardware does not support descriptor DMA mode -\n");
1066 "falling back to buffer DMA mode.\n");
1067 hsotg->core_params->dma_desc_enable = 0;
1069 hcfg = dwc2_readl(hsotg->regs + HCFG);
1070 hcfg |= HCFG_DESCDMA;
1071 dwc2_writel(hcfg, hsotg->regs + HCFG);
1075 /* Configure data FIFO sizes */
1076 dwc2_config_fifos(hsotg);
1078 /* TODO - check this */
1079 /* Clear Host Set HNP Enable in the OTG Control Register */
1080 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1081 otgctl &= ~GOTGCTL_HSTSETHNPEN;
1082 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1084 /* Make sure the FIFOs are flushed */
1085 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
1086 dwc2_flush_rx_fifo(hsotg);
1088 /* Clear Host Set HNP Enable in the OTG Control Register */
1089 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1090 otgctl &= ~GOTGCTL_HSTSETHNPEN;
1091 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1093 if (hsotg->core_params->dma_desc_enable <= 0) {
1094 int num_channels, i;
1097 /* Flush out any leftover queued requests */
1098 num_channels = hsotg->core_params->host_channels;
1099 for (i = 0; i < num_channels; i++) {
1100 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1101 hcchar &= ~HCCHAR_CHENA;
1102 hcchar |= HCCHAR_CHDIS;
1103 hcchar &= ~HCCHAR_EPDIR;
1104 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1107 /* Halt all channels to put them into a known state */
1108 for (i = 0; i < num_channels; i++) {
1111 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1112 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
1113 hcchar &= ~HCCHAR_EPDIR;
1114 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1115 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
1118 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1119 if (++count > 1000) {
1121 "Unable to clear enable on channel %d\n",
1126 } while (hcchar & HCCHAR_CHENA);
1130 /* Turn on the vbus power */
1131 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
1132 if (hsotg->op_state == OTG_STATE_A_HOST) {
1133 u32 hprt0 = dwc2_read_hprt0(hsotg);
1135 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
1136 !!(hprt0 & HPRT0_PWR));
1137 if (!(hprt0 & HPRT0_PWR)) {
1139 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1143 dwc2_enable_host_interrupts(hsotg);
1146 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
1147 struct dwc2_host_chan *chan)
1149 u32 hcintmsk = HCINTMSK_CHHLTD;
1151 switch (chan->ep_type) {
1152 case USB_ENDPOINT_XFER_CONTROL:
1153 case USB_ENDPOINT_XFER_BULK:
1154 dev_vdbg(hsotg->dev, "control/bulk\n");
1155 hcintmsk |= HCINTMSK_XFERCOMPL;
1156 hcintmsk |= HCINTMSK_STALL;
1157 hcintmsk |= HCINTMSK_XACTERR;
1158 hcintmsk |= HCINTMSK_DATATGLERR;
1159 if (chan->ep_is_in) {
1160 hcintmsk |= HCINTMSK_BBLERR;
1162 hcintmsk |= HCINTMSK_NAK;
1163 hcintmsk |= HCINTMSK_NYET;
1165 hcintmsk |= HCINTMSK_ACK;
1168 if (chan->do_split) {
1169 hcintmsk |= HCINTMSK_NAK;
1170 if (chan->complete_split)
1171 hcintmsk |= HCINTMSK_NYET;
1173 hcintmsk |= HCINTMSK_ACK;
1176 if (chan->error_state)
1177 hcintmsk |= HCINTMSK_ACK;
1180 case USB_ENDPOINT_XFER_INT:
1182 dev_vdbg(hsotg->dev, "intr\n");
1183 hcintmsk |= HCINTMSK_XFERCOMPL;
1184 hcintmsk |= HCINTMSK_NAK;
1185 hcintmsk |= HCINTMSK_STALL;
1186 hcintmsk |= HCINTMSK_XACTERR;
1187 hcintmsk |= HCINTMSK_DATATGLERR;
1188 hcintmsk |= HCINTMSK_FRMOVRUN;
1191 hcintmsk |= HCINTMSK_BBLERR;
1192 if (chan->error_state)
1193 hcintmsk |= HCINTMSK_ACK;
1194 if (chan->do_split) {
1195 if (chan->complete_split)
1196 hcintmsk |= HCINTMSK_NYET;
1198 hcintmsk |= HCINTMSK_ACK;
1202 case USB_ENDPOINT_XFER_ISOC:
1204 dev_vdbg(hsotg->dev, "isoc\n");
1205 hcintmsk |= HCINTMSK_XFERCOMPL;
1206 hcintmsk |= HCINTMSK_FRMOVRUN;
1207 hcintmsk |= HCINTMSK_ACK;
1209 if (chan->ep_is_in) {
1210 hcintmsk |= HCINTMSK_XACTERR;
1211 hcintmsk |= HCINTMSK_BBLERR;
1215 dev_err(hsotg->dev, "## Unknown EP type ##\n");
1219 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1221 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1224 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
1225 struct dwc2_host_chan *chan)
1227 u32 hcintmsk = HCINTMSK_CHHLTD;
1230 * For Descriptor DMA mode core halts the channel on AHB error.
1231 * Interrupt is not required.
1233 if (hsotg->core_params->dma_desc_enable <= 0) {
1235 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1236 hcintmsk |= HCINTMSK_AHBERR;
1239 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
1240 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1241 hcintmsk |= HCINTMSK_XFERCOMPL;
1244 if (chan->error_state && !chan->do_split &&
1245 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1247 dev_vdbg(hsotg->dev, "setting ACK\n");
1248 hcintmsk |= HCINTMSK_ACK;
1249 if (chan->ep_is_in) {
1250 hcintmsk |= HCINTMSK_DATATGLERR;
1251 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
1252 hcintmsk |= HCINTMSK_NAK;
1256 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1258 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1261 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
1262 struct dwc2_host_chan *chan)
1266 if (hsotg->core_params->dma_enable > 0) {
1268 dev_vdbg(hsotg->dev, "DMA enabled\n");
1269 dwc2_hc_enable_dma_ints(hsotg, chan);
1272 dev_vdbg(hsotg->dev, "DMA disabled\n");
1273 dwc2_hc_enable_slave_ints(hsotg, chan);
1276 /* Enable the top level host channel interrupt */
1277 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
1278 intmsk |= 1 << chan->hc_num;
1279 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
1281 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
1283 /* Make sure host channel interrupts are enabled */
1284 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
1285 intmsk |= GINTSTS_HCHINT;
1286 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
1288 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
1292 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
1293 * a specific endpoint
1295 * @hsotg: Programming view of DWC_otg controller
1296 * @chan: Information needed to initialize the host channel
1298 * The HCCHARn register is set up with the characteristics specified in chan.
1299 * Host channel interrupts that may need to be serviced while this transfer is
1300 * in progress are enabled.
1302 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1304 u8 hc_num = chan->hc_num;
1310 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1312 /* Clear old interrupt conditions for this host channel */
1313 hcintmsk = 0xffffffff;
1314 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1315 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
1317 /* Enable channel interrupts required for this transfer */
1318 dwc2_hc_enable_ints(hsotg, chan);
1321 * Program the HCCHARn register with the endpoint characteristics for
1322 * the current transfer
1324 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
1325 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
1327 hcchar |= HCCHAR_EPDIR;
1328 if (chan->speed == USB_SPEED_LOW)
1329 hcchar |= HCCHAR_LSPDDEV;
1330 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
1331 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
1332 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
1334 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
1337 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
1339 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
1341 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
1343 dev_vdbg(hsotg->dev, " Is In: %d\n",
1345 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
1346 chan->speed == USB_SPEED_LOW);
1347 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
1349 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
1353 /* Program the HCSPLT register for SPLITs */
1354 if (chan->do_split) {
1356 dev_vdbg(hsotg->dev,
1357 "Programming HC %d with split --> %s\n",
1359 chan->complete_split ? "CSPLIT" : "SSPLIT");
1360 if (chan->complete_split)
1361 hcsplt |= HCSPLT_COMPSPLT;
1362 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
1363 HCSPLT_XACTPOS_MASK;
1364 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
1365 HCSPLT_HUBADDR_MASK;
1366 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
1367 HCSPLT_PRTADDR_MASK;
1369 dev_vdbg(hsotg->dev, " comp split %d\n",
1370 chan->complete_split);
1371 dev_vdbg(hsotg->dev, " xact pos %d\n",
1373 dev_vdbg(hsotg->dev, " hub addr %d\n",
1375 dev_vdbg(hsotg->dev, " hub port %d\n",
1377 dev_vdbg(hsotg->dev, " is_in %d\n",
1379 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
1381 dev_vdbg(hsotg->dev, " xferlen %d\n",
1386 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
1390 * dwc2_hc_halt() - Attempts to halt a host channel
1392 * @hsotg: Controller register interface
1393 * @chan: Host channel to halt
1394 * @halt_status: Reason for halting the channel
1396 * This function should only be called in Slave mode or to abort a transfer in
1397 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
1398 * controller halts the channel when the transfer is complete or a condition
1399 * occurs that requires application intervention.
1401 * In slave mode, checks for a free request queue entry, then sets the Channel
1402 * Enable and Channel Disable bits of the Host Channel Characteristics
1403 * register of the specified channel to intiate the halt. If there is no free
1404 * request queue entry, sets only the Channel Disable bit of the HCCHARn
1405 * register to flush requests for this channel. In the latter case, sets a
1406 * flag to indicate that the host channel needs to be halted when a request
1407 * queue slot is open.
1409 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
1410 * HCCHARn register. The controller ensures there is space in the request
1411 * queue before submitting the halt request.
1413 * Some time may elapse before the core flushes any posted requests for this
1414 * host channel and halts. The Channel Halted interrupt handler completes the
1415 * deactivation of the host channel.
1417 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1418 enum dwc2_halt_status halt_status)
1420 u32 nptxsts, hptxsts, hcchar;
1423 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1424 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1425 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1427 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1428 halt_status == DWC2_HC_XFER_AHB_ERR) {
1430 * Disable all channel interrupts except Ch Halted. The QTD
1431 * and QH state associated with this transfer has been cleared
1432 * (in the case of URB_DEQUEUE), so the channel needs to be
1433 * shut down carefully to prevent crashes.
1435 u32 hcintmsk = HCINTMSK_CHHLTD;
1437 dev_vdbg(hsotg->dev, "dequeue/error\n");
1438 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1441 * Make sure no other interrupts besides halt are currently
1442 * pending. Handling another interrupt could cause a crash due
1443 * to the QTD and QH state.
1445 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1448 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1449 * even if the channel was already halted for some other
1452 chan->halt_status = halt_status;
1454 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1455 if (!(hcchar & HCCHAR_CHENA)) {
1457 * The channel is either already halted or it hasn't
1458 * started yet. In DMA mode, the transfer may halt if
1459 * it finishes normally or a condition occurs that
1460 * requires driver intervention. Don't want to halt
1461 * the channel again. In either Slave or DMA mode,
1462 * it's possible that the transfer has been assigned
1463 * to a channel, but not started yet when an URB is
1464 * dequeued. Don't want to halt a channel that hasn't
1470 if (chan->halt_pending) {
1472 * A halt has already been issued for this channel. This might
1473 * happen when a transfer is aborted by a higher level in
1476 dev_vdbg(hsotg->dev,
1477 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1478 __func__, chan->hc_num);
1482 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1484 /* No need to set the bit in DDMA for disabling the channel */
1485 /* TODO check it everywhere channel is disabled */
1486 if (hsotg->core_params->dma_desc_enable <= 0) {
1488 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1489 hcchar |= HCCHAR_CHENA;
1492 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1494 hcchar |= HCCHAR_CHDIS;
1496 if (hsotg->core_params->dma_enable <= 0) {
1498 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1499 hcchar |= HCCHAR_CHENA;
1501 /* Check for space in the request queue to issue the halt */
1502 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1503 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1504 dev_vdbg(hsotg->dev, "control/bulk\n");
1505 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1506 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1507 dev_vdbg(hsotg->dev, "Disabling channel\n");
1508 hcchar &= ~HCCHAR_CHENA;
1512 dev_vdbg(hsotg->dev, "isoc/intr\n");
1513 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1514 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1515 hsotg->queuing_high_bandwidth) {
1517 dev_vdbg(hsotg->dev, "Disabling channel\n");
1518 hcchar &= ~HCCHAR_CHENA;
1523 dev_vdbg(hsotg->dev, "DMA enabled\n");
1526 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1527 chan->halt_status = halt_status;
1529 if (hcchar & HCCHAR_CHENA) {
1531 dev_vdbg(hsotg->dev, "Channel enabled\n");
1532 chan->halt_pending = 1;
1533 chan->halt_on_queue = 0;
1536 dev_vdbg(hsotg->dev, "Channel disabled\n");
1537 chan->halt_on_queue = 1;
1541 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1543 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1545 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1546 chan->halt_pending);
1547 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1548 chan->halt_on_queue);
1549 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1555 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1557 * @hsotg: Programming view of DWC_otg controller
1558 * @chan: Identifies the host channel to clean up
1560 * This function is normally called after a transfer is done and the host
1561 * channel is being released
1563 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1567 chan->xfer_started = 0;
1570 * Clear channel interrupt enables and any unhandled channel interrupt
1573 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1574 hcintmsk = 0xffffffff;
1575 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1576 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1580 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1581 * which frame a periodic transfer should occur
1583 * @hsotg: Programming view of DWC_otg controller
1584 * @chan: Identifies the host channel to set up and its properties
1585 * @hcchar: Current value of the HCCHAR register for the specified host channel
1587 * This function has no effect on non-periodic transfers
1589 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1590 struct dwc2_host_chan *chan, u32 *hcchar)
1592 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1593 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1594 /* 1 if _next_ frame is odd, 0 if it's even */
1595 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1596 *hcchar |= HCCHAR_ODDFRM;
1600 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1602 /* Set up the initial PID for the transfer */
1603 if (chan->speed == USB_SPEED_HIGH) {
1604 if (chan->ep_is_in) {
1605 if (chan->multi_count == 1)
1606 chan->data_pid_start = DWC2_HC_PID_DATA0;
1607 else if (chan->multi_count == 2)
1608 chan->data_pid_start = DWC2_HC_PID_DATA1;
1610 chan->data_pid_start = DWC2_HC_PID_DATA2;
1612 if (chan->multi_count == 1)
1613 chan->data_pid_start = DWC2_HC_PID_DATA0;
1615 chan->data_pid_start = DWC2_HC_PID_MDATA;
1618 chan->data_pid_start = DWC2_HC_PID_DATA0;
1623 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1626 * @hsotg: Programming view of DWC_otg controller
1627 * @chan: Information needed to initialize the host channel
1629 * This function should only be called in Slave mode. For a channel associated
1630 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1631 * associated with a periodic EP, the periodic Tx FIFO is written.
1633 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1634 * the number of bytes written to the Tx FIFO.
1636 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1637 struct dwc2_host_chan *chan)
1640 u32 remaining_count;
1643 u32 __iomem *data_fifo;
1644 u32 *data_buf = (u32 *)chan->xfer_buf;
1647 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1649 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1651 remaining_count = chan->xfer_len - chan->xfer_count;
1652 if (remaining_count > chan->max_packet)
1653 byte_count = chan->max_packet;
1655 byte_count = remaining_count;
1657 dword_count = (byte_count + 3) / 4;
1659 if (((unsigned long)data_buf & 0x3) == 0) {
1660 /* xfer_buf is DWORD aligned */
1661 for (i = 0; i < dword_count; i++, data_buf++)
1662 dwc2_writel(*data_buf, data_fifo);
1664 /* xfer_buf is not DWORD aligned */
1665 for (i = 0; i < dword_count; i++, data_buf++) {
1666 u32 data = data_buf[0] | data_buf[1] << 8 |
1667 data_buf[2] << 16 | data_buf[3] << 24;
1668 dwc2_writel(data, data_fifo);
1672 chan->xfer_count += byte_count;
1673 chan->xfer_buf += byte_count;
1677 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1678 * channel and starts the transfer
1680 * @hsotg: Programming view of DWC_otg controller
1681 * @chan: Information needed to initialize the host channel. The xfer_len value
1682 * may be reduced to accommodate the max widths of the XferSize and
1683 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1684 * changed to reflect the final xfer_len value.
1686 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1687 * the caller must ensure that there is sufficient space in the request queue
1690 * For an OUT transfer in Slave mode, it loads a data packet into the
1691 * appropriate FIFO. If necessary, additional data packets are loaded in the
1694 * For an IN transfer in Slave mode, a data packet is requested. The data
1695 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1696 * additional data packets are requested in the Host ISR.
1698 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1699 * register along with a packet count of 1 and the channel is enabled. This
1700 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1701 * simply set to 0 since no data transfer occurs in this case.
1703 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1704 * all the information required to perform the subsequent data transfer. In
1705 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1706 * controller performs the entire PING protocol, then starts the data
1709 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1710 struct dwc2_host_chan *chan)
1712 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1713 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1719 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1721 if (chan->do_ping) {
1722 if (hsotg->core_params->dma_enable <= 0) {
1724 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1725 dwc2_hc_do_ping(hsotg, chan);
1726 chan->xfer_started = 1;
1730 dev_vdbg(hsotg->dev, "ping, DMA\n");
1731 hctsiz |= TSIZ_DOPNG;
1735 if (chan->do_split) {
1737 dev_vdbg(hsotg->dev, "split\n");
1740 if (chan->complete_split && !chan->ep_is_in)
1742 * For CSPLIT OUT Transfer, set the size to 0 so the
1743 * core doesn't expect any data written to the FIFO
1746 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1747 chan->xfer_len = chan->max_packet;
1748 else if (!chan->ep_is_in && chan->xfer_len > 188)
1749 chan->xfer_len = 188;
1751 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1755 dev_vdbg(hsotg->dev, "no split\n");
1757 * Ensure that the transfer length and packet count will fit
1758 * in the widths allocated for them in the HCTSIZn register
1760 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1761 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1763 * Make sure the transfer size is no larger than one
1764 * (micro)frame's worth of data. (A check was done
1765 * when the periodic transfer was accepted to ensure
1766 * that a (micro)frame's worth of data can be
1767 * programmed into a channel.)
1769 u32 max_periodic_len =
1770 chan->multi_count * chan->max_packet;
1772 if (chan->xfer_len > max_periodic_len)
1773 chan->xfer_len = max_periodic_len;
1774 } else if (chan->xfer_len > max_hc_xfer_size) {
1776 * Make sure that xfer_len is a multiple of max packet
1780 max_hc_xfer_size - chan->max_packet + 1;
1783 if (chan->xfer_len > 0) {
1784 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1786 if (num_packets > max_hc_pkt_count) {
1787 num_packets = max_hc_pkt_count;
1788 chan->xfer_len = num_packets * chan->max_packet;
1791 /* Need 1 packet for transfer length of 0 */
1797 * Always program an integral # of max packets for IN
1800 chan->xfer_len = num_packets * chan->max_packet;
1802 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1803 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1805 * Make sure that the multi_count field matches the
1806 * actual transfer length
1808 chan->multi_count = num_packets;
1810 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1811 dwc2_set_pid_isoc(chan);
1813 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1817 chan->start_pkt_count = num_packets;
1818 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1819 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1820 TSIZ_SC_MC_PID_MASK;
1821 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1823 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1824 hctsiz, chan->hc_num);
1826 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1828 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1829 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1830 TSIZ_XFERSIZE_SHIFT);
1831 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1832 (hctsiz & TSIZ_PKTCNT_MASK) >>
1834 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1835 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1836 TSIZ_SC_MC_PID_SHIFT);
1839 if (hsotg->core_params->dma_enable > 0) {
1840 dma_addr_t dma_addr;
1842 if (chan->align_buf) {
1844 dev_vdbg(hsotg->dev, "align_buf\n");
1845 dma_addr = chan->align_buf;
1847 dma_addr = chan->xfer_dma;
1849 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1851 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1852 (unsigned long)dma_addr, chan->hc_num);
1855 /* Start the split */
1856 if (chan->do_split) {
1857 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1859 hcsplt |= HCSPLT_SPLTENA;
1860 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1863 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1864 hcchar &= ~HCCHAR_MULTICNT_MASK;
1865 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1866 HCCHAR_MULTICNT_MASK;
1867 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1869 if (hcchar & HCCHAR_CHDIS)
1870 dev_warn(hsotg->dev,
1871 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1872 __func__, chan->hc_num, hcchar);
1874 /* Set host channel enable after all other setup is complete */
1875 hcchar |= HCCHAR_CHENA;
1876 hcchar &= ~HCCHAR_CHDIS;
1879 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1880 (hcchar & HCCHAR_MULTICNT_MASK) >>
1881 HCCHAR_MULTICNT_SHIFT);
1883 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1885 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1888 chan->xfer_started = 1;
1891 if (hsotg->core_params->dma_enable <= 0 &&
1892 !chan->ep_is_in && chan->xfer_len > 0)
1893 /* Load OUT packet into the appropriate Tx FIFO */
1894 dwc2_hc_write_packet(hsotg, chan);
1898 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1899 * host channel and starts the transfer in Descriptor DMA mode
1901 * @hsotg: Programming view of DWC_otg controller
1902 * @chan: Information needed to initialize the host channel
1904 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1905 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1906 * with micro-frame bitmap.
1908 * Initializes HCDMA register with descriptor list address and CTD value then
1909 * starts the transfer via enabling the channel.
1911 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1912 struct dwc2_host_chan *chan)
1919 hctsiz |= TSIZ_DOPNG;
1921 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1922 dwc2_set_pid_isoc(chan);
1924 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1925 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1926 TSIZ_SC_MC_PID_MASK;
1928 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1929 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1931 /* Non-zero only for high-speed interrupt endpoints */
1932 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1935 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1937 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1938 chan->data_pid_start);
1939 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1942 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1944 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
1946 /* Always start from first descriptor */
1947 hc_dma &= ~HCDMA_CTD_MASK;
1948 dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
1950 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
1951 hc_dma, chan->hc_num);
1953 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1954 hcchar &= ~HCCHAR_MULTICNT_MASK;
1955 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1956 HCCHAR_MULTICNT_MASK;
1958 if (hcchar & HCCHAR_CHDIS)
1959 dev_warn(hsotg->dev,
1960 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1961 __func__, chan->hc_num, hcchar);
1963 /* Set host channel enable after all other setup is complete */
1964 hcchar |= HCCHAR_CHENA;
1965 hcchar &= ~HCCHAR_CHDIS;
1968 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1969 (hcchar & HCCHAR_MULTICNT_MASK) >>
1970 HCCHAR_MULTICNT_SHIFT);
1972 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1974 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1977 chan->xfer_started = 1;
1982 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1983 * a previous call to dwc2_hc_start_transfer()
1985 * @hsotg: Programming view of DWC_otg controller
1986 * @chan: Information needed to initialize the host channel
1988 * The caller must ensure there is sufficient space in the request queue and Tx
1989 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1990 * the controller acts autonomously to complete transfers programmed to a host
1993 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1994 * if there is any data remaining to be queued. For an IN transfer, another
1995 * data packet is always requested. For the SETUP phase of a control transfer,
1996 * this function does nothing.
1998 * Return: 1 if a new request is queued, 0 if no more requests are required
2001 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
2002 struct dwc2_host_chan *chan)
2005 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2009 /* SPLITs always queue just once per channel */
2012 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
2013 /* SETUPs are queued only once since they can't be NAK'd */
2016 if (chan->ep_is_in) {
2018 * Always queue another request for other IN transfers. If
2019 * back-to-back INs are issued and NAKs are received for both,
2020 * the driver may still be processing the first NAK when the
2021 * second NAK is received. When the interrupt handler clears
2022 * the NAK interrupt for the first NAK, the second NAK will
2023 * not be seen. So we can't depend on the NAK interrupt
2024 * handler to requeue a NAK'd request. Instead, IN requests
2025 * are issued each time this function is called. When the
2026 * transfer completes, the extra requests for the channel will
2029 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2031 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
2032 hcchar |= HCCHAR_CHENA;
2033 hcchar &= ~HCCHAR_CHDIS;
2035 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
2037 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2044 if (chan->xfer_count < chan->xfer_len) {
2045 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2046 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2047 u32 hcchar = dwc2_readl(hsotg->regs +
2048 HCCHAR(chan->hc_num));
2050 dwc2_hc_set_even_odd_frame(hsotg, chan,
2054 /* Load OUT packet into the appropriate Tx FIFO */
2055 dwc2_hc_write_packet(hsotg, chan);
2064 * dwc2_hc_do_ping() - Starts a PING transfer
2066 * @hsotg: Programming view of DWC_otg controller
2067 * @chan: Information needed to initialize the host channel
2069 * This function should only be called in Slave mode. The Do Ping bit is set in
2070 * the HCTSIZ register, then the channel is enabled.
2072 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
2078 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2082 hctsiz = TSIZ_DOPNG;
2083 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
2084 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
2086 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2087 hcchar |= HCCHAR_CHENA;
2088 hcchar &= ~HCCHAR_CHDIS;
2089 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2093 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
2094 * the HFIR register according to PHY type and speed
2096 * @hsotg: Programming view of DWC_otg controller
2098 * NOTE: The caller can modify the value of the HFIR register only after the
2099 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
2102 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
2106 int clock = 60; /* default value */
2108 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2109 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2111 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
2112 !(usbcfg & GUSBCFG_PHYIF16))
2114 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
2115 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
2117 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2118 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2120 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2121 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
2123 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2124 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2126 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
2127 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
2129 if ((usbcfg & GUSBCFG_PHYSEL) &&
2130 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2133 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
2134 /* High speed case */
2138 return 1000 * clock;
2142 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
2145 * @core_if: Programming view of DWC_otg controller
2146 * @dest: Destination buffer for the packet
2147 * @bytes: Number of bytes to copy to the destination
2149 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
2151 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
2152 u32 *data_buf = (u32 *)dest;
2153 int word_count = (bytes + 3) / 4;
2157 * Todo: Account for the case where dest is not dword aligned. This
2158 * requires reading data from the FIFO into a u32 temp buffer, then
2159 * moving it into the data buffer.
2162 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
2164 for (i = 0; i < word_count; i++, data_buf++)
2165 *data_buf = dwc2_readl(fifo);
2169 * dwc2_dump_host_registers() - Prints the host registers
2171 * @hsotg: Programming view of DWC_otg controller
2173 * NOTE: This function will be removed once the peripheral controller code
2174 * is integrated and the driver is stable
2176 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
2182 dev_dbg(hsotg->dev, "Host Global Registers\n");
2183 addr = hsotg->regs + HCFG;
2184 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
2185 (unsigned long)addr, dwc2_readl(addr));
2186 addr = hsotg->regs + HFIR;
2187 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
2188 (unsigned long)addr, dwc2_readl(addr));
2189 addr = hsotg->regs + HFNUM;
2190 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
2191 (unsigned long)addr, dwc2_readl(addr));
2192 addr = hsotg->regs + HPTXSTS;
2193 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
2194 (unsigned long)addr, dwc2_readl(addr));
2195 addr = hsotg->regs + HAINT;
2196 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
2197 (unsigned long)addr, dwc2_readl(addr));
2198 addr = hsotg->regs + HAINTMSK;
2199 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
2200 (unsigned long)addr, dwc2_readl(addr));
2201 if (hsotg->core_params->dma_desc_enable > 0) {
2202 addr = hsotg->regs + HFLBADDR;
2203 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
2204 (unsigned long)addr, dwc2_readl(addr));
2207 addr = hsotg->regs + HPRT0;
2208 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
2209 (unsigned long)addr, dwc2_readl(addr));
2211 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2212 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
2213 addr = hsotg->regs + HCCHAR(i);
2214 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
2215 (unsigned long)addr, dwc2_readl(addr));
2216 addr = hsotg->regs + HCSPLT(i);
2217 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
2218 (unsigned long)addr, dwc2_readl(addr));
2219 addr = hsotg->regs + HCINT(i);
2220 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
2221 (unsigned long)addr, dwc2_readl(addr));
2222 addr = hsotg->regs + HCINTMSK(i);
2223 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
2224 (unsigned long)addr, dwc2_readl(addr));
2225 addr = hsotg->regs + HCTSIZ(i);
2226 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
2227 (unsigned long)addr, dwc2_readl(addr));
2228 addr = hsotg->regs + HCDMA(i);
2229 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
2230 (unsigned long)addr, dwc2_readl(addr));
2231 if (hsotg->core_params->dma_desc_enable > 0) {
2232 addr = hsotg->regs + HCDMAB(i);
2233 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
2234 (unsigned long)addr, dwc2_readl(addr));
2241 * dwc2_dump_global_registers() - Prints the core global registers
2243 * @hsotg: Programming view of DWC_otg controller
2245 * NOTE: This function will be removed once the peripheral controller code
2246 * is integrated and the driver is stable
2248 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
2253 dev_dbg(hsotg->dev, "Core Global Registers\n");
2254 addr = hsotg->regs + GOTGCTL;
2255 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
2256 (unsigned long)addr, dwc2_readl(addr));
2257 addr = hsotg->regs + GOTGINT;
2258 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
2259 (unsigned long)addr, dwc2_readl(addr));
2260 addr = hsotg->regs + GAHBCFG;
2261 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
2262 (unsigned long)addr, dwc2_readl(addr));
2263 addr = hsotg->regs + GUSBCFG;
2264 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
2265 (unsigned long)addr, dwc2_readl(addr));
2266 addr = hsotg->regs + GRSTCTL;
2267 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
2268 (unsigned long)addr, dwc2_readl(addr));
2269 addr = hsotg->regs + GINTSTS;
2270 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
2271 (unsigned long)addr, dwc2_readl(addr));
2272 addr = hsotg->regs + GINTMSK;
2273 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
2274 (unsigned long)addr, dwc2_readl(addr));
2275 addr = hsotg->regs + GRXSTSR;
2276 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
2277 (unsigned long)addr, dwc2_readl(addr));
2278 addr = hsotg->regs + GRXFSIZ;
2279 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
2280 (unsigned long)addr, dwc2_readl(addr));
2281 addr = hsotg->regs + GNPTXFSIZ;
2282 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
2283 (unsigned long)addr, dwc2_readl(addr));
2284 addr = hsotg->regs + GNPTXSTS;
2285 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
2286 (unsigned long)addr, dwc2_readl(addr));
2287 addr = hsotg->regs + GI2CCTL;
2288 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
2289 (unsigned long)addr, dwc2_readl(addr));
2290 addr = hsotg->regs + GPVNDCTL;
2291 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
2292 (unsigned long)addr, dwc2_readl(addr));
2293 addr = hsotg->regs + GGPIO;
2294 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
2295 (unsigned long)addr, dwc2_readl(addr));
2296 addr = hsotg->regs + GUID;
2297 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
2298 (unsigned long)addr, dwc2_readl(addr));
2299 addr = hsotg->regs + GSNPSID;
2300 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
2301 (unsigned long)addr, dwc2_readl(addr));
2302 addr = hsotg->regs + GHWCFG1;
2303 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
2304 (unsigned long)addr, dwc2_readl(addr));
2305 addr = hsotg->regs + GHWCFG2;
2306 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
2307 (unsigned long)addr, dwc2_readl(addr));
2308 addr = hsotg->regs + GHWCFG3;
2309 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
2310 (unsigned long)addr, dwc2_readl(addr));
2311 addr = hsotg->regs + GHWCFG4;
2312 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
2313 (unsigned long)addr, dwc2_readl(addr));
2314 addr = hsotg->regs + GLPMCFG;
2315 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
2316 (unsigned long)addr, dwc2_readl(addr));
2317 addr = hsotg->regs + GPWRDN;
2318 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
2319 (unsigned long)addr, dwc2_readl(addr));
2320 addr = hsotg->regs + GDFIFOCFG;
2321 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
2322 (unsigned long)addr, dwc2_readl(addr));
2323 addr = hsotg->regs + HPTXFSIZ;
2324 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
2325 (unsigned long)addr, dwc2_readl(addr));
2327 addr = hsotg->regs + PCGCTL;
2328 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
2329 (unsigned long)addr, dwc2_readl(addr));
2334 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
2336 * @hsotg: Programming view of DWC_otg controller
2337 * @num: Tx FIFO to flush
2339 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
2344 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
2346 greset = GRSTCTL_TXFFLSH;
2347 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
2348 dwc2_writel(greset, hsotg->regs + GRSTCTL);
2351 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2352 if (++count > 10000) {
2353 dev_warn(hsotg->dev,
2354 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
2356 dwc2_readl(hsotg->regs + GNPTXSTS));
2360 } while (greset & GRSTCTL_TXFFLSH);
2362 /* Wait for at least 3 PHY Clocks */
2367 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
2369 * @hsotg: Programming view of DWC_otg controller
2371 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
2376 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2378 greset = GRSTCTL_RXFFLSH;
2379 dwc2_writel(greset, hsotg->regs + GRSTCTL);
2382 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2383 if (++count > 10000) {
2384 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
2389 } while (greset & GRSTCTL_RXFFLSH);
2391 /* Wait for at least 3 PHY Clocks */
2395 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
2397 /* Parameter access functions */
2398 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
2403 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
2404 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
2407 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
2408 switch (hsotg->hw_params.op_mode) {
2409 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2410 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2411 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2412 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2419 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
2430 "%d invalid for otg_cap parameter. Check HW configuration.\n",
2432 switch (hsotg->hw_params.op_mode) {
2433 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2434 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
2436 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2437 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2438 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2439 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2442 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2445 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2448 hsotg->core_params->otg_cap = val;
2451 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2455 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
2463 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2465 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
2466 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2469 hsotg->core_params->dma_enable = val;
2472 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2476 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2477 !hsotg->hw_params.dma_desc_enable))
2485 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2487 val = (hsotg->core_params->dma_enable > 0 &&
2488 hsotg->hw_params.dma_desc_enable);
2489 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2492 hsotg->core_params->dma_desc_enable = val;
2495 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2498 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2501 "Wrong value for host_support_fs_low_power\n");
2503 "host_support_fs_low_power must be 0 or 1\n");
2507 "Setting host_support_fs_low_power to %d\n", val);
2510 hsotg->core_params->host_support_fs_ls_low_power = val;
2513 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2517 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
2525 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2527 val = hsotg->hw_params.enable_dynamic_fifo;
2528 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2531 hsotg->core_params->enable_dynamic_fifo = val;
2534 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2538 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
2544 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2546 val = hsotg->hw_params.host_rx_fifo_size;
2547 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2550 hsotg->core_params->host_rx_fifo_size = val;
2553 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2557 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
2563 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2565 val = hsotg->hw_params.host_nperio_tx_fifo_size;
2566 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2570 hsotg->core_params->host_nperio_tx_fifo_size = val;
2573 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2577 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
2583 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2585 val = hsotg->hw_params.host_perio_tx_fifo_size;
2586 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2590 hsotg->core_params->host_perio_tx_fifo_size = val;
2593 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2597 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
2603 "%d invalid for max_transfer_size. Check HW configuration.\n",
2605 val = hsotg->hw_params.max_transfer_size;
2606 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2609 hsotg->core_params->max_transfer_size = val;
2612 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2616 if (val < 15 || val > hsotg->hw_params.max_packet_count)
2622 "%d invalid for max_packet_count. Check HW configuration.\n",
2624 val = hsotg->hw_params.max_packet_count;
2625 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2628 hsotg->core_params->max_packet_count = val;
2631 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2635 if (val < 1 || val > hsotg->hw_params.host_channels)
2641 "%d invalid for host_channels. Check HW configuration.\n",
2643 val = hsotg->hw_params.host_channels;
2644 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2647 hsotg->core_params->host_channels = val;
2650 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2653 u32 hs_phy_type, fs_phy_type;
2655 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
2656 DWC2_PHY_TYPE_PARAM_ULPI)) {
2658 dev_err(hsotg->dev, "Wrong value for phy_type\n");
2659 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2665 hs_phy_type = hsotg->hw_params.hs_phy_type;
2666 fs_phy_type = hsotg->hw_params.fs_phy_type;
2667 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2668 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2669 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2671 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2672 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2673 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2675 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2676 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2682 "%d invalid for phy_type. Check HW configuration.\n",
2684 val = DWC2_PHY_TYPE_PARAM_FS;
2685 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2686 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2687 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2688 val = DWC2_PHY_TYPE_PARAM_UTMI;
2690 val = DWC2_PHY_TYPE_PARAM_ULPI;
2692 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2695 hsotg->core_params->phy_type = val;
2698 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2700 return hsotg->core_params->phy_type;
2703 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2707 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2709 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2710 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2715 if (val == DWC2_SPEED_PARAM_HIGH &&
2716 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2722 "%d invalid for speed parameter. Check HW configuration.\n",
2724 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2725 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2726 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2729 hsotg->core_params->speed = val;
2732 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2736 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2737 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2740 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2742 "host_ls_low_power_phy_clk must be 0 or 1\n");
2747 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2748 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2754 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2756 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2757 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2758 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2759 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2763 hsotg->core_params->host_ls_low_power_phy_clk = val;
2766 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2768 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2770 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2771 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2774 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2777 hsotg->core_params->phy_ulpi_ddr = val;
2780 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2782 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2785 "Wrong value for phy_ulpi_ext_vbus\n");
2787 "phy_ulpi_ext_vbus must be 0 or 1\n");
2790 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2793 hsotg->core_params->phy_ulpi_ext_vbus = val;
2796 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2800 switch (hsotg->hw_params.utmi_phy_data_width) {
2801 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
2804 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
2805 valid = (val == 16);
2807 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
2808 valid = (val == 8 || val == 16);
2815 "%d invalid for phy_utmi_width. Check HW configuration.\n",
2818 val = (hsotg->hw_params.utmi_phy_data_width ==
2819 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
2820 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2823 hsotg->core_params->phy_utmi_width = val;
2826 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2828 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2830 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2831 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2834 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2837 hsotg->core_params->ulpi_fs_ls = val;
2840 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2842 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2844 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2845 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2848 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2851 hsotg->core_params->ts_dline = val;
2854 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2858 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2860 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2861 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2867 if (val == 1 && !(hsotg->hw_params.i2c_enable))
2873 "%d invalid for i2c_enable. Check HW configuration.\n",
2875 val = hsotg->hw_params.i2c_enable;
2876 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2879 hsotg->core_params->i2c_enable = val;
2882 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2886 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2889 "Wrong value for en_multiple_tx_fifo,\n");
2891 "en_multiple_tx_fifo must be 0 or 1\n");
2896 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
2902 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2904 val = hsotg->hw_params.en_multiple_tx_fifo;
2905 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2908 hsotg->core_params->en_multiple_tx_fifo = val;
2911 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2915 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2918 "'%d' invalid for parameter reload_ctl\n", val);
2919 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2924 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
2930 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2932 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
2933 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2936 hsotg->core_params->reload_ctl = val;
2939 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
2942 hsotg->core_params->ahbcfg = val;
2944 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
2945 GAHBCFG_HBSTLEN_SHIFT;
2948 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2950 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2953 "'%d' invalid for parameter otg_ver\n", val);
2955 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2958 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2961 hsotg->core_params->otg_ver = val;
2964 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
2966 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2969 "'%d' invalid for parameter uframe_sched\n",
2971 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
2974 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
2977 hsotg->core_params->uframe_sched = val;
2980 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
2983 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2986 "'%d' invalid for parameter external_id_pin_ctl\n",
2988 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
2991 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
2994 hsotg->core_params->external_id_pin_ctl = val;
2997 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
3000 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3003 "'%d' invalid for parameter hibernation\n",
3005 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
3008 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
3011 hsotg->core_params->hibernation = val;
3015 * This function is called during module intialization to pass module parameters
3016 * for the DWC_otg core.
3018 void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
3019 const struct dwc2_core_params *params)
3021 dev_dbg(hsotg->dev, "%s()\n", __func__);
3023 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
3024 dwc2_set_param_dma_enable(hsotg, params->dma_enable);
3025 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
3026 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
3027 params->host_support_fs_ls_low_power);
3028 dwc2_set_param_enable_dynamic_fifo(hsotg,
3029 params->enable_dynamic_fifo);
3030 dwc2_set_param_host_rx_fifo_size(hsotg,
3031 params->host_rx_fifo_size);
3032 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
3033 params->host_nperio_tx_fifo_size);
3034 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
3035 params->host_perio_tx_fifo_size);
3036 dwc2_set_param_max_transfer_size(hsotg,
3037 params->max_transfer_size);
3038 dwc2_set_param_max_packet_count(hsotg,
3039 params->max_packet_count);
3040 dwc2_set_param_host_channels(hsotg, params->host_channels);
3041 dwc2_set_param_phy_type(hsotg, params->phy_type);
3042 dwc2_set_param_speed(hsotg, params->speed);
3043 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
3044 params->host_ls_low_power_phy_clk);
3045 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
3046 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
3047 params->phy_ulpi_ext_vbus);
3048 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
3049 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
3050 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
3051 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
3052 dwc2_set_param_en_multiple_tx_fifo(hsotg,
3053 params->en_multiple_tx_fifo);
3054 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
3055 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
3056 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
3057 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
3058 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
3059 dwc2_set_param_hibernation(hsotg, params->hibernation);
3063 * During device initialization, read various hardware configuration
3064 * registers and interpret the contents.
3066 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
3068 struct dwc2_hw_params *hw = &hsotg->hw_params;
3070 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
3071 u32 hptxfsiz, grxfsiz, gnptxfsiz;
3075 * Attempt to ensure this device is really a DWC_otg Controller.
3076 * Read and verify the GSNPSID register contents. The value should be
3077 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
3078 * as in "OTG version 2.xx" or "OTG version 3.xx".
3080 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
3081 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
3082 (hw->snpsid & 0xfffff000) != 0x4f543000) {
3083 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
3088 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
3089 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
3090 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
3092 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
3093 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
3094 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
3095 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
3096 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
3098 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
3099 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
3100 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
3101 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
3102 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
3104 /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
3105 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3106 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3107 dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
3108 hsotg->regs + GUSBCFG);
3109 usleep_range(100000, 150000);
3112 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
3113 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
3114 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
3115 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
3116 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3117 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
3118 usleep_range(100000, 150000);
3122 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
3123 GHWCFG2_OP_MODE_SHIFT;
3124 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
3125 GHWCFG2_ARCHITECTURE_SHIFT;
3126 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
3127 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
3128 GHWCFG2_NUM_HOST_CHAN_SHIFT);
3129 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
3130 GHWCFG2_HS_PHY_TYPE_SHIFT;
3131 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
3132 GHWCFG2_FS_PHY_TYPE_SHIFT;
3133 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
3134 GHWCFG2_NUM_DEV_EP_SHIFT;
3135 hw->nperio_tx_q_depth =
3136 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
3137 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
3138 hw->host_perio_tx_q_depth =
3139 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
3140 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
3141 hw->dev_token_q_depth =
3142 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
3143 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
3146 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
3147 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
3148 hw->max_transfer_size = (1 << (width + 11)) - 1;
3150 * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates
3151 * coherent buffers with this size, and if it's too large we can
3152 * exhaust the coherent DMA pool.
3154 if (hw->max_transfer_size > 65535)
3155 hw->max_transfer_size = 65535;
3156 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
3157 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
3158 hw->max_packet_count = (1 << (width + 4)) - 1;
3159 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
3160 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
3161 GHWCFG3_DFIFO_DEPTH_SHIFT;
3164 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
3165 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
3166 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
3167 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
3168 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
3169 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
3170 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
3173 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
3174 GRXFSIZ_DEPTH_SHIFT;
3175 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3176 FIFOSIZE_DEPTH_SHIFT;
3177 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3178 FIFOSIZE_DEPTH_SHIFT;
3180 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
3181 dev_dbg(hsotg->dev, " op_mode=%d\n",
3183 dev_dbg(hsotg->dev, " arch=%d\n",
3185 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
3186 hw->dma_desc_enable);
3187 dev_dbg(hsotg->dev, " power_optimized=%d\n",
3188 hw->power_optimized);
3189 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
3191 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
3193 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
3195 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
3196 hw->utmi_phy_data_width);
3197 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
3199 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
3200 hw->num_dev_perio_in_ep);
3201 dev_dbg(hsotg->dev, " host_channels=%d\n",
3203 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
3204 hw->max_transfer_size);
3205 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
3206 hw->max_packet_count);
3207 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
3208 hw->nperio_tx_q_depth);
3209 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
3210 hw->host_perio_tx_q_depth);
3211 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
3212 hw->dev_token_q_depth);
3213 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
3214 hw->enable_dynamic_fifo);
3215 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
3216 hw->en_multiple_tx_fifo);
3217 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
3218 hw->total_fifo_size);
3219 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
3220 hw->host_rx_fifo_size);
3221 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
3222 hw->host_nperio_tx_fifo_size);
3223 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
3224 hw->host_perio_tx_fifo_size);
3225 dev_dbg(hsotg->dev, "\n");
3231 * Sets all parameters to the given value.
3233 * Assumes that the dwc2_core_params struct contains only integers.
3235 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
3237 int *p = (int *)params;
3238 size_t size = sizeof(*params) / sizeof(*p);
3241 for (i = 0; i < size; i++)
3246 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
3248 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
3251 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
3253 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
3260 * dwc2_enable_global_interrupts() - Enables the controller's Global
3261 * Interrupt in the AHB Config register
3263 * @hsotg: Programming view of DWC_otg controller
3265 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
3267 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3269 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
3270 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3274 * dwc2_disable_global_interrupts() - Disables the controller's Global
3275 * Interrupt in the AHB Config register
3277 * @hsotg: Programming view of DWC_otg controller
3279 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
3281 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3283 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
3284 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3287 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
3288 MODULE_AUTHOR("Synopsys, Inc.");
3289 MODULE_LICENSE("Dual BSD/GPL");