drivers/usb/dwc2/core.c

   1 /*
   2  * core.c - DesignWare HS OTG Controller common routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * The Core code provides basic services for accessing and managing the
  39  * DWC_otg hardware. These services are used by both the Host Controller
  40  * Driver and the Peripheral Controller Driver.
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  60 /**
  61  * dwc2_backup_host_registers() - Backup controller host registers.
  62  * When suspending usb bus, registers needs to be backuped
  63  * if controller power is disabled once suspended.
  64  *
  65  * @hsotg: Programming view of the DWC_otg controller
  66  */
  67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
  68 {
  69         struct dwc2_hregs_backup *hr;
  70         int i;
  71
  72         dev_dbg(hsotg->dev, "%s\n", __func__);
  73
  74         /* Backup Host regs */
  75         hr = &hsotg->hr_backup;
  76         hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
  77         hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
  78         for (i = 0; i < hsotg->core_params->host_channels; ++i)
  79                 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
  80
  81         hr->hprt0 = dwc2_read_hprt0(hsotg);
  82         hr->hfir = dwc2_readl(hsotg->regs + HFIR);
  83         hr->valid = true;
  84
  85         return 0;
  86 }
  87
  88 /**
  89  * dwc2_restore_host_registers() - Restore controller host registers.
  90  * When resuming usb bus, device registers needs to be restored
  91  * if controller power were disabled.
  92  *
  93  * @hsotg: Programming view of the DWC_otg controller
  94  */
  95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
  96 {
  97         struct dwc2_hregs_backup *hr;
  98         int i;
  99
 100         dev_dbg(hsotg->dev, "%s\n", __func__);
 101
 102         /* Restore host regs */
 103         hr = &hsotg->hr_backup;
 104         if (!hr->valid) {
 105                 dev_err(hsotg->dev, "%s: no host registers to restore\n",
 106                                 __func__);
 107                 return -EINVAL;
 108         }
 109         hr->valid = false;
 110
 111         dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
 112         dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
 113
 114         for (i = 0; i < hsotg->core_params->host_channels; ++i)
 115                 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
 116
 117         dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
 118         dwc2_writel(hr->hfir, hsotg->regs + HFIR);
 119         hsotg->frame_number = 0;
 120
 121         return 0;
 122 }
 123 #else
 124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
 125 { return 0; }
 126
 127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
 128 { return 0; }
 129 #endif
 130
 131 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
 132         IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
 133 /**
 134  * dwc2_backup_device_registers() - Backup controller device registers.
 135  * When suspending usb bus, registers needs to be backuped
 136  * if controller power is disabled once suspended.
 137  *
 138  * @hsotg: Programming view of the DWC_otg controller
 139  */
 140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
 141 {
 142         struct dwc2_dregs_backup *dr;
 143         int i;
 144
 145         dev_dbg(hsotg->dev, "%s\n", __func__);
 146
 147         /* Backup dev regs */
 148         dr = &hsotg->dr_backup;
 149
 150         dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
 151         dr->dctl = dwc2_readl(hsotg->regs + DCTL);
 152         dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
 153         dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
 154         dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
 155
 156         for (i = 0; i < hsotg->num_of_eps; i++) {
 157                 /* Backup IN EPs */
 158                 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
 159
 160                 /* Ensure DATA PID is correctly configured */
 161                 if (dr->diepctl[i] & DXEPCTL_DPID)
 162                         dr->diepctl[i] |= DXEPCTL_SETD1PID;
 163                 else
 164                         dr->diepctl[i] |= DXEPCTL_SETD0PID;
 165
 166                 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
 167                 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
 168
 169                 /* Backup OUT EPs */
 170                 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
 171
 172                 /* Ensure DATA PID is correctly configured */
 173                 if (dr->doepctl[i] & DXEPCTL_DPID)
 174                         dr->doepctl[i] |= DXEPCTL_SETD1PID;
 175                 else
 176                         dr->doepctl[i] |= DXEPCTL_SETD0PID;
 177
 178                 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
 179                 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
 180         }
 181         dr->valid = true;
 182         return 0;
 183 }
 184
 185 /**
 186  * dwc2_restore_device_registers() - Restore controller device registers.
 187  * When resuming usb bus, device registers needs to be restored
 188  * if controller power were disabled.
 189  *
 190  * @hsotg: Programming view of the DWC_otg controller
 191  */
 192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
 193 {
 194         struct dwc2_dregs_backup *dr;
 195         u32 dctl;
 196         int i;
 197
 198         dev_dbg(hsotg->dev, "%s\n", __func__);
 199
 200         /* Restore dev regs */
 201         dr = &hsotg->dr_backup;
 202         if (!dr->valid) {
 203                 dev_err(hsotg->dev, "%s: no device registers to restore\n",
 204                                 __func__);
 205                 return -EINVAL;
 206         }
 207         dr->valid = false;
 208
 209         dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
 210         dwc2_writel(dr->dctl, hsotg->regs + DCTL);
 211         dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
 212         dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
 213         dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
 214
 215         for (i = 0; i < hsotg->num_of_eps; i++) {
 216                 /* Restore IN EPs */
 217                 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
 218                 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
 219                 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
 220
 221                 /* Restore OUT EPs */
 222                 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
 223                 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
 224                 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
 225         }
 226
 227         /* Set the Power-On Programming done bit */
 228         dctl = dwc2_readl(hsotg->regs + DCTL);
 229         dctl |= DCTL_PWRONPRGDONE;
 230         dwc2_writel(dctl, hsotg->regs + DCTL);
 231
 232         return 0;
 233 }
 234 #else
 235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
 236 { return 0; }
 237
 238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
 239 { return 0; }
 240 #endif
 241
 242 /**
 243  * dwc2_backup_global_registers() - Backup global controller registers.
 244  * When suspending usb bus, registers needs to be backuped
 245  * if controller power is disabled once suspended.
 246  *
 247  * @hsotg: Programming view of the DWC_otg controller
 248  */
 249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
 250 {
 251         struct dwc2_gregs_backup *gr;
 252         int i;
 253
 254         /* Backup global regs */
 255         gr = &hsotg->gr_backup;
 256
 257         gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 258         gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 259         gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 260         gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 261         gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 262         gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
 263         gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
 264         gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
 265         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 266                 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
 267
 268         gr->valid = true;
 269         return 0;
 270 }
 271
 272 /**
 273  * dwc2_restore_global_registers() - Restore controller global registers.
 274  * When resuming usb bus, device registers needs to be restored
 275  * if controller power were disabled.
 276  *
 277  * @hsotg: Programming view of the DWC_otg controller
 278  */
 279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
 280 {
 281         struct dwc2_gregs_backup *gr;
 282         int i;
 283
 284         dev_dbg(hsotg->dev, "%s\n", __func__);
 285
 286         /* Restore global regs */
 287         gr = &hsotg->gr_backup;
 288         if (!gr->valid) {
 289                 dev_err(hsotg->dev, "%s: no global registers to restore\n",
 290                                 __func__);
 291                 return -EINVAL;
 292         }
 293         gr->valid = false;
 294
 295         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 296         dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
 297         dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
 298         dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
 299         dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
 300         dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
 301         dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
 302         dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
 303         dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
 304         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 305                 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
 312  *
 313  * @hsotg: Programming view of the DWC_otg controller
 314  * @restore: Controller registers need to be restored
 315  */
 316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
 317 {
 318         u32 pcgcctl;
 319         int ret = 0;
 320
 321         if (!hsotg->core_params->hibernation)
 322                 return -ENOTSUPP;
 323
 324         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 325         pcgcctl &= ~PCGCTL_STOPPCLK;
 326         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 327
 328         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 329         pcgcctl &= ~PCGCTL_PWRCLMP;
 330         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 331
 332         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 333         pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
 334         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 335
 336         udelay(100);
 337         if (restore) {
 338                 ret = dwc2_restore_global_registers(hsotg);
 339                 if (ret) {
 340                         dev_err(hsotg->dev, "%s: failed to restore registers\n",
 341                                         __func__);
 342                         return ret;
 343                 }
 344                 if (dwc2_is_host_mode(hsotg)) {
 345                         ret = dwc2_restore_host_registers(hsotg);
 346                         if (ret) {
 347                                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
 348                                                 __func__);
 349                                 return ret;
 350                         }
 351                 } else {
 352                         ret = dwc2_restore_device_registers(hsotg);
 353                         if (ret) {
 354                                 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
 355                                                 __func__);
 356                                 return ret;
 357                         }
 358                 }
 359         }
 360
 361         return ret;
 362 }
 363
 364 /**
 365  * dwc2_enter_hibernation() - Put controller in Partial Power Down.
 366  *
 367  * @hsotg: Programming view of the DWC_otg controller
 368  */
 369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
 370 {
 371         u32 pcgcctl;
 372         int ret = 0;
 373
 374         if (!hsotg->core_params->hibernation)
 375                 return -ENOTSUPP;
 376
 377         /* Backup all registers */
 378         ret = dwc2_backup_global_registers(hsotg);
 379         if (ret) {
 380                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
 381                                 __func__);
 382                 return ret;
 383         }
 384
 385         if (dwc2_is_host_mode(hsotg)) {
 386                 ret = dwc2_backup_host_registers(hsotg);
 387                 if (ret) {
 388                         dev_err(hsotg->dev, "%s: failed to backup host registers\n",
 389                                         __func__);
 390                         return ret;
 391                 }
 392         } else {
 393                 ret = dwc2_backup_device_registers(hsotg);
 394                 if (ret) {
 395                         dev_err(hsotg->dev, "%s: failed to backup device registers\n",
 396                                         __func__);
 397                         return ret;
 398                 }
 399         }
 400
 401         /*
 402          * Clear any pending interrupts since dwc2 will not be able to
 403          * clear them after entering hibernation.
 404          */
 405         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 406
 407         /* Put the controller in low power state */
 408         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 409
 410         pcgcctl |= PCGCTL_PWRCLMP;
 411         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 412         ndelay(20);
 413
 414         pcgcctl |= PCGCTL_RSTPDWNMODULE;
 415         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 416         ndelay(20);
 417
 418         pcgcctl |= PCGCTL_STOPPCLK;
 419         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 420
 421         return ret;
 422 }
 423
 424 /**
 425  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
 426  * used in both device and host modes
 427  *
 428  * @hsotg: Programming view of the DWC_otg controller
 429  */
 430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
 431 {
 432         u32 intmsk;
 433
 434         /* Clear any pending OTG Interrupts */
 435         dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
 436
 437         /* Clear any pending interrupts */
 438         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 439
 440         /* Enable the interrupts in the GINTMSK */
 441         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
 442
 443         if (hsotg->core_params->dma_enable <= 0)
 444                 intmsk |= GINTSTS_RXFLVL;
 445         if (hsotg->core_params->external_id_pin_ctl <= 0)
 446                 intmsk |= GINTSTS_CONIDSTSCHNG;
 447
 448         intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
 449                   GINTSTS_SESSREQINT;
 450
 451         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 452 }
 453
 454 /*
 455  * Initializes the FSLSPClkSel field of the HCFG register depending on the
 456  * PHY type
 457  */
 458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 459 {
 460         u32 hcfg, val;
 461
 462         if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 463              hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 464              hsotg->core_params->ulpi_fs_ls > 0) ||
 465             hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 466                 /* Full speed PHY */
 467                 val = HCFG_FSLSPCLKSEL_48_MHZ;
 468         } else {
 469                 /* High speed PHY running at full speed or high speed */
 470                 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
 471         }
 472
 473         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
 474         hcfg = dwc2_readl(hsotg->regs + HCFG);
 475         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 476         hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
 477         dwc2_writel(hcfg, hsotg->regs + HCFG);
 478 }
 479
 480 /*
 481  * Do core a soft reset of the core.  Be careful with this because it
 482  * resets all the internal state machines of the core.
 483  */
 484 int dwc2_core_reset(struct dwc2_hsotg *hsotg)
 485 {
 486         u32 greset;
 487         int count = 0;
 488         u32 gusbcfg;
 489
 490         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 491
 492         /* Core Soft Reset */
 493         greset = dwc2_readl(hsotg->regs + GRSTCTL);
 494         greset |= GRSTCTL_CSFTRST;
 495         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 496         do {
 497                 udelay(1);
 498                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 499                 if (++count > 50) {
 500                         dev_warn(hsotg->dev,
 501                                  "%s() HANG! Soft Reset GRSTCTL=%0x\n",
 502                                  __func__, greset);
 503                         return -EBUSY;
 504                 }
 505         } while (greset & GRSTCTL_CSFTRST);
 506
 507         /* Wait for AHB master IDLE state */
 508         count = 0;
 509         do {
 510                 udelay(1);
 511                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 512                 if (++count > 50) {
 513                         dev_warn(hsotg->dev,
 514                                  "%s() HANG! AHB Idle GRSTCTL=%0x\n",
 515                                  __func__, greset);
 516                         return -EBUSY;
 517                 }
 518         } while (!(greset & GRSTCTL_AHBIDLE));
 519
 520         if (hsotg->dr_mode == USB_DR_MODE_HOST) {
 521                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 522                 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 523                 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
 524                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 525         } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
 526                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 527                 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 528                 gusbcfg |= GUSBCFG_FORCEDEVMODE;
 529                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 530         } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
 531                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 532                 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 533                 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 534                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 535         }
 536
 537         /*
 538          * NOTE: This long sleep is _very_ important, otherwise the core will
 539          * not stay in host mode after a connector ID change!
 540          */
 541         usleep_range(150000, 160000);
 542
 543         return 0;
 544 }
 545
 546 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 547 {
 548         u32 usbcfg, i2cctl;
 549         int retval = 0;
 550
 551         /*
 552          * core_init() is now called on every switch so only call the
 553          * following for the first time through
 554          */
 555         if (select_phy) {
 556                 dev_dbg(hsotg->dev, "FS PHY selected\n");
 557
 558                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 559                 if (!(usbcfg & GUSBCFG_PHYSEL)) {
 560                         usbcfg |= GUSBCFG_PHYSEL;
 561                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 562
 563                         /* Reset after a PHY select */
 564                         retval = dwc2_core_reset(hsotg);
 565
 566                         if (retval) {
 567                                 dev_err(hsotg->dev,
 568                                         "%s: Reset failed, aborting", __func__);
 569                                 return retval;
 570                         }
 571                 }
 572         }
 573
 574         /*
 575          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
 576          * do this on HNP Dev/Host mode switches (done in dev_init and
 577          * host_init).
 578          */
 579         if (dwc2_is_host_mode(hsotg))
 580                 dwc2_init_fs_ls_pclk_sel(hsotg);
 581
 582         if (hsotg->core_params->i2c_enable > 0) {
 583                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 584
 585                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 586                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 587                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 588                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 589
 590                 /* Program GI2CCTL.I2CEn */
 591                 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
 592                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 593                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 594                 i2cctl &= ~GI2CCTL_I2CEN;
 595                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 596                 i2cctl |= GI2CCTL_I2CEN;
 597                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 598         }
 599
 600         return retval;
 601 }
 602
 603 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 604 {
 605         u32 usbcfg, usbcfg_old;
 606         int retval = 0;
 607
 608         if (!select_phy)
 609                 return 0;
 610
 611         usbcfg = usbcfg_old = dwc2_readl(hsotg->regs + GUSBCFG);
 612
 613         /*
 614          * HS PHY parameters. These parameters are preserved during soft reset
 615          * so only program the first time. Do a soft reset immediately after
 616          * setting phyif.
 617          */
 618         switch (hsotg->core_params->phy_type) {
 619         case DWC2_PHY_TYPE_PARAM_ULPI:
 620                 /* ULPI interface */
 621                 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
 622                 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 623                 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 624                 if (hsotg->core_params->phy_ulpi_ddr > 0)
 625                         usbcfg |= GUSBCFG_DDRSEL;
 626                 break;
 627         case DWC2_PHY_TYPE_PARAM_UTMI:
 628                 /* UTMI+ interface */
 629                 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
 630                 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 631                 if (hsotg->core_params->phy_utmi_width == 16)
 632                         usbcfg |= GUSBCFG_PHYIF16;
 633                 break;
 634         default:
 635                 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
 636                 break;
 637         }
 638
 639         if (usbcfg != usbcfg_old) {
 640                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 641
 642                 /* Reset after setting the PHY parameters */
 643                 retval = dwc2_core_reset(hsotg);
 644                 if (retval) {
 645                         dev_err(hsotg->dev,
 646                                 "%s: Reset failed, aborting", __func__);
 647                         return retval;
 648                 }
 649         }
 650
 651         return retval;
 652 }
 653
 654 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 655 {
 656         u32 usbcfg;
 657         int retval = 0;
 658
 659         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
 660             hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 661                 /* If FS mode with FS PHY */
 662                 retval = dwc2_fs_phy_init(hsotg, select_phy);
 663                 if (retval)
 664                         return retval;
 665         } else {
 666                 /* High speed PHY */
 667                 retval = dwc2_hs_phy_init(hsotg, select_phy);
 668                 if (retval)
 669                         return retval;
 670         }
 671
 672         if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 673             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 674             hsotg->core_params->ulpi_fs_ls > 0) {
 675                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 676                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 677                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 678                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 679                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 680         } else {
 681                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 682                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 683                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 684                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 685         }
 686
 687         return retval;
 688 }
 689
 690 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 691 {
 692         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 693
 694         switch (hsotg->hw_params.arch) {
 695         case GHWCFG2_EXT_DMA_ARCH:
 696                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 697                 return -EINVAL;
 698
 699         case GHWCFG2_INT_DMA_ARCH:
 700                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 701                 if (hsotg->core_params->ahbcfg != -1) {
 702                         ahbcfg &= GAHBCFG_CTRL_MASK;
 703                         ahbcfg |= hsotg->core_params->ahbcfg &
 704                                   ~GAHBCFG_CTRL_MASK;
 705                 }
 706                 break;
 707
 708         case GHWCFG2_SLAVE_ONLY_ARCH:
 709         default:
 710                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 711                 break;
 712         }
 713
 714         dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
 715                 hsotg->core_params->dma_enable,
 716                 hsotg->core_params->dma_desc_enable);
 717
 718         if (hsotg->core_params->dma_enable > 0) {
 719                 if (hsotg->core_params->dma_desc_enable > 0)
 720                         dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
 721                 else
 722                         dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
 723         } else {
 724                 dev_dbg(hsotg->dev, "Using Slave mode\n");
 725                 hsotg->core_params->dma_desc_enable = 0;
 726         }
 727
 728         if (hsotg->core_params->dma_enable > 0)
 729                 ahbcfg |= GAHBCFG_DMA_EN;
 730
 731         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 732
 733         return 0;
 734 }
 735
 736 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 737 {
 738         u32 usbcfg;
 739
 740         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 741         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 742
 743         switch (hsotg->hw_params.op_mode) {
 744         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 745                 if (hsotg->core_params->otg_cap ==
 746                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 747                         usbcfg |= GUSBCFG_HNPCAP;
 748                 if (hsotg->core_params->otg_cap !=
 749                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 750                         usbcfg |= GUSBCFG_SRPCAP;
 751                 break;
 752
 753         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 754         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 755         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 756                 if (hsotg->core_params->otg_cap !=
 757                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 758                         usbcfg |= GUSBCFG_SRPCAP;
 759                 break;
 760
 761         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 762         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 763         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 764         default:
 765                 break;
 766         }
 767
 768         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 769 }
 770
 771 /**
 772  * dwc2_core_init() - Initializes the DWC_otg controller registers and
 773  * prepares the core for device mode or host mode operation
 774  *
 775  * @hsotg:         Programming view of the DWC_otg controller
 776  * @initial_setup: If true then this is the first init for this instance.
 777  */
 778 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
 779 {
 780         u32 usbcfg, otgctl;
 781         int retval;
 782
 783         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 784
 785         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 786
 787         /* Set ULPI External VBUS bit if needed */
 788         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
 789         if (hsotg->core_params->phy_ulpi_ext_vbus ==
 790                                 DWC2_PHY_ULPI_EXTERNAL_VBUS)
 791                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
 792
 793         /* Set external TS Dline pulsing bit if needed */
 794         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
 795         if (hsotg->core_params->ts_dline > 0)
 796                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
 797
 798         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 799
 800         /*
 801          * Reset the Controller
 802          *
 803          * We only need to reset the controller if this is a re-init.
 804          * For the first init we know for sure that earlier code reset us (it
 805          * needed to in order to properly detect various parameters).
 806          */
 807         if (!initial_setup) {
 808                 retval = dwc2_core_reset(hsotg);
 809                 if (retval) {
 810                         dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
 811                                         __func__);
 812                         return retval;
 813                 }
 814         }
 815
 816         /*
 817          * This needs to happen in FS mode before any other programming occurs
 818          */
 819         retval = dwc2_phy_init(hsotg, initial_setup);
 820         if (retval)
 821                 return retval;
 822
 823         /* Program the GAHBCFG Register */
 824         retval = dwc2_gahbcfg_init(hsotg);
 825         if (retval)
 826                 return retval;
 827
 828         /* Program the GUSBCFG register */
 829         dwc2_gusbcfg_init(hsotg);
 830
 831         /* Program the GOTGCTL register */
 832         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 833         otgctl &= ~GOTGCTL_OTGVER;
 834         if (hsotg->core_params->otg_ver > 0)
 835                 otgctl |= GOTGCTL_OTGVER;
 836         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
 837         dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
 838
 839         /* Clear the SRP success bit for FS-I2c */
 840         hsotg->srp_success = 0;
 841
 842         /* Enable common interrupts */
 843         dwc2_enable_common_interrupts(hsotg);
 844
 845         /*
 846          * Do device or host initialization based on mode during PCD and
 847          * HCD initialization
 848          */
 849         if (dwc2_is_host_mode(hsotg)) {
 850                 dev_dbg(hsotg->dev, "Host Mode\n");
 851                 hsotg->op_state = OTG_STATE_A_HOST;
 852         } else {
 853                 dev_dbg(hsotg->dev, "Device Mode\n");
 854                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 855         }
 856
 857         return 0;
 858 }
 859
 860 /**
 861  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 862  *
 863  * @hsotg: Programming view of DWC_otg controller
 864  */
 865 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 866 {
 867         u32 intmsk;
 868
 869         dev_dbg(hsotg->dev, "%s()\n", __func__);
 870
 871         /* Disable all interrupts */
 872         dwc2_writel(0, hsotg->regs + GINTMSK);
 873         dwc2_writel(0, hsotg->regs + HAINTMSK);
 874
 875         /* Enable the common interrupts */
 876         dwc2_enable_common_interrupts(hsotg);
 877
 878         /* Enable host mode interrupts without disturbing common interrupts */
 879         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 880         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 881         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 882 }
 883
 884 /**
 885  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 886  *
 887  * @hsotg: Programming view of DWC_otg controller
 888  */
 889 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 890 {
 891         u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 892
 893         /* Disable host mode interrupts without disturbing common interrupts */
 894         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 895                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
 896         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 897 }
 898
 899 /*
 900  * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
 901  * For system that have a total fifo depth that is smaller than the default
 902  * RX + TX fifo size.
 903  *
 904  * @hsotg: Programming view of DWC_otg controller
 905  */
 906 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
 907 {
 908         struct dwc2_core_params *params = hsotg->core_params;
 909         struct dwc2_hw_params *hw = &hsotg->hw_params;
 910         u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
 911
 912         total_fifo_size = hw->total_fifo_size;
 913         rxfsiz = params->host_rx_fifo_size;
 914         nptxfsiz = params->host_nperio_tx_fifo_size;
 915         ptxfsiz = params->host_perio_tx_fifo_size;
 916
 917         /*
 918          * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
 919          * allocation with support for high bandwidth endpoints. Synopsys
 920          * defines MPS(Max Packet size) for a periodic EP=1024, and for
 921          * non-periodic as 512.
 922          */
 923         if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
 924                 /*
 925                  * For Buffer DMA mode/Scatter Gather DMA mode
 926                  * 2 * ((Largest Packet size / 4) + 1 + 1) + n
 927                  * with n = number of host channel.
 928                  * 2 * ((1024/4) + 2) = 516
 929                  */
 930                 rxfsiz = 516 + hw->host_channels;
 931
 932                 /*
 933                  * min non-periodic tx fifo depth
 934                  * 2 * (largest non-periodic USB packet used / 4)
 935                  * 2 * (512/4) = 256
 936                  */
 937                 nptxfsiz = 256;
 938
 939                 /*
 940                  * min periodic tx fifo depth
 941                  * (largest packet size*MC)/4
 942                  * (1024 * 3)/4 = 768
 943                  */
 944                 ptxfsiz = 768;
 945
 946                 params->host_rx_fifo_size = rxfsiz;
 947                 params->host_nperio_tx_fifo_size = nptxfsiz;
 948                 params->host_perio_tx_fifo_size = ptxfsiz;
 949         }
 950
 951         /*
 952          * If the summation of RX, NPTX and PTX fifo sizes is still
 953          * bigger than the total_fifo_size, then we have a problem.
 954          *
 955          * We won't be able to allocate as many endpoints. Right now,
 956          * we're just printing an error message, but ideally this FIFO
 957          * allocation algorithm would be improved in the future.
 958          *
 959          * FIXME improve this FIFO allocation algorithm.
 960          */
 961         if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
 962                 dev_err(hsotg->dev, "invalid fifo sizes\n");
 963 }
 964
 965 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 966 {
 967         struct dwc2_core_params *params = hsotg->core_params;
 968         u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
 969
 970         if (!params->enable_dynamic_fifo)
 971                 return;
 972
 973         dwc2_calculate_dynamic_fifo(hsotg);
 974
 975         /* Rx FIFO */
 976         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 977         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 978         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 979         grxfsiz |= params->host_rx_fifo_size <<
 980                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 981         dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
 982         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
 983                 dwc2_readl(hsotg->regs + GRXFSIZ));
 984
 985         /* Non-periodic Tx FIFO */
 986         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 987                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 988         nptxfsiz = params->host_nperio_tx_fifo_size <<
 989                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 990         nptxfsiz |= params->host_rx_fifo_size <<
 991                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 992         dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 993         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 994                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 995
 996         /* Periodic Tx FIFO */
 997         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 998                 dwc2_readl(hsotg->regs + HPTXFSIZ));
 999         hptxfsiz = params->host_perio_tx_fifo_size <<
1000                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
1001         hptxfsiz |= (params->host_rx_fifo_size +
1002                      params->host_nperio_tx_fifo_size) <<
1003                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
1004         dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
1005         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
1006                 dwc2_readl(hsotg->regs + HPTXFSIZ));
1007
1008         if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
1009             hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
1010                 /*
1011                  * Global DFIFOCFG calculation for Host mode -
1012                  * include RxFIFO, NPTXFIFO and HPTXFIFO
1013                  */
1014                 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
1015                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
1016                 dfifocfg |= (params->host_rx_fifo_size +
1017                              params->host_nperio_tx_fifo_size +
1018                              params->host_perio_tx_fifo_size) <<
1019                             GDFIFOCFG_EPINFOBASE_SHIFT &
1020                             GDFIFOCFG_EPINFOBASE_MASK;
1021                 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
1022         }
1023 }
1024
1025 /**
1026  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
1027  * Host mode
1028  *
1029  * @hsotg: Programming view of DWC_otg controller
1030  *
1031  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
1032  * request queues. Host channels are reset to ensure that they are ready for
1033  * performing transfers.
1034  */
1035 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
1036 {
1037         u32 hcfg, hfir, otgctl;
1038
1039         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
1040
1041         /* Restart the Phy Clock */
1042         dwc2_writel(0, hsotg->regs + PCGCTL);
1043
1044         /* Initialize Host Configuration Register */
1045         dwc2_init_fs_ls_pclk_sel(hsotg);
1046         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
1047                 hcfg = dwc2_readl(hsotg->regs + HCFG);
1048                 hcfg |= HCFG_FSLSSUPP;
1049                 dwc2_writel(hcfg, hsotg->regs + HCFG);
1050         }
1051
1052         /*
1053          * This bit allows dynamic reloading of the HFIR register during
1054          * runtime. This bit needs to be programmed during initial configuration
1055          * and its value must not be changed during runtime.
1056          */
1057         if (hsotg->core_params->reload_ctl > 0) {
1058                 hfir = dwc2_readl(hsotg->regs + HFIR);
1059                 hfir |= HFIR_RLDCTRL;
1060                 dwc2_writel(hfir, hsotg->regs + HFIR);
1061         }
1062
1063         if (hsotg->core_params->dma_desc_enable > 0) {
1064                 u32 op_mode = hsotg->hw_params.op_mode;
1065                 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
1066                     !hsotg->hw_params.dma_desc_enable ||
1067                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
1068                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
1069                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
1070                         dev_err(hsotg->dev,
1071                                 "Hardware does not support descriptor DMA mode -\n");
1072                         dev_err(hsotg->dev,
1073                                 "falling back to buffer DMA mode.\n");
1074                         hsotg->core_params->dma_desc_enable = 0;
1075                 } else {
1076                         hcfg = dwc2_readl(hsotg->regs + HCFG);
1077                         hcfg |= HCFG_DESCDMA;
1078                         dwc2_writel(hcfg, hsotg->regs + HCFG);
1079                 }
1080         }
1081
1082         /* Configure data FIFO sizes */
1083         dwc2_config_fifos(hsotg);
1084
1085         /* TODO - check this */
1086         /* Clear Host Set HNP Enable in the OTG Control Register */
1087         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1088         otgctl &= ~GOTGCTL_HSTSETHNPEN;
1089         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1090
1091         /* Make sure the FIFOs are flushed */
1092         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
1093         dwc2_flush_rx_fifo(hsotg);
1094
1095         /* Clear Host Set HNP Enable in the OTG Control Register */
1096         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1097         otgctl &= ~GOTGCTL_HSTSETHNPEN;
1098         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1099
1100         if (hsotg->core_params->dma_desc_enable <= 0) {
1101                 int num_channels, i;
1102                 u32 hcchar;
1103
1104                 /* Flush out any leftover queued requests */
1105                 num_channels = hsotg->core_params->host_channels;
1106                 for (i = 0; i < num_channels; i++) {
1107                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1108                         hcchar &= ~HCCHAR_CHENA;
1109                         hcchar |= HCCHAR_CHDIS;
1110                         hcchar &= ~HCCHAR_EPDIR;
1111                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1112                 }
1113
1114                 /* Halt all channels to put them into a known state */
1115                 for (i = 0; i < num_channels; i++) {
1116                         int count = 0;
1117
1118                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1119                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
1120                         hcchar &= ~HCCHAR_EPDIR;
1121                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1122                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
1123                                 __func__, i);
1124                         do {
1125                                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1126                                 if (++count > 1000) {
1127                                         dev_err(hsotg->dev,
1128                                                 "Unable to clear enable on channel %d\n",
1129                                                 i);
1130                                         break;
1131                                 }
1132                                 udelay(1);
1133                         } while (hcchar & HCCHAR_CHENA);
1134                 }
1135         }
1136
1137         /* Turn on the vbus power */
1138         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
1139         if (hsotg->op_state == OTG_STATE_A_HOST) {
1140                 u32 hprt0 = dwc2_read_hprt0(hsotg);
1141
1142                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
1143                         !!(hprt0 & HPRT0_PWR));
1144                 if (!(hprt0 & HPRT0_PWR)) {
1145                         hprt0 |= HPRT0_PWR;
1146                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1147                 }
1148         }
1149
1150         dwc2_enable_host_interrupts(hsotg);
1151 }
1152
1153 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
1154                                       struct dwc2_host_chan *chan)
1155 {
1156         u32 hcintmsk = HCINTMSK_CHHLTD;
1157
1158         switch (chan->ep_type) {
1159         case USB_ENDPOINT_XFER_CONTROL:
1160         case USB_ENDPOINT_XFER_BULK:
1161                 dev_vdbg(hsotg->dev, "control/bulk\n");
1162                 hcintmsk |= HCINTMSK_XFERCOMPL;
1163                 hcintmsk |= HCINTMSK_STALL;
1164                 hcintmsk |= HCINTMSK_XACTERR;
1165                 hcintmsk |= HCINTMSK_DATATGLERR;
1166                 if (chan->ep_is_in) {
1167                         hcintmsk |= HCINTMSK_BBLERR;
1168                 } else {
1169                         hcintmsk |= HCINTMSK_NAK;
1170                         hcintmsk |= HCINTMSK_NYET;
1171                         if (chan->do_ping)
1172                                 hcintmsk |= HCINTMSK_ACK;
1173                 }
1174
1175                 if (chan->do_split) {
1176                         hcintmsk |= HCINTMSK_NAK;
1177                         if (chan->complete_split)
1178                                 hcintmsk |= HCINTMSK_NYET;
1179                         else
1180                                 hcintmsk |= HCINTMSK_ACK;
1181                 }
1182
1183                 if (chan->error_state)
1184                         hcintmsk |= HCINTMSK_ACK;
1185                 break;
1186
1187         case USB_ENDPOINT_XFER_INT:
1188                 if (dbg_perio())
1189                         dev_vdbg(hsotg->dev, "intr\n");
1190                 hcintmsk |= HCINTMSK_XFERCOMPL;
1191                 hcintmsk |= HCINTMSK_NAK;
1192                 hcintmsk |= HCINTMSK_STALL;
1193                 hcintmsk |= HCINTMSK_XACTERR;
1194                 hcintmsk |= HCINTMSK_DATATGLERR;
1195                 hcintmsk |= HCINTMSK_FRMOVRUN;
1196
1197                 if (chan->ep_is_in)
1198                         hcintmsk |= HCINTMSK_BBLERR;
1199                 if (chan->error_state)
1200                         hcintmsk |= HCINTMSK_ACK;
1201                 if (chan->do_split) {
1202                         if (chan->complete_split)
1203                                 hcintmsk |= HCINTMSK_NYET;
1204                         else
1205                                 hcintmsk |= HCINTMSK_ACK;
1206                 }
1207                 break;
1208
1209         case USB_ENDPOINT_XFER_ISOC:
1210                 if (dbg_perio())
1211                         dev_vdbg(hsotg->dev, "isoc\n");
1212                 hcintmsk |= HCINTMSK_XFERCOMPL;
1213                 hcintmsk |= HCINTMSK_FRMOVRUN;
1214                 hcintmsk |= HCINTMSK_ACK;
1215
1216                 if (chan->ep_is_in) {
1217                         hcintmsk |= HCINTMSK_XACTERR;
1218                         hcintmsk |= HCINTMSK_BBLERR;
1219                 }
1220                 break;
1221         default:
1222                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
1223                 break;
1224         }
1225
1226         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1227         if (dbg_hc(chan))
1228                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1229 }
1230
1231 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
1232                                     struct dwc2_host_chan *chan)
1233 {
1234         u32 hcintmsk = HCINTMSK_CHHLTD;
1235
1236         /*
1237          * For Descriptor DMA mode core halts the channel on AHB error.
1238          * Interrupt is not required.
1239          */
1240         if (hsotg->core_params->dma_desc_enable <= 0) {
1241                 if (dbg_hc(chan))
1242                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1243                 hcintmsk |= HCINTMSK_AHBERR;
1244         } else {
1245                 if (dbg_hc(chan))
1246                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
1247                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1248                         hcintmsk |= HCINTMSK_XFERCOMPL;
1249         }
1250
1251         if (chan->error_state && !chan->do_split &&
1252             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1253                 if (dbg_hc(chan))
1254                         dev_vdbg(hsotg->dev, "setting ACK\n");
1255                 hcintmsk |= HCINTMSK_ACK;
1256                 if (chan->ep_is_in) {
1257                         hcintmsk |= HCINTMSK_DATATGLERR;
1258                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
1259                                 hcintmsk |= HCINTMSK_NAK;
1260                 }
1261         }
1262
1263         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1264         if (dbg_hc(chan))
1265                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1266 }
1267
1268 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
1269                                 struct dwc2_host_chan *chan)
1270 {
1271         u32 intmsk;
1272
1273         if (hsotg->core_params->dma_enable > 0) {
1274                 if (dbg_hc(chan))
1275                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1276                 dwc2_hc_enable_dma_ints(hsotg, chan);
1277         } else {
1278                 if (dbg_hc(chan))
1279                         dev_vdbg(hsotg->dev, "DMA disabled\n");
1280                 dwc2_hc_enable_slave_ints(hsotg, chan);
1281         }
1282
1283         /* Enable the top level host channel interrupt */
1284         intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
1285         intmsk |= 1 << chan->hc_num;
1286         dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
1287         if (dbg_hc(chan))
1288                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
1289
1290         /* Make sure host channel interrupts are enabled */
1291         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
1292         intmsk |= GINTSTS_HCHINT;
1293         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
1294         if (dbg_hc(chan))
1295                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
1296 }
1297
1298 /**
1299  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
1300  * a specific endpoint
1301  *
1302  * @hsotg: Programming view of DWC_otg controller
1303  * @chan:  Information needed to initialize the host channel
1304  *
1305  * The HCCHARn register is set up with the characteristics specified in chan.
1306  * Host channel interrupts that may need to be serviced while this transfer is
1307  * in progress are enabled.
1308  */
1309 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1310 {
1311         u8 hc_num = chan->hc_num;
1312         u32 hcintmsk;
1313         u32 hcchar;
1314         u32 hcsplt = 0;
1315
1316         if (dbg_hc(chan))
1317                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1318
1319         /* Clear old interrupt conditions for this host channel */
1320         hcintmsk = 0xffffffff;
1321         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1322         dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
1323
1324         /* Enable channel interrupts required for this transfer */
1325         dwc2_hc_enable_ints(hsotg, chan);
1326
1327         /*
1328          * Program the HCCHARn register with the endpoint characteristics for
1329          * the current transfer
1330          */
1331         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
1332         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
1333         if (chan->ep_is_in)
1334                 hcchar |= HCCHAR_EPDIR;
1335         if (chan->speed == USB_SPEED_LOW)
1336                 hcchar |= HCCHAR_LSPDDEV;
1337         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
1338         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
1339         dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
1340         if (dbg_hc(chan)) {
1341                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
1342                          hc_num, hcchar);
1343
1344                 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
1345                          __func__, hc_num);
1346                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
1347                          chan->dev_addr);
1348                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
1349                          chan->ep_num);
1350                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
1351                          chan->ep_is_in);
1352                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
1353                          chan->speed == USB_SPEED_LOW);
1354                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
1355                          chan->ep_type);
1356                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
1357                          chan->max_packet);
1358         }
1359
1360         /* Program the HCSPLT register for SPLITs */
1361         if (chan->do_split) {
1362                 if (dbg_hc(chan))
1363                         dev_vdbg(hsotg->dev,
1364                                  "Programming HC %d with split --> %s\n",
1365                                  hc_num,
1366                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
1367                 if (chan->complete_split)
1368                         hcsplt |= HCSPLT_COMPSPLT;
1369                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
1370                           HCSPLT_XACTPOS_MASK;
1371                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
1372                           HCSPLT_HUBADDR_MASK;
1373                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
1374                           HCSPLT_PRTADDR_MASK;
1375                 if (dbg_hc(chan)) {
1376                         dev_vdbg(hsotg->dev, "    comp split %d\n",
1377                                  chan->complete_split);
1378                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
1379                                  chan->xact_pos);
1380                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
1381                                  chan->hub_addr);
1382                         dev_vdbg(hsotg->dev, "    hub port %d\n",
1383                                  chan->hub_port);
1384                         dev_vdbg(hsotg->dev, "    is_in %d\n",
1385                                  chan->ep_is_in);
1386                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
1387                                  chan->max_packet);
1388                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
1389                                  chan->xfer_len);
1390                 }
1391         }
1392
1393         dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
1394 }
1395
1396 /**
1397  * dwc2_hc_halt() - Attempts to halt a host channel
1398  *
1399  * @hsotg:       Controller register interface
1400  * @chan:        Host channel to halt
1401  * @halt_status: Reason for halting the channel
1402  *
1403  * This function should only be called in Slave mode or to abort a transfer in
1404  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
1405  * controller halts the channel when the transfer is complete or a condition
1406  * occurs that requires application intervention.
1407  *
1408  * In slave mode, checks for a free request queue entry, then sets the Channel
1409  * Enable and Channel Disable bits of the Host Channel Characteristics
1410  * register of the specified channel to intiate the halt. If there is no free
1411  * request queue entry, sets only the Channel Disable bit of the HCCHARn
1412  * register to flush requests for this channel. In the latter case, sets a
1413  * flag to indicate that the host channel needs to be halted when a request
1414  * queue slot is open.
1415  *
1416  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
1417  * HCCHARn register. The controller ensures there is space in the request
1418  * queue before submitting the halt request.
1419  *
1420  * Some time may elapse before the core flushes any posted requests for this
1421  * host channel and halts. The Channel Halted interrupt handler completes the
1422  * deactivation of the host channel.
1423  */
1424 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1425                   enum dwc2_halt_status halt_status)
1426 {
1427         u32 nptxsts, hptxsts, hcchar;
1428
1429         if (dbg_hc(chan))
1430                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1431         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1432                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1433
1434         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1435             halt_status == DWC2_HC_XFER_AHB_ERR) {
1436                 /*
1437                  * Disable all channel interrupts except Ch Halted. The QTD
1438                  * and QH state associated with this transfer has been cleared
1439                  * (in the case of URB_DEQUEUE), so the channel needs to be
1440                  * shut down carefully to prevent crashes.
1441                  */
1442                 u32 hcintmsk = HCINTMSK_CHHLTD;
1443
1444                 dev_vdbg(hsotg->dev, "dequeue/error\n");
1445                 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1446
1447                 /*
1448                  * Make sure no other interrupts besides halt are currently
1449                  * pending. Handling another interrupt could cause a crash due
1450                  * to the QTD and QH state.
1451                  */
1452                 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1453
1454                 /*
1455                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1456                  * even if the channel was already halted for some other
1457                  * reason
1458                  */
1459                 chan->halt_status = halt_status;
1460
1461                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1462                 if (!(hcchar & HCCHAR_CHENA)) {
1463                         /*
1464                          * The channel is either already halted or it hasn't
1465                          * started yet. In DMA mode, the transfer may halt if
1466                          * it finishes normally or a condition occurs that
1467                          * requires driver intervention. Don't want to halt
1468                          * the channel again. In either Slave or DMA mode,
1469                          * it's possible that the transfer has been assigned
1470                          * to a channel, but not started yet when an URB is
1471                          * dequeued. Don't want to halt a channel that hasn't
1472                          * started yet.
1473                          */
1474                         return;
1475                 }
1476         }
1477         if (chan->halt_pending) {
1478                 /*
1479                  * A halt has already been issued for this channel. This might
1480                  * happen when a transfer is aborted by a higher level in
1481                  * the stack.
1482                  */
1483                 dev_vdbg(hsotg->dev,
1484                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
1485                          __func__, chan->hc_num);
1486                 return;
1487         }
1488
1489         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1490
1491         /* No need to set the bit in DDMA for disabling the channel */
1492         /* TODO check it everywhere channel is disabled */
1493         if (hsotg->core_params->dma_desc_enable <= 0) {
1494                 if (dbg_hc(chan))
1495                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1496                 hcchar |= HCCHAR_CHENA;
1497         } else {
1498                 if (dbg_hc(chan))
1499                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
1500         }
1501         hcchar |= HCCHAR_CHDIS;
1502
1503         if (hsotg->core_params->dma_enable <= 0) {
1504                 if (dbg_hc(chan))
1505                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
1506                 hcchar |= HCCHAR_CHENA;
1507
1508                 /* Check for space in the request queue to issue the halt */
1509                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1510                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1511                         dev_vdbg(hsotg->dev, "control/bulk\n");
1512                         nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1513                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1514                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
1515                                 hcchar &= ~HCCHAR_CHENA;
1516                         }
1517                 } else {
1518                         if (dbg_perio())
1519                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
1520                         hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1521                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1522                             hsotg->queuing_high_bandwidth) {
1523                                 if (dbg_perio())
1524                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
1525                                 hcchar &= ~HCCHAR_CHENA;
1526                         }
1527                 }
1528         } else {
1529                 if (dbg_hc(chan))
1530                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1531         }
1532
1533         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1534         chan->halt_status = halt_status;
1535
1536         if (hcchar & HCCHAR_CHENA) {
1537                 if (dbg_hc(chan))
1538                         dev_vdbg(hsotg->dev, "Channel enabled\n");
1539                 chan->halt_pending = 1;
1540                 chan->halt_on_queue = 0;
1541         } else {
1542                 if (dbg_hc(chan))
1543                         dev_vdbg(hsotg->dev, "Channel disabled\n");
1544                 chan->halt_on_queue = 1;
1545         }
1546
1547         if (dbg_hc(chan)) {
1548                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1549                          chan->hc_num);
1550                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
1551                          hcchar);
1552                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
1553                          chan->halt_pending);
1554                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
1555                          chan->halt_on_queue);
1556                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
1557                          chan->halt_status);
1558         }
1559 }
1560
1561 /**
1562  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1563  *
1564  * @hsotg: Programming view of DWC_otg controller
1565  * @chan:  Identifies the host channel to clean up
1566  *
1567  * This function is normally called after a transfer is done and the host
1568  * channel is being released
1569  */
1570 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1571 {
1572         u32 hcintmsk;
1573
1574         chan->xfer_started = 0;
1575
1576         /*
1577          * Clear channel interrupt enables and any unhandled channel interrupt
1578          * conditions
1579          */
1580         dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1581         hcintmsk = 0xffffffff;
1582         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1583         dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1584 }
1585
1586 /**
1587  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1588  * which frame a periodic transfer should occur
1589  *
1590  * @hsotg:  Programming view of DWC_otg controller
1591  * @chan:   Identifies the host channel to set up and its properties
1592  * @hcchar: Current value of the HCCHAR register for the specified host channel
1593  *
1594  * This function has no effect on non-periodic transfers
1595  */
1596 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1597                                        struct dwc2_host_chan *chan, u32 *hcchar)
1598 {
1599         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1600             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1601                 /* 1 if _next_ frame is odd, 0 if it's even */
1602                 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1603                         *hcchar |= HCCHAR_ODDFRM;
1604         }
1605 }
1606
1607 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1608 {
1609         /* Set up the initial PID for the transfer */
1610         if (chan->speed == USB_SPEED_HIGH) {
1611                 if (chan->ep_is_in) {
1612                         if (chan->multi_count == 1)
1613                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1614                         else if (chan->multi_count == 2)
1615                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1616                         else
1617                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1618                 } else {
1619                         if (chan->multi_count == 1)
1620                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1621                         else
1622                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1623                 }
1624         } else {
1625                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1626         }
1627 }
1628
1629 /**
1630  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1631  * the Host Channel
1632  *
1633  * @hsotg: Programming view of DWC_otg controller
1634  * @chan:  Information needed to initialize the host channel
1635  *
1636  * This function should only be called in Slave mode. For a channel associated
1637  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1638  * associated with a periodic EP, the periodic Tx FIFO is written.
1639  *
1640  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1641  * the number of bytes written to the Tx FIFO.
1642  */
1643 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1644                                  struct dwc2_host_chan *chan)
1645 {
1646         u32 i;
1647         u32 remaining_count;
1648         u32 byte_count;
1649         u32 dword_count;
1650         u32 __iomem *data_fifo;
1651         u32 *data_buf = (u32 *)chan->xfer_buf;
1652
1653         if (dbg_hc(chan))
1654                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1655
1656         data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1657
1658         remaining_count = chan->xfer_len - chan->xfer_count;
1659         if (remaining_count > chan->max_packet)
1660                 byte_count = chan->max_packet;
1661         else
1662                 byte_count = remaining_count;
1663
1664         dword_count = (byte_count + 3) / 4;
1665
1666         if (((unsigned long)data_buf & 0x3) == 0) {
1667                 /* xfer_buf is DWORD aligned */
1668                 for (i = 0; i < dword_count; i++, data_buf++)
1669                         dwc2_writel(*data_buf, data_fifo);
1670         } else {
1671                 /* xfer_buf is not DWORD aligned */
1672                 for (i = 0; i < dword_count; i++, data_buf++) {
1673                         u32 data = data_buf[0] | data_buf[1] << 8 |
1674                                    data_buf[2] << 16 | data_buf[3] << 24;
1675                         dwc2_writel(data, data_fifo);
1676                 }
1677         }
1678
1679         chan->xfer_count += byte_count;
1680         chan->xfer_buf += byte_count;
1681 }
1682
1683 /**
1684  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1685  * channel and starts the transfer
1686  *
1687  * @hsotg: Programming view of DWC_otg controller
1688  * @chan:  Information needed to initialize the host channel. The xfer_len value
1689  *         may be reduced to accommodate the max widths of the XferSize and
1690  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1691  *         changed to reflect the final xfer_len value.
1692  *
1693  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1694  * the caller must ensure that there is sufficient space in the request queue
1695  * and Tx Data FIFO.
1696  *
1697  * For an OUT transfer in Slave mode, it loads a data packet into the
1698  * appropriate FIFO. If necessary, additional data packets are loaded in the
1699  * Host ISR.
1700  *
1701  * For an IN transfer in Slave mode, a data packet is requested. The data
1702  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1703  * additional data packets are requested in the Host ISR.
1704  *
1705  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1706  * register along with a packet count of 1 and the channel is enabled. This
1707  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1708  * simply set to 0 since no data transfer occurs in this case.
1709  *
1710  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1711  * all the information required to perform the subsequent data transfer. In
1712  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1713  * controller performs the entire PING protocol, then starts the data
1714  * transfer.
1715  */
1716 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1717                             struct dwc2_host_chan *chan)
1718 {
1719         u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1720         u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1721         u32 hcchar;
1722         u32 hctsiz = 0;
1723         u16 num_packets;
1724         u32 ec_mc;
1725
1726         if (dbg_hc(chan))
1727                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1728
1729         if (chan->do_ping) {
1730                 if (hsotg->core_params->dma_enable <= 0) {
1731                         if (dbg_hc(chan))
1732                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1733                         dwc2_hc_do_ping(hsotg, chan);
1734                         chan->xfer_started = 1;
1735                         return;
1736                 } else {
1737                         if (dbg_hc(chan))
1738                                 dev_vdbg(hsotg->dev, "ping, DMA\n");
1739                         hctsiz |= TSIZ_DOPNG;
1740                 }
1741         }
1742
1743         if (chan->do_split) {
1744                 if (dbg_hc(chan))
1745                         dev_vdbg(hsotg->dev, "split\n");
1746                 num_packets = 1;
1747
1748                 if (chan->complete_split && !chan->ep_is_in)
1749                         /*
1750                          * For CSPLIT OUT Transfer, set the size to 0 so the
1751                          * core doesn't expect any data written to the FIFO
1752                          */
1753                         chan->xfer_len = 0;
1754                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1755                         chan->xfer_len = chan->max_packet;
1756                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1757                         chan->xfer_len = 188;
1758
1759                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1760                           TSIZ_XFERSIZE_MASK;
1761
1762                 /* For split set ec_mc for immediate retries */
1763                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1764                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1765                         ec_mc = 3;
1766                 else
1767                         ec_mc = 1;
1768         } else {
1769                 if (dbg_hc(chan))
1770                         dev_vdbg(hsotg->dev, "no split\n");
1771                 /*
1772                  * Ensure that the transfer length and packet count will fit
1773                  * in the widths allocated for them in the HCTSIZn register
1774                  */
1775                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1776                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1777                         /*
1778                          * Make sure the transfer size is no larger than one
1779                          * (micro)frame's worth of data. (A check was done
1780                          * when the periodic transfer was accepted to ensure
1781                          * that a (micro)frame's worth of data can be
1782                          * programmed into a channel.)
1783                          */
1784                         u32 max_periodic_len =
1785                                 chan->multi_count * chan->max_packet;
1786
1787                         if (chan->xfer_len > max_periodic_len)
1788                                 chan->xfer_len = max_periodic_len;
1789                 } else if (chan->xfer_len > max_hc_xfer_size) {
1790                         /*
1791                          * Make sure that xfer_len is a multiple of max packet
1792                          * size
1793                          */
1794                         chan->xfer_len =
1795                                 max_hc_xfer_size - chan->max_packet + 1;
1796                 }
1797
1798                 if (chan->xfer_len > 0) {
1799                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1800                                         chan->max_packet;
1801                         if (num_packets > max_hc_pkt_count) {
1802                                 num_packets = max_hc_pkt_count;
1803                                 chan->xfer_len = num_packets * chan->max_packet;
1804                         }
1805                 } else {
1806                         /* Need 1 packet for transfer length of 0 */
1807                         num_packets = 1;
1808                 }
1809
1810                 if (chan->ep_is_in)
1811                         /*
1812                          * Always program an integral # of max packets for IN
1813                          * transfers
1814                          */
1815                         chan->xfer_len = num_packets * chan->max_packet;
1816
1817                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1818                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1819                         /*
1820                          * Make sure that the multi_count field matches the
1821                          * actual transfer length
1822                          */
1823                         chan->multi_count = num_packets;
1824
1825                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1826                         dwc2_set_pid_isoc(chan);
1827
1828                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1829                           TSIZ_XFERSIZE_MASK;
1830
1831                 /* The ec_mc gets the multi_count for non-split */
1832                 ec_mc = chan->multi_count;
1833         }
1834
1835         chan->start_pkt_count = num_packets;
1836         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1837         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1838                   TSIZ_SC_MC_PID_MASK;
1839         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1840         if (dbg_hc(chan)) {
1841                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1842                          hctsiz, chan->hc_num);
1843
1844                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1845                          chan->hc_num);
1846                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1847                          (hctsiz & TSIZ_XFERSIZE_MASK) >>
1848                          TSIZ_XFERSIZE_SHIFT);
1849                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1850                          (hctsiz & TSIZ_PKTCNT_MASK) >>
1851                          TSIZ_PKTCNT_SHIFT);
1852                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1853                          (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1854                          TSIZ_SC_MC_PID_SHIFT);
1855         }
1856
1857         if (hsotg->core_params->dma_enable > 0) {
1858                 dma_addr_t dma_addr;
1859
1860                 if (chan->align_buf) {
1861                         if (dbg_hc(chan))
1862                                 dev_vdbg(hsotg->dev, "align_buf\n");
1863                         dma_addr = chan->align_buf;
1864                 } else {
1865                         dma_addr = chan->xfer_dma;
1866                 }
1867                 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1868                 if (dbg_hc(chan))
1869                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1870                                  (unsigned long)dma_addr, chan->hc_num);
1871         }
1872
1873         /* Start the split */
1874         if (chan->do_split) {
1875                 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1876
1877                 hcsplt |= HCSPLT_SPLTENA;
1878                 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1879         }
1880
1881         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1882         hcchar &= ~HCCHAR_MULTICNT_MASK;
1883         hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1884         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1885
1886         if (hcchar & HCCHAR_CHDIS)
1887                 dev_warn(hsotg->dev,
1888                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1889                          __func__, chan->hc_num, hcchar);
1890
1891         /* Set host channel enable after all other setup is complete */
1892         hcchar |= HCCHAR_CHENA;
1893         hcchar &= ~HCCHAR_CHDIS;
1894
1895         if (dbg_hc(chan))
1896                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1897                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1898                          HCCHAR_MULTICNT_SHIFT);
1899
1900         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1901         if (dbg_hc(chan))
1902                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1903                          chan->hc_num);
1904
1905         chan->xfer_started = 1;
1906         chan->requests++;
1907
1908         if (hsotg->core_params->dma_enable <= 0 &&
1909             !chan->ep_is_in && chan->xfer_len > 0)
1910                 /* Load OUT packet into the appropriate Tx FIFO */
1911                 dwc2_hc_write_packet(hsotg, chan);
1912 }
1913
1914 /**
1915  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1916  * host channel and starts the transfer in Descriptor DMA mode
1917  *
1918  * @hsotg: Programming view of DWC_otg controller
1919  * @chan:  Information needed to initialize the host channel
1920  *
1921  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1922  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1923  * with micro-frame bitmap.
1924  *
1925  * Initializes HCDMA register with descriptor list address and CTD value then
1926  * starts the transfer via enabling the channel.
1927  */
1928 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1929                                  struct dwc2_host_chan *chan)
1930 {
1931         u32 hcchar;
1932         u32 hctsiz = 0;
1933
1934         if (chan->do_ping)
1935                 hctsiz |= TSIZ_DOPNG;
1936
1937         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1938                 dwc2_set_pid_isoc(chan);
1939
1940         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1941         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1942                   TSIZ_SC_MC_PID_MASK;
1943
1944         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1945         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1946
1947         /* Non-zero only for high-speed interrupt endpoints */
1948         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1949
1950         if (dbg_hc(chan)) {
1951                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1952                          chan->hc_num);
1953                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1954                          chan->data_pid_start);
1955                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1956         }
1957
1958         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1959
1960         dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1961                                    chan->desc_list_sz, DMA_TO_DEVICE);
1962
1963         dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1964
1965         if (dbg_hc(chan))
1966                 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1967                          &chan->desc_list_addr, chan->hc_num);
1968
1969         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1970         hcchar &= ~HCCHAR_MULTICNT_MASK;
1971         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1972                   HCCHAR_MULTICNT_MASK;
1973
1974         if (hcchar & HCCHAR_CHDIS)
1975                 dev_warn(hsotg->dev,
1976                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1977                          __func__, chan->hc_num, hcchar);
1978
1979         /* Set host channel enable after all other setup is complete */
1980         hcchar |= HCCHAR_CHENA;
1981         hcchar &= ~HCCHAR_CHDIS;
1982
1983         if (dbg_hc(chan))
1984                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1985                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1986                          HCCHAR_MULTICNT_SHIFT);
1987
1988         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1989         if (dbg_hc(chan))
1990                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1991                          chan->hc_num);
1992
1993         chan->xfer_started = 1;
1994         chan->requests++;
1995 }
1996
1997 /**
1998  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1999  * a previous call to dwc2_hc_start_transfer()
2000  *
2001  * @hsotg: Programming view of DWC_otg controller
2002  * @chan:  Information needed to initialize the host channel
2003  *
2004  * The caller must ensure there is sufficient space in the request queue and Tx
2005  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
2006  * the controller acts autonomously to complete transfers programmed to a host
2007  * channel.
2008  *
2009  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2010  * if there is any data remaining to be queued. For an IN transfer, another
2011  * data packet is always requested. For the SETUP phase of a control transfer,
2012  * this function does nothing.
2013  *
2014  * Return: 1 if a new request is queued, 0 if no more requests are required
2015  * for this transfer
2016  */
2017 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
2018                               struct dwc2_host_chan *chan)
2019 {
2020         if (dbg_hc(chan))
2021                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2022                          chan->hc_num);
2023
2024         if (chan->do_split)
2025                 /* SPLITs always queue just once per channel */
2026                 return 0;
2027
2028         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
2029                 /* SETUPs are queued only once since they can't be NAK'd */
2030                 return 0;
2031
2032         if (chan->ep_is_in) {
2033                 /*
2034                  * Always queue another request for other IN transfers. If
2035                  * back-to-back INs are issued and NAKs are received for both,
2036                  * the driver may still be processing the first NAK when the
2037                  * second NAK is received. When the interrupt handler clears
2038                  * the NAK interrupt for the first NAK, the second NAK will
2039                  * not be seen. So we can't depend on the NAK interrupt
2040                  * handler to requeue a NAK'd request. Instead, IN requests
2041                  * are issued each time this function is called. When the
2042                  * transfer completes, the extra requests for the channel will
2043                  * be flushed.
2044                  */
2045                 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2046
2047                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
2048                 hcchar |= HCCHAR_CHENA;
2049                 hcchar &= ~HCCHAR_CHDIS;
2050                 if (dbg_hc(chan))
2051                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
2052                                  hcchar);
2053                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2054                 chan->requests++;
2055                 return 1;
2056         }
2057
2058         /* OUT transfers */
2059
2060         if (chan->xfer_count < chan->xfer_len) {
2061                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2062                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2063                         u32 hcchar = dwc2_readl(hsotg->regs +
2064                                                 HCCHAR(chan->hc_num));
2065
2066                         dwc2_hc_set_even_odd_frame(hsotg, chan,
2067                                                    &hcchar);
2068                 }
2069
2070                 /* Load OUT packet into the appropriate Tx FIFO */
2071                 dwc2_hc_write_packet(hsotg, chan);
2072                 chan->requests++;
2073                 return 1;
2074         }
2075
2076         return 0;
2077 }
2078
2079 /**
2080  * dwc2_hc_do_ping() - Starts a PING transfer
2081  *
2082  * @hsotg: Programming view of DWC_otg controller
2083  * @chan:  Information needed to initialize the host channel
2084  *
2085  * This function should only be called in Slave mode. The Do Ping bit is set in
2086  * the HCTSIZ register, then the channel is enabled.
2087  */
2088 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
2089 {
2090         u32 hcchar;
2091         u32 hctsiz;
2092
2093         if (dbg_hc(chan))
2094                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2095                          chan->hc_num);
2096
2097
2098         hctsiz = TSIZ_DOPNG;
2099         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
2100         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
2101
2102         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2103         hcchar |= HCCHAR_CHENA;
2104         hcchar &= ~HCCHAR_CHDIS;
2105         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2106 }
2107
2108 /**
2109  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
2110  * the HFIR register according to PHY type and speed
2111  *
2112  * @hsotg: Programming view of DWC_otg controller
2113  *
2114  * NOTE: The caller can modify the value of the HFIR register only after the
2115  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
2116  * has been set
2117  */
2118 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
2119 {
2120         u32 usbcfg;
2121         u32 hprt0;
2122         int clock = 60; /* default value */
2123
2124         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2125         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2126
2127         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
2128             !(usbcfg & GUSBCFG_PHYIF16))
2129                 clock = 60;
2130         if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
2131             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
2132                 clock = 48;
2133         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2134             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2135                 clock = 30;
2136         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2137             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
2138                 clock = 60;
2139         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2140             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2141                 clock = 48;
2142         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
2143             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
2144                 clock = 48;
2145         if ((usbcfg & GUSBCFG_PHYSEL) &&
2146             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2147                 clock = 48;
2148
2149         if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
2150                 /* High speed case */
2151                 return 125 * clock;
2152         else
2153                 /* FS/LS case */
2154                 return 1000 * clock;
2155 }
2156
2157 /**
2158  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
2159  * buffer
2160  *
2161  * @core_if: Programming view of DWC_otg controller
2162  * @dest:    Destination buffer for the packet
2163  * @bytes:   Number of bytes to copy to the destination
2164  */
2165 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
2166 {
2167         u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
2168         u32 *data_buf = (u32 *)dest;
2169         int word_count = (bytes + 3) / 4;
2170         int i;
2171
2172         /*
2173          * Todo: Account for the case where dest is not dword aligned. This
2174          * requires reading data from the FIFO into a u32 temp buffer, then
2175          * moving it into the data buffer.
2176          */
2177
2178         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
2179
2180         for (i = 0; i < word_count; i++, data_buf++)
2181                 *data_buf = dwc2_readl(fifo);
2182 }
2183
2184 /**
2185  * dwc2_dump_host_registers() - Prints the host registers
2186  *
2187  * @hsotg: Programming view of DWC_otg controller
2188  *
2189  * NOTE: This function will be removed once the peripheral controller code
2190  * is integrated and the driver is stable
2191  */
2192 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
2193 {
2194 #ifdef DEBUG
2195         u32 __iomem *addr;
2196         int i;
2197
2198         dev_dbg(hsotg->dev, "Host Global Registers\n");
2199         addr = hsotg->regs + HCFG;
2200         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
2201                 (unsigned long)addr, dwc2_readl(addr));
2202         addr = hsotg->regs + HFIR;
2203         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
2204                 (unsigned long)addr, dwc2_readl(addr));
2205         addr = hsotg->regs + HFNUM;
2206         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
2207                 (unsigned long)addr, dwc2_readl(addr));
2208         addr = hsotg->regs + HPTXSTS;
2209         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
2210                 (unsigned long)addr, dwc2_readl(addr));
2211         addr = hsotg->regs + HAINT;
2212         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
2213                 (unsigned long)addr, dwc2_readl(addr));
2214         addr = hsotg->regs + HAINTMSK;
2215         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
2216                 (unsigned long)addr, dwc2_readl(addr));
2217         if (hsotg->core_params->dma_desc_enable > 0) {
2218                 addr = hsotg->regs + HFLBADDR;
2219                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
2220                         (unsigned long)addr, dwc2_readl(addr));
2221         }
2222
2223         addr = hsotg->regs + HPRT0;
2224         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
2225                 (unsigned long)addr, dwc2_readl(addr));
2226
2227         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2228                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
2229                 addr = hsotg->regs + HCCHAR(i);
2230                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
2231                         (unsigned long)addr, dwc2_readl(addr));
2232                 addr = hsotg->regs + HCSPLT(i);
2233                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
2234                         (unsigned long)addr, dwc2_readl(addr));
2235                 addr = hsotg->regs + HCINT(i);
2236                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
2237                         (unsigned long)addr, dwc2_readl(addr));
2238                 addr = hsotg->regs + HCINTMSK(i);
2239                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
2240                         (unsigned long)addr, dwc2_readl(addr));
2241                 addr = hsotg->regs + HCTSIZ(i);
2242                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
2243                         (unsigned long)addr, dwc2_readl(addr));
2244                 addr = hsotg->regs + HCDMA(i);
2245                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
2246                         (unsigned long)addr, dwc2_readl(addr));
2247                 if (hsotg->core_params->dma_desc_enable > 0) {
2248                         addr = hsotg->regs + HCDMAB(i);
2249                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
2250                                 (unsigned long)addr, dwc2_readl(addr));
2251                 }
2252         }
2253 #endif
2254 }
2255
2256 /**
2257  * dwc2_dump_global_registers() - Prints the core global registers
2258  *
2259  * @hsotg: Programming view of DWC_otg controller
2260  *
2261  * NOTE: This function will be removed once the peripheral controller code
2262  * is integrated and the driver is stable
2263  */
2264 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
2265 {
2266 #ifdef DEBUG
2267         u32 __iomem *addr;
2268
2269         dev_dbg(hsotg->dev, "Core Global Registers\n");
2270         addr = hsotg->regs + GOTGCTL;
2271         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
2272                 (unsigned long)addr, dwc2_readl(addr));
2273         addr = hsotg->regs + GOTGINT;
2274         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
2275                 (unsigned long)addr, dwc2_readl(addr));
2276         addr = hsotg->regs + GAHBCFG;
2277         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
2278                 (unsigned long)addr, dwc2_readl(addr));
2279         addr = hsotg->regs + GUSBCFG;
2280         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
2281                 (unsigned long)addr, dwc2_readl(addr));
2282         addr = hsotg->regs + GRSTCTL;
2283         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
2284                 (unsigned long)addr, dwc2_readl(addr));
2285         addr = hsotg->regs + GINTSTS;
2286         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
2287                 (unsigned long)addr, dwc2_readl(addr));
2288         addr = hsotg->regs + GINTMSK;
2289         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
2290                 (unsigned long)addr, dwc2_readl(addr));
2291         addr = hsotg->regs + GRXSTSR;
2292         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
2293                 (unsigned long)addr, dwc2_readl(addr));
2294         addr = hsotg->regs + GRXFSIZ;
2295         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
2296                 (unsigned long)addr, dwc2_readl(addr));
2297         addr = hsotg->regs + GNPTXFSIZ;
2298         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
2299                 (unsigned long)addr, dwc2_readl(addr));
2300         addr = hsotg->regs + GNPTXSTS;
2301         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
2302                 (unsigned long)addr, dwc2_readl(addr));
2303         addr = hsotg->regs + GI2CCTL;
2304         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
2305                 (unsigned long)addr, dwc2_readl(addr));
2306         addr = hsotg->regs + GPVNDCTL;
2307         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
2308                 (unsigned long)addr, dwc2_readl(addr));
2309         addr = hsotg->regs + GGPIO;
2310         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
2311                 (unsigned long)addr, dwc2_readl(addr));
2312         addr = hsotg->regs + GUID;
2313         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
2314                 (unsigned long)addr, dwc2_readl(addr));
2315         addr = hsotg->regs + GSNPSID;
2316         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
2317                 (unsigned long)addr, dwc2_readl(addr));
2318         addr = hsotg->regs + GHWCFG1;
2319         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
2320                 (unsigned long)addr, dwc2_readl(addr));
2321         addr = hsotg->regs + GHWCFG2;
2322         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
2323                 (unsigned long)addr, dwc2_readl(addr));
2324         addr = hsotg->regs + GHWCFG3;
2325         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
2326                 (unsigned long)addr, dwc2_readl(addr));
2327         addr = hsotg->regs + GHWCFG4;
2328         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
2329                 (unsigned long)addr, dwc2_readl(addr));
2330         addr = hsotg->regs + GLPMCFG;
2331         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
2332                 (unsigned long)addr, dwc2_readl(addr));
2333         addr = hsotg->regs + GPWRDN;
2334         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
2335                 (unsigned long)addr, dwc2_readl(addr));
2336         addr = hsotg->regs + GDFIFOCFG;
2337         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
2338                 (unsigned long)addr, dwc2_readl(addr));
2339         addr = hsotg->regs + HPTXFSIZ;
2340         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
2341                 (unsigned long)addr, dwc2_readl(addr));
2342
2343         addr = hsotg->regs + PCGCTL;
2344         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
2345                 (unsigned long)addr, dwc2_readl(addr));
2346 #endif
2347 }
2348
2349 /**
2350  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
2351  *
2352  * @hsotg: Programming view of DWC_otg controller
2353  * @num:   Tx FIFO to flush
2354  */
2355 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
2356 {
2357         u32 greset;
2358         int count = 0;
2359
2360         dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
2361
2362         greset = GRSTCTL_TXFFLSH;
2363         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
2364         dwc2_writel(greset, hsotg->regs + GRSTCTL);
2365
2366         do {
2367                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2368                 if (++count > 10000) {
2369                         dev_warn(hsotg->dev,
2370                                  "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
2371                                  __func__, greset,
2372                                  dwc2_readl(hsotg->regs + GNPTXSTS));
2373                         break;
2374                 }
2375                 udelay(1);
2376         } while (greset & GRSTCTL_TXFFLSH);
2377
2378         /* Wait for at least 3 PHY Clocks */
2379         udelay(1);
2380 }
2381
2382 /**
2383  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
2384  *
2385  * @hsotg: Programming view of DWC_otg controller
2386  */
2387 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
2388 {
2389         u32 greset;
2390         int count = 0;
2391
2392         dev_vdbg(hsotg->dev, "%s()\n", __func__);
2393
2394         greset = GRSTCTL_RXFFLSH;
2395         dwc2_writel(greset, hsotg->regs + GRSTCTL);
2396
2397         do {
2398                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2399                 if (++count > 10000) {
2400                         dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
2401                                  __func__, greset);
2402                         break;
2403                 }
2404                 udelay(1);
2405         } while (greset & GRSTCTL_RXFFLSH);
2406
2407         /* Wait for at least 3 PHY Clocks */
2408         udelay(1);
2409 }
2410
2411 #define DWC2_OUT_OF_BOUNDS(a, b, c)     ((a) < (b) || (a) > (c))
2412
2413 /* Parameter access functions */
2414 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
2415 {
2416         int valid = 1;
2417
2418         switch (val) {
2419         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
2420                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
2421                         valid = 0;
2422                 break;
2423         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
2424                 switch (hsotg->hw_params.op_mode) {
2425                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2426                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2427                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2428                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2429                         break;
2430                 default:
2431                         valid = 0;
2432                         break;
2433                 }
2434                 break;
2435         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
2436                 /* always valid */
2437                 break;
2438         default:
2439                 valid = 0;
2440                 break;
2441         }
2442
2443         if (!valid) {
2444                 if (val >= 0)
2445                         dev_err(hsotg->dev,
2446                                 "%d invalid for otg_cap parameter. Check HW configuration.\n",
2447                                 val);
2448                 switch (hsotg->hw_params.op_mode) {
2449                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2450                         val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
2451                         break;
2452                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2453                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2454                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2455                         val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2456                         break;
2457                 default:
2458                         val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2459                         break;
2460                 }
2461                 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2462         }
2463
2464         hsotg->core_params->otg_cap = val;
2465 }
2466
2467 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2468 {
2469         int valid = 1;
2470
2471         if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
2472                 valid = 0;
2473         if (val < 0)
2474                 valid = 0;
2475
2476         if (!valid) {
2477                 if (val >= 0)
2478                         dev_err(hsotg->dev,
2479                                 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2480                                 val);
2481                 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
2482                 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2483         }
2484
2485         hsotg->core_params->dma_enable = val;
2486 }
2487
2488 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2489 {
2490         int valid = 1;
2491
2492         if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2493                         !hsotg->hw_params.dma_desc_enable))
2494                 valid = 0;
2495         if (val < 0)
2496                 valid = 0;
2497
2498         if (!valid) {
2499                 if (val >= 0)
2500                         dev_err(hsotg->dev,
2501                                 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2502                                 val);
2503                 val = (hsotg->core_params->dma_enable > 0 &&
2504                         hsotg->hw_params.dma_desc_enable);
2505                 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2506         }
2507
2508         hsotg->core_params->dma_desc_enable = val;
2509 }
2510
2511 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
2512 {
2513         int valid = 1;
2514
2515         if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2516                         !hsotg->hw_params.dma_desc_enable))
2517                 valid = 0;
2518         if (val < 0)
2519                 valid = 0;
2520
2521         if (!valid) {
2522                 if (val >= 0)
2523                         dev_err(hsotg->dev,
2524                                 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
2525                                 val);
2526                 val = (hsotg->core_params->dma_enable > 0 &&
2527                         hsotg->hw_params.dma_desc_enable);
2528         }
2529
2530         hsotg->core_params->dma_desc_fs_enable = val;
2531         dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
2532 }
2533
2534 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2535                                                  int val)
2536 {
2537         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2538                 if (val >= 0) {
2539                         dev_err(hsotg->dev,
2540                                 "Wrong value for host_support_fs_low_power\n");
2541                         dev_err(hsotg->dev,
2542                                 "host_support_fs_low_power must be 0 or 1\n");
2543                 }
2544                 val = 0;
2545                 dev_dbg(hsotg->dev,
2546                         "Setting host_support_fs_low_power to %d\n", val);
2547         }
2548
2549         hsotg->core_params->host_support_fs_ls_low_power = val;
2550 }
2551
2552 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2553 {
2554         int valid = 1;
2555
2556         if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
2557                 valid = 0;
2558         if (val < 0)
2559                 valid = 0;
2560
2561         if (!valid) {
2562                 if (val >= 0)
2563                         dev_err(hsotg->dev,
2564                                 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2565                                 val);
2566                 val = hsotg->hw_params.enable_dynamic_fifo;
2567                 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2568         }
2569
2570         hsotg->core_params->enable_dynamic_fifo = val;
2571 }
2572
2573 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2574 {
2575         int valid = 1;
2576
2577         if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
2578                 valid = 0;
2579
2580         if (!valid) {
2581                 if (val >= 0)
2582                         dev_err(hsotg->dev,
2583                                 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2584                                 val);
2585                 val = hsotg->hw_params.host_rx_fifo_size;
2586                 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2587         }
2588
2589         hsotg->core_params->host_rx_fifo_size = val;
2590 }
2591
2592 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2593 {
2594         int valid = 1;
2595
2596         if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
2597                 valid = 0;
2598
2599         if (!valid) {
2600                 if (val >= 0)
2601                         dev_err(hsotg->dev,
2602                                 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2603                                 val);
2604                 val = hsotg->hw_params.host_nperio_tx_fifo_size;
2605                 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2606                         val);
2607         }
2608
2609         hsotg->core_params->host_nperio_tx_fifo_size = val;
2610 }
2611
2612 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2613 {
2614         int valid = 1;
2615
2616         if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
2617                 valid = 0;
2618
2619         if (!valid) {
2620                 if (val >= 0)
2621                         dev_err(hsotg->dev,
2622                                 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2623                                 val);
2624                 val = hsotg->hw_params.host_perio_tx_fifo_size;
2625                 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2626                         val);
2627         }
2628
2629         hsotg->core_params->host_perio_tx_fifo_size = val;
2630 }
2631
2632 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2633 {
2634         int valid = 1;
2635
2636         if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
2637                 valid = 0;
2638
2639         if (!valid) {
2640                 if (val >= 0)
2641                         dev_err(hsotg->dev,
2642                                 "%d invalid for max_transfer_size. Check HW configuration.\n",
2643                                 val);
2644                 val = hsotg->hw_params.max_transfer_size;
2645                 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2646         }
2647
2648         hsotg->core_params->max_transfer_size = val;
2649 }
2650
2651 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2652 {
2653         int valid = 1;
2654
2655         if (val < 15 || val > hsotg->hw_params.max_packet_count)
2656                 valid = 0;
2657
2658         if (!valid) {
2659                 if (val >= 0)
2660                         dev_err(hsotg->dev,
2661                                 "%d invalid for max_packet_count. Check HW configuration.\n",
2662                                 val);
2663                 val = hsotg->hw_params.max_packet_count;
2664                 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2665         }
2666
2667         hsotg->core_params->max_packet_count = val;
2668 }
2669
2670 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2671 {
2672         int valid = 1;
2673
2674         if (val < 1 || val > hsotg->hw_params.host_channels)
2675                 valid = 0;
2676
2677         if (!valid) {
2678                 if (val >= 0)
2679                         dev_err(hsotg->dev,
2680                                 "%d invalid for host_channels. Check HW configuration.\n",
2681                                 val);
2682                 val = hsotg->hw_params.host_channels;
2683                 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2684         }
2685
2686         hsotg->core_params->host_channels = val;
2687 }
2688
2689 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2690 {
2691         int valid = 0;
2692         u32 hs_phy_type, fs_phy_type;
2693
2694         if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
2695                                DWC2_PHY_TYPE_PARAM_ULPI)) {
2696                 if (val >= 0) {
2697                         dev_err(hsotg->dev, "Wrong value for phy_type\n");
2698                         dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2699                 }
2700
2701                 valid = 0;
2702         }
2703
2704         hs_phy_type = hsotg->hw_params.hs_phy_type;
2705         fs_phy_type = hsotg->hw_params.fs_phy_type;
2706         if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2707             (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2708              hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2709                 valid = 1;
2710         else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2711                  (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2712                   hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2713                 valid = 1;
2714         else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2715                  fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2716                 valid = 1;
2717
2718         if (!valid) {
2719                 if (val >= 0)
2720                         dev_err(hsotg->dev,
2721                                 "%d invalid for phy_type. Check HW configuration.\n",
2722                                 val);
2723                 val = DWC2_PHY_TYPE_PARAM_FS;
2724                 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2725                         if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2726                             hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2727                                 val = DWC2_PHY_TYPE_PARAM_UTMI;
2728                         else
2729                                 val = DWC2_PHY_TYPE_PARAM_ULPI;
2730                 }
2731                 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2732         }
2733
2734         hsotg->core_params->phy_type = val;
2735 }
2736
2737 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2738 {
2739         return hsotg->core_params->phy_type;
2740 }
2741
2742 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2743 {
2744         int valid = 1;
2745
2746         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2747                 if (val >= 0) {
2748                         dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2749                         dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2750                 }
2751                 valid = 0;
2752         }
2753
2754         if (val == DWC2_SPEED_PARAM_HIGH &&
2755             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2756                 valid = 0;
2757
2758         if (!valid) {
2759                 if (val >= 0)
2760                         dev_err(hsotg->dev,
2761                                 "%d invalid for speed parameter. Check HW configuration.\n",
2762                                 val);
2763                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2764                                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2765                 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2766         }
2767
2768         hsotg->core_params->speed = val;
2769 }
2770
2771 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2772 {
2773         int valid = 1;
2774
2775         if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2776                                DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2777                 if (val >= 0) {
2778                         dev_err(hsotg->dev,
2779                                 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2780                         dev_err(hsotg->dev,
2781                                 "host_ls_low_power_phy_clk must be 0 or 1\n");
2782                 }
2783                 valid = 0;
2784         }
2785
2786         if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2787             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2788                 valid = 0;
2789
2790         if (!valid) {
2791                 if (val >= 0)
2792                         dev_err(hsotg->dev,
2793                                 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2794                                 val);
2795                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2796                         ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2797                         : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2798                 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2799                         val);
2800         }
2801
2802         hsotg->core_params->host_ls_low_power_phy_clk = val;
2803 }
2804
2805 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2806 {
2807         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2808                 if (val >= 0) {
2809                         dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2810                         dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2811                 }
2812                 val = 0;
2813                 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2814         }
2815
2816         hsotg->core_params->phy_ulpi_ddr = val;
2817 }
2818
2819 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2820 {
2821         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2822                 if (val >= 0) {
2823                         dev_err(hsotg->dev,
2824                                 "Wrong value for phy_ulpi_ext_vbus\n");
2825                         dev_err(hsotg->dev,
2826                                 "phy_ulpi_ext_vbus must be 0 or 1\n");
2827                 }
2828                 val = 0;
2829                 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2830         }
2831
2832         hsotg->core_params->phy_ulpi_ext_vbus = val;
2833 }
2834
2835 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2836 {
2837         int valid = 0;
2838
2839         switch (hsotg->hw_params.utmi_phy_data_width) {
2840         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
2841                 valid = (val == 8);
2842                 break;
2843         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
2844                 valid = (val == 16);
2845                 break;
2846         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
2847                 valid = (val == 8 || val == 16);
2848                 break;
2849         }
2850
2851         if (!valid) {
2852                 if (val >= 0) {
2853                         dev_err(hsotg->dev,
2854                                 "%d invalid for phy_utmi_width. Check HW configuration.\n",
2855                                 val);
2856                 }
2857                 val = (hsotg->hw_params.utmi_phy_data_width ==
2858                        GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
2859                 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2860         }
2861
2862         hsotg->core_params->phy_utmi_width = val;
2863 }
2864
2865 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2866 {
2867         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2868                 if (val >= 0) {
2869                         dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2870                         dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2871                 }
2872                 val = 0;
2873                 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2874         }
2875
2876         hsotg->core_params->ulpi_fs_ls = val;
2877 }
2878
2879 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2880 {
2881         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2882                 if (val >= 0) {
2883                         dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2884                         dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2885                 }
2886                 val = 0;
2887                 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2888         }
2889
2890         hsotg->core_params->ts_dline = val;
2891 }
2892
2893 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2894 {
2895         int valid = 1;
2896
2897         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2898                 if (val >= 0) {
2899                         dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2900                         dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2901                 }
2902
2903                 valid = 0;
2904         }
2905
2906         if (val == 1 && !(hsotg->hw_params.i2c_enable))
2907                 valid = 0;
2908
2909         if (!valid) {
2910                 if (val >= 0)
2911                         dev_err(hsotg->dev,
2912                                 "%d invalid for i2c_enable. Check HW configuration.\n",
2913                                 val);
2914                 val = hsotg->hw_params.i2c_enable;
2915                 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2916         }
2917
2918         hsotg->core_params->i2c_enable = val;
2919 }
2920
2921 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2922 {
2923         int valid = 1;
2924
2925         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2926                 if (val >= 0) {
2927                         dev_err(hsotg->dev,
2928                                 "Wrong value for en_multiple_tx_fifo,\n");
2929                         dev_err(hsotg->dev,
2930                                 "en_multiple_tx_fifo must be 0 or 1\n");
2931                 }
2932                 valid = 0;
2933         }
2934
2935         if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
2936                 valid = 0;
2937
2938         if (!valid) {
2939                 if (val >= 0)
2940                         dev_err(hsotg->dev,
2941                                 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2942                                 val);
2943                 val = hsotg->hw_params.en_multiple_tx_fifo;
2944                 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2945         }
2946
2947         hsotg->core_params->en_multiple_tx_fifo = val;
2948 }
2949
2950 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2951 {
2952         int valid = 1;
2953
2954         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2955                 if (val >= 0) {
2956                         dev_err(hsotg->dev,
2957                                 "'%d' invalid for parameter reload_ctl\n", val);
2958                         dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2959                 }
2960                 valid = 0;
2961         }
2962
2963         if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
2964                 valid = 0;
2965
2966         if (!valid) {
2967                 if (val >= 0)
2968                         dev_err(hsotg->dev,
2969                                 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2970                                 val);
2971                 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
2972                 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2973         }
2974
2975         hsotg->core_params->reload_ctl = val;
2976 }
2977
2978 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
2979 {
2980         if (val != -1)
2981                 hsotg->core_params->ahbcfg = val;
2982         else
2983                 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
2984                                                 GAHBCFG_HBSTLEN_SHIFT;
2985 }
2986
2987 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2988 {
2989         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2990                 if (val >= 0) {
2991                         dev_err(hsotg->dev,
2992                                 "'%d' invalid for parameter otg_ver\n", val);
2993                         dev_err(hsotg->dev,
2994                                 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2995                 }
2996                 val = 0;
2997                 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2998         }
2999
3000         hsotg->core_params->otg_ver = val;
3001 }
3002
3003 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
3004 {
3005         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3006                 if (val >= 0) {
3007                         dev_err(hsotg->dev,
3008                                 "'%d' invalid for parameter uframe_sched\n",
3009                                 val);
3010                         dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
3011                 }
3012                 val = 1;
3013                 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
3014         }
3015
3016         hsotg->core_params->uframe_sched = val;
3017 }
3018
3019 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
3020                 int val)
3021 {
3022         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3023                 if (val >= 0) {
3024                         dev_err(hsotg->dev,
3025                                 "'%d' invalid for parameter external_id_pin_ctl\n",
3026                                 val);
3027                         dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
3028                 }
3029                 val = 0;
3030                 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
3031         }
3032
3033         hsotg->core_params->external_id_pin_ctl = val;
3034 }
3035
3036 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
3037                 int val)
3038 {
3039         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3040                 if (val >= 0) {
3041                         dev_err(hsotg->dev,
3042                                 "'%d' invalid for parameter hibernation\n",
3043                                 val);
3044                         dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
3045                 }
3046                 val = 0;
3047                 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
3048         }
3049
3050         hsotg->core_params->hibernation = val;
3051 }
3052
3053 /*
3054  * This function is called during module intialization to pass module parameters
3055  * for the DWC_otg core.
3056  */
3057 void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
3058                          const struct dwc2_core_params *params)
3059 {
3060         dev_dbg(hsotg->dev, "%s()\n", __func__);
3061
3062         dwc2_set_param_otg_cap(hsotg, params->otg_cap);
3063         dwc2_set_param_dma_enable(hsotg, params->dma_enable);
3064         dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
3065         dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
3066         dwc2_set_param_host_support_fs_ls_low_power(hsotg,
3067                         params->host_support_fs_ls_low_power);
3068         dwc2_set_param_enable_dynamic_fifo(hsotg,
3069                         params->enable_dynamic_fifo);
3070         dwc2_set_param_host_rx_fifo_size(hsotg,
3071                         params->host_rx_fifo_size);
3072         dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
3073                         params->host_nperio_tx_fifo_size);
3074         dwc2_set_param_host_perio_tx_fifo_size(hsotg,
3075                         params->host_perio_tx_fifo_size);
3076         dwc2_set_param_max_transfer_size(hsotg,
3077                         params->max_transfer_size);
3078         dwc2_set_param_max_packet_count(hsotg,
3079                         params->max_packet_count);
3080         dwc2_set_param_host_channels(hsotg, params->host_channels);
3081         dwc2_set_param_phy_type(hsotg, params->phy_type);
3082         dwc2_set_param_speed(hsotg, params->speed);
3083         dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
3084                         params->host_ls_low_power_phy_clk);
3085         dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
3086         dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
3087                         params->phy_ulpi_ext_vbus);
3088         dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
3089         dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
3090         dwc2_set_param_ts_dline(hsotg, params->ts_dline);
3091         dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
3092         dwc2_set_param_en_multiple_tx_fifo(hsotg,
3093                         params->en_multiple_tx_fifo);
3094         dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
3095         dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
3096         dwc2_set_param_otg_ver(hsotg, params->otg_ver);
3097         dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
3098         dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
3099         dwc2_set_param_hibernation(hsotg, params->hibernation);
3100 }
3101
3102 /**
3103  * During device initialization, read various hardware configuration
3104  * registers and interpret the contents.
3105  */
3106 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
3107 {
3108         struct dwc2_hw_params *hw = &hsotg->hw_params;
3109         unsigned width;
3110         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
3111         u32 hptxfsiz, grxfsiz, gnptxfsiz;
3112         u32 gusbcfg = 0;
3113
3114         /*
3115          * Attempt to ensure this device is really a DWC_otg Controller.
3116          * Read and verify the GSNPSID register contents. The value should be
3117          * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
3118          * as in "OTG version 2.xx" or "OTG version 3.xx".
3119          */
3120         hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
3121         if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
3122             (hw->snpsid & 0xfffff000) != 0x4f543000) {
3123                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
3124                         hw->snpsid);
3125                 return -ENODEV;
3126         }
3127
3128         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
3129                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
3130                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
3131
3132         hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
3133         hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
3134         hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
3135         hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
3136         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
3137
3138         dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
3139         dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
3140         dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
3141         dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
3142         dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
3143
3144         /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
3145         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3146                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3147                 dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
3148                             hsotg->regs + GUSBCFG);
3149                 usleep_range(25000, 50000);
3150         }
3151
3152         gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
3153         hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
3154         dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
3155         dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
3156         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3157                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
3158                 usleep_range(25000, 50000);
3159         }
3160
3161         /* hwcfg2 */
3162         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
3163                       GHWCFG2_OP_MODE_SHIFT;
3164         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
3165                    GHWCFG2_ARCHITECTURE_SHIFT;
3166         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
3167         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
3168                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
3169         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
3170                           GHWCFG2_HS_PHY_TYPE_SHIFT;
3171         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
3172                           GHWCFG2_FS_PHY_TYPE_SHIFT;
3173         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
3174                          GHWCFG2_NUM_DEV_EP_SHIFT;
3175         hw->nperio_tx_q_depth =
3176                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
3177                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
3178         hw->host_perio_tx_q_depth =
3179                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
3180                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
3181         hw->dev_token_q_depth =
3182                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
3183                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
3184
3185         /* hwcfg3 */
3186         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
3187                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
3188         hw->max_transfer_size = (1 << (width + 11)) - 1;
3189         /*
3190          * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates
3191          * coherent buffers with this size, and if it's too large we can
3192          * exhaust the coherent DMA pool.
3193          */
3194         if (hw->max_transfer_size > 65535)
3195                 hw->max_transfer_size = 65535;
3196         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
3197                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
3198         hw->max_packet_count = (1 << (width + 4)) - 1;
3199         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
3200         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
3201                               GHWCFG3_DFIFO_DEPTH_SHIFT;
3202
3203         /* hwcfg4 */
3204         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
3205         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
3206                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
3207         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
3208         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
3209         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
3210                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
3211
3212         /* fifo sizes */
3213         hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
3214                                 GRXFSIZ_DEPTH_SHIFT;
3215         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3216                                        FIFOSIZE_DEPTH_SHIFT;
3217         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3218                                       FIFOSIZE_DEPTH_SHIFT;
3219
3220         dev_dbg(hsotg->dev, "Detected values from hardware:\n");
3221         dev_dbg(hsotg->dev, "  op_mode=%d\n",
3222                 hw->op_mode);
3223         dev_dbg(hsotg->dev, "  arch=%d\n",
3224                 hw->arch);
3225         dev_dbg(hsotg->dev, "  dma_desc_enable=%d\n",
3226                 hw->dma_desc_enable);
3227         dev_dbg(hsotg->dev, "  power_optimized=%d\n",
3228                 hw->power_optimized);
3229         dev_dbg(hsotg->dev, "  i2c_enable=%d\n",
3230                 hw->i2c_enable);
3231         dev_dbg(hsotg->dev, "  hs_phy_type=%d\n",
3232                 hw->hs_phy_type);
3233         dev_dbg(hsotg->dev, "  fs_phy_type=%d\n",
3234                 hw->fs_phy_type);
3235         dev_dbg(hsotg->dev, "  utmi_phy_data_width=%d\n",
3236                 hw->utmi_phy_data_width);
3237         dev_dbg(hsotg->dev, "  num_dev_ep=%d\n",
3238                 hw->num_dev_ep);
3239         dev_dbg(hsotg->dev, "  num_dev_perio_in_ep=%d\n",
3240                 hw->num_dev_perio_in_ep);
3241         dev_dbg(hsotg->dev, "  host_channels=%d\n",
3242                 hw->host_channels);
3243         dev_dbg(hsotg->dev, "  max_transfer_size=%d\n",
3244                 hw->max_transfer_size);
3245         dev_dbg(hsotg->dev, "  max_packet_count=%d\n",
3246                 hw->max_packet_count);
3247         dev_dbg(hsotg->dev, "  nperio_tx_q_depth=0x%0x\n",
3248                 hw->nperio_tx_q_depth);
3249         dev_dbg(hsotg->dev, "  host_perio_tx_q_depth=0x%0x\n",
3250                 hw->host_perio_tx_q_depth);
3251         dev_dbg(hsotg->dev, "  dev_token_q_depth=0x%0x\n",
3252                 hw->dev_token_q_depth);
3253         dev_dbg(hsotg->dev, "  enable_dynamic_fifo=%d\n",
3254                 hw->enable_dynamic_fifo);
3255         dev_dbg(hsotg->dev, "  en_multiple_tx_fifo=%d\n",
3256                 hw->en_multiple_tx_fifo);
3257         dev_dbg(hsotg->dev, "  total_fifo_size=%d\n",
3258                 hw->total_fifo_size);
3259         dev_dbg(hsotg->dev, "  host_rx_fifo_size=%d\n",
3260                 hw->host_rx_fifo_size);
3261         dev_dbg(hsotg->dev, "  host_nperio_tx_fifo_size=%d\n",
3262                 hw->host_nperio_tx_fifo_size);
3263         dev_dbg(hsotg->dev, "  host_perio_tx_fifo_size=%d\n",
3264                 hw->host_perio_tx_fifo_size);
3265         dev_dbg(hsotg->dev, "\n");
3266
3267         return 0;
3268 }
3269
3270 /*
3271  * Sets all parameters to the given value.
3272  *
3273  * Assumes that the dwc2_core_params struct contains only integers.
3274  */
3275 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
3276 {
3277         int *p = (int *)params;
3278         size_t size = sizeof(*params) / sizeof(*p);
3279         int i;
3280
3281         for (i = 0; i < size; i++)
3282                 p[i] = value;
3283 }
3284
3285
3286 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
3287 {
3288         return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
3289 }
3290
3291 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
3292 {
3293         if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
3294                 return false;
3295         else
3296                 return true;
3297 }
3298
3299 /**
3300  * dwc2_enable_global_interrupts() - Enables the controller's Global
3301  * Interrupt in the AHB Config register
3302  *
3303  * @hsotg: Programming view of DWC_otg controller
3304  */
3305 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
3306 {
3307         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3308
3309         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
3310         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3311 }
3312
3313 /**
3314  * dwc2_disable_global_interrupts() - Disables the controller's Global
3315  * Interrupt in the AHB Config register
3316  *
3317  * @hsotg: Programming view of DWC_otg controller
3318  */
3319 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
3320 {
3321         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3322
3323         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
3324         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3325 }
3326
3327 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
3328 MODULE_AUTHOR("Synopsys, Inc.");
3329 MODULE_LICENSE("Dual BSD/GPL");