2 * core.c - DesignWare HS OTG Controller common routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
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17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * The Core code provides basic services for accessing and managing the
39 * DWC_otg hardware. These services are used by both the Host Controller
40 * Driver and the Peripheral Controller Driver.
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/moduleparam.h>
45 #include <linux/spinlock.h>
46 #include <linux/interrupt.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
61 * dwc2_backup_host_registers() - Backup controller host registers.
62 * When suspending usb bus, registers needs to be backuped
63 * if controller power is disabled once suspended.
65 * @hsotg: Programming view of the DWC_otg controller
67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
69 struct dwc2_hregs_backup *hr;
72 dev_dbg(hsotg->dev, "%s\n", __func__);
74 /* Backup Host regs */
75 hr = &hsotg->hr_backup;
76 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
77 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
78 for (i = 0; i < hsotg->core_params->host_channels; ++i)
79 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
81 hr->hprt0 = dwc2_read_hprt0(hsotg);
82 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
89 * dwc2_restore_host_registers() - Restore controller host registers.
90 * When resuming usb bus, device registers needs to be restored
91 * if controller power were disabled.
93 * @hsotg: Programming view of the DWC_otg controller
95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
97 struct dwc2_hregs_backup *hr;
100 dev_dbg(hsotg->dev, "%s\n", __func__);
102 /* Restore host regs */
103 hr = &hsotg->hr_backup;
105 dev_err(hsotg->dev, "%s: no host registers to restore\n",
111 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
112 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
114 for (i = 0; i < hsotg->core_params->host_channels; ++i)
115 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
117 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
118 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
119 hsotg->frame_number = 0;
124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
131 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
132 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
134 * dwc2_backup_device_registers() - Backup controller device registers.
135 * When suspending usb bus, registers needs to be backuped
136 * if controller power is disabled once suspended.
138 * @hsotg: Programming view of the DWC_otg controller
140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
142 struct dwc2_dregs_backup *dr;
145 dev_dbg(hsotg->dev, "%s\n", __func__);
147 /* Backup dev regs */
148 dr = &hsotg->dr_backup;
150 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
151 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
152 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
153 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
154 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
156 for (i = 0; i < hsotg->num_of_eps; i++) {
158 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
160 /* Ensure DATA PID is correctly configured */
161 if (dr->diepctl[i] & DXEPCTL_DPID)
162 dr->diepctl[i] |= DXEPCTL_SETD1PID;
164 dr->diepctl[i] |= DXEPCTL_SETD0PID;
166 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
167 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
170 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
172 /* Ensure DATA PID is correctly configured */
173 if (dr->doepctl[i] & DXEPCTL_DPID)
174 dr->doepctl[i] |= DXEPCTL_SETD1PID;
176 dr->doepctl[i] |= DXEPCTL_SETD0PID;
178 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
179 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
186 * dwc2_restore_device_registers() - Restore controller device registers.
187 * When resuming usb bus, device registers needs to be restored
188 * if controller power were disabled.
190 * @hsotg: Programming view of the DWC_otg controller
192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
194 struct dwc2_dregs_backup *dr;
198 dev_dbg(hsotg->dev, "%s\n", __func__);
200 /* Restore dev regs */
201 dr = &hsotg->dr_backup;
203 dev_err(hsotg->dev, "%s: no device registers to restore\n",
209 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
210 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
211 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
212 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
213 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
215 for (i = 0; i < hsotg->num_of_eps; i++) {
217 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
218 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
219 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
221 /* Restore OUT EPs */
222 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
223 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
224 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
227 /* Set the Power-On Programming done bit */
228 dctl = dwc2_readl(hsotg->regs + DCTL);
229 dctl |= DCTL_PWRONPRGDONE;
230 dwc2_writel(dctl, hsotg->regs + DCTL);
235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
243 * dwc2_backup_global_registers() - Backup global controller registers.
244 * When suspending usb bus, registers needs to be backuped
245 * if controller power is disabled once suspended.
247 * @hsotg: Programming view of the DWC_otg controller
249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
251 struct dwc2_gregs_backup *gr;
254 /* Backup global regs */
255 gr = &hsotg->gr_backup;
257 gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
258 gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
259 gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
260 gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
261 gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
262 gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
263 gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
264 gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
265 for (i = 0; i < MAX_EPS_CHANNELS; i++)
266 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
273 * dwc2_restore_global_registers() - Restore controller global registers.
274 * When resuming usb bus, device registers needs to be restored
275 * if controller power were disabled.
277 * @hsotg: Programming view of the DWC_otg controller
279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
281 struct dwc2_gregs_backup *gr;
284 dev_dbg(hsotg->dev, "%s\n", __func__);
286 /* Restore global regs */
287 gr = &hsotg->gr_backup;
289 dev_err(hsotg->dev, "%s: no global registers to restore\n",
295 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
296 dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
297 dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
298 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
299 dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
300 dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
301 dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
302 dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
303 dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
304 for (i = 0; i < MAX_EPS_CHANNELS; i++)
305 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
311 * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
313 * @hsotg: Programming view of the DWC_otg controller
314 * @restore: Controller registers need to be restored
316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
321 if (!hsotg->core_params->hibernation)
324 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
325 pcgcctl &= ~PCGCTL_STOPPCLK;
326 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
328 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
329 pcgcctl &= ~PCGCTL_PWRCLMP;
330 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
332 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
333 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
334 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
338 ret = dwc2_restore_global_registers(hsotg);
340 dev_err(hsotg->dev, "%s: failed to restore registers\n",
344 if (dwc2_is_host_mode(hsotg)) {
345 ret = dwc2_restore_host_registers(hsotg);
347 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
352 ret = dwc2_restore_device_registers(hsotg);
354 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
365 * dwc2_enter_hibernation() - Put controller in Partial Power Down.
367 * @hsotg: Programming view of the DWC_otg controller
369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
374 if (!hsotg->core_params->hibernation)
377 /* Backup all registers */
378 ret = dwc2_backup_global_registers(hsotg);
380 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
385 if (dwc2_is_host_mode(hsotg)) {
386 ret = dwc2_backup_host_registers(hsotg);
388 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
393 ret = dwc2_backup_device_registers(hsotg);
395 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
402 * Clear any pending interrupts since dwc2 will not be able to
403 * clear them after entering hibernation.
405 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
407 /* Put the controller in low power state */
408 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
410 pcgcctl |= PCGCTL_PWRCLMP;
411 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
414 pcgcctl |= PCGCTL_RSTPDWNMODULE;
415 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
418 pcgcctl |= PCGCTL_STOPPCLK;
419 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
425 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
426 * used in both device and host modes
428 * @hsotg: Programming view of the DWC_otg controller
430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
434 /* Clear any pending OTG Interrupts */
435 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
437 /* Clear any pending interrupts */
438 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
440 /* Enable the interrupts in the GINTMSK */
441 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
443 if (hsotg->core_params->dma_enable <= 0)
444 intmsk |= GINTSTS_RXFLVL;
445 if (hsotg->core_params->external_id_pin_ctl <= 0)
446 intmsk |= GINTSTS_CONIDSTSCHNG;
448 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
451 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
455 * Initializes the FSLSPClkSel field of the HCFG register depending on the
458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
462 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
463 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
464 hsotg->core_params->ulpi_fs_ls > 0) ||
465 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
467 val = HCFG_FSLSPCLKSEL_48_MHZ;
469 /* High speed PHY running at full speed or high speed */
470 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
473 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
474 hcfg = dwc2_readl(hsotg->regs + HCFG);
475 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
476 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
477 dwc2_writel(hcfg, hsotg->regs + HCFG);
481 * Do core a soft reset of the core. Be careful with this because it
482 * resets all the internal state machines of the core.
484 int dwc2_core_reset(struct dwc2_hsotg *hsotg)
490 dev_vdbg(hsotg->dev, "%s()\n", __func__);
492 /* Core Soft Reset */
493 greset = dwc2_readl(hsotg->regs + GRSTCTL);
494 greset |= GRSTCTL_CSFTRST;
495 dwc2_writel(greset, hsotg->regs + GRSTCTL);
498 greset = dwc2_readl(hsotg->regs + GRSTCTL);
501 "%s() HANG! Soft Reset GRSTCTL=%0x\n",
505 } while (greset & GRSTCTL_CSFTRST);
507 /* Wait for AHB master IDLE state */
511 greset = dwc2_readl(hsotg->regs + GRSTCTL);
514 "%s() HANG! AHB Idle GRSTCTL=%0x\n",
518 } while (!(greset & GRSTCTL_AHBIDLE));
520 if (hsotg->dr_mode == USB_DR_MODE_HOST) {
521 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
522 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
523 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
524 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
525 } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
526 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
527 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
528 gusbcfg |= GUSBCFG_FORCEDEVMODE;
529 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
530 } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
531 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
532 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
533 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
534 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
538 * NOTE: This long sleep is _very_ important, otherwise the core will
539 * not stay in host mode after a connector ID change!
541 usleep_range(150000, 160000);
546 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
552 * core_init() is now called on every switch so only call the
553 * following for the first time through
556 dev_dbg(hsotg->dev, "FS PHY selected\n");
558 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
559 if (!(usbcfg & GUSBCFG_PHYSEL)) {
560 usbcfg |= GUSBCFG_PHYSEL;
561 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
563 /* Reset after a PHY select */
564 retval = dwc2_core_reset(hsotg);
568 "%s: Reset failed, aborting", __func__);
575 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
576 * do this on HNP Dev/Host mode switches (done in dev_init and
579 if (dwc2_is_host_mode(hsotg))
580 dwc2_init_fs_ls_pclk_sel(hsotg);
582 if (hsotg->core_params->i2c_enable > 0) {
583 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
585 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
586 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
587 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
588 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
590 /* Program GI2CCTL.I2CEn */
591 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
592 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
593 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
594 i2cctl &= ~GI2CCTL_I2CEN;
595 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
596 i2cctl |= GI2CCTL_I2CEN;
597 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
603 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
605 u32 usbcfg, usbcfg_old;
611 usbcfg = usbcfg_old = dwc2_readl(hsotg->regs + GUSBCFG);
614 * HS PHY parameters. These parameters are preserved during soft reset
615 * so only program the first time. Do a soft reset immediately after
618 switch (hsotg->core_params->phy_type) {
619 case DWC2_PHY_TYPE_PARAM_ULPI:
621 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
622 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
623 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
624 if (hsotg->core_params->phy_ulpi_ddr > 0)
625 usbcfg |= GUSBCFG_DDRSEL;
627 case DWC2_PHY_TYPE_PARAM_UTMI:
628 /* UTMI+ interface */
629 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
630 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
631 if (hsotg->core_params->phy_utmi_width == 16)
632 usbcfg |= GUSBCFG_PHYIF16;
635 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
639 if (usbcfg != usbcfg_old) {
640 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
642 /* Reset after setting the PHY parameters */
643 retval = dwc2_core_reset(hsotg);
646 "%s: Reset failed, aborting", __func__);
654 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
659 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
660 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
661 /* If FS mode with FS PHY */
662 retval = dwc2_fs_phy_init(hsotg, select_phy);
667 retval = dwc2_hs_phy_init(hsotg, select_phy);
672 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
673 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
674 hsotg->core_params->ulpi_fs_ls > 0) {
675 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
676 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
677 usbcfg |= GUSBCFG_ULPI_FS_LS;
678 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
679 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
681 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
682 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
683 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
684 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
690 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
692 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
694 switch (hsotg->hw_params.arch) {
695 case GHWCFG2_EXT_DMA_ARCH:
696 dev_err(hsotg->dev, "External DMA Mode not supported\n");
699 case GHWCFG2_INT_DMA_ARCH:
700 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
701 if (hsotg->core_params->ahbcfg != -1) {
702 ahbcfg &= GAHBCFG_CTRL_MASK;
703 ahbcfg |= hsotg->core_params->ahbcfg &
708 case GHWCFG2_SLAVE_ONLY_ARCH:
710 dev_dbg(hsotg->dev, "Slave Only Mode\n");
714 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
715 hsotg->core_params->dma_enable,
716 hsotg->core_params->dma_desc_enable);
718 if (hsotg->core_params->dma_enable > 0) {
719 if (hsotg->core_params->dma_desc_enable > 0)
720 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
722 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
724 dev_dbg(hsotg->dev, "Using Slave mode\n");
725 hsotg->core_params->dma_desc_enable = 0;
728 if (hsotg->core_params->dma_enable > 0)
729 ahbcfg |= GAHBCFG_DMA_EN;
731 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
736 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
740 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
741 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
743 switch (hsotg->hw_params.op_mode) {
744 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
745 if (hsotg->core_params->otg_cap ==
746 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
747 usbcfg |= GUSBCFG_HNPCAP;
748 if (hsotg->core_params->otg_cap !=
749 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
750 usbcfg |= GUSBCFG_SRPCAP;
753 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
754 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
755 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
756 if (hsotg->core_params->otg_cap !=
757 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
758 usbcfg |= GUSBCFG_SRPCAP;
761 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
762 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
763 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
768 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
772 * dwc2_core_init() - Initializes the DWC_otg controller registers and
773 * prepares the core for device mode or host mode operation
775 * @hsotg: Programming view of the DWC_otg controller
776 * @initial_setup: If true then this is the first init for this instance.
778 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
783 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
785 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
787 /* Set ULPI External VBUS bit if needed */
788 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
789 if (hsotg->core_params->phy_ulpi_ext_vbus ==
790 DWC2_PHY_ULPI_EXTERNAL_VBUS)
791 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
793 /* Set external TS Dline pulsing bit if needed */
794 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
795 if (hsotg->core_params->ts_dline > 0)
796 usbcfg |= GUSBCFG_TERMSELDLPULSE;
798 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
801 * Reset the Controller
803 * We only need to reset the controller if this is a re-init.
804 * For the first init we know for sure that earlier code reset us (it
805 * needed to in order to properly detect various parameters).
807 if (!initial_setup) {
808 retval = dwc2_core_reset(hsotg);
810 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
817 * This needs to happen in FS mode before any other programming occurs
819 retval = dwc2_phy_init(hsotg, initial_setup);
823 /* Program the GAHBCFG Register */
824 retval = dwc2_gahbcfg_init(hsotg);
828 /* Program the GUSBCFG register */
829 dwc2_gusbcfg_init(hsotg);
831 /* Program the GOTGCTL register */
832 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
833 otgctl &= ~GOTGCTL_OTGVER;
834 if (hsotg->core_params->otg_ver > 0)
835 otgctl |= GOTGCTL_OTGVER;
836 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
837 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
839 /* Clear the SRP success bit for FS-I2c */
840 hsotg->srp_success = 0;
842 /* Enable common interrupts */
843 dwc2_enable_common_interrupts(hsotg);
846 * Do device or host initialization based on mode during PCD and
849 if (dwc2_is_host_mode(hsotg)) {
850 dev_dbg(hsotg->dev, "Host Mode\n");
851 hsotg->op_state = OTG_STATE_A_HOST;
853 dev_dbg(hsotg->dev, "Device Mode\n");
854 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
861 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
863 * @hsotg: Programming view of DWC_otg controller
865 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
869 dev_dbg(hsotg->dev, "%s()\n", __func__);
871 /* Disable all interrupts */
872 dwc2_writel(0, hsotg->regs + GINTMSK);
873 dwc2_writel(0, hsotg->regs + HAINTMSK);
875 /* Enable the common interrupts */
876 dwc2_enable_common_interrupts(hsotg);
878 /* Enable host mode interrupts without disturbing common interrupts */
879 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
880 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
881 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
885 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
887 * @hsotg: Programming view of DWC_otg controller
889 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
891 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
893 /* Disable host mode interrupts without disturbing common interrupts */
894 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
895 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
896 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
900 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
901 * For system that have a total fifo depth that is smaller than the default
904 * @hsotg: Programming view of DWC_otg controller
906 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
908 struct dwc2_core_params *params = hsotg->core_params;
909 struct dwc2_hw_params *hw = &hsotg->hw_params;
910 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
912 total_fifo_size = hw->total_fifo_size;
913 rxfsiz = params->host_rx_fifo_size;
914 nptxfsiz = params->host_nperio_tx_fifo_size;
915 ptxfsiz = params->host_perio_tx_fifo_size;
918 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
919 * allocation with support for high bandwidth endpoints. Synopsys
920 * defines MPS(Max Packet size) for a periodic EP=1024, and for
921 * non-periodic as 512.
923 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
925 * For Buffer DMA mode/Scatter Gather DMA mode
926 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
927 * with n = number of host channel.
928 * 2 * ((1024/4) + 2) = 516
930 rxfsiz = 516 + hw->host_channels;
933 * min non-periodic tx fifo depth
934 * 2 * (largest non-periodic USB packet used / 4)
940 * min periodic tx fifo depth
941 * (largest packet size*MC)/4
946 params->host_rx_fifo_size = rxfsiz;
947 params->host_nperio_tx_fifo_size = nptxfsiz;
948 params->host_perio_tx_fifo_size = ptxfsiz;
952 * If the summation of RX, NPTX and PTX fifo sizes is still
953 * bigger than the total_fifo_size, then we have a problem.
955 * We won't be able to allocate as many endpoints. Right now,
956 * we're just printing an error message, but ideally this FIFO
957 * allocation algorithm would be improved in the future.
959 * FIXME improve this FIFO allocation algorithm.
961 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
962 dev_err(hsotg->dev, "invalid fifo sizes\n");
965 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
967 struct dwc2_core_params *params = hsotg->core_params;
968 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
970 if (!params->enable_dynamic_fifo)
973 dwc2_calculate_dynamic_fifo(hsotg);
976 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
977 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
978 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
979 grxfsiz |= params->host_rx_fifo_size <<
980 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
981 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
982 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
983 dwc2_readl(hsotg->regs + GRXFSIZ));
985 /* Non-periodic Tx FIFO */
986 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
987 dwc2_readl(hsotg->regs + GNPTXFSIZ));
988 nptxfsiz = params->host_nperio_tx_fifo_size <<
989 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
990 nptxfsiz |= params->host_rx_fifo_size <<
991 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
992 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
993 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
994 dwc2_readl(hsotg->regs + GNPTXFSIZ));
996 /* Periodic Tx FIFO */
997 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
998 dwc2_readl(hsotg->regs + HPTXFSIZ));
999 hptxfsiz = params->host_perio_tx_fifo_size <<
1000 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
1001 hptxfsiz |= (params->host_rx_fifo_size +
1002 params->host_nperio_tx_fifo_size) <<
1003 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
1004 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
1005 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
1006 dwc2_readl(hsotg->regs + HPTXFSIZ));
1008 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
1009 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
1011 * Global DFIFOCFG calculation for Host mode -
1012 * include RxFIFO, NPTXFIFO and HPTXFIFO
1014 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
1015 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
1016 dfifocfg |= (params->host_rx_fifo_size +
1017 params->host_nperio_tx_fifo_size +
1018 params->host_perio_tx_fifo_size) <<
1019 GDFIFOCFG_EPINFOBASE_SHIFT &
1020 GDFIFOCFG_EPINFOBASE_MASK;
1021 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
1026 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
1029 * @hsotg: Programming view of DWC_otg controller
1031 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
1032 * request queues. Host channels are reset to ensure that they are ready for
1033 * performing transfers.
1035 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
1037 u32 hcfg, hfir, otgctl;
1039 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
1041 /* Restart the Phy Clock */
1042 dwc2_writel(0, hsotg->regs + PCGCTL);
1044 /* Initialize Host Configuration Register */
1045 dwc2_init_fs_ls_pclk_sel(hsotg);
1046 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
1047 hcfg = dwc2_readl(hsotg->regs + HCFG);
1048 hcfg |= HCFG_FSLSSUPP;
1049 dwc2_writel(hcfg, hsotg->regs + HCFG);
1053 * This bit allows dynamic reloading of the HFIR register during
1054 * runtime. This bit needs to be programmed during initial configuration
1055 * and its value must not be changed during runtime.
1057 if (hsotg->core_params->reload_ctl > 0) {
1058 hfir = dwc2_readl(hsotg->regs + HFIR);
1059 hfir |= HFIR_RLDCTRL;
1060 dwc2_writel(hfir, hsotg->regs + HFIR);
1063 if (hsotg->core_params->dma_desc_enable > 0) {
1064 u32 op_mode = hsotg->hw_params.op_mode;
1065 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
1066 !hsotg->hw_params.dma_desc_enable ||
1067 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
1068 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
1069 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
1071 "Hardware does not support descriptor DMA mode -\n");
1073 "falling back to buffer DMA mode.\n");
1074 hsotg->core_params->dma_desc_enable = 0;
1076 hcfg = dwc2_readl(hsotg->regs + HCFG);
1077 hcfg |= HCFG_DESCDMA;
1078 dwc2_writel(hcfg, hsotg->regs + HCFG);
1082 /* Configure data FIFO sizes */
1083 dwc2_config_fifos(hsotg);
1085 /* TODO - check this */
1086 /* Clear Host Set HNP Enable in the OTG Control Register */
1087 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1088 otgctl &= ~GOTGCTL_HSTSETHNPEN;
1089 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1091 /* Make sure the FIFOs are flushed */
1092 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
1093 dwc2_flush_rx_fifo(hsotg);
1095 /* Clear Host Set HNP Enable in the OTG Control Register */
1096 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1097 otgctl &= ~GOTGCTL_HSTSETHNPEN;
1098 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1100 if (hsotg->core_params->dma_desc_enable <= 0) {
1101 int num_channels, i;
1104 /* Flush out any leftover queued requests */
1105 num_channels = hsotg->core_params->host_channels;
1106 for (i = 0; i < num_channels; i++) {
1107 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1108 hcchar &= ~HCCHAR_CHENA;
1109 hcchar |= HCCHAR_CHDIS;
1110 hcchar &= ~HCCHAR_EPDIR;
1111 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1114 /* Halt all channels to put them into a known state */
1115 for (i = 0; i < num_channels; i++) {
1118 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1119 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
1120 hcchar &= ~HCCHAR_EPDIR;
1121 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1122 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
1125 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1126 if (++count > 1000) {
1128 "Unable to clear enable on channel %d\n",
1133 } while (hcchar & HCCHAR_CHENA);
1137 /* Turn on the vbus power */
1138 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
1139 if (hsotg->op_state == OTG_STATE_A_HOST) {
1140 u32 hprt0 = dwc2_read_hprt0(hsotg);
1142 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
1143 !!(hprt0 & HPRT0_PWR));
1144 if (!(hprt0 & HPRT0_PWR)) {
1146 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1150 dwc2_enable_host_interrupts(hsotg);
1153 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
1154 struct dwc2_host_chan *chan)
1156 u32 hcintmsk = HCINTMSK_CHHLTD;
1158 switch (chan->ep_type) {
1159 case USB_ENDPOINT_XFER_CONTROL:
1160 case USB_ENDPOINT_XFER_BULK:
1161 dev_vdbg(hsotg->dev, "control/bulk\n");
1162 hcintmsk |= HCINTMSK_XFERCOMPL;
1163 hcintmsk |= HCINTMSK_STALL;
1164 hcintmsk |= HCINTMSK_XACTERR;
1165 hcintmsk |= HCINTMSK_DATATGLERR;
1166 if (chan->ep_is_in) {
1167 hcintmsk |= HCINTMSK_BBLERR;
1169 hcintmsk |= HCINTMSK_NAK;
1170 hcintmsk |= HCINTMSK_NYET;
1172 hcintmsk |= HCINTMSK_ACK;
1175 if (chan->do_split) {
1176 hcintmsk |= HCINTMSK_NAK;
1177 if (chan->complete_split)
1178 hcintmsk |= HCINTMSK_NYET;
1180 hcintmsk |= HCINTMSK_ACK;
1183 if (chan->error_state)
1184 hcintmsk |= HCINTMSK_ACK;
1187 case USB_ENDPOINT_XFER_INT:
1189 dev_vdbg(hsotg->dev, "intr\n");
1190 hcintmsk |= HCINTMSK_XFERCOMPL;
1191 hcintmsk |= HCINTMSK_NAK;
1192 hcintmsk |= HCINTMSK_STALL;
1193 hcintmsk |= HCINTMSK_XACTERR;
1194 hcintmsk |= HCINTMSK_DATATGLERR;
1195 hcintmsk |= HCINTMSK_FRMOVRUN;
1198 hcintmsk |= HCINTMSK_BBLERR;
1199 if (chan->error_state)
1200 hcintmsk |= HCINTMSK_ACK;
1201 if (chan->do_split) {
1202 if (chan->complete_split)
1203 hcintmsk |= HCINTMSK_NYET;
1205 hcintmsk |= HCINTMSK_ACK;
1209 case USB_ENDPOINT_XFER_ISOC:
1211 dev_vdbg(hsotg->dev, "isoc\n");
1212 hcintmsk |= HCINTMSK_XFERCOMPL;
1213 hcintmsk |= HCINTMSK_FRMOVRUN;
1214 hcintmsk |= HCINTMSK_ACK;
1216 if (chan->ep_is_in) {
1217 hcintmsk |= HCINTMSK_XACTERR;
1218 hcintmsk |= HCINTMSK_BBLERR;
1222 dev_err(hsotg->dev, "## Unknown EP type ##\n");
1226 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1228 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1231 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
1232 struct dwc2_host_chan *chan)
1234 u32 hcintmsk = HCINTMSK_CHHLTD;
1237 * For Descriptor DMA mode core halts the channel on AHB error.
1238 * Interrupt is not required.
1240 if (hsotg->core_params->dma_desc_enable <= 0) {
1242 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1243 hcintmsk |= HCINTMSK_AHBERR;
1246 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
1247 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1248 hcintmsk |= HCINTMSK_XFERCOMPL;
1251 if (chan->error_state && !chan->do_split &&
1252 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1254 dev_vdbg(hsotg->dev, "setting ACK\n");
1255 hcintmsk |= HCINTMSK_ACK;
1256 if (chan->ep_is_in) {
1257 hcintmsk |= HCINTMSK_DATATGLERR;
1258 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
1259 hcintmsk |= HCINTMSK_NAK;
1263 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1265 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1268 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
1269 struct dwc2_host_chan *chan)
1273 if (hsotg->core_params->dma_enable > 0) {
1275 dev_vdbg(hsotg->dev, "DMA enabled\n");
1276 dwc2_hc_enable_dma_ints(hsotg, chan);
1279 dev_vdbg(hsotg->dev, "DMA disabled\n");
1280 dwc2_hc_enable_slave_ints(hsotg, chan);
1283 /* Enable the top level host channel interrupt */
1284 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
1285 intmsk |= 1 << chan->hc_num;
1286 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
1288 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
1290 /* Make sure host channel interrupts are enabled */
1291 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
1292 intmsk |= GINTSTS_HCHINT;
1293 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
1295 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
1299 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
1300 * a specific endpoint
1302 * @hsotg: Programming view of DWC_otg controller
1303 * @chan: Information needed to initialize the host channel
1305 * The HCCHARn register is set up with the characteristics specified in chan.
1306 * Host channel interrupts that may need to be serviced while this transfer is
1307 * in progress are enabled.
1309 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1311 u8 hc_num = chan->hc_num;
1317 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1319 /* Clear old interrupt conditions for this host channel */
1320 hcintmsk = 0xffffffff;
1321 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1322 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
1324 /* Enable channel interrupts required for this transfer */
1325 dwc2_hc_enable_ints(hsotg, chan);
1328 * Program the HCCHARn register with the endpoint characteristics for
1329 * the current transfer
1331 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
1332 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
1334 hcchar |= HCCHAR_EPDIR;
1335 if (chan->speed == USB_SPEED_LOW)
1336 hcchar |= HCCHAR_LSPDDEV;
1337 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
1338 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
1339 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
1341 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
1344 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
1346 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
1348 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
1350 dev_vdbg(hsotg->dev, " Is In: %d\n",
1352 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
1353 chan->speed == USB_SPEED_LOW);
1354 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
1356 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
1360 /* Program the HCSPLT register for SPLITs */
1361 if (chan->do_split) {
1363 dev_vdbg(hsotg->dev,
1364 "Programming HC %d with split --> %s\n",
1366 chan->complete_split ? "CSPLIT" : "SSPLIT");
1367 if (chan->complete_split)
1368 hcsplt |= HCSPLT_COMPSPLT;
1369 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
1370 HCSPLT_XACTPOS_MASK;
1371 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
1372 HCSPLT_HUBADDR_MASK;
1373 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
1374 HCSPLT_PRTADDR_MASK;
1376 dev_vdbg(hsotg->dev, " comp split %d\n",
1377 chan->complete_split);
1378 dev_vdbg(hsotg->dev, " xact pos %d\n",
1380 dev_vdbg(hsotg->dev, " hub addr %d\n",
1382 dev_vdbg(hsotg->dev, " hub port %d\n",
1384 dev_vdbg(hsotg->dev, " is_in %d\n",
1386 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
1388 dev_vdbg(hsotg->dev, " xferlen %d\n",
1393 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
1397 * dwc2_hc_halt() - Attempts to halt a host channel
1399 * @hsotg: Controller register interface
1400 * @chan: Host channel to halt
1401 * @halt_status: Reason for halting the channel
1403 * This function should only be called in Slave mode or to abort a transfer in
1404 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
1405 * controller halts the channel when the transfer is complete or a condition
1406 * occurs that requires application intervention.
1408 * In slave mode, checks for a free request queue entry, then sets the Channel
1409 * Enable and Channel Disable bits of the Host Channel Characteristics
1410 * register of the specified channel to intiate the halt. If there is no free
1411 * request queue entry, sets only the Channel Disable bit of the HCCHARn
1412 * register to flush requests for this channel. In the latter case, sets a
1413 * flag to indicate that the host channel needs to be halted when a request
1414 * queue slot is open.
1416 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
1417 * HCCHARn register. The controller ensures there is space in the request
1418 * queue before submitting the halt request.
1420 * Some time may elapse before the core flushes any posted requests for this
1421 * host channel and halts. The Channel Halted interrupt handler completes the
1422 * deactivation of the host channel.
1424 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1425 enum dwc2_halt_status halt_status)
1427 u32 nptxsts, hptxsts, hcchar;
1430 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1431 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1432 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1434 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1435 halt_status == DWC2_HC_XFER_AHB_ERR) {
1437 * Disable all channel interrupts except Ch Halted. The QTD
1438 * and QH state associated with this transfer has been cleared
1439 * (in the case of URB_DEQUEUE), so the channel needs to be
1440 * shut down carefully to prevent crashes.
1442 u32 hcintmsk = HCINTMSK_CHHLTD;
1444 dev_vdbg(hsotg->dev, "dequeue/error\n");
1445 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1448 * Make sure no other interrupts besides halt are currently
1449 * pending. Handling another interrupt could cause a crash due
1450 * to the QTD and QH state.
1452 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1455 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1456 * even if the channel was already halted for some other
1459 chan->halt_status = halt_status;
1461 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1462 if (!(hcchar & HCCHAR_CHENA)) {
1464 * The channel is either already halted or it hasn't
1465 * started yet. In DMA mode, the transfer may halt if
1466 * it finishes normally or a condition occurs that
1467 * requires driver intervention. Don't want to halt
1468 * the channel again. In either Slave or DMA mode,
1469 * it's possible that the transfer has been assigned
1470 * to a channel, but not started yet when an URB is
1471 * dequeued. Don't want to halt a channel that hasn't
1477 if (chan->halt_pending) {
1479 * A halt has already been issued for this channel. This might
1480 * happen when a transfer is aborted by a higher level in
1483 dev_vdbg(hsotg->dev,
1484 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1485 __func__, chan->hc_num);
1489 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1491 /* No need to set the bit in DDMA for disabling the channel */
1492 /* TODO check it everywhere channel is disabled */
1493 if (hsotg->core_params->dma_desc_enable <= 0) {
1495 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1496 hcchar |= HCCHAR_CHENA;
1499 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1501 hcchar |= HCCHAR_CHDIS;
1503 if (hsotg->core_params->dma_enable <= 0) {
1505 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1506 hcchar |= HCCHAR_CHENA;
1508 /* Check for space in the request queue to issue the halt */
1509 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1510 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1511 dev_vdbg(hsotg->dev, "control/bulk\n");
1512 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1513 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1514 dev_vdbg(hsotg->dev, "Disabling channel\n");
1515 hcchar &= ~HCCHAR_CHENA;
1519 dev_vdbg(hsotg->dev, "isoc/intr\n");
1520 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1521 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1522 hsotg->queuing_high_bandwidth) {
1524 dev_vdbg(hsotg->dev, "Disabling channel\n");
1525 hcchar &= ~HCCHAR_CHENA;
1530 dev_vdbg(hsotg->dev, "DMA enabled\n");
1533 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1534 chan->halt_status = halt_status;
1536 if (hcchar & HCCHAR_CHENA) {
1538 dev_vdbg(hsotg->dev, "Channel enabled\n");
1539 chan->halt_pending = 1;
1540 chan->halt_on_queue = 0;
1543 dev_vdbg(hsotg->dev, "Channel disabled\n");
1544 chan->halt_on_queue = 1;
1548 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1550 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1552 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1553 chan->halt_pending);
1554 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1555 chan->halt_on_queue);
1556 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1562 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1564 * @hsotg: Programming view of DWC_otg controller
1565 * @chan: Identifies the host channel to clean up
1567 * This function is normally called after a transfer is done and the host
1568 * channel is being released
1570 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1574 chan->xfer_started = 0;
1577 * Clear channel interrupt enables and any unhandled channel interrupt
1580 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1581 hcintmsk = 0xffffffff;
1582 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1583 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1587 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1588 * which frame a periodic transfer should occur
1590 * @hsotg: Programming view of DWC_otg controller
1591 * @chan: Identifies the host channel to set up and its properties
1592 * @hcchar: Current value of the HCCHAR register for the specified host channel
1594 * This function has no effect on non-periodic transfers
1596 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1597 struct dwc2_host_chan *chan, u32 *hcchar)
1599 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1600 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1601 /* 1 if _next_ frame is odd, 0 if it's even */
1602 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1603 *hcchar |= HCCHAR_ODDFRM;
1607 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1609 /* Set up the initial PID for the transfer */
1610 if (chan->speed == USB_SPEED_HIGH) {
1611 if (chan->ep_is_in) {
1612 if (chan->multi_count == 1)
1613 chan->data_pid_start = DWC2_HC_PID_DATA0;
1614 else if (chan->multi_count == 2)
1615 chan->data_pid_start = DWC2_HC_PID_DATA1;
1617 chan->data_pid_start = DWC2_HC_PID_DATA2;
1619 if (chan->multi_count == 1)
1620 chan->data_pid_start = DWC2_HC_PID_DATA0;
1622 chan->data_pid_start = DWC2_HC_PID_MDATA;
1625 chan->data_pid_start = DWC2_HC_PID_DATA0;
1630 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1633 * @hsotg: Programming view of DWC_otg controller
1634 * @chan: Information needed to initialize the host channel
1636 * This function should only be called in Slave mode. For a channel associated
1637 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1638 * associated with a periodic EP, the periodic Tx FIFO is written.
1640 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1641 * the number of bytes written to the Tx FIFO.
1643 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1644 struct dwc2_host_chan *chan)
1647 u32 remaining_count;
1650 u32 __iomem *data_fifo;
1651 u32 *data_buf = (u32 *)chan->xfer_buf;
1654 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1656 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1658 remaining_count = chan->xfer_len - chan->xfer_count;
1659 if (remaining_count > chan->max_packet)
1660 byte_count = chan->max_packet;
1662 byte_count = remaining_count;
1664 dword_count = (byte_count + 3) / 4;
1666 if (((unsigned long)data_buf & 0x3) == 0) {
1667 /* xfer_buf is DWORD aligned */
1668 for (i = 0; i < dword_count; i++, data_buf++)
1669 dwc2_writel(*data_buf, data_fifo);
1671 /* xfer_buf is not DWORD aligned */
1672 for (i = 0; i < dword_count; i++, data_buf++) {
1673 u32 data = data_buf[0] | data_buf[1] << 8 |
1674 data_buf[2] << 16 | data_buf[3] << 24;
1675 dwc2_writel(data, data_fifo);
1679 chan->xfer_count += byte_count;
1680 chan->xfer_buf += byte_count;
1684 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1685 * channel and starts the transfer
1687 * @hsotg: Programming view of DWC_otg controller
1688 * @chan: Information needed to initialize the host channel. The xfer_len value
1689 * may be reduced to accommodate the max widths of the XferSize and
1690 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1691 * changed to reflect the final xfer_len value.
1693 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1694 * the caller must ensure that there is sufficient space in the request queue
1697 * For an OUT transfer in Slave mode, it loads a data packet into the
1698 * appropriate FIFO. If necessary, additional data packets are loaded in the
1701 * For an IN transfer in Slave mode, a data packet is requested. The data
1702 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1703 * additional data packets are requested in the Host ISR.
1705 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1706 * register along with a packet count of 1 and the channel is enabled. This
1707 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1708 * simply set to 0 since no data transfer occurs in this case.
1710 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1711 * all the information required to perform the subsequent data transfer. In
1712 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1713 * controller performs the entire PING protocol, then starts the data
1716 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1717 struct dwc2_host_chan *chan)
1719 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1720 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1726 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1728 if (chan->do_ping) {
1729 if (hsotg->core_params->dma_enable <= 0) {
1731 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1732 dwc2_hc_do_ping(hsotg, chan);
1733 chan->xfer_started = 1;
1737 dev_vdbg(hsotg->dev, "ping, DMA\n");
1738 hctsiz |= TSIZ_DOPNG;
1742 if (chan->do_split) {
1744 dev_vdbg(hsotg->dev, "split\n");
1747 if (chan->complete_split && !chan->ep_is_in)
1749 * For CSPLIT OUT Transfer, set the size to 0 so the
1750 * core doesn't expect any data written to the FIFO
1753 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1754 chan->xfer_len = chan->max_packet;
1755 else if (!chan->ep_is_in && chan->xfer_len > 188)
1756 chan->xfer_len = 188;
1758 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1762 dev_vdbg(hsotg->dev, "no split\n");
1764 * Ensure that the transfer length and packet count will fit
1765 * in the widths allocated for them in the HCTSIZn register
1767 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1768 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1770 * Make sure the transfer size is no larger than one
1771 * (micro)frame's worth of data. (A check was done
1772 * when the periodic transfer was accepted to ensure
1773 * that a (micro)frame's worth of data can be
1774 * programmed into a channel.)
1776 u32 max_periodic_len =
1777 chan->multi_count * chan->max_packet;
1779 if (chan->xfer_len > max_periodic_len)
1780 chan->xfer_len = max_periodic_len;
1781 } else if (chan->xfer_len > max_hc_xfer_size) {
1783 * Make sure that xfer_len is a multiple of max packet
1787 max_hc_xfer_size - chan->max_packet + 1;
1790 if (chan->xfer_len > 0) {
1791 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1793 if (num_packets > max_hc_pkt_count) {
1794 num_packets = max_hc_pkt_count;
1795 chan->xfer_len = num_packets * chan->max_packet;
1798 /* Need 1 packet for transfer length of 0 */
1804 * Always program an integral # of max packets for IN
1807 chan->xfer_len = num_packets * chan->max_packet;
1809 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1810 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1812 * Make sure that the multi_count field matches the
1813 * actual transfer length
1815 chan->multi_count = num_packets;
1817 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1818 dwc2_set_pid_isoc(chan);
1820 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1824 chan->start_pkt_count = num_packets;
1825 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1826 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1827 TSIZ_SC_MC_PID_MASK;
1828 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1830 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1831 hctsiz, chan->hc_num);
1833 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1835 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1836 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1837 TSIZ_XFERSIZE_SHIFT);
1838 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1839 (hctsiz & TSIZ_PKTCNT_MASK) >>
1841 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1842 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1843 TSIZ_SC_MC_PID_SHIFT);
1846 if (hsotg->core_params->dma_enable > 0) {
1847 dma_addr_t dma_addr;
1849 if (chan->align_buf) {
1851 dev_vdbg(hsotg->dev, "align_buf\n");
1852 dma_addr = chan->align_buf;
1854 dma_addr = chan->xfer_dma;
1856 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1858 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1859 (unsigned long)dma_addr, chan->hc_num);
1862 /* Start the split */
1863 if (chan->do_split) {
1864 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1866 hcsplt |= HCSPLT_SPLTENA;
1867 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1870 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1871 hcchar &= ~HCCHAR_MULTICNT_MASK;
1872 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1873 HCCHAR_MULTICNT_MASK;
1874 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1876 if (hcchar & HCCHAR_CHDIS)
1877 dev_warn(hsotg->dev,
1878 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1879 __func__, chan->hc_num, hcchar);
1881 /* Set host channel enable after all other setup is complete */
1882 hcchar |= HCCHAR_CHENA;
1883 hcchar &= ~HCCHAR_CHDIS;
1886 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1887 (hcchar & HCCHAR_MULTICNT_MASK) >>
1888 HCCHAR_MULTICNT_SHIFT);
1890 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1892 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1895 chan->xfer_started = 1;
1898 if (hsotg->core_params->dma_enable <= 0 &&
1899 !chan->ep_is_in && chan->xfer_len > 0)
1900 /* Load OUT packet into the appropriate Tx FIFO */
1901 dwc2_hc_write_packet(hsotg, chan);
1905 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1906 * host channel and starts the transfer in Descriptor DMA mode
1908 * @hsotg: Programming view of DWC_otg controller
1909 * @chan: Information needed to initialize the host channel
1911 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1912 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1913 * with micro-frame bitmap.
1915 * Initializes HCDMA register with descriptor list address and CTD value then
1916 * starts the transfer via enabling the channel.
1918 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1919 struct dwc2_host_chan *chan)
1926 hctsiz |= TSIZ_DOPNG;
1928 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1929 dwc2_set_pid_isoc(chan);
1931 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1932 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1933 TSIZ_SC_MC_PID_MASK;
1935 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1936 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1938 /* Non-zero only for high-speed interrupt endpoints */
1939 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1942 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1944 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1945 chan->data_pid_start);
1946 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1949 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1951 hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
1953 /* Always start from first descriptor */
1954 hc_dma &= ~HCDMA_CTD_MASK;
1955 dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
1957 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
1958 hc_dma, chan->hc_num);
1960 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1961 hcchar &= ~HCCHAR_MULTICNT_MASK;
1962 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1963 HCCHAR_MULTICNT_MASK;
1965 if (hcchar & HCCHAR_CHDIS)
1966 dev_warn(hsotg->dev,
1967 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1968 __func__, chan->hc_num, hcchar);
1970 /* Set host channel enable after all other setup is complete */
1971 hcchar |= HCCHAR_CHENA;
1972 hcchar &= ~HCCHAR_CHDIS;
1975 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1976 (hcchar & HCCHAR_MULTICNT_MASK) >>
1977 HCCHAR_MULTICNT_SHIFT);
1979 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1981 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1984 chan->xfer_started = 1;
1989 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1990 * a previous call to dwc2_hc_start_transfer()
1992 * @hsotg: Programming view of DWC_otg controller
1993 * @chan: Information needed to initialize the host channel
1995 * The caller must ensure there is sufficient space in the request queue and Tx
1996 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1997 * the controller acts autonomously to complete transfers programmed to a host
2000 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2001 * if there is any data remaining to be queued. For an IN transfer, another
2002 * data packet is always requested. For the SETUP phase of a control transfer,
2003 * this function does nothing.
2005 * Return: 1 if a new request is queued, 0 if no more requests are required
2008 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
2009 struct dwc2_host_chan *chan)
2012 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2016 /* SPLITs always queue just once per channel */
2019 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
2020 /* SETUPs are queued only once since they can't be NAK'd */
2023 if (chan->ep_is_in) {
2025 * Always queue another request for other IN transfers. If
2026 * back-to-back INs are issued and NAKs are received for both,
2027 * the driver may still be processing the first NAK when the
2028 * second NAK is received. When the interrupt handler clears
2029 * the NAK interrupt for the first NAK, the second NAK will
2030 * not be seen. So we can't depend on the NAK interrupt
2031 * handler to requeue a NAK'd request. Instead, IN requests
2032 * are issued each time this function is called. When the
2033 * transfer completes, the extra requests for the channel will
2036 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2038 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
2039 hcchar |= HCCHAR_CHENA;
2040 hcchar &= ~HCCHAR_CHDIS;
2042 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
2044 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2051 if (chan->xfer_count < chan->xfer_len) {
2052 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2053 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2054 u32 hcchar = dwc2_readl(hsotg->regs +
2055 HCCHAR(chan->hc_num));
2057 dwc2_hc_set_even_odd_frame(hsotg, chan,
2061 /* Load OUT packet into the appropriate Tx FIFO */
2062 dwc2_hc_write_packet(hsotg, chan);
2071 * dwc2_hc_do_ping() - Starts a PING transfer
2073 * @hsotg: Programming view of DWC_otg controller
2074 * @chan: Information needed to initialize the host channel
2076 * This function should only be called in Slave mode. The Do Ping bit is set in
2077 * the HCTSIZ register, then the channel is enabled.
2079 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
2085 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2089 hctsiz = TSIZ_DOPNG;
2090 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
2091 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
2093 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2094 hcchar |= HCCHAR_CHENA;
2095 hcchar &= ~HCCHAR_CHDIS;
2096 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2100 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
2101 * the HFIR register according to PHY type and speed
2103 * @hsotg: Programming view of DWC_otg controller
2105 * NOTE: The caller can modify the value of the HFIR register only after the
2106 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
2109 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
2113 int clock = 60; /* default value */
2115 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2116 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2118 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
2119 !(usbcfg & GUSBCFG_PHYIF16))
2121 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
2122 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
2124 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2125 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2127 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2128 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
2130 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2131 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2133 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
2134 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
2136 if ((usbcfg & GUSBCFG_PHYSEL) &&
2137 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2140 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
2141 /* High speed case */
2145 return 1000 * clock;
2149 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
2152 * @core_if: Programming view of DWC_otg controller
2153 * @dest: Destination buffer for the packet
2154 * @bytes: Number of bytes to copy to the destination
2156 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
2158 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
2159 u32 *data_buf = (u32 *)dest;
2160 int word_count = (bytes + 3) / 4;
2164 * Todo: Account for the case where dest is not dword aligned. This
2165 * requires reading data from the FIFO into a u32 temp buffer, then
2166 * moving it into the data buffer.
2169 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
2171 for (i = 0; i < word_count; i++, data_buf++)
2172 *data_buf = dwc2_readl(fifo);
2176 * dwc2_dump_host_registers() - Prints the host registers
2178 * @hsotg: Programming view of DWC_otg controller
2180 * NOTE: This function will be removed once the peripheral controller code
2181 * is integrated and the driver is stable
2183 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
2189 dev_dbg(hsotg->dev, "Host Global Registers\n");
2190 addr = hsotg->regs + HCFG;
2191 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
2192 (unsigned long)addr, dwc2_readl(addr));
2193 addr = hsotg->regs + HFIR;
2194 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
2195 (unsigned long)addr, dwc2_readl(addr));
2196 addr = hsotg->regs + HFNUM;
2197 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
2198 (unsigned long)addr, dwc2_readl(addr));
2199 addr = hsotg->regs + HPTXSTS;
2200 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
2201 (unsigned long)addr, dwc2_readl(addr));
2202 addr = hsotg->regs + HAINT;
2203 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
2204 (unsigned long)addr, dwc2_readl(addr));
2205 addr = hsotg->regs + HAINTMSK;
2206 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
2207 (unsigned long)addr, dwc2_readl(addr));
2208 if (hsotg->core_params->dma_desc_enable > 0) {
2209 addr = hsotg->regs + HFLBADDR;
2210 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
2211 (unsigned long)addr, dwc2_readl(addr));
2214 addr = hsotg->regs + HPRT0;
2215 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
2216 (unsigned long)addr, dwc2_readl(addr));
2218 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2219 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
2220 addr = hsotg->regs + HCCHAR(i);
2221 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
2222 (unsigned long)addr, dwc2_readl(addr));
2223 addr = hsotg->regs + HCSPLT(i);
2224 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
2225 (unsigned long)addr, dwc2_readl(addr));
2226 addr = hsotg->regs + HCINT(i);
2227 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
2228 (unsigned long)addr, dwc2_readl(addr));
2229 addr = hsotg->regs + HCINTMSK(i);
2230 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
2231 (unsigned long)addr, dwc2_readl(addr));
2232 addr = hsotg->regs + HCTSIZ(i);
2233 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
2234 (unsigned long)addr, dwc2_readl(addr));
2235 addr = hsotg->regs + HCDMA(i);
2236 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
2237 (unsigned long)addr, dwc2_readl(addr));
2238 if (hsotg->core_params->dma_desc_enable > 0) {
2239 addr = hsotg->regs + HCDMAB(i);
2240 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
2241 (unsigned long)addr, dwc2_readl(addr));
2248 * dwc2_dump_global_registers() - Prints the core global registers
2250 * @hsotg: Programming view of DWC_otg controller
2252 * NOTE: This function will be removed once the peripheral controller code
2253 * is integrated and the driver is stable
2255 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
2260 dev_dbg(hsotg->dev, "Core Global Registers\n");
2261 addr = hsotg->regs + GOTGCTL;
2262 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
2263 (unsigned long)addr, dwc2_readl(addr));
2264 addr = hsotg->regs + GOTGINT;
2265 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
2266 (unsigned long)addr, dwc2_readl(addr));
2267 addr = hsotg->regs + GAHBCFG;
2268 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
2269 (unsigned long)addr, dwc2_readl(addr));
2270 addr = hsotg->regs + GUSBCFG;
2271 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
2272 (unsigned long)addr, dwc2_readl(addr));
2273 addr = hsotg->regs + GRSTCTL;
2274 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
2275 (unsigned long)addr, dwc2_readl(addr));
2276 addr = hsotg->regs + GINTSTS;
2277 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
2278 (unsigned long)addr, dwc2_readl(addr));
2279 addr = hsotg->regs + GINTMSK;
2280 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
2281 (unsigned long)addr, dwc2_readl(addr));
2282 addr = hsotg->regs + GRXSTSR;
2283 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
2284 (unsigned long)addr, dwc2_readl(addr));
2285 addr = hsotg->regs + GRXFSIZ;
2286 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
2287 (unsigned long)addr, dwc2_readl(addr));
2288 addr = hsotg->regs + GNPTXFSIZ;
2289 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
2290 (unsigned long)addr, dwc2_readl(addr));
2291 addr = hsotg->regs + GNPTXSTS;
2292 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
2293 (unsigned long)addr, dwc2_readl(addr));
2294 addr = hsotg->regs + GI2CCTL;
2295 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
2296 (unsigned long)addr, dwc2_readl(addr));
2297 addr = hsotg->regs + GPVNDCTL;
2298 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
2299 (unsigned long)addr, dwc2_readl(addr));
2300 addr = hsotg->regs + GGPIO;
2301 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
2302 (unsigned long)addr, dwc2_readl(addr));
2303 addr = hsotg->regs + GUID;
2304 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
2305 (unsigned long)addr, dwc2_readl(addr));
2306 addr = hsotg->regs + GSNPSID;
2307 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
2308 (unsigned long)addr, dwc2_readl(addr));
2309 addr = hsotg->regs + GHWCFG1;
2310 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
2311 (unsigned long)addr, dwc2_readl(addr));
2312 addr = hsotg->regs + GHWCFG2;
2313 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
2314 (unsigned long)addr, dwc2_readl(addr));
2315 addr = hsotg->regs + GHWCFG3;
2316 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
2317 (unsigned long)addr, dwc2_readl(addr));
2318 addr = hsotg->regs + GHWCFG4;
2319 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
2320 (unsigned long)addr, dwc2_readl(addr));
2321 addr = hsotg->regs + GLPMCFG;
2322 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
2323 (unsigned long)addr, dwc2_readl(addr));
2324 addr = hsotg->regs + GPWRDN;
2325 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
2326 (unsigned long)addr, dwc2_readl(addr));
2327 addr = hsotg->regs + GDFIFOCFG;
2328 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
2329 (unsigned long)addr, dwc2_readl(addr));
2330 addr = hsotg->regs + HPTXFSIZ;
2331 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
2332 (unsigned long)addr, dwc2_readl(addr));
2334 addr = hsotg->regs + PCGCTL;
2335 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
2336 (unsigned long)addr, dwc2_readl(addr));
2341 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
2343 * @hsotg: Programming view of DWC_otg controller
2344 * @num: Tx FIFO to flush
2346 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
2351 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
2353 greset = GRSTCTL_TXFFLSH;
2354 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
2355 dwc2_writel(greset, hsotg->regs + GRSTCTL);
2358 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2359 if (++count > 10000) {
2360 dev_warn(hsotg->dev,
2361 "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
2363 dwc2_readl(hsotg->regs + GNPTXSTS));
2367 } while (greset & GRSTCTL_TXFFLSH);
2369 /* Wait for at least 3 PHY Clocks */
2374 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
2376 * @hsotg: Programming view of DWC_otg controller
2378 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
2383 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2385 greset = GRSTCTL_RXFFLSH;
2386 dwc2_writel(greset, hsotg->regs + GRSTCTL);
2389 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2390 if (++count > 10000) {
2391 dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
2396 } while (greset & GRSTCTL_RXFFLSH);
2398 /* Wait for at least 3 PHY Clocks */
2402 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c))
2404 /* Parameter access functions */
2405 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
2410 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
2411 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
2414 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
2415 switch (hsotg->hw_params.op_mode) {
2416 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2417 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2418 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2419 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2426 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
2437 "%d invalid for otg_cap parameter. Check HW configuration.\n",
2439 switch (hsotg->hw_params.op_mode) {
2440 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2441 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
2443 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2444 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2445 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2446 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2449 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2452 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2455 hsotg->core_params->otg_cap = val;
2458 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2462 if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
2470 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2472 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
2473 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2476 hsotg->core_params->dma_enable = val;
2479 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2483 if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2484 !hsotg->hw_params.dma_desc_enable))
2492 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2494 val = (hsotg->core_params->dma_enable > 0 &&
2495 hsotg->hw_params.dma_desc_enable);
2496 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2499 hsotg->core_params->dma_desc_enable = val;
2502 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2505 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2508 "Wrong value for host_support_fs_low_power\n");
2510 "host_support_fs_low_power must be 0 or 1\n");
2514 "Setting host_support_fs_low_power to %d\n", val);
2517 hsotg->core_params->host_support_fs_ls_low_power = val;
2520 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2524 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
2532 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2534 val = hsotg->hw_params.enable_dynamic_fifo;
2535 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2538 hsotg->core_params->enable_dynamic_fifo = val;
2541 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2545 if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
2551 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2553 val = hsotg->hw_params.host_rx_fifo_size;
2554 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2557 hsotg->core_params->host_rx_fifo_size = val;
2560 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2564 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
2570 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2572 val = hsotg->hw_params.host_nperio_tx_fifo_size;
2573 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2577 hsotg->core_params->host_nperio_tx_fifo_size = val;
2580 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2584 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
2590 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2592 val = hsotg->hw_params.host_perio_tx_fifo_size;
2593 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2597 hsotg->core_params->host_perio_tx_fifo_size = val;
2600 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2604 if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
2610 "%d invalid for max_transfer_size. Check HW configuration.\n",
2612 val = hsotg->hw_params.max_transfer_size;
2613 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2616 hsotg->core_params->max_transfer_size = val;
2619 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2623 if (val < 15 || val > hsotg->hw_params.max_packet_count)
2629 "%d invalid for max_packet_count. Check HW configuration.\n",
2631 val = hsotg->hw_params.max_packet_count;
2632 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2635 hsotg->core_params->max_packet_count = val;
2638 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2642 if (val < 1 || val > hsotg->hw_params.host_channels)
2648 "%d invalid for host_channels. Check HW configuration.\n",
2650 val = hsotg->hw_params.host_channels;
2651 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2654 hsotg->core_params->host_channels = val;
2657 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2660 u32 hs_phy_type, fs_phy_type;
2662 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
2663 DWC2_PHY_TYPE_PARAM_ULPI)) {
2665 dev_err(hsotg->dev, "Wrong value for phy_type\n");
2666 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2672 hs_phy_type = hsotg->hw_params.hs_phy_type;
2673 fs_phy_type = hsotg->hw_params.fs_phy_type;
2674 if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2675 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2676 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2678 else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2679 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2680 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2682 else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2683 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2689 "%d invalid for phy_type. Check HW configuration.\n",
2691 val = DWC2_PHY_TYPE_PARAM_FS;
2692 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2693 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2694 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2695 val = DWC2_PHY_TYPE_PARAM_UTMI;
2697 val = DWC2_PHY_TYPE_PARAM_ULPI;
2699 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2702 hsotg->core_params->phy_type = val;
2705 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2707 return hsotg->core_params->phy_type;
2710 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2714 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2716 dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2717 dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2722 if (val == DWC2_SPEED_PARAM_HIGH &&
2723 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2729 "%d invalid for speed parameter. Check HW configuration.\n",
2731 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2732 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2733 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2736 hsotg->core_params->speed = val;
2739 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2743 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2744 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2747 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2749 "host_ls_low_power_phy_clk must be 0 or 1\n");
2754 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2755 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2761 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2763 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2764 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2765 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2766 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2770 hsotg->core_params->host_ls_low_power_phy_clk = val;
2773 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2775 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2777 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2778 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2781 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2784 hsotg->core_params->phy_ulpi_ddr = val;
2787 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2789 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2792 "Wrong value for phy_ulpi_ext_vbus\n");
2794 "phy_ulpi_ext_vbus must be 0 or 1\n");
2797 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2800 hsotg->core_params->phy_ulpi_ext_vbus = val;
2803 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2807 switch (hsotg->hw_params.utmi_phy_data_width) {
2808 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
2811 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
2812 valid = (val == 16);
2814 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
2815 valid = (val == 8 || val == 16);
2822 "%d invalid for phy_utmi_width. Check HW configuration.\n",
2825 val = (hsotg->hw_params.utmi_phy_data_width ==
2826 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
2827 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2830 hsotg->core_params->phy_utmi_width = val;
2833 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2835 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2837 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2838 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2841 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2844 hsotg->core_params->ulpi_fs_ls = val;
2847 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2849 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2851 dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2852 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2855 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2858 hsotg->core_params->ts_dline = val;
2861 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2865 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2867 dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2868 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2874 if (val == 1 && !(hsotg->hw_params.i2c_enable))
2880 "%d invalid for i2c_enable. Check HW configuration.\n",
2882 val = hsotg->hw_params.i2c_enable;
2883 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2886 hsotg->core_params->i2c_enable = val;
2889 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2893 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2896 "Wrong value for en_multiple_tx_fifo,\n");
2898 "en_multiple_tx_fifo must be 0 or 1\n");
2903 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
2909 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2911 val = hsotg->hw_params.en_multiple_tx_fifo;
2912 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2915 hsotg->core_params->en_multiple_tx_fifo = val;
2918 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2922 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2925 "'%d' invalid for parameter reload_ctl\n", val);
2926 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2931 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
2937 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2939 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
2940 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2943 hsotg->core_params->reload_ctl = val;
2946 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
2949 hsotg->core_params->ahbcfg = val;
2951 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
2952 GAHBCFG_HBSTLEN_SHIFT;
2955 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2957 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2960 "'%d' invalid for parameter otg_ver\n", val);
2962 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2965 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2968 hsotg->core_params->otg_ver = val;
2971 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
2973 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2976 "'%d' invalid for parameter uframe_sched\n",
2978 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
2981 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
2984 hsotg->core_params->uframe_sched = val;
2987 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
2990 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2993 "'%d' invalid for parameter external_id_pin_ctl\n",
2995 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
2998 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
3001 hsotg->core_params->external_id_pin_ctl = val;
3004 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
3007 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3010 "'%d' invalid for parameter hibernation\n",
3012 dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
3015 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
3018 hsotg->core_params->hibernation = val;
3022 * This function is called during module intialization to pass module parameters
3023 * for the DWC_otg core.
3025 void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
3026 const struct dwc2_core_params *params)
3028 dev_dbg(hsotg->dev, "%s()\n", __func__);
3030 dwc2_set_param_otg_cap(hsotg, params->otg_cap);
3031 dwc2_set_param_dma_enable(hsotg, params->dma_enable);
3032 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
3033 dwc2_set_param_host_support_fs_ls_low_power(hsotg,
3034 params->host_support_fs_ls_low_power);
3035 dwc2_set_param_enable_dynamic_fifo(hsotg,
3036 params->enable_dynamic_fifo);
3037 dwc2_set_param_host_rx_fifo_size(hsotg,
3038 params->host_rx_fifo_size);
3039 dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
3040 params->host_nperio_tx_fifo_size);
3041 dwc2_set_param_host_perio_tx_fifo_size(hsotg,
3042 params->host_perio_tx_fifo_size);
3043 dwc2_set_param_max_transfer_size(hsotg,
3044 params->max_transfer_size);
3045 dwc2_set_param_max_packet_count(hsotg,
3046 params->max_packet_count);
3047 dwc2_set_param_host_channels(hsotg, params->host_channels);
3048 dwc2_set_param_phy_type(hsotg, params->phy_type);
3049 dwc2_set_param_speed(hsotg, params->speed);
3050 dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
3051 params->host_ls_low_power_phy_clk);
3052 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
3053 dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
3054 params->phy_ulpi_ext_vbus);
3055 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
3056 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
3057 dwc2_set_param_ts_dline(hsotg, params->ts_dline);
3058 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
3059 dwc2_set_param_en_multiple_tx_fifo(hsotg,
3060 params->en_multiple_tx_fifo);
3061 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
3062 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
3063 dwc2_set_param_otg_ver(hsotg, params->otg_ver);
3064 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
3065 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
3066 dwc2_set_param_hibernation(hsotg, params->hibernation);
3070 * During device initialization, read various hardware configuration
3071 * registers and interpret the contents.
3073 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
3075 struct dwc2_hw_params *hw = &hsotg->hw_params;
3077 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
3078 u32 hptxfsiz, grxfsiz, gnptxfsiz;
3082 * Attempt to ensure this device is really a DWC_otg Controller.
3083 * Read and verify the GSNPSID register contents. The value should be
3084 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
3085 * as in "OTG version 2.xx" or "OTG version 3.xx".
3087 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
3088 if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
3089 (hw->snpsid & 0xfffff000) != 0x4f543000) {
3090 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
3095 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
3096 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
3097 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
3099 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
3100 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
3101 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
3102 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
3103 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
3105 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
3106 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
3107 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
3108 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
3109 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
3111 /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
3112 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3113 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3114 dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
3115 hsotg->regs + GUSBCFG);
3116 usleep_range(25000, 50000);
3119 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
3120 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
3121 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
3122 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
3123 if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3124 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
3125 usleep_range(25000, 50000);
3129 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
3130 GHWCFG2_OP_MODE_SHIFT;
3131 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
3132 GHWCFG2_ARCHITECTURE_SHIFT;
3133 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
3134 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
3135 GHWCFG2_NUM_HOST_CHAN_SHIFT);
3136 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
3137 GHWCFG2_HS_PHY_TYPE_SHIFT;
3138 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
3139 GHWCFG2_FS_PHY_TYPE_SHIFT;
3140 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
3141 GHWCFG2_NUM_DEV_EP_SHIFT;
3142 hw->nperio_tx_q_depth =
3143 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
3144 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
3145 hw->host_perio_tx_q_depth =
3146 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
3147 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
3148 hw->dev_token_q_depth =
3149 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
3150 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
3153 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
3154 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
3155 hw->max_transfer_size = (1 << (width + 11)) - 1;
3157 * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates
3158 * coherent buffers with this size, and if it's too large we can
3159 * exhaust the coherent DMA pool.
3161 if (hw->max_transfer_size > 65535)
3162 hw->max_transfer_size = 65535;
3163 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
3164 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
3165 hw->max_packet_count = (1 << (width + 4)) - 1;
3166 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
3167 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
3168 GHWCFG3_DFIFO_DEPTH_SHIFT;
3171 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
3172 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
3173 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
3174 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
3175 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
3176 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
3177 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
3180 hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
3181 GRXFSIZ_DEPTH_SHIFT;
3182 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3183 FIFOSIZE_DEPTH_SHIFT;
3184 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3185 FIFOSIZE_DEPTH_SHIFT;
3187 dev_dbg(hsotg->dev, "Detected values from hardware:\n");
3188 dev_dbg(hsotg->dev, " op_mode=%d\n",
3190 dev_dbg(hsotg->dev, " arch=%d\n",
3192 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n",
3193 hw->dma_desc_enable);
3194 dev_dbg(hsotg->dev, " power_optimized=%d\n",
3195 hw->power_optimized);
3196 dev_dbg(hsotg->dev, " i2c_enable=%d\n",
3198 dev_dbg(hsotg->dev, " hs_phy_type=%d\n",
3200 dev_dbg(hsotg->dev, " fs_phy_type=%d\n",
3202 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n",
3203 hw->utmi_phy_data_width);
3204 dev_dbg(hsotg->dev, " num_dev_ep=%d\n",
3206 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n",
3207 hw->num_dev_perio_in_ep);
3208 dev_dbg(hsotg->dev, " host_channels=%d\n",
3210 dev_dbg(hsotg->dev, " max_transfer_size=%d\n",
3211 hw->max_transfer_size);
3212 dev_dbg(hsotg->dev, " max_packet_count=%d\n",
3213 hw->max_packet_count);
3214 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n",
3215 hw->nperio_tx_q_depth);
3216 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n",
3217 hw->host_perio_tx_q_depth);
3218 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n",
3219 hw->dev_token_q_depth);
3220 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n",
3221 hw->enable_dynamic_fifo);
3222 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n",
3223 hw->en_multiple_tx_fifo);
3224 dev_dbg(hsotg->dev, " total_fifo_size=%d\n",
3225 hw->total_fifo_size);
3226 dev_dbg(hsotg->dev, " host_rx_fifo_size=%d\n",
3227 hw->host_rx_fifo_size);
3228 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n",
3229 hw->host_nperio_tx_fifo_size);
3230 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n",
3231 hw->host_perio_tx_fifo_size);
3232 dev_dbg(hsotg->dev, "\n");
3238 * Sets all parameters to the given value.
3240 * Assumes that the dwc2_core_params struct contains only integers.
3242 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
3244 int *p = (int *)params;
3245 size_t size = sizeof(*params) / sizeof(*p);
3248 for (i = 0; i < size; i++)
3253 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
3255 return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
3258 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
3260 if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
3267 * dwc2_enable_global_interrupts() - Enables the controller's Global
3268 * Interrupt in the AHB Config register
3270 * @hsotg: Programming view of DWC_otg controller
3272 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
3274 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3276 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
3277 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3281 * dwc2_disable_global_interrupts() - Disables the controller's Global
3282 * Interrupt in the AHB Config register
3284 * @hsotg: Programming view of DWC_otg controller
3286 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
3288 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3290 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
3291 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3294 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
3295 MODULE_AUTHOR("Synopsys, Inc.");
3296 MODULE_LICENSE("Dual BSD/GPL");