2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/of_platform.h>
31 #include <linux/phy/phy.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
41 /* conversion functions */
42 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
44 return container_of(req, struct s3c_hsotg_req, req);
47 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
49 return container_of(ep, struct s3c_hsotg_ep, ep);
52 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
54 return container_of(gadget, struct dwc2_hsotg, gadget);
57 static inline void __orr32(void __iomem *ptr, u32 val)
59 writel(readl(ptr) | val, ptr);
62 static inline void __bic32(void __iomem *ptr, u32 val)
64 writel(readl(ptr) & ~val, ptr);
67 /* forward decleration of functions */
68 static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg);
71 * using_dma - return the DMA status of the driver.
72 * @hsotg: The driver state.
74 * Return true if we're using DMA.
76 * Currently, we have the DMA support code worked into everywhere
77 * that needs it, but the AMBA DMA implementation in the hardware can
78 * only DMA from 32bit aligned addresses. This means that gadgets such
79 * as the CDC Ethernet cannot work as they often pass packets which are
82 * Unfortunately the choice to use DMA or not is global to the controller
83 * and seems to be only settable when the controller is being put through
84 * a core reset. This means we either need to fix the gadgets to take
85 * account of DMA alignment, or add bounce buffers (yuerk).
87 * Until this issue is sorted out, we always return 'false'.
89 static inline bool using_dma(struct dwc2_hsotg *hsotg)
91 return false; /* support is not complete */
95 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
96 * @hsotg: The device state
97 * @ints: A bitmask of the interrupts to enable
99 static void s3c_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
101 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
104 new_gsintmsk = gsintmsk | ints;
106 if (new_gsintmsk != gsintmsk) {
107 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
108 writel(new_gsintmsk, hsotg->regs + GINTMSK);
113 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
114 * @hsotg: The device state
115 * @ints: A bitmask of the interrupts to enable
117 static void s3c_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
119 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
122 new_gsintmsk = gsintmsk & ~ints;
124 if (new_gsintmsk != gsintmsk)
125 writel(new_gsintmsk, hsotg->regs + GINTMSK);
129 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
130 * @hsotg: The device state
131 * @ep: The endpoint index
132 * @dir_in: True if direction is in.
133 * @en: The enable value, true to enable
135 * Set or clear the mask for an individual endpoint's interrupt
138 static void s3c_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
139 unsigned int ep, unsigned int dir_in,
149 local_irq_save(flags);
150 daint = readl(hsotg->regs + DAINTMSK);
155 writel(daint, hsotg->regs + DAINTMSK);
156 local_irq_restore(flags);
160 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
161 * @hsotg: The device instance.
163 static void s3c_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
171 /* set FIFO sizes to 2048/1024 */
173 writel(2048, hsotg->regs + GRXFSIZ);
174 writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
175 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
178 * arange all the rest of the TX FIFOs, as some versions of this
179 * block have overlapping default addresses. This also ensures
180 * that if the settings have been changed, then they are set to
184 /* start at the end of the GNPTXFSIZ, rounded up */
188 * Because we have not enough memory to have each TX FIFO of size at
189 * least 3072 bytes (the maximum single packet size), we create four
190 * FIFOs of lenght 1024, and four of length 3072 bytes, and assing
191 * them to endpoints dynamically according to maxpacket size value of
195 /* 256*4=1024 bytes FIFO length */
197 for (ep = 1; ep <= 4; ep++) {
199 val |= size << FIFOSIZE_DEPTH_SHIFT;
200 WARN_ONCE(addr + size > hsotg->fifo_mem,
201 "insufficient fifo memory");
204 writel(val, hsotg->regs + DPTXFSIZN(ep));
206 /* 768*4=3072 bytes FIFO length */
208 for (ep = 5; ep <= 8; ep++) {
210 val |= size << FIFOSIZE_DEPTH_SHIFT;
211 WARN_ONCE(addr + size > hsotg->fifo_mem,
212 "insufficient fifo memory");
215 writel(val, hsotg->regs + DPTXFSIZN(ep));
219 * according to p428 of the design guide, we need to ensure that
220 * all fifos are flushed before continuing
223 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
224 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
226 /* wait until the fifos are both flushed */
229 val = readl(hsotg->regs + GRSTCTL);
231 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
234 if (--timeout == 0) {
236 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
243 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
247 * @ep: USB endpoint to allocate request for.
248 * @flags: Allocation flags
250 * Allocate a new USB request structure appropriate for the specified endpoint
252 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
255 struct s3c_hsotg_req *req;
257 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
261 INIT_LIST_HEAD(&req->queue);
267 * is_ep_periodic - return true if the endpoint is in periodic mode.
268 * @hs_ep: The endpoint to query.
270 * Returns true if the endpoint is in periodic mode, meaning it is being
271 * used for an Interrupt or ISO transfer.
273 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
275 return hs_ep->periodic;
279 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
280 * @hsotg: The device state.
281 * @hs_ep: The endpoint for the request
282 * @hs_req: The request being processed.
284 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
285 * of a request to ensure the buffer is ready for access by the caller.
287 static void s3c_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
288 struct s3c_hsotg_ep *hs_ep,
289 struct s3c_hsotg_req *hs_req)
291 struct usb_request *req = &hs_req->req;
293 /* ignore this if we're not moving any data */
294 if (hs_req->req.length == 0)
297 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
301 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
302 * @hsotg: The controller state.
303 * @hs_ep: The endpoint we're going to write for.
304 * @hs_req: The request to write data for.
306 * This is called when the TxFIFO has some space in it to hold a new
307 * transmission and we have something to give it. The actual setup of
308 * the data size is done elsewhere, so all we have to do is to actually
311 * The return value is zero if there is more space (or nothing was done)
312 * otherwise -ENOSPC is returned if the FIFO space was used up.
314 * This routine is only needed for PIO
316 static int s3c_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
317 struct s3c_hsotg_ep *hs_ep,
318 struct s3c_hsotg_req *hs_req)
320 bool periodic = is_ep_periodic(hs_ep);
321 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
322 int buf_pos = hs_req->req.actual;
323 int to_write = hs_ep->size_loaded;
329 to_write -= (buf_pos - hs_ep->last_load);
331 /* if there's nothing to write, get out early */
335 if (periodic && !hsotg->dedicated_fifos) {
336 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
341 * work out how much data was loaded so we can calculate
342 * how much data is left in the fifo.
345 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
348 * if shared fifo, we cannot write anything until the
349 * previous data has been completely sent.
351 if (hs_ep->fifo_load != 0) {
352 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
356 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
358 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
360 /* how much of the data has moved */
361 size_done = hs_ep->size_loaded - size_left;
363 /* how much data is left in the fifo */
364 can_write = hs_ep->fifo_load - size_done;
365 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
366 __func__, can_write);
368 can_write = hs_ep->fifo_size - can_write;
369 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
370 __func__, can_write);
372 if (can_write <= 0) {
373 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
376 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
377 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
382 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
384 "%s: no queue slots available (0x%08x)\n",
387 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
391 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
392 can_write *= 4; /* fifo size is in 32bit quantities. */
395 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
397 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
398 __func__, gnptxsts, can_write, to_write, max_transfer);
401 * limit to 512 bytes of data, it seems at least on the non-periodic
402 * FIFO, requests of >512 cause the endpoint to get stuck with a
403 * fragment of the end of the transfer in it.
405 if (can_write > 512 && !periodic)
409 * limit the write to one max-packet size worth of data, but allow
410 * the transfer to return that it did not run out of fifo space
413 if (to_write > max_transfer) {
414 to_write = max_transfer;
416 /* it's needed only when we do not use dedicated fifos */
417 if (!hsotg->dedicated_fifos)
418 s3c_hsotg_en_gsint(hsotg,
419 periodic ? GINTSTS_PTXFEMP :
423 /* see if we can write data */
425 if (to_write > can_write) {
426 to_write = can_write;
427 pkt_round = to_write % max_transfer;
430 * Round the write down to an
431 * exact number of packets.
433 * Note, we do not currently check to see if we can ever
434 * write a full packet or not to the FIFO.
438 to_write -= pkt_round;
441 * enable correct FIFO interrupt to alert us when there
445 /* it's needed only when we do not use dedicated fifos */
446 if (!hsotg->dedicated_fifos)
447 s3c_hsotg_en_gsint(hsotg,
448 periodic ? GINTSTS_PTXFEMP :
452 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
453 to_write, hs_req->req.length, can_write, buf_pos);
458 hs_req->req.actual = buf_pos + to_write;
459 hs_ep->total_data += to_write;
462 hs_ep->fifo_load += to_write;
464 to_write = DIV_ROUND_UP(to_write, 4);
465 data = hs_req->req.buf + buf_pos;
467 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
469 return (to_write >= can_write) ? -ENOSPC : 0;
473 * get_ep_limit - get the maximum data legnth for this endpoint
474 * @hs_ep: The endpoint
476 * Return the maximum data that can be queued in one go on a given endpoint
477 * so that transfers that are too long can be split.
479 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
481 int index = hs_ep->index;
486 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
487 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
491 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
496 /* we made the constant loading easier above by using +1 */
501 * constrain by packet count if maxpkts*pktsize is greater
502 * than the length register size.
505 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
506 maxsize = maxpkt * hs_ep->ep.maxpacket;
512 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
513 * @hsotg: The controller state.
514 * @hs_ep: The endpoint to process a request for
515 * @hs_req: The request to start.
516 * @continuing: True if we are doing more for the current request.
518 * Start the given request running by setting the endpoint registers
519 * appropriately, and writing any data to the FIFOs.
521 static void s3c_hsotg_start_req(struct dwc2_hsotg *hsotg,
522 struct s3c_hsotg_ep *hs_ep,
523 struct s3c_hsotg_req *hs_req,
526 struct usb_request *ureq = &hs_req->req;
527 int index = hs_ep->index;
528 int dir_in = hs_ep->dir_in;
538 if (hs_ep->req && !continuing) {
539 dev_err(hsotg->dev, "%s: active request\n", __func__);
542 } else if (hs_ep->req != hs_req && continuing) {
544 "%s: continue different req\n", __func__);
550 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
551 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
553 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
554 __func__, readl(hsotg->regs + epctrl_reg), index,
555 hs_ep->dir_in ? "in" : "out");
557 /* If endpoint is stalled, we will restart request later */
558 ctrl = readl(hsotg->regs + epctrl_reg);
560 if (ctrl & DXEPCTL_STALL) {
561 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
565 length = ureq->length - ureq->actual;
566 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
567 ureq->length, ureq->actual);
570 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
571 ureq->buf, length, &ureq->dma,
572 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
574 maxreq = get_ep_limit(hs_ep);
575 if (length > maxreq) {
576 int round = maxreq % hs_ep->ep.maxpacket;
578 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
579 __func__, length, maxreq, round);
581 /* round down to multiple of packets */
589 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
591 packets = 1; /* send one packet if length is zero. */
593 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
594 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
598 if (dir_in && index != 0)
599 if (hs_ep->isochronous)
600 epsize = DXEPTSIZ_MC(packets);
602 epsize = DXEPTSIZ_MC(1);
606 if (index != 0 && ureq->zero) {
608 * test for the packets being exactly right for the
612 if (length == (packets * hs_ep->ep.maxpacket))
616 epsize |= DXEPTSIZ_PKTCNT(packets);
617 epsize |= DXEPTSIZ_XFERSIZE(length);
619 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
620 __func__, packets, length, ureq->length, epsize, epsize_reg);
622 /* store the request as the current one we're doing */
625 /* write size / packets */
626 writel(epsize, hsotg->regs + epsize_reg);
628 if (using_dma(hsotg) && !continuing) {
629 unsigned int dma_reg;
632 * write DMA address to control register, buffer already
633 * synced by s3c_hsotg_ep_queue().
636 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
637 writel(ureq->dma, hsotg->regs + dma_reg);
639 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
640 __func__, &ureq->dma, dma_reg);
643 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
644 ctrl |= DXEPCTL_USBACTEP;
646 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
648 /* For Setup request do not clear NAK */
649 if (hsotg->setup && index == 0)
652 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
655 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
656 writel(ctrl, hsotg->regs + epctrl_reg);
659 * set these, it seems that DMA support increments past the end
660 * of the packet buffer so we need to calculate the length from
663 hs_ep->size_loaded = length;
664 hs_ep->last_load = ureq->actual;
666 if (dir_in && !using_dma(hsotg)) {
667 /* set these anyway, we may need them for non-periodic in */
668 hs_ep->fifo_load = 0;
670 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
674 * clear the INTknTXFEmpMsk when we start request, more as a aide
675 * to debugging to see what is going on.
678 writel(DIEPMSK_INTKNTXFEMPMSK,
679 hsotg->regs + DIEPINT(index));
682 * Note, trying to clear the NAK here causes problems with transmit
683 * on the S3C6400 ending up with the TXFIFO becoming full.
686 /* check ep is enabled */
687 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
689 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
690 index, readl(hsotg->regs + epctrl_reg));
692 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
693 __func__, readl(hsotg->regs + epctrl_reg));
695 /* enable ep interrupts */
696 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
700 * s3c_hsotg_map_dma - map the DMA memory being used for the request
701 * @hsotg: The device state.
702 * @hs_ep: The endpoint the request is on.
703 * @req: The request being processed.
705 * We've been asked to queue a request, so ensure that the memory buffer
706 * is correctly setup for DMA. If we've been passed an extant DMA address
707 * then ensure the buffer has been synced to memory. If our buffer has no
708 * DMA memory, then we map the memory and mark our request to allow us to
709 * cleanup on completion.
711 static int s3c_hsotg_map_dma(struct dwc2_hsotg *hsotg,
712 struct s3c_hsotg_ep *hs_ep,
713 struct usb_request *req)
715 struct s3c_hsotg_req *hs_req = our_req(req);
718 /* if the length is zero, ignore the DMA data */
719 if (hs_req->req.length == 0)
722 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
729 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
730 __func__, req->buf, req->length);
735 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
738 struct s3c_hsotg_req *hs_req = our_req(req);
739 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
740 struct dwc2_hsotg *hs = hs_ep->parent;
743 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
744 ep->name, req, req->length, req->buf, req->no_interrupt,
745 req->zero, req->short_not_ok);
747 /* initialise status of the request */
748 INIT_LIST_HEAD(&hs_req->queue);
750 req->status = -EINPROGRESS;
752 /* if we're using DMA, sync the buffers as necessary */
754 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
759 first = list_empty(&hs_ep->queue);
760 list_add_tail(&hs_req->queue, &hs_ep->queue);
763 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
768 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
771 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
772 struct dwc2_hsotg *hs = hs_ep->parent;
773 unsigned long flags = 0;
776 spin_lock_irqsave(&hs->lock, flags);
777 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
778 spin_unlock_irqrestore(&hs->lock, flags);
783 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
784 struct usb_request *req)
786 struct s3c_hsotg_req *hs_req = our_req(req);
792 * s3c_hsotg_complete_oursetup - setup completion callback
793 * @ep: The endpoint the request was on.
794 * @req: The request completed.
796 * Called on completion of any requests the driver itself
797 * submitted that need cleaning up.
799 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
800 struct usb_request *req)
802 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
803 struct dwc2_hsotg *hsotg = hs_ep->parent;
805 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
807 s3c_hsotg_ep_free_request(ep, req);
811 * ep_from_windex - convert control wIndex value to endpoint
812 * @hsotg: The driver state.
813 * @windex: The control request wIndex field (in host order).
815 * Convert the given wIndex into a pointer to an driver endpoint
816 * structure, or return NULL if it is not a valid endpoint.
818 static struct s3c_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
821 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
822 int dir = (windex & USB_DIR_IN) ? 1 : 0;
823 int idx = windex & 0x7F;
828 if (idx > hsotg->num_of_eps)
831 if (idx && ep->dir_in != dir)
838 * s3c_hsotg_send_reply - send reply to control request
839 * @hsotg: The device state
841 * @buff: Buffer for request
842 * @length: Length of reply.
844 * Create a request and queue it on the given endpoint. This is useful as
845 * an internal method of sending replies to certain control requests, etc.
847 static int s3c_hsotg_send_reply(struct dwc2_hsotg *hsotg,
848 struct s3c_hsotg_ep *ep,
852 struct usb_request *req;
855 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
857 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
858 hsotg->ep0_reply = req;
860 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
864 req->buf = hsotg->ep0_buff;
865 req->length = length;
866 req->zero = 1; /* always do zero-length final transfer */
867 req->complete = s3c_hsotg_complete_oursetup;
870 memcpy(req->buf, buff, length);
874 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
876 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
884 * s3c_hsotg_process_req_status - process request GET_STATUS
885 * @hsotg: The device state
886 * @ctrl: USB control request
888 static int s3c_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
889 struct usb_ctrlrequest *ctrl)
891 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
892 struct s3c_hsotg_ep *ep;
896 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
899 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
903 switch (ctrl->bRequestType & USB_RECIP_MASK) {
904 case USB_RECIP_DEVICE:
905 reply = cpu_to_le16(0); /* bit 0 => self powered,
906 * bit 1 => remote wakeup */
909 case USB_RECIP_INTERFACE:
910 /* currently, the data result should be zero */
911 reply = cpu_to_le16(0);
914 case USB_RECIP_ENDPOINT:
915 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
919 reply = cpu_to_le16(ep->halted ? 1 : 0);
926 if (le16_to_cpu(ctrl->wLength) != 2)
929 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
931 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
938 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
941 * get_ep_head - return the first request on the endpoint
942 * @hs_ep: The controller endpoint to get
944 * Get the first request on the endpoint.
946 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
948 if (list_empty(&hs_ep->queue))
951 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
955 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
956 * @hsotg: The device state
957 * @ctrl: USB control request
959 static int s3c_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
960 struct usb_ctrlrequest *ctrl)
962 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
963 struct s3c_hsotg_req *hs_req;
965 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
966 struct s3c_hsotg_ep *ep;
970 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
971 __func__, set ? "SET" : "CLEAR");
973 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
974 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
976 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
977 __func__, le16_to_cpu(ctrl->wIndex));
981 switch (le16_to_cpu(ctrl->wValue)) {
982 case USB_ENDPOINT_HALT:
985 s3c_hsotg_ep_sethalt(&ep->ep, set);
987 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
990 "%s: failed to send reply\n", __func__);
995 * we have to complete all requests for ep if it was
996 * halted, and the halt was cleared by CLEAR_FEATURE
999 if (!set && halted) {
1001 * If we have request in progress,
1007 list_del_init(&hs_req->queue);
1008 usb_gadget_giveback_request(&ep->ep,
1012 /* If we have pending request, then start it */
1013 restart = !list_empty(&ep->queue);
1015 hs_req = get_ep_head(ep);
1016 s3c_hsotg_start_req(hsotg, ep,
1027 return -ENOENT; /* currently only deal with endpoint */
1032 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1033 static void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg);
1036 * s3c_hsotg_stall_ep0 - stall ep0
1037 * @hsotg: The device state
1039 * Set stall for ep0 as response for setup request.
1041 static void s3c_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1043 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1047 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1048 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1051 * DxEPCTL_Stall will be cleared by EP once it has
1052 * taken effect, so no need to clear later.
1055 ctrl = readl(hsotg->regs + reg);
1056 ctrl |= DXEPCTL_STALL;
1057 ctrl |= DXEPCTL_CNAK;
1058 writel(ctrl, hsotg->regs + reg);
1061 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1062 ctrl, reg, readl(hsotg->regs + reg));
1065 * complete won't be called, so we enqueue
1066 * setup request here
1068 s3c_hsotg_enqueue_setup(hsotg);
1072 * s3c_hsotg_process_control - process a control request
1073 * @hsotg: The device state
1074 * @ctrl: The control request received
1076 * The controller has received the SETUP phase of a control request, and
1077 * needs to work out what to do next (and whether to pass it on to the
1080 static void s3c_hsotg_process_control(struct dwc2_hsotg *hsotg,
1081 struct usb_ctrlrequest *ctrl)
1083 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1089 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1090 ctrl->bRequest, ctrl->bRequestType,
1091 ctrl->wValue, ctrl->wLength);
1094 * record the direction of the request, for later use when enquing
1098 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1099 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1102 * if we've no data with this request, then the last part of the
1103 * transaction is going to implicitly be IN.
1105 if (ctrl->wLength == 0)
1108 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1109 switch (ctrl->bRequest) {
1110 case USB_REQ_SET_ADDRESS:
1111 s3c_hsotg_disconnect(hsotg);
1112 dcfg = readl(hsotg->regs + DCFG);
1113 dcfg &= ~DCFG_DEVADDR_MASK;
1114 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1115 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1116 writel(dcfg, hsotg->regs + DCFG);
1118 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1120 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1123 case USB_REQ_GET_STATUS:
1124 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1127 case USB_REQ_CLEAR_FEATURE:
1128 case USB_REQ_SET_FEATURE:
1129 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1134 /* as a fallback, try delivering it to the driver to deal with */
1136 if (ret == 0 && hsotg->driver) {
1137 spin_unlock(&hsotg->lock);
1138 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1139 spin_lock(&hsotg->lock);
1141 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1145 * the request is either unhandlable, or is not formatted correctly
1146 * so respond with a STALL for the status stage to indicate failure.
1150 s3c_hsotg_stall_ep0(hsotg);
1154 * s3c_hsotg_complete_setup - completion of a setup transfer
1155 * @ep: The endpoint the request was on.
1156 * @req: The request completed.
1158 * Called on completion of any requests the driver itself submitted for
1161 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1162 struct usb_request *req)
1164 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1165 struct dwc2_hsotg *hsotg = hs_ep->parent;
1167 if (req->status < 0) {
1168 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1172 spin_lock(&hsotg->lock);
1173 if (req->actual == 0)
1174 s3c_hsotg_enqueue_setup(hsotg);
1176 s3c_hsotg_process_control(hsotg, req->buf);
1177 spin_unlock(&hsotg->lock);
1181 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1182 * @hsotg: The device state.
1184 * Enqueue a request on EP0 if necessary to received any SETUP packets
1185 * received from the host.
1187 static void s3c_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1189 struct usb_request *req = hsotg->ctrl_req;
1190 struct s3c_hsotg_req *hs_req = our_req(req);
1193 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1197 req->buf = hsotg->ctrl_buff;
1198 req->complete = s3c_hsotg_complete_setup;
1200 if (!list_empty(&hs_req->queue)) {
1201 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1205 hsotg->eps[0].dir_in = 0;
1207 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1209 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1211 * Don't think there's much we can do other than watch the
1218 * s3c_hsotg_complete_request - complete a request given to us
1219 * @hsotg: The device state.
1220 * @hs_ep: The endpoint the request was on.
1221 * @hs_req: The request to complete.
1222 * @result: The result code (0 => Ok, otherwise errno)
1224 * The given request has finished, so call the necessary completion
1225 * if it has one and then look to see if we can start a new request
1228 * Note, expects the ep to already be locked as appropriate.
1230 static void s3c_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1231 struct s3c_hsotg_ep *hs_ep,
1232 struct s3c_hsotg_req *hs_req,
1238 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1242 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1243 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1246 * only replace the status if we've not already set an error
1247 * from a previous transaction
1250 if (hs_req->req.status == -EINPROGRESS)
1251 hs_req->req.status = result;
1254 list_del_init(&hs_req->queue);
1256 if (using_dma(hsotg))
1257 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1260 * call the complete request with the locks off, just in case the
1261 * request tries to queue more work for this endpoint.
1264 if (hs_req->req.complete) {
1265 spin_unlock(&hsotg->lock);
1266 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1267 spin_lock(&hsotg->lock);
1271 * Look to see if there is anything else to do. Note, the completion
1272 * of the previous request may have caused a new request to be started
1273 * so be careful when doing this.
1276 if (!hs_ep->req && result >= 0) {
1277 restart = !list_empty(&hs_ep->queue);
1279 hs_req = get_ep_head(hs_ep);
1280 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1286 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1287 * @hsotg: The device state.
1288 * @ep_idx: The endpoint index for the data
1289 * @size: The size of data in the fifo, in bytes
1291 * The FIFO status shows there is data to read from the FIFO for a given
1292 * endpoint, so sort out whether we need to read the data into a request
1293 * that has been made for that endpoint.
1295 static void s3c_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1297 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1298 struct s3c_hsotg_req *hs_req = hs_ep->req;
1299 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1306 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1309 dev_warn(hsotg->dev,
1310 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1311 __func__, size, ep_idx, epctl);
1313 /* dump the data from the FIFO, we've nothing we can do */
1314 for (ptr = 0; ptr < size; ptr += 4)
1321 read_ptr = hs_req->req.actual;
1322 max_req = hs_req->req.length - read_ptr;
1324 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1325 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1327 if (to_read > max_req) {
1329 * more data appeared than we where willing
1330 * to deal with in this request.
1333 /* currently we don't deal this */
1337 hs_ep->total_data += to_read;
1338 hs_req->req.actual += to_read;
1339 to_read = DIV_ROUND_UP(to_read, 4);
1342 * note, we might over-write the buffer end by 3 bytes depending on
1343 * alignment of the data.
1345 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1349 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1350 * @hsotg: The device instance
1351 * @req: The request currently on this endpoint
1353 * Generate a zero-length IN packet request for terminating a SETUP
1356 * Note, since we don't write any data to the TxFIFO, then it is
1357 * currently believed that we do not need to wait for any space in
1360 static void s3c_hsotg_send_zlp(struct dwc2_hsotg *hsotg,
1361 struct s3c_hsotg_req *req)
1366 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1370 if (req->req.length == 0) {
1371 hsotg->eps[0].sent_zlp = 1;
1372 s3c_hsotg_enqueue_setup(hsotg);
1376 hsotg->eps[0].dir_in = 1;
1377 hsotg->eps[0].sent_zlp = 1;
1379 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1381 /* issue a zero-sized packet to terminate this */
1382 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1383 DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
1385 ctrl = readl(hsotg->regs + DIEPCTL0);
1386 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1387 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1388 ctrl |= DXEPCTL_USBACTEP;
1389 writel(ctrl, hsotg->regs + DIEPCTL0);
1393 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1394 * @hsotg: The device instance
1395 * @epnum: The endpoint received from
1396 * @was_setup: Set if processing a SetupDone event.
1398 * The RXFIFO has delivered an OutDone event, which means that the data
1399 * transfer for an OUT endpoint has been completed, either by a short
1400 * packet or by the finish of a transfer.
1402 static void s3c_hsotg_handle_outdone(struct dwc2_hsotg *hsotg,
1403 int epnum, bool was_setup)
1405 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1406 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1407 struct s3c_hsotg_req *hs_req = hs_ep->req;
1408 struct usb_request *req = &hs_req->req;
1409 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1413 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1417 if (using_dma(hsotg)) {
1421 * Calculate the size of the transfer by checking how much
1422 * is left in the endpoint size register and then working it
1423 * out from the amount we loaded for the transfer.
1425 * We need to do this as DMA pointers are always 32bit aligned
1426 * so may overshoot/undershoot the transfer.
1429 size_done = hs_ep->size_loaded - size_left;
1430 size_done += hs_ep->last_load;
1432 req->actual = size_done;
1435 /* if there is more request to do, schedule new transfer */
1436 if (req->actual < req->length && size_left == 0) {
1437 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1439 } else if (epnum == 0) {
1441 * After was_setup = 1 =>
1442 * set CNAK for non Setup requests
1444 hsotg->setup = was_setup ? 0 : 1;
1447 if (req->actual < req->length && req->short_not_ok) {
1448 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1449 __func__, req->actual, req->length);
1452 * todo - what should we return here? there's no one else
1453 * even bothering to check the status.
1459 * Condition req->complete != s3c_hsotg_complete_setup says:
1460 * send ZLP when we have an asynchronous request from gadget
1462 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1463 s3c_hsotg_send_zlp(hsotg, hs_req);
1466 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1470 * s3c_hsotg_read_frameno - read current frame number
1471 * @hsotg: The device instance
1473 * Return the current frame number
1475 static u32 s3c_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1479 dsts = readl(hsotg->regs + DSTS);
1480 dsts &= DSTS_SOFFN_MASK;
1481 dsts >>= DSTS_SOFFN_SHIFT;
1487 * s3c_hsotg_handle_rx - RX FIFO has data
1488 * @hsotg: The device instance
1490 * The IRQ handler has detected that the RX FIFO has some data in it
1491 * that requires processing, so find out what is in there and do the
1494 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1495 * chunks, so if you have x packets received on an endpoint you'll get x
1496 * FIFO events delivered, each with a packet's worth of data in it.
1498 * When using DMA, we should not be processing events from the RXFIFO
1499 * as the actual data should be sent to the memory directly and we turn
1500 * on the completion interrupts to get notifications of transfer completion.
1502 static void s3c_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1504 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1505 u32 epnum, status, size;
1507 WARN_ON(using_dma(hsotg));
1509 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1510 status = grxstsr & GRXSTS_PKTSTS_MASK;
1512 size = grxstsr & GRXSTS_BYTECNT_MASK;
1513 size >>= GRXSTS_BYTECNT_SHIFT;
1516 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1517 __func__, grxstsr, size, epnum);
1519 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1520 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1521 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1524 case GRXSTS_PKTSTS_OUTDONE:
1525 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1526 s3c_hsotg_read_frameno(hsotg));
1528 if (!using_dma(hsotg))
1529 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1532 case GRXSTS_PKTSTS_SETUPDONE:
1534 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1535 s3c_hsotg_read_frameno(hsotg),
1536 readl(hsotg->regs + DOEPCTL(0)));
1538 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1541 case GRXSTS_PKTSTS_OUTRX:
1542 s3c_hsotg_rx_data(hsotg, epnum, size);
1545 case GRXSTS_PKTSTS_SETUPRX:
1547 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1548 s3c_hsotg_read_frameno(hsotg),
1549 readl(hsotg->regs + DOEPCTL(0)));
1551 s3c_hsotg_rx_data(hsotg, epnum, size);
1555 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1558 s3c_hsotg_dump(hsotg);
1564 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1565 * @mps: The maximum packet size in bytes.
1567 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1571 return D0EPCTL_MPS_64;
1573 return D0EPCTL_MPS_32;
1575 return D0EPCTL_MPS_16;
1577 return D0EPCTL_MPS_8;
1580 /* bad max packet size, warn and return invalid result */
1586 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1587 * @hsotg: The driver state.
1588 * @ep: The index number of the endpoint
1589 * @mps: The maximum packet size in bytes
1591 * Configure the maximum packet size for the given endpoint, updating
1592 * the hardware control registers to reflect this.
1594 static void s3c_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1595 unsigned int ep, unsigned int mps)
1597 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1598 void __iomem *regs = hsotg->regs;
1604 /* EP0 is a special case */
1605 mpsval = s3c_hsotg_ep0_mps(mps);
1608 hs_ep->ep.maxpacket = mps;
1611 mpsval = mps & DXEPCTL_MPS_MASK;
1614 mcval = ((mps >> 11) & 0x3) + 1;
1618 hs_ep->ep.maxpacket = mpsval;
1622 * update both the in and out endpoint controldir_ registers, even
1623 * if one of the directions may not be in use.
1626 reg = readl(regs + DIEPCTL(ep));
1627 reg &= ~DXEPCTL_MPS_MASK;
1629 writel(reg, regs + DIEPCTL(ep));
1632 reg = readl(regs + DOEPCTL(ep));
1633 reg &= ~DXEPCTL_MPS_MASK;
1635 writel(reg, regs + DOEPCTL(ep));
1641 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1645 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1646 * @hsotg: The driver state
1647 * @idx: The index for the endpoint (0..15)
1649 static void s3c_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1654 writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1655 hsotg->regs + GRSTCTL);
1657 /* wait until the fifo is flushed */
1661 val = readl(hsotg->regs + GRSTCTL);
1663 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1666 if (--timeout == 0) {
1668 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1678 * s3c_hsotg_trytx - check to see if anything needs transmitting
1679 * @hsotg: The driver state
1680 * @hs_ep: The driver endpoint to check.
1682 * Check to see if there is a request that has data to send, and if so
1683 * make an attempt to write data into the FIFO.
1685 static int s3c_hsotg_trytx(struct dwc2_hsotg *hsotg,
1686 struct s3c_hsotg_ep *hs_ep)
1688 struct s3c_hsotg_req *hs_req = hs_ep->req;
1690 if (!hs_ep->dir_in || !hs_req) {
1692 * if request is not enqueued, we disable interrupts
1693 * for endpoints, excepting ep0
1695 if (hs_ep->index != 0)
1696 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1701 if (hs_req->req.actual < hs_req->req.length) {
1702 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1704 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1711 * s3c_hsotg_complete_in - complete IN transfer
1712 * @hsotg: The device state.
1713 * @hs_ep: The endpoint that has just completed.
1715 * An IN transfer has been completed, update the transfer's state and then
1716 * call the relevant completion routines.
1718 static void s3c_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1719 struct s3c_hsotg_ep *hs_ep)
1721 struct s3c_hsotg_req *hs_req = hs_ep->req;
1722 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1723 int size_left, size_done;
1726 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1730 /* Finish ZLP handling for IN EP0 transactions */
1731 if (hsotg->eps[0].sent_zlp) {
1732 dev_dbg(hsotg->dev, "zlp packet received\n");
1733 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1738 * Calculate the size of the transfer by checking how much is left
1739 * in the endpoint size register and then working it out from
1740 * the amount we loaded for the transfer.
1742 * We do this even for DMA, as the transfer may have incremented
1743 * past the end of the buffer (DMA transfers are always 32bit
1747 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1749 size_done = hs_ep->size_loaded - size_left;
1750 size_done += hs_ep->last_load;
1752 if (hs_req->req.actual != size_done)
1753 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1754 __func__, hs_req->req.actual, size_done);
1756 hs_req->req.actual = size_done;
1757 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1758 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1761 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1762 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1763 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1764 * inform the host that no more data is available.
1765 * The state of req.zero member is checked to be sure that the value to
1766 * send is smaller than wValue expected from host.
1767 * Check req.length to NOT send another ZLP when the current one is
1768 * under completion (the one for which this completion has been called).
1770 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1771 hs_req->req.length == hs_req->req.actual &&
1772 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1774 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1775 s3c_hsotg_send_zlp(hsotg, hs_req);
1780 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1781 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1782 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1784 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1788 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1789 * @hsotg: The driver state
1790 * @idx: The index for the endpoint (0..15)
1791 * @dir_in: Set if this is an IN endpoint
1793 * Process and clear any interrupt pending for an individual endpoint
1795 static void s3c_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1798 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1799 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1800 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1801 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1805 ints = readl(hsotg->regs + epint_reg);
1806 ctrl = readl(hsotg->regs + epctl_reg);
1808 /* Clear endpoint interrupts */
1809 writel(ints, hsotg->regs + epint_reg);
1811 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1812 __func__, idx, dir_in ? "in" : "out", ints);
1814 if (ints & DXEPINT_XFERCOMPL) {
1815 if (hs_ep->isochronous && hs_ep->interval == 1) {
1816 if (ctrl & DXEPCTL_EOFRNUM)
1817 ctrl |= DXEPCTL_SETEVENFR;
1819 ctrl |= DXEPCTL_SETODDFR;
1820 writel(ctrl, hsotg->regs + epctl_reg);
1824 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1825 __func__, readl(hsotg->regs + epctl_reg),
1826 readl(hsotg->regs + epsiz_reg));
1829 * we get OutDone from the FIFO, so we only need to look
1830 * at completing IN requests here
1833 s3c_hsotg_complete_in(hsotg, hs_ep);
1835 if (idx == 0 && !hs_ep->req)
1836 s3c_hsotg_enqueue_setup(hsotg);
1837 } else if (using_dma(hsotg)) {
1839 * We're using DMA, we need to fire an OutDone here
1840 * as we ignore the RXFIFO.
1843 s3c_hsotg_handle_outdone(hsotg, idx, false);
1847 if (ints & DXEPINT_EPDISBLD) {
1848 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1851 int epctl = readl(hsotg->regs + epctl_reg);
1853 s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
1855 if ((epctl & DXEPCTL_STALL) &&
1856 (epctl & DXEPCTL_EPTYPE_BULK)) {
1857 int dctl = readl(hsotg->regs + DCTL);
1859 dctl |= DCTL_CGNPINNAK;
1860 writel(dctl, hsotg->regs + DCTL);
1865 if (ints & DXEPINT_AHBERR)
1866 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1868 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
1869 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1871 if (using_dma(hsotg) && idx == 0) {
1873 * this is the notification we've received a
1874 * setup packet. In non-DMA mode we'd get this
1875 * from the RXFIFO, instead we need to process
1882 s3c_hsotg_handle_outdone(hsotg, 0, true);
1886 if (ints & DXEPINT_BACK2BACKSETUP)
1887 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1889 if (dir_in && !hs_ep->isochronous) {
1890 /* not sure if this is important, but we'll clear it anyway */
1891 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
1892 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1896 /* this probably means something bad is happening */
1897 if (ints & DIEPMSK_INTKNEPMISMSK) {
1898 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1902 /* FIFO has space or is empty (see GAHBCFG) */
1903 if (hsotg->dedicated_fifos &&
1904 ints & DIEPMSK_TXFIFOEMPTY) {
1905 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1907 if (!using_dma(hsotg))
1908 s3c_hsotg_trytx(hsotg, hs_ep);
1914 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1915 * @hsotg: The device state.
1917 * Handle updating the device settings after the enumeration phase has
1920 static void s3c_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
1922 u32 dsts = readl(hsotg->regs + DSTS);
1923 int ep0_mps = 0, ep_mps = 8;
1926 * This should signal the finish of the enumeration phase
1927 * of the USB handshaking, so we should now know what rate
1931 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1934 * note, since we're limited by the size of transfer on EP0, and
1935 * it seems IN transfers must be a even number of packets we do
1936 * not advertise a 64byte MPS on EP0.
1939 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1940 switch (dsts & DSTS_ENUMSPD_MASK) {
1941 case DSTS_ENUMSPD_FS:
1942 case DSTS_ENUMSPD_FS48:
1943 hsotg->gadget.speed = USB_SPEED_FULL;
1944 ep0_mps = EP0_MPS_LIMIT;
1948 case DSTS_ENUMSPD_HS:
1949 hsotg->gadget.speed = USB_SPEED_HIGH;
1950 ep0_mps = EP0_MPS_LIMIT;
1954 case DSTS_ENUMSPD_LS:
1955 hsotg->gadget.speed = USB_SPEED_LOW;
1957 * note, we don't actually support LS in this driver at the
1958 * moment, and the documentation seems to imply that it isn't
1959 * supported by the PHYs on some of the devices.
1963 dev_info(hsotg->dev, "new device is %s\n",
1964 usb_speed_string(hsotg->gadget.speed));
1967 * we should now know the maximum packet size for an
1968 * endpoint, so set the endpoints to a default value.
1973 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1974 for (i = 1; i < hsotg->num_of_eps; i++)
1975 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1978 /* ensure after enumeration our EP0 is active */
1980 s3c_hsotg_enqueue_setup(hsotg);
1982 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1983 readl(hsotg->regs + DIEPCTL0),
1984 readl(hsotg->regs + DOEPCTL0));
1988 * kill_all_requests - remove all requests from the endpoint's queue
1989 * @hsotg: The device state.
1990 * @ep: The endpoint the requests may be on.
1991 * @result: The result code to use.
1992 * @force: Force removal of any current requests
1994 * Go through the requests on the given endpoint and mark them
1995 * completed with the given result code.
1997 static void kill_all_requests(struct dwc2_hsotg *hsotg,
1998 struct s3c_hsotg_ep *ep,
1999 int result, bool force)
2001 struct s3c_hsotg_req *req, *treq;
2004 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2006 * currently, we can't do much about an already
2007 * running request on an in endpoint
2010 if (ep->req == req && ep->dir_in && !force)
2013 s3c_hsotg_complete_request(hsotg, ep, req,
2016 if (!hsotg->dedicated_fifos)
2018 size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2019 if (size < ep->fifo_size)
2020 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2024 * s3c_hsotg_disconnect - disconnect service
2025 * @hsotg: The device state.
2027 * The device has been disconnected. Remove all current
2028 * transactions and signal the gadget driver that this
2031 static void s3c_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2035 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2036 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2038 call_gadget(hsotg, disconnect);
2042 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2043 * @hsotg: The device state:
2044 * @periodic: True if this is a periodic FIFO interrupt
2046 static void s3c_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2048 struct s3c_hsotg_ep *ep;
2051 /* look through for any more data to transmit */
2053 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2054 ep = &hsotg->eps[epno];
2059 if ((periodic && !ep->periodic) ||
2060 (!periodic && ep->periodic))
2063 ret = s3c_hsotg_trytx(hsotg, ep);
2069 /* IRQ flags which will trigger a retry around the IRQ loop */
2070 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2075 * s3c_hsotg_corereset - issue softreset to the core
2076 * @hsotg: The device state
2078 * Issue a soft reset to the core, and await the core finishing it.
2080 static int s3c_hsotg_corereset(struct dwc2_hsotg *hsotg)
2085 dev_dbg(hsotg->dev, "resetting core\n");
2087 /* issue soft reset */
2088 writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
2092 grstctl = readl(hsotg->regs + GRSTCTL);
2093 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
2095 if (grstctl & GRSTCTL_CSFTRST) {
2096 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2103 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2105 if (timeout-- < 0) {
2106 dev_info(hsotg->dev,
2107 "%s: reset failed, GRSTCTL=%08x\n",
2112 if (!(grstctl & GRSTCTL_AHBIDLE))
2115 break; /* reset done */
2118 dev_dbg(hsotg->dev, "reset successful\n");
2123 * s3c_hsotg_core_init - issue softreset to the core
2124 * @hsotg: The device state
2126 * Issue a soft reset to the core, and await the core finishing it.
2128 static void s3c_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg)
2130 s3c_hsotg_corereset(hsotg);
2133 * we must now enable ep0 ready for host detection and then
2134 * set configuration.
2137 /* set the PLL on, remove the HNP/SRP and set the PHY */
2138 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2139 (0x5 << 10), hsotg->regs + GUSBCFG);
2141 s3c_hsotg_init_fifo(hsotg);
2143 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2145 writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2147 /* Clear any pending OTG interrupts */
2148 writel(0xffffffff, hsotg->regs + GOTGINT);
2150 /* Clear any pending interrupts */
2151 writel(0xffffffff, hsotg->regs + GINTSTS);
2153 writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2154 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2155 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2156 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2157 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2158 hsotg->regs + GINTMSK);
2160 if (using_dma(hsotg))
2161 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2162 GAHBCFG_HBSTLEN_INCR4,
2163 hsotg->regs + GAHBCFG);
2165 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2166 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2167 GAHBCFG_GLBL_INTR_EN,
2168 hsotg->regs + GAHBCFG);
2171 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2172 * when we have no data to transfer. Otherwise we get being flooded by
2176 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
2177 DIEPMSK_INTKNTXFEMPMSK : 0) |
2178 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2179 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2180 DIEPMSK_INTKNEPMISMSK,
2181 hsotg->regs + DIEPMSK);
2184 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2185 * DMA mode we may need this.
2187 writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2188 DIEPMSK_TIMEOUTMSK) : 0) |
2189 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2191 hsotg->regs + DOEPMSK);
2193 writel(0, hsotg->regs + DAINTMSK);
2195 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2196 readl(hsotg->regs + DIEPCTL0),
2197 readl(hsotg->regs + DOEPCTL0));
2199 /* enable in and out endpoint interrupts */
2200 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2203 * Enable the RXFIFO when in slave mode, as this is how we collect
2204 * the data. In DMA mode, we get events from the FIFO but also
2205 * things we cannot process, so do not use it.
2207 if (!using_dma(hsotg))
2208 s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2210 /* Enable interrupts for EP0 in and out */
2211 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2212 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2214 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2215 udelay(10); /* see openiboot */
2216 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2218 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2221 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2222 * writing to the EPCTL register..
2225 /* set to read 1 8byte packet */
2226 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2227 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2229 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2230 DXEPCTL_CNAK | DXEPCTL_EPENA |
2232 hsotg->regs + DOEPCTL0);
2234 /* enable, but don't activate EP0in */
2235 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2236 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2238 s3c_hsotg_enqueue_setup(hsotg);
2240 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2241 readl(hsotg->regs + DIEPCTL0),
2242 readl(hsotg->regs + DOEPCTL0));
2244 /* clear global NAKs */
2245 writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK | DCTL_SFTDISCON,
2246 hsotg->regs + DCTL);
2248 /* must be at-least 3ms to allow bus to see disconnect */
2251 hsotg->last_rst = jiffies;
2254 static void s3c_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2256 /* set the soft-disconnect bit */
2257 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2260 static void s3c_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2262 /* remove the soft-disconnect and let's go */
2263 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2267 * s3c_hsotg_irq - handle device interrupt
2268 * @irq: The IRQ number triggered
2269 * @pw: The pw value when registered the handler.
2271 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2273 struct dwc2_hsotg *hsotg = pw;
2274 int retry_count = 8;
2278 spin_lock(&hsotg->lock);
2280 gintsts = readl(hsotg->regs + GINTSTS);
2281 gintmsk = readl(hsotg->regs + GINTMSK);
2283 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2284 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2288 if (gintsts & GINTSTS_OTGINT) {
2289 u32 otgint = readl(hsotg->regs + GOTGINT);
2291 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2293 writel(otgint, hsotg->regs + GOTGINT);
2296 if (gintsts & GINTSTS_SESSREQINT) {
2297 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2298 writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
2301 if (gintsts & GINTSTS_ENUMDONE) {
2302 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2304 s3c_hsotg_irq_enumdone(hsotg);
2307 if (gintsts & GINTSTS_CONIDSTSCHNG) {
2308 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2309 readl(hsotg->regs + DSTS),
2310 readl(hsotg->regs + GOTGCTL));
2312 writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
2315 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2316 u32 daint = readl(hsotg->regs + DAINT);
2317 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2318 u32 daint_out, daint_in;
2322 daint_out = daint >> DAINT_OUTEP_SHIFT;
2323 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2325 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2327 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2329 s3c_hsotg_epint(hsotg, ep, 0);
2332 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2334 s3c_hsotg_epint(hsotg, ep, 1);
2338 if (gintsts & GINTSTS_USBRST) {
2340 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2342 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2343 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2344 readl(hsotg->regs + GNPTXSTS));
2346 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2348 if (usb_status & GOTGCTL_BSESVLD) {
2349 if (time_after(jiffies, hsotg->last_rst +
2350 msecs_to_jiffies(200))) {
2352 kill_all_requests(hsotg, &hsotg->eps[0],
2355 s3c_hsotg_core_init_disconnected(hsotg);
2356 s3c_hsotg_core_connect(hsotg);
2361 /* check both FIFOs */
2363 if (gintsts & GINTSTS_NPTXFEMP) {
2364 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2367 * Disable the interrupt to stop it happening again
2368 * unless one of these endpoint routines decides that
2369 * it needs re-enabling
2372 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2373 s3c_hsotg_irq_fifoempty(hsotg, false);
2376 if (gintsts & GINTSTS_PTXFEMP) {
2377 dev_dbg(hsotg->dev, "PTxFEmp\n");
2379 /* See note in GINTSTS_NPTxFEmp */
2381 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2382 s3c_hsotg_irq_fifoempty(hsotg, true);
2385 if (gintsts & GINTSTS_RXFLVL) {
2387 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2388 * we need to retry s3c_hsotg_handle_rx if this is still
2392 s3c_hsotg_handle_rx(hsotg);
2395 if (gintsts & GINTSTS_MODEMIS) {
2396 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2397 writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
2400 if (gintsts & GINTSTS_USBSUSP) {
2401 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2402 writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
2404 call_gadget(hsotg, suspend);
2407 if (gintsts & GINTSTS_WKUPINT) {
2408 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2409 writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
2411 call_gadget(hsotg, resume);
2414 if (gintsts & GINTSTS_ERLYSUSP) {
2415 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2416 writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2420 * these next two seem to crop-up occasionally causing the core
2421 * to shutdown the USB transfer, so try clearing them and logging
2425 if (gintsts & GINTSTS_GOUTNAKEFF) {
2426 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2428 writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
2430 s3c_hsotg_dump(hsotg);
2433 if (gintsts & GINTSTS_GINNAKEFF) {
2434 dev_info(hsotg->dev, "GINNakEff triggered\n");
2436 writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2438 s3c_hsotg_dump(hsotg);
2442 * if we've had fifo events, we should try and go around the
2443 * loop again to see if there's any point in returning yet.
2446 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2449 spin_unlock(&hsotg->lock);
2455 * s3c_hsotg_ep_enable - enable the given endpoint
2456 * @ep: The USB endpint to configure
2457 * @desc: The USB endpoint descriptor to configure with.
2459 * This is called from the USB gadget code's usb_ep_enable().
2461 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2462 const struct usb_endpoint_descriptor *desc)
2464 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2465 struct dwc2_hsotg *hsotg = hs_ep->parent;
2466 unsigned long flags;
2467 int index = hs_ep->index;
2476 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2477 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2478 desc->wMaxPacketSize, desc->bInterval);
2480 /* not to be called for EP0 */
2481 WARN_ON(index == 0);
2483 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2484 if (dir_in != hs_ep->dir_in) {
2485 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2489 mps = usb_endpoint_maxp(desc);
2491 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2493 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2494 epctrl = readl(hsotg->regs + epctrl_reg);
2496 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2497 __func__, epctrl, epctrl_reg);
2499 spin_lock_irqsave(&hsotg->lock, flags);
2501 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2502 epctrl |= DXEPCTL_MPS(mps);
2505 * mark the endpoint as active, otherwise the core may ignore
2506 * transactions entirely for this endpoint
2508 epctrl |= DXEPCTL_USBACTEP;
2511 * set the NAK status on the endpoint, otherwise we might try and
2512 * do something with data that we've yet got a request to process
2513 * since the RXFIFO will take data for an endpoint even if the
2514 * size register hasn't been set.
2517 epctrl |= DXEPCTL_SNAK;
2519 /* update the endpoint state */
2520 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2522 /* default, set to non-periodic */
2523 hs_ep->isochronous = 0;
2524 hs_ep->periodic = 0;
2526 hs_ep->interval = desc->bInterval;
2528 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2529 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2531 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2532 case USB_ENDPOINT_XFER_ISOC:
2533 epctrl |= DXEPCTL_EPTYPE_ISO;
2534 epctrl |= DXEPCTL_SETEVENFR;
2535 hs_ep->isochronous = 1;
2537 hs_ep->periodic = 1;
2540 case USB_ENDPOINT_XFER_BULK:
2541 epctrl |= DXEPCTL_EPTYPE_BULK;
2544 case USB_ENDPOINT_XFER_INT:
2546 hs_ep->periodic = 1;
2548 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2551 case USB_ENDPOINT_XFER_CONTROL:
2552 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2557 * if the hardware has dedicated fifos, we must give each IN EP
2558 * a unique tx-fifo even if it is non-periodic.
2560 if (dir_in && hsotg->dedicated_fifos) {
2561 size = hs_ep->ep.maxpacket*hs_ep->mc;
2562 for (i = 1; i <= 8; ++i) {
2563 if (hsotg->fifo_map & (1<<i))
2565 val = readl(hsotg->regs + DPTXFSIZN(i));
2566 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2569 hsotg->fifo_map |= 1<<i;
2571 epctrl |= DXEPCTL_TXFNUM(i);
2572 hs_ep->fifo_index = i;
2573 hs_ep->fifo_size = val;
2582 /* for non control endpoints, set PID to D0 */
2584 epctrl |= DXEPCTL_SETD0PID;
2586 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2589 writel(epctrl, hsotg->regs + epctrl_reg);
2590 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2591 __func__, readl(hsotg->regs + epctrl_reg));
2593 /* enable the endpoint interrupt */
2594 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2597 spin_unlock_irqrestore(&hsotg->lock, flags);
2602 * s3c_hsotg_ep_disable - disable given endpoint
2603 * @ep: The endpoint to disable.
2605 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2607 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2608 struct dwc2_hsotg *hsotg = hs_ep->parent;
2609 int dir_in = hs_ep->dir_in;
2610 int index = hs_ep->index;
2611 unsigned long flags;
2615 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2617 if (ep == &hsotg->eps[0].ep) {
2618 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2622 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2624 spin_lock_irqsave(&hsotg->lock, flags);
2625 /* terminate all requests with shutdown */
2626 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2628 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2629 hs_ep->fifo_index = 0;
2630 hs_ep->fifo_size = 0;
2632 ctrl = readl(hsotg->regs + epctrl_reg);
2633 ctrl &= ~DXEPCTL_EPENA;
2634 ctrl &= ~DXEPCTL_USBACTEP;
2635 ctrl |= DXEPCTL_SNAK;
2637 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2638 writel(ctrl, hsotg->regs + epctrl_reg);
2640 /* disable endpoint interrupts */
2641 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2643 spin_unlock_irqrestore(&hsotg->lock, flags);
2648 * on_list - check request is on the given endpoint
2649 * @ep: The endpoint to check.
2650 * @test: The request to test if it is on the endpoint.
2652 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2654 struct s3c_hsotg_req *req, *treq;
2656 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2665 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2666 * @ep: The endpoint to dequeue.
2667 * @req: The request to be removed from a queue.
2669 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2671 struct s3c_hsotg_req *hs_req = our_req(req);
2672 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2673 struct dwc2_hsotg *hs = hs_ep->parent;
2674 unsigned long flags;
2676 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2678 spin_lock_irqsave(&hs->lock, flags);
2680 if (!on_list(hs_ep, hs_req)) {
2681 spin_unlock_irqrestore(&hs->lock, flags);
2685 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2686 spin_unlock_irqrestore(&hs->lock, flags);
2692 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2693 * @ep: The endpoint to set halt.
2694 * @value: Set or unset the halt.
2696 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2698 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2699 struct dwc2_hsotg *hs = hs_ep->parent;
2700 int index = hs_ep->index;
2705 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2709 s3c_hsotg_stall_ep0(hs);
2712 "%s: can't clear halt on ep0\n", __func__);
2716 /* write both IN and OUT control registers */
2718 epreg = DIEPCTL(index);
2719 epctl = readl(hs->regs + epreg);
2722 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2723 if (epctl & DXEPCTL_EPENA)
2724 epctl |= DXEPCTL_EPDIS;
2726 epctl &= ~DXEPCTL_STALL;
2727 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2728 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2729 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2730 epctl |= DXEPCTL_SETD0PID;
2733 writel(epctl, hs->regs + epreg);
2735 epreg = DOEPCTL(index);
2736 epctl = readl(hs->regs + epreg);
2739 epctl |= DXEPCTL_STALL;
2741 epctl &= ~DXEPCTL_STALL;
2742 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2743 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2744 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2745 epctl |= DXEPCTL_SETD0PID;
2748 writel(epctl, hs->regs + epreg);
2750 hs_ep->halted = value;
2756 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2757 * @ep: The endpoint to set halt.
2758 * @value: Set or unset the halt.
2760 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2762 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2763 struct dwc2_hsotg *hs = hs_ep->parent;
2764 unsigned long flags = 0;
2767 spin_lock_irqsave(&hs->lock, flags);
2768 ret = s3c_hsotg_ep_sethalt(ep, value);
2769 spin_unlock_irqrestore(&hs->lock, flags);
2774 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2775 .enable = s3c_hsotg_ep_enable,
2776 .disable = s3c_hsotg_ep_disable,
2777 .alloc_request = s3c_hsotg_ep_alloc_request,
2778 .free_request = s3c_hsotg_ep_free_request,
2779 .queue = s3c_hsotg_ep_queue_lock,
2780 .dequeue = s3c_hsotg_ep_dequeue,
2781 .set_halt = s3c_hsotg_ep_sethalt_lock,
2782 /* note, don't believe we have any call for the fifo routines */
2786 * s3c_hsotg_phy_enable - enable platform phy dev
2787 * @hsotg: The driver state
2789 * A wrapper for platform code responsible for controlling
2790 * low-level USB code
2792 static void s3c_hsotg_phy_enable(struct dwc2_hsotg *hsotg)
2794 struct platform_device *pdev = to_platform_device(hsotg->dev);
2796 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2799 usb_phy_init(hsotg->uphy);
2800 else if (hsotg->plat && hsotg->plat->phy_init)
2801 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2803 phy_init(hsotg->phy);
2804 phy_power_on(hsotg->phy);
2809 * s3c_hsotg_phy_disable - disable platform phy dev
2810 * @hsotg: The driver state
2812 * A wrapper for platform code responsible for controlling
2813 * low-level USB code
2815 static void s3c_hsotg_phy_disable(struct dwc2_hsotg *hsotg)
2817 struct platform_device *pdev = to_platform_device(hsotg->dev);
2820 usb_phy_shutdown(hsotg->uphy);
2821 else if (hsotg->plat && hsotg->plat->phy_exit)
2822 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2824 phy_power_off(hsotg->phy);
2825 phy_exit(hsotg->phy);
2830 * s3c_hsotg_init - initalize the usb core
2831 * @hsotg: The driver state
2833 static void s3c_hsotg_init(struct dwc2_hsotg *hsotg)
2835 /* unmask subset of endpoint interrupts */
2837 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2838 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2839 hsotg->regs + DIEPMSK);
2841 writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2842 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2843 hsotg->regs + DOEPMSK);
2845 writel(0, hsotg->regs + DAINTMSK);
2847 /* Be in disconnected state until gadget is registered */
2848 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2851 /* post global nak until we're ready */
2852 writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2853 hsotg->regs + DCTL);
2858 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2859 readl(hsotg->regs + GRXFSIZ),
2860 readl(hsotg->regs + GNPTXFSIZ));
2862 s3c_hsotg_init_fifo(hsotg);
2864 /* set the PLL on, remove the HNP/SRP and set the PHY */
2865 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2866 hsotg->regs + GUSBCFG);
2868 writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
2869 hsotg->regs + GAHBCFG);
2873 * s3c_hsotg_udc_start - prepare the udc for work
2874 * @gadget: The usb gadget state
2875 * @driver: The usb gadget driver
2877 * Perform initialization to prepare udc device and driver
2880 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2881 struct usb_gadget_driver *driver)
2883 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2884 unsigned long flags;
2888 pr_err("%s: called with no device\n", __func__);
2893 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2897 if (driver->max_speed < USB_SPEED_FULL)
2898 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2900 if (!driver->setup) {
2901 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2905 WARN_ON(hsotg->driver);
2907 driver->driver.bus = NULL;
2908 hsotg->driver = driver;
2909 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
2910 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2912 clk_enable(hsotg->clk);
2914 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2917 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2921 s3c_hsotg_phy_enable(hsotg);
2923 spin_lock_irqsave(&hsotg->lock, flags);
2924 s3c_hsotg_init(hsotg);
2925 s3c_hsotg_core_init_disconnected(hsotg);
2926 spin_unlock_irqrestore(&hsotg->lock, flags);
2928 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2933 hsotg->driver = NULL;
2938 * s3c_hsotg_udc_stop - stop the udc
2939 * @gadget: The usb gadget state
2940 * @driver: The usb gadget driver
2942 * Stop udc hw block and stay tunned for future transmissions
2944 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget)
2946 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2947 unsigned long flags = 0;
2953 /* all endpoints should be shutdown */
2954 for (ep = 1; ep < hsotg->num_of_eps; ep++)
2955 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2957 spin_lock_irqsave(&hsotg->lock, flags);
2959 hsotg->driver = NULL;
2960 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2962 spin_unlock_irqrestore(&hsotg->lock, flags);
2964 s3c_hsotg_phy_disable(hsotg);
2966 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2968 clk_disable(hsotg->clk);
2974 * s3c_hsotg_gadget_getframe - read the frame number
2975 * @gadget: The usb gadget state
2977 * Read the {micro} frame number
2979 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2981 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2985 * s3c_hsotg_pullup - connect/disconnect the USB PHY
2986 * @gadget: The usb gadget state
2987 * @is_on: Current state of the USB PHY
2989 * Connect/Disconnect the USB PHY pullup
2991 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
2993 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
2994 unsigned long flags = 0;
2996 dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on);
2998 spin_lock_irqsave(&hsotg->lock, flags);
3000 clk_enable(hsotg->clk);
3001 s3c_hsotg_core_connect(hsotg);
3003 s3c_hsotg_core_disconnect(hsotg);
3004 clk_disable(hsotg->clk);
3007 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3008 spin_unlock_irqrestore(&hsotg->lock, flags);
3013 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3014 .get_frame = s3c_hsotg_gadget_getframe,
3015 .udc_start = s3c_hsotg_udc_start,
3016 .udc_stop = s3c_hsotg_udc_stop,
3017 .pullup = s3c_hsotg_pullup,
3021 * s3c_hsotg_initep - initialise a single endpoint
3022 * @hsotg: The device state.
3023 * @hs_ep: The endpoint to be initialised.
3024 * @epnum: The endpoint number
3026 * Initialise the given endpoint (as part of the probe and device state
3027 * creation) to give to the gadget driver. Setup the endpoint name, any
3028 * direction information and other state that may be required.
3030 static void s3c_hsotg_initep(struct dwc2_hsotg *hsotg,
3031 struct s3c_hsotg_ep *hs_ep,
3038 else if ((epnum % 2) == 0) {
3045 hs_ep->index = epnum;
3047 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3049 INIT_LIST_HEAD(&hs_ep->queue);
3050 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3052 /* add to the list of endpoints known by the gadget driver */
3054 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3056 hs_ep->parent = hsotg;
3057 hs_ep->ep.name = hs_ep->name;
3058 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3059 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3062 * if we're using dma, we need to set the next-endpoint pointer
3063 * to be something valid.
3066 if (using_dma(hsotg)) {
3067 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3068 writel(next, hsotg->regs + DIEPCTL(epnum));
3069 writel(next, hsotg->regs + DOEPCTL(epnum));
3074 * s3c_hsotg_hw_cfg - read HW configuration registers
3075 * @param: The device state
3077 * Read the USB core HW configuration registers
3079 static void s3c_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3081 u32 cfg2, cfg3, cfg4;
3082 /* check hardware configuration */
3084 cfg2 = readl(hsotg->regs + 0x48);
3085 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3087 cfg3 = readl(hsotg->regs + 0x4C);
3088 hsotg->fifo_mem = (cfg3 >> 16);
3090 cfg4 = readl(hsotg->regs + 0x50);
3091 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3093 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3095 hsotg->dedicated_fifos ? "dedicated" : "shared",
3100 * s3c_hsotg_dump - dump state of the udc
3101 * @param: The device state
3103 static void s3c_hsotg_dump(struct dwc2_hsotg *hsotg)
3106 struct device *dev = hsotg->dev;
3107 void __iomem *regs = hsotg->regs;
3111 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3112 readl(regs + DCFG), readl(regs + DCTL),
3113 readl(regs + DIEPMSK));
3115 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3116 readl(regs + GAHBCFG), readl(regs + 0x44));
3118 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3119 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3121 /* show periodic fifo settings */
3123 for (idx = 1; idx <= 15; idx++) {
3124 val = readl(regs + DPTXFSIZN(idx));
3125 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3126 val >> FIFOSIZE_DEPTH_SHIFT,
3127 val & FIFOSIZE_STARTADDR_MASK);
3130 for (idx = 0; idx < 15; idx++) {
3132 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3133 readl(regs + DIEPCTL(idx)),
3134 readl(regs + DIEPTSIZ(idx)),
3135 readl(regs + DIEPDMA(idx)));
3137 val = readl(regs + DOEPCTL(idx));
3139 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3140 idx, readl(regs + DOEPCTL(idx)),
3141 readl(regs + DOEPTSIZ(idx)),
3142 readl(regs + DOEPDMA(idx)));
3146 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3147 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3152 * state_show - debugfs: show overall driver and device state.
3153 * @seq: The seq file to write to.
3154 * @v: Unused parameter.
3156 * This debugfs entry shows the overall state of the hardware and
3157 * some general information about each of the endpoints available
3160 static int state_show(struct seq_file *seq, void *v)
3162 struct dwc2_hsotg *hsotg = seq->private;
3163 void __iomem *regs = hsotg->regs;
3166 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3169 readl(regs + DSTS));
3171 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3172 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3174 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3175 readl(regs + GINTMSK),
3176 readl(regs + GINTSTS));
3178 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3179 readl(regs + DAINTMSK),
3180 readl(regs + DAINT));
3182 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3183 readl(regs + GNPTXSTS),
3184 readl(regs + GRXSTSR));
3186 seq_puts(seq, "\nEndpoint status:\n");
3188 for (idx = 0; idx < 15; idx++) {
3191 in = readl(regs + DIEPCTL(idx));
3192 out = readl(regs + DOEPCTL(idx));
3194 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3197 in = readl(regs + DIEPTSIZ(idx));
3198 out = readl(regs + DOEPTSIZ(idx));
3200 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3203 seq_puts(seq, "\n");
3209 static int state_open(struct inode *inode, struct file *file)
3211 return single_open(file, state_show, inode->i_private);
3214 static const struct file_operations state_fops = {
3215 .owner = THIS_MODULE,
3218 .llseek = seq_lseek,
3219 .release = single_release,
3223 * fifo_show - debugfs: show the fifo information
3224 * @seq: The seq_file to write data to.
3225 * @v: Unused parameter.
3227 * Show the FIFO information for the overall fifo and all the
3228 * periodic transmission FIFOs.
3230 static int fifo_show(struct seq_file *seq, void *v)
3232 struct dwc2_hsotg *hsotg = seq->private;
3233 void __iomem *regs = hsotg->regs;
3237 seq_puts(seq, "Non-periodic FIFOs:\n");
3238 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3240 val = readl(regs + GNPTXFSIZ);
3241 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3242 val >> FIFOSIZE_DEPTH_SHIFT,
3243 val & FIFOSIZE_DEPTH_MASK);
3245 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3247 for (idx = 1; idx <= 15; idx++) {
3248 val = readl(regs + DPTXFSIZN(idx));
3250 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3251 val >> FIFOSIZE_DEPTH_SHIFT,
3252 val & FIFOSIZE_STARTADDR_MASK);
3258 static int fifo_open(struct inode *inode, struct file *file)
3260 return single_open(file, fifo_show, inode->i_private);
3263 static const struct file_operations fifo_fops = {
3264 .owner = THIS_MODULE,
3267 .llseek = seq_lseek,
3268 .release = single_release,
3272 static const char *decode_direction(int is_in)
3274 return is_in ? "in" : "out";
3278 * ep_show - debugfs: show the state of an endpoint.
3279 * @seq: The seq_file to write data to.
3280 * @v: Unused parameter.
3282 * This debugfs entry shows the state of the given endpoint (one is
3283 * registered for each available).
3285 static int ep_show(struct seq_file *seq, void *v)
3287 struct s3c_hsotg_ep *ep = seq->private;
3288 struct dwc2_hsotg *hsotg = ep->parent;
3289 struct s3c_hsotg_req *req;
3290 void __iomem *regs = hsotg->regs;
3291 int index = ep->index;
3292 int show_limit = 15;
3293 unsigned long flags;
3295 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3296 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3298 /* first show the register state */
3300 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3301 readl(regs + DIEPCTL(index)),
3302 readl(regs + DOEPCTL(index)));
3304 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3305 readl(regs + DIEPDMA(index)),
3306 readl(regs + DOEPDMA(index)));
3308 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3309 readl(regs + DIEPINT(index)),
3310 readl(regs + DOEPINT(index)));
3312 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3313 readl(regs + DIEPTSIZ(index)),
3314 readl(regs + DOEPTSIZ(index)));
3316 seq_puts(seq, "\n");
3317 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3318 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3320 seq_printf(seq, "request list (%p,%p):\n",
3321 ep->queue.next, ep->queue.prev);
3323 spin_lock_irqsave(&hsotg->lock, flags);
3325 list_for_each_entry(req, &ep->queue, queue) {
3326 if (--show_limit < 0) {
3327 seq_puts(seq, "not showing more requests...\n");
3331 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3332 req == ep->req ? '*' : ' ',
3333 req, req->req.length, req->req.buf);
3334 seq_printf(seq, "%d done, res %d\n",
3335 req->req.actual, req->req.status);
3338 spin_unlock_irqrestore(&hsotg->lock, flags);
3343 static int ep_open(struct inode *inode, struct file *file)
3345 return single_open(file, ep_show, inode->i_private);
3348 static const struct file_operations ep_fops = {
3349 .owner = THIS_MODULE,
3352 .llseek = seq_lseek,
3353 .release = single_release,
3357 * s3c_hsotg_create_debug - create debugfs directory and files
3358 * @hsotg: The driver state
3360 * Create the debugfs files to allow the user to get information
3361 * about the state of the system. The directory name is created
3362 * with the same name as the device itself, in case we end up
3363 * with multiple blocks in future systems.
3365 static void s3c_hsotg_create_debug(struct dwc2_hsotg *hsotg)
3367 struct dentry *root;
3370 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3371 hsotg->debug_root = root;
3373 dev_err(hsotg->dev, "cannot create debug root\n");
3377 /* create general state file */
3379 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3380 hsotg, &state_fops);
3382 if (IS_ERR(hsotg->debug_file))
3383 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3385 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3388 if (IS_ERR(hsotg->debug_fifo))
3389 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3391 /* create one file for each endpoint */
3393 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3394 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3396 ep->debugfs = debugfs_create_file(ep->name, 0444,
3397 root, ep, &ep_fops);
3399 if (IS_ERR(ep->debugfs))
3400 dev_err(hsotg->dev, "failed to create %s debug file\n",
3406 * s3c_hsotg_delete_debug - cleanup debugfs entries
3407 * @hsotg: The driver state
3409 * Cleanup (remove) the debugfs files for use on module exit.
3411 static void s3c_hsotg_delete_debug(struct dwc2_hsotg *hsotg)
3415 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3416 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3417 debugfs_remove(ep->debugfs);
3420 debugfs_remove(hsotg->debug_file);
3421 debugfs_remove(hsotg->debug_fifo);
3422 debugfs_remove(hsotg->debug_root);
3426 * s3c_hsotg_probe - probe function for hsotg driver
3427 * @pdev: The platform information for the driver
3429 static int s3c_hsotg_probe(struct platform_device *pdev)
3431 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3433 struct usb_phy *uphy;
3434 struct device *dev = &pdev->dev;
3435 struct s3c_hsotg_ep *eps;
3436 struct dwc2_hsotg *hsotg;
3437 struct resource *res;
3442 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct dwc2_hsotg), GFP_KERNEL);
3446 /* Set default UTMI width */
3447 hsotg->phyif = GUSBCFG_PHYIF16;
3450 * Attempt to find a generic PHY, then look for an old style
3451 * USB PHY, finally fall back to pdata
3453 phy = devm_phy_get(&pdev->dev, "usb2-phy");
3455 uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3457 /* Fallback for pdata */
3458 plat = dev_get_platdata(&pdev->dev);
3461 "no platform data or transceiver defined\n");
3462 return -EPROBE_DEFER;
3470 * If using the generic PHY framework, check if the PHY bus
3471 * width is 8-bit and set the phyif appropriately.
3473 if (phy_get_bus_width(phy) == 8)
3474 hsotg->phyif = GUSBCFG_PHYIF8;
3479 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3480 if (IS_ERR(hsotg->clk)) {
3481 dev_err(dev, "cannot get otg clock\n");
3482 return PTR_ERR(hsotg->clk);
3485 platform_set_drvdata(pdev, hsotg);
3487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3489 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3490 if (IS_ERR(hsotg->regs)) {
3491 ret = PTR_ERR(hsotg->regs);
3495 ret = platform_get_irq(pdev, 0);
3497 dev_err(dev, "cannot find IRQ\n");
3501 spin_lock_init(&hsotg->lock);
3505 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3507 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3508 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3509 hsotg->gadget.name = dev_name(dev);
3511 /* reset the system */
3513 clk_prepare_enable(hsotg->clk);
3517 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3518 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3520 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3523 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
3527 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3531 dev_err(dev, "failed to enable supplies: %d\n", ret);
3535 /* usb phy enable */
3536 s3c_hsotg_phy_enable(hsotg);
3538 s3c_hsotg_corereset(hsotg);
3539 s3c_hsotg_hw_cfg(hsotg);
3540 s3c_hsotg_init(hsotg);
3542 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3543 dev_name(dev), hsotg);
3545 s3c_hsotg_phy_disable(hsotg);
3546 clk_disable_unprepare(hsotg->clk);
3547 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3549 dev_err(dev, "cannot claim IRQ\n");
3553 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3555 if (hsotg->num_of_eps == 0) {
3556 dev_err(dev, "wrong number of EPs (zero)\n");
3561 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3570 /* setup endpoint information */
3572 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3573 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3575 /* allocate EP0 request */
3577 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3579 if (!hsotg->ctrl_req) {
3580 dev_err(dev, "failed to allocate ctrl req\n");
3585 /* initialise the endpoints now the core has been initialised */
3586 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3587 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3589 /* disable power and clock */
3590 s3c_hsotg_phy_disable(hsotg);
3592 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3595 dev_err(&pdev->dev, "failed to disable supplies: %d\n", ret);
3599 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3603 s3c_hsotg_create_debug(hsotg);
3605 s3c_hsotg_dump(hsotg);
3612 s3c_hsotg_phy_disable(hsotg);
3614 clk_disable_unprepare(hsotg->clk);
3620 * s3c_hsotg_remove - remove function for hsotg driver
3621 * @pdev: The platform information for the driver
3623 static int s3c_hsotg_remove(struct platform_device *pdev)
3625 struct dwc2_hsotg *hsotg = platform_get_drvdata(pdev);
3627 usb_del_gadget_udc(&hsotg->gadget);
3628 s3c_hsotg_delete_debug(hsotg);
3629 clk_disable_unprepare(hsotg->clk);
3634 static int s3c_hsotg_suspend(struct platform_device *pdev, pm_message_t state)
3636 struct dwc2_hsotg *hsotg = platform_get_drvdata(pdev);
3637 unsigned long flags;
3641 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3642 hsotg->driver->driver.name);
3644 spin_lock_irqsave(&hsotg->lock, flags);
3645 s3c_hsotg_core_disconnect(hsotg);
3646 s3c_hsotg_disconnect(hsotg);
3647 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3648 spin_unlock_irqrestore(&hsotg->lock, flags);
3650 s3c_hsotg_phy_disable(hsotg);
3652 if (hsotg->driver) {
3654 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3655 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3657 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3659 clk_disable(hsotg->clk);
3665 static int s3c_hsotg_resume(struct platform_device *pdev)
3667 struct dwc2_hsotg *hsotg = platform_get_drvdata(pdev);
3668 unsigned long flags;
3671 if (hsotg->driver) {
3672 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3673 hsotg->driver->driver.name);
3675 clk_enable(hsotg->clk);
3676 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3680 s3c_hsotg_phy_enable(hsotg);
3682 spin_lock_irqsave(&hsotg->lock, flags);
3683 s3c_hsotg_core_init_disconnected(hsotg);
3684 s3c_hsotg_core_connect(hsotg);
3685 spin_unlock_irqrestore(&hsotg->lock, flags);
3691 static const struct of_device_id s3c_hsotg_of_ids[] = {
3692 { .compatible = "samsung,s3c6400-hsotg", },
3693 { .compatible = "snps,dwc2", },
3696 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3699 static struct platform_driver s3c_hsotg_driver = {
3701 .name = "s3c-hsotg",
3702 .owner = THIS_MODULE,
3703 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3705 .probe = s3c_hsotg_probe,
3706 .remove = s3c_hsotg_remove,
3707 .suspend = s3c_hsotg_suspend,
3708 .resume = s3c_hsotg_resume,
3711 module_platform_driver(s3c_hsotg_driver);
3713 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3714 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3715 MODULE_LICENSE("GPL");
3716 MODULE_ALIAS("platform:s3c-hsotg");