2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/debugfs.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/of_platform.h>
31 #include <linux/phy/phy.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
40 /* conversion functions */
41 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
43 return container_of(req, struct s3c_hsotg_req, req);
46 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
48 return container_of(ep, struct s3c_hsotg_ep, ep);
51 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
53 return container_of(gadget, struct s3c_hsotg, gadget);
56 static inline void __orr32(void __iomem *ptr, u32 val)
58 writel(readl(ptr) | val, ptr);
61 static inline void __bic32(void __iomem *ptr, u32 val)
63 writel(readl(ptr) & ~val, ptr);
66 /* forward decleration of functions */
67 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
70 * using_dma - return the DMA status of the driver.
71 * @hsotg: The driver state.
73 * Return true if we're using DMA.
75 * Currently, we have the DMA support code worked into everywhere
76 * that needs it, but the AMBA DMA implementation in the hardware can
77 * only DMA from 32bit aligned addresses. This means that gadgets such
78 * as the CDC Ethernet cannot work as they often pass packets which are
81 * Unfortunately the choice to use DMA or not is global to the controller
82 * and seems to be only settable when the controller is being put through
83 * a core reset. This means we either need to fix the gadgets to take
84 * account of DMA alignment, or add bounce buffers (yuerk).
86 * Until this issue is sorted out, we always return 'false'.
88 static inline bool using_dma(struct s3c_hsotg *hsotg)
90 return false; /* support is not complete */
94 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
95 * @hsotg: The device state
96 * @ints: A bitmask of the interrupts to enable
98 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
100 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
103 new_gsintmsk = gsintmsk | ints;
105 if (new_gsintmsk != gsintmsk) {
106 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
107 writel(new_gsintmsk, hsotg->regs + GINTMSK);
112 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
113 * @hsotg: The device state
114 * @ints: A bitmask of the interrupts to enable
116 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
118 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
121 new_gsintmsk = gsintmsk & ~ints;
123 if (new_gsintmsk != gsintmsk)
124 writel(new_gsintmsk, hsotg->regs + GINTMSK);
128 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
129 * @hsotg: The device state
130 * @ep: The endpoint index
131 * @dir_in: True if direction is in.
132 * @en: The enable value, true to enable
134 * Set or clear the mask for an individual endpoint's interrupt
137 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
138 unsigned int ep, unsigned int dir_in,
148 local_irq_save(flags);
149 daint = readl(hsotg->regs + DAINTMSK);
154 writel(daint, hsotg->regs + DAINTMSK);
155 local_irq_restore(flags);
159 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
160 * @hsotg: The device instance.
162 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
170 /* set FIFO sizes to 2048/1024 */
172 writel(2048, hsotg->regs + GRXFSIZ);
173 writel((2048 << FIFOSIZE_STARTADDR_SHIFT) |
174 (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
177 * arange all the rest of the TX FIFOs, as some versions of this
178 * block have overlapping default addresses. This also ensures
179 * that if the settings have been changed, then they are set to
183 /* start at the end of the GNPTXFSIZ, rounded up */
187 * Because we have not enough memory to have each TX FIFO of size at
188 * least 3072 bytes (the maximum single packet size), we create four
189 * FIFOs of lenght 1024, and four of length 3072 bytes, and assing
190 * them to endpoints dynamically according to maxpacket size value of
194 /* 256*4=1024 bytes FIFO length */
196 for (ep = 1; ep <= 4; ep++) {
198 val |= size << FIFOSIZE_DEPTH_SHIFT;
199 WARN_ONCE(addr + size > hsotg->fifo_mem,
200 "insufficient fifo memory");
203 writel(val, hsotg->regs + DPTXFSIZN(ep));
205 /* 768*4=3072 bytes FIFO length */
207 for (ep = 5; ep <= 8; ep++) {
209 val |= size << FIFOSIZE_DEPTH_SHIFT;
210 WARN_ONCE(addr + size > hsotg->fifo_mem,
211 "insufficient fifo memory");
214 writel(val, hsotg->regs + DPTXFSIZN(ep));
218 * according to p428 of the design guide, we need to ensure that
219 * all fifos are flushed before continuing
222 writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
223 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
225 /* wait until the fifos are both flushed */
228 val = readl(hsotg->regs + GRSTCTL);
230 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
233 if (--timeout == 0) {
235 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
242 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
246 * @ep: USB endpoint to allocate request for.
247 * @flags: Allocation flags
249 * Allocate a new USB request structure appropriate for the specified endpoint
251 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
254 struct s3c_hsotg_req *req;
256 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
260 INIT_LIST_HEAD(&req->queue);
266 * is_ep_periodic - return true if the endpoint is in periodic mode.
267 * @hs_ep: The endpoint to query.
269 * Returns true if the endpoint is in periodic mode, meaning it is being
270 * used for an Interrupt or ISO transfer.
272 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
274 return hs_ep->periodic;
278 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
279 * @hsotg: The device state.
280 * @hs_ep: The endpoint for the request
281 * @hs_req: The request being processed.
283 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
284 * of a request to ensure the buffer is ready for access by the caller.
286 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
287 struct s3c_hsotg_ep *hs_ep,
288 struct s3c_hsotg_req *hs_req)
290 struct usb_request *req = &hs_req->req;
292 /* ignore this if we're not moving any data */
293 if (hs_req->req.length == 0)
296 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
300 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
301 * @hsotg: The controller state.
302 * @hs_ep: The endpoint we're going to write for.
303 * @hs_req: The request to write data for.
305 * This is called when the TxFIFO has some space in it to hold a new
306 * transmission and we have something to give it. The actual setup of
307 * the data size is done elsewhere, so all we have to do is to actually
310 * The return value is zero if there is more space (or nothing was done)
311 * otherwise -ENOSPC is returned if the FIFO space was used up.
313 * This routine is only needed for PIO
315 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
316 struct s3c_hsotg_ep *hs_ep,
317 struct s3c_hsotg_req *hs_req)
319 bool periodic = is_ep_periodic(hs_ep);
320 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
321 int buf_pos = hs_req->req.actual;
322 int to_write = hs_ep->size_loaded;
328 to_write -= (buf_pos - hs_ep->last_load);
330 /* if there's nothing to write, get out early */
334 if (periodic && !hsotg->dedicated_fifos) {
335 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
340 * work out how much data was loaded so we can calculate
341 * how much data is left in the fifo.
344 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
347 * if shared fifo, we cannot write anything until the
348 * previous data has been completely sent.
350 if (hs_ep->fifo_load != 0) {
351 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
355 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
357 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
359 /* how much of the data has moved */
360 size_done = hs_ep->size_loaded - size_left;
362 /* how much data is left in the fifo */
363 can_write = hs_ep->fifo_load - size_done;
364 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
365 __func__, can_write);
367 can_write = hs_ep->fifo_size - can_write;
368 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
369 __func__, can_write);
371 if (can_write <= 0) {
372 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
375 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
376 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
381 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
383 "%s: no queue slots available (0x%08x)\n",
386 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
390 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
391 can_write *= 4; /* fifo size is in 32bit quantities. */
394 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
396 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
397 __func__, gnptxsts, can_write, to_write, max_transfer);
400 * limit to 512 bytes of data, it seems at least on the non-periodic
401 * FIFO, requests of >512 cause the endpoint to get stuck with a
402 * fragment of the end of the transfer in it.
404 if (can_write > 512 && !periodic)
408 * limit the write to one max-packet size worth of data, but allow
409 * the transfer to return that it did not run out of fifo space
412 if (to_write > max_transfer) {
413 to_write = max_transfer;
415 /* it's needed only when we do not use dedicated fifos */
416 if (!hsotg->dedicated_fifos)
417 s3c_hsotg_en_gsint(hsotg,
418 periodic ? GINTSTS_PTXFEMP :
422 /* see if we can write data */
424 if (to_write > can_write) {
425 to_write = can_write;
426 pkt_round = to_write % max_transfer;
429 * Round the write down to an
430 * exact number of packets.
432 * Note, we do not currently check to see if we can ever
433 * write a full packet or not to the FIFO.
437 to_write -= pkt_round;
440 * enable correct FIFO interrupt to alert us when there
444 /* it's needed only when we do not use dedicated fifos */
445 if (!hsotg->dedicated_fifos)
446 s3c_hsotg_en_gsint(hsotg,
447 periodic ? GINTSTS_PTXFEMP :
451 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
452 to_write, hs_req->req.length, can_write, buf_pos);
457 hs_req->req.actual = buf_pos + to_write;
458 hs_ep->total_data += to_write;
461 hs_ep->fifo_load += to_write;
463 to_write = DIV_ROUND_UP(to_write, 4);
464 data = hs_req->req.buf + buf_pos;
466 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
468 return (to_write >= can_write) ? -ENOSPC : 0;
472 * get_ep_limit - get the maximum data legnth for this endpoint
473 * @hs_ep: The endpoint
475 * Return the maximum data that can be queued in one go on a given endpoint
476 * so that transfers that are too long can be split.
478 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
480 int index = hs_ep->index;
485 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
486 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
490 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
495 /* we made the constant loading easier above by using +1 */
500 * constrain by packet count if maxpkts*pktsize is greater
501 * than the length register size.
504 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
505 maxsize = maxpkt * hs_ep->ep.maxpacket;
511 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
512 * @hsotg: The controller state.
513 * @hs_ep: The endpoint to process a request for
514 * @hs_req: The request to start.
515 * @continuing: True if we are doing more for the current request.
517 * Start the given request running by setting the endpoint registers
518 * appropriately, and writing any data to the FIFOs.
520 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
521 struct s3c_hsotg_ep *hs_ep,
522 struct s3c_hsotg_req *hs_req,
525 struct usb_request *ureq = &hs_req->req;
526 int index = hs_ep->index;
527 int dir_in = hs_ep->dir_in;
537 if (hs_ep->req && !continuing) {
538 dev_err(hsotg->dev, "%s: active request\n", __func__);
541 } else if (hs_ep->req != hs_req && continuing) {
543 "%s: continue different req\n", __func__);
549 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
550 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
552 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
553 __func__, readl(hsotg->regs + epctrl_reg), index,
554 hs_ep->dir_in ? "in" : "out");
556 /* If endpoint is stalled, we will restart request later */
557 ctrl = readl(hsotg->regs + epctrl_reg);
559 if (ctrl & DXEPCTL_STALL) {
560 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
564 length = ureq->length - ureq->actual;
565 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
566 ureq->length, ureq->actual);
569 "REQ buf %p len %d dma %pad noi=%d zp=%d snok=%d\n",
570 ureq->buf, length, &ureq->dma,
571 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
573 maxreq = get_ep_limit(hs_ep);
574 if (length > maxreq) {
575 int round = maxreq % hs_ep->ep.maxpacket;
577 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
578 __func__, length, maxreq, round);
580 /* round down to multiple of packets */
588 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
590 packets = 1; /* send one packet if length is zero. */
592 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
593 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
597 if (dir_in && index != 0)
598 if (hs_ep->isochronous)
599 epsize = DXEPTSIZ_MC(packets);
601 epsize = DXEPTSIZ_MC(1);
605 if (index != 0 && ureq->zero) {
607 * test for the packets being exactly right for the
611 if (length == (packets * hs_ep->ep.maxpacket))
615 epsize |= DXEPTSIZ_PKTCNT(packets);
616 epsize |= DXEPTSIZ_XFERSIZE(length);
618 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
619 __func__, packets, length, ureq->length, epsize, epsize_reg);
621 /* store the request as the current one we're doing */
624 /* write size / packets */
625 writel(epsize, hsotg->regs + epsize_reg);
627 if (using_dma(hsotg) && !continuing) {
628 unsigned int dma_reg;
631 * write DMA address to control register, buffer already
632 * synced by s3c_hsotg_ep_queue().
635 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
636 writel(ureq->dma, hsotg->regs + dma_reg);
638 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
639 __func__, &ureq->dma, dma_reg);
642 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
643 ctrl |= DXEPCTL_USBACTEP;
645 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
647 /* For Setup request do not clear NAK */
648 if (hsotg->setup && index == 0)
651 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
654 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
655 writel(ctrl, hsotg->regs + epctrl_reg);
658 * set these, it seems that DMA support increments past the end
659 * of the packet buffer so we need to calculate the length from
662 hs_ep->size_loaded = length;
663 hs_ep->last_load = ureq->actual;
665 if (dir_in && !using_dma(hsotg)) {
666 /* set these anyway, we may need them for non-periodic in */
667 hs_ep->fifo_load = 0;
669 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
673 * clear the INTknTXFEmpMsk when we start request, more as a aide
674 * to debugging to see what is going on.
677 writel(DIEPMSK_INTKNTXFEMPMSK,
678 hsotg->regs + DIEPINT(index));
681 * Note, trying to clear the NAK here causes problems with transmit
682 * on the S3C6400 ending up with the TXFIFO becoming full.
685 /* check ep is enabled */
686 if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
688 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
689 index, readl(hsotg->regs + epctrl_reg));
691 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
692 __func__, readl(hsotg->regs + epctrl_reg));
694 /* enable ep interrupts */
695 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
699 * s3c_hsotg_map_dma - map the DMA memory being used for the request
700 * @hsotg: The device state.
701 * @hs_ep: The endpoint the request is on.
702 * @req: The request being processed.
704 * We've been asked to queue a request, so ensure that the memory buffer
705 * is correctly setup for DMA. If we've been passed an extant DMA address
706 * then ensure the buffer has been synced to memory. If our buffer has no
707 * DMA memory, then we map the memory and mark our request to allow us to
708 * cleanup on completion.
710 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
711 struct s3c_hsotg_ep *hs_ep,
712 struct usb_request *req)
714 struct s3c_hsotg_req *hs_req = our_req(req);
717 /* if the length is zero, ignore the DMA data */
718 if (hs_req->req.length == 0)
721 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
728 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
729 __func__, req->buf, req->length);
734 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
737 struct s3c_hsotg_req *hs_req = our_req(req);
738 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
739 struct s3c_hsotg *hs = hs_ep->parent;
742 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
743 ep->name, req, req->length, req->buf, req->no_interrupt,
744 req->zero, req->short_not_ok);
746 /* initialise status of the request */
747 INIT_LIST_HEAD(&hs_req->queue);
749 req->status = -EINPROGRESS;
751 /* if we're using DMA, sync the buffers as necessary */
753 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
758 first = list_empty(&hs_ep->queue);
759 list_add_tail(&hs_req->queue, &hs_ep->queue);
762 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
767 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
770 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
771 struct s3c_hsotg *hs = hs_ep->parent;
772 unsigned long flags = 0;
775 spin_lock_irqsave(&hs->lock, flags);
776 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
777 spin_unlock_irqrestore(&hs->lock, flags);
782 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
783 struct usb_request *req)
785 struct s3c_hsotg_req *hs_req = our_req(req);
791 * s3c_hsotg_complete_oursetup - setup completion callback
792 * @ep: The endpoint the request was on.
793 * @req: The request completed.
795 * Called on completion of any requests the driver itself
796 * submitted that need cleaning up.
798 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
799 struct usb_request *req)
801 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
802 struct s3c_hsotg *hsotg = hs_ep->parent;
804 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
806 s3c_hsotg_ep_free_request(ep, req);
810 * ep_from_windex - convert control wIndex value to endpoint
811 * @hsotg: The driver state.
812 * @windex: The control request wIndex field (in host order).
814 * Convert the given wIndex into a pointer to an driver endpoint
815 * structure, or return NULL if it is not a valid endpoint.
817 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
820 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
821 int dir = (windex & USB_DIR_IN) ? 1 : 0;
822 int idx = windex & 0x7F;
827 if (idx > hsotg->num_of_eps)
830 if (idx && ep->dir_in != dir)
837 * s3c_hsotg_send_reply - send reply to control request
838 * @hsotg: The device state
840 * @buff: Buffer for request
841 * @length: Length of reply.
843 * Create a request and queue it on the given endpoint. This is useful as
844 * an internal method of sending replies to certain control requests, etc.
846 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
847 struct s3c_hsotg_ep *ep,
851 struct usb_request *req;
854 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
856 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
857 hsotg->ep0_reply = req;
859 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
863 req->buf = hsotg->ep0_buff;
864 req->length = length;
865 req->zero = 1; /* always do zero-length final transfer */
866 req->complete = s3c_hsotg_complete_oursetup;
869 memcpy(req->buf, buff, length);
873 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
875 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
883 * s3c_hsotg_process_req_status - process request GET_STATUS
884 * @hsotg: The device state
885 * @ctrl: USB control request
887 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
888 struct usb_ctrlrequest *ctrl)
890 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
891 struct s3c_hsotg_ep *ep;
895 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
898 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
902 switch (ctrl->bRequestType & USB_RECIP_MASK) {
903 case USB_RECIP_DEVICE:
904 reply = cpu_to_le16(0); /* bit 0 => self powered,
905 * bit 1 => remote wakeup */
908 case USB_RECIP_INTERFACE:
909 /* currently, the data result should be zero */
910 reply = cpu_to_le16(0);
913 case USB_RECIP_ENDPOINT:
914 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
918 reply = cpu_to_le16(ep->halted ? 1 : 0);
925 if (le16_to_cpu(ctrl->wLength) != 2)
928 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
930 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
937 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
940 * get_ep_head - return the first request on the endpoint
941 * @hs_ep: The controller endpoint to get
943 * Get the first request on the endpoint.
945 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
947 if (list_empty(&hs_ep->queue))
950 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
954 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
955 * @hsotg: The device state
956 * @ctrl: USB control request
958 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
959 struct usb_ctrlrequest *ctrl)
961 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
962 struct s3c_hsotg_req *hs_req;
964 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
965 struct s3c_hsotg_ep *ep;
969 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
970 __func__, set ? "SET" : "CLEAR");
972 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
973 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
975 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
976 __func__, le16_to_cpu(ctrl->wIndex));
980 switch (le16_to_cpu(ctrl->wValue)) {
981 case USB_ENDPOINT_HALT:
984 s3c_hsotg_ep_sethalt(&ep->ep, set);
986 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
989 "%s: failed to send reply\n", __func__);
994 * we have to complete all requests for ep if it was
995 * halted, and the halt was cleared by CLEAR_FEATURE
998 if (!set && halted) {
1000 * If we have request in progress,
1006 list_del_init(&hs_req->queue);
1007 usb_gadget_giveback_request(&ep->ep,
1011 /* If we have pending request, then start it */
1012 restart = !list_empty(&ep->queue);
1014 hs_req = get_ep_head(ep);
1015 s3c_hsotg_start_req(hsotg, ep,
1026 return -ENOENT; /* currently only deal with endpoint */
1031 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1032 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg);
1035 * s3c_hsotg_stall_ep0 - stall ep0
1036 * @hsotg: The device state
1038 * Set stall for ep0 as response for setup request.
1040 static void s3c_hsotg_stall_ep0(struct s3c_hsotg *hsotg)
1042 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1046 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1047 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1050 * DxEPCTL_Stall will be cleared by EP once it has
1051 * taken effect, so no need to clear later.
1054 ctrl = readl(hsotg->regs + reg);
1055 ctrl |= DXEPCTL_STALL;
1056 ctrl |= DXEPCTL_CNAK;
1057 writel(ctrl, hsotg->regs + reg);
1060 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1061 ctrl, reg, readl(hsotg->regs + reg));
1064 * complete won't be called, so we enqueue
1065 * setup request here
1067 s3c_hsotg_enqueue_setup(hsotg);
1071 * s3c_hsotg_process_control - process a control request
1072 * @hsotg: The device state
1073 * @ctrl: The control request received
1075 * The controller has received the SETUP phase of a control request, and
1076 * needs to work out what to do next (and whether to pass it on to the
1079 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1080 struct usb_ctrlrequest *ctrl)
1082 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1088 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1089 ctrl->bRequest, ctrl->bRequestType,
1090 ctrl->wValue, ctrl->wLength);
1093 * record the direction of the request, for later use when enquing
1097 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1098 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1101 * if we've no data with this request, then the last part of the
1102 * transaction is going to implicitly be IN.
1104 if (ctrl->wLength == 0)
1107 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1108 switch (ctrl->bRequest) {
1109 case USB_REQ_SET_ADDRESS:
1110 s3c_hsotg_disconnect(hsotg);
1111 dcfg = readl(hsotg->regs + DCFG);
1112 dcfg &= ~DCFG_DEVADDR_MASK;
1113 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1114 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1115 writel(dcfg, hsotg->regs + DCFG);
1117 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1119 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1122 case USB_REQ_GET_STATUS:
1123 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1126 case USB_REQ_CLEAR_FEATURE:
1127 case USB_REQ_SET_FEATURE:
1128 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1133 /* as a fallback, try delivering it to the driver to deal with */
1135 if (ret == 0 && hsotg->driver) {
1136 spin_unlock(&hsotg->lock);
1137 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1138 spin_lock(&hsotg->lock);
1140 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1144 * the request is either unhandlable, or is not formatted correctly
1145 * so respond with a STALL for the status stage to indicate failure.
1149 s3c_hsotg_stall_ep0(hsotg);
1153 * s3c_hsotg_complete_setup - completion of a setup transfer
1154 * @ep: The endpoint the request was on.
1155 * @req: The request completed.
1157 * Called on completion of any requests the driver itself submitted for
1160 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1161 struct usb_request *req)
1163 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1164 struct s3c_hsotg *hsotg = hs_ep->parent;
1166 if (req->status < 0) {
1167 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1171 spin_lock(&hsotg->lock);
1172 if (req->actual == 0)
1173 s3c_hsotg_enqueue_setup(hsotg);
1175 s3c_hsotg_process_control(hsotg, req->buf);
1176 spin_unlock(&hsotg->lock);
1180 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1181 * @hsotg: The device state.
1183 * Enqueue a request on EP0 if necessary to received any SETUP packets
1184 * received from the host.
1186 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1188 struct usb_request *req = hsotg->ctrl_req;
1189 struct s3c_hsotg_req *hs_req = our_req(req);
1192 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1196 req->buf = hsotg->ctrl_buff;
1197 req->complete = s3c_hsotg_complete_setup;
1199 if (!list_empty(&hs_req->queue)) {
1200 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1204 hsotg->eps[0].dir_in = 0;
1206 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1208 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1210 * Don't think there's much we can do other than watch the
1217 * s3c_hsotg_complete_request - complete a request given to us
1218 * @hsotg: The device state.
1219 * @hs_ep: The endpoint the request was on.
1220 * @hs_req: The request to complete.
1221 * @result: The result code (0 => Ok, otherwise errno)
1223 * The given request has finished, so call the necessary completion
1224 * if it has one and then look to see if we can start a new request
1227 * Note, expects the ep to already be locked as appropriate.
1229 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1230 struct s3c_hsotg_ep *hs_ep,
1231 struct s3c_hsotg_req *hs_req,
1237 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1241 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1242 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1245 * only replace the status if we've not already set an error
1246 * from a previous transaction
1249 if (hs_req->req.status == -EINPROGRESS)
1250 hs_req->req.status = result;
1253 list_del_init(&hs_req->queue);
1255 if (using_dma(hsotg))
1256 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1259 * call the complete request with the locks off, just in case the
1260 * request tries to queue more work for this endpoint.
1263 if (hs_req->req.complete) {
1264 spin_unlock(&hsotg->lock);
1265 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1266 spin_lock(&hsotg->lock);
1270 * Look to see if there is anything else to do. Note, the completion
1271 * of the previous request may have caused a new request to be started
1272 * so be careful when doing this.
1275 if (!hs_ep->req && result >= 0) {
1276 restart = !list_empty(&hs_ep->queue);
1278 hs_req = get_ep_head(hs_ep);
1279 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1285 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1286 * @hsotg: The device state.
1287 * @ep_idx: The endpoint index for the data
1288 * @size: The size of data in the fifo, in bytes
1290 * The FIFO status shows there is data to read from the FIFO for a given
1291 * endpoint, so sort out whether we need to read the data into a request
1292 * that has been made for that endpoint.
1294 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1296 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1297 struct s3c_hsotg_req *hs_req = hs_ep->req;
1298 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1305 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1308 dev_warn(hsotg->dev,
1309 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1310 __func__, size, ep_idx, epctl);
1312 /* dump the data from the FIFO, we've nothing we can do */
1313 for (ptr = 0; ptr < size; ptr += 4)
1320 read_ptr = hs_req->req.actual;
1321 max_req = hs_req->req.length - read_ptr;
1323 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1324 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1326 if (to_read > max_req) {
1328 * more data appeared than we where willing
1329 * to deal with in this request.
1332 /* currently we don't deal this */
1336 hs_ep->total_data += to_read;
1337 hs_req->req.actual += to_read;
1338 to_read = DIV_ROUND_UP(to_read, 4);
1341 * note, we might over-write the buffer end by 3 bytes depending on
1342 * alignment of the data.
1344 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1348 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1349 * @hsotg: The device instance
1350 * @req: The request currently on this endpoint
1352 * Generate a zero-length IN packet request for terminating a SETUP
1355 * Note, since we don't write any data to the TxFIFO, then it is
1356 * currently believed that we do not need to wait for any space in
1359 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1360 struct s3c_hsotg_req *req)
1365 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1369 if (req->req.length == 0) {
1370 hsotg->eps[0].sent_zlp = 1;
1371 s3c_hsotg_enqueue_setup(hsotg);
1375 hsotg->eps[0].dir_in = 1;
1376 hsotg->eps[0].sent_zlp = 1;
1378 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1380 /* issue a zero-sized packet to terminate this */
1381 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1382 DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0));
1384 ctrl = readl(hsotg->regs + DIEPCTL0);
1385 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1386 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1387 ctrl |= DXEPCTL_USBACTEP;
1388 writel(ctrl, hsotg->regs + DIEPCTL0);
1392 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1393 * @hsotg: The device instance
1394 * @epnum: The endpoint received from
1395 * @was_setup: Set if processing a SetupDone event.
1397 * The RXFIFO has delivered an OutDone event, which means that the data
1398 * transfer for an OUT endpoint has been completed, either by a short
1399 * packet or by the finish of a transfer.
1401 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1402 int epnum, bool was_setup)
1404 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1405 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1406 struct s3c_hsotg_req *hs_req = hs_ep->req;
1407 struct usb_request *req = &hs_req->req;
1408 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1412 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1416 if (using_dma(hsotg)) {
1420 * Calculate the size of the transfer by checking how much
1421 * is left in the endpoint size register and then working it
1422 * out from the amount we loaded for the transfer.
1424 * We need to do this as DMA pointers are always 32bit aligned
1425 * so may overshoot/undershoot the transfer.
1428 size_done = hs_ep->size_loaded - size_left;
1429 size_done += hs_ep->last_load;
1431 req->actual = size_done;
1434 /* if there is more request to do, schedule new transfer */
1435 if (req->actual < req->length && size_left == 0) {
1436 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1438 } else if (epnum == 0) {
1440 * After was_setup = 1 =>
1441 * set CNAK for non Setup requests
1443 hsotg->setup = was_setup ? 0 : 1;
1446 if (req->actual < req->length && req->short_not_ok) {
1447 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1448 __func__, req->actual, req->length);
1451 * todo - what should we return here? there's no one else
1452 * even bothering to check the status.
1458 * Condition req->complete != s3c_hsotg_complete_setup says:
1459 * send ZLP when we have an asynchronous request from gadget
1461 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1462 s3c_hsotg_send_zlp(hsotg, hs_req);
1465 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1469 * s3c_hsotg_read_frameno - read current frame number
1470 * @hsotg: The device instance
1472 * Return the current frame number
1474 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1478 dsts = readl(hsotg->regs + DSTS);
1479 dsts &= DSTS_SOFFN_MASK;
1480 dsts >>= DSTS_SOFFN_SHIFT;
1486 * s3c_hsotg_handle_rx - RX FIFO has data
1487 * @hsotg: The device instance
1489 * The IRQ handler has detected that the RX FIFO has some data in it
1490 * that requires processing, so find out what is in there and do the
1493 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1494 * chunks, so if you have x packets received on an endpoint you'll get x
1495 * FIFO events delivered, each with a packet's worth of data in it.
1497 * When using DMA, we should not be processing events from the RXFIFO
1498 * as the actual data should be sent to the memory directly and we turn
1499 * on the completion interrupts to get notifications of transfer completion.
1501 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1503 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1504 u32 epnum, status, size;
1506 WARN_ON(using_dma(hsotg));
1508 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1509 status = grxstsr & GRXSTS_PKTSTS_MASK;
1511 size = grxstsr & GRXSTS_BYTECNT_MASK;
1512 size >>= GRXSTS_BYTECNT_SHIFT;
1515 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1516 __func__, grxstsr, size, epnum);
1518 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1519 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1520 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1523 case GRXSTS_PKTSTS_OUTDONE:
1524 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1525 s3c_hsotg_read_frameno(hsotg));
1527 if (!using_dma(hsotg))
1528 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1531 case GRXSTS_PKTSTS_SETUPDONE:
1533 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1534 s3c_hsotg_read_frameno(hsotg),
1535 readl(hsotg->regs + DOEPCTL(0)));
1537 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1540 case GRXSTS_PKTSTS_OUTRX:
1541 s3c_hsotg_rx_data(hsotg, epnum, size);
1544 case GRXSTS_PKTSTS_SETUPRX:
1546 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1547 s3c_hsotg_read_frameno(hsotg),
1548 readl(hsotg->regs + DOEPCTL(0)));
1550 s3c_hsotg_rx_data(hsotg, epnum, size);
1554 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1557 s3c_hsotg_dump(hsotg);
1563 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1564 * @mps: The maximum packet size in bytes.
1566 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1570 return D0EPCTL_MPS_64;
1572 return D0EPCTL_MPS_32;
1574 return D0EPCTL_MPS_16;
1576 return D0EPCTL_MPS_8;
1579 /* bad max packet size, warn and return invalid result */
1585 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1586 * @hsotg: The driver state.
1587 * @ep: The index number of the endpoint
1588 * @mps: The maximum packet size in bytes
1590 * Configure the maximum packet size for the given endpoint, updating
1591 * the hardware control registers to reflect this.
1593 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1594 unsigned int ep, unsigned int mps)
1596 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1597 void __iomem *regs = hsotg->regs;
1603 /* EP0 is a special case */
1604 mpsval = s3c_hsotg_ep0_mps(mps);
1607 hs_ep->ep.maxpacket = mps;
1610 mpsval = mps & DXEPCTL_MPS_MASK;
1613 mcval = ((mps >> 11) & 0x3) + 1;
1617 hs_ep->ep.maxpacket = mpsval;
1621 * update both the in and out endpoint controldir_ registers, even
1622 * if one of the directions may not be in use.
1625 reg = readl(regs + DIEPCTL(ep));
1626 reg &= ~DXEPCTL_MPS_MASK;
1628 writel(reg, regs + DIEPCTL(ep));
1631 reg = readl(regs + DOEPCTL(ep));
1632 reg &= ~DXEPCTL_MPS_MASK;
1634 writel(reg, regs + DOEPCTL(ep));
1640 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1644 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1645 * @hsotg: The driver state
1646 * @idx: The index for the endpoint (0..15)
1648 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1653 writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1654 hsotg->regs + GRSTCTL);
1656 /* wait until the fifo is flushed */
1660 val = readl(hsotg->regs + GRSTCTL);
1662 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1665 if (--timeout == 0) {
1667 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1677 * s3c_hsotg_trytx - check to see if anything needs transmitting
1678 * @hsotg: The driver state
1679 * @hs_ep: The driver endpoint to check.
1681 * Check to see if there is a request that has data to send, and if so
1682 * make an attempt to write data into the FIFO.
1684 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1685 struct s3c_hsotg_ep *hs_ep)
1687 struct s3c_hsotg_req *hs_req = hs_ep->req;
1689 if (!hs_ep->dir_in || !hs_req) {
1691 * if request is not enqueued, we disable interrupts
1692 * for endpoints, excepting ep0
1694 if (hs_ep->index != 0)
1695 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1700 if (hs_req->req.actual < hs_req->req.length) {
1701 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1703 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1710 * s3c_hsotg_complete_in - complete IN transfer
1711 * @hsotg: The device state.
1712 * @hs_ep: The endpoint that has just completed.
1714 * An IN transfer has been completed, update the transfer's state and then
1715 * call the relevant completion routines.
1717 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1718 struct s3c_hsotg_ep *hs_ep)
1720 struct s3c_hsotg_req *hs_req = hs_ep->req;
1721 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1722 int size_left, size_done;
1725 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1729 /* Finish ZLP handling for IN EP0 transactions */
1730 if (hsotg->eps[0].sent_zlp) {
1731 dev_dbg(hsotg->dev, "zlp packet received\n");
1732 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1737 * Calculate the size of the transfer by checking how much is left
1738 * in the endpoint size register and then working it out from
1739 * the amount we loaded for the transfer.
1741 * We do this even for DMA, as the transfer may have incremented
1742 * past the end of the buffer (DMA transfers are always 32bit
1746 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1748 size_done = hs_ep->size_loaded - size_left;
1749 size_done += hs_ep->last_load;
1751 if (hs_req->req.actual != size_done)
1752 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1753 __func__, hs_req->req.actual, size_done);
1755 hs_req->req.actual = size_done;
1756 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1757 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1760 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1761 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1762 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1763 * inform the host that no more data is available.
1764 * The state of req.zero member is checked to be sure that the value to
1765 * send is smaller than wValue expected from host.
1766 * Check req.length to NOT send another ZLP when the current one is
1767 * under completion (the one for which this completion has been called).
1769 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1770 hs_req->req.length == hs_req->req.actual &&
1771 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1773 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1774 s3c_hsotg_send_zlp(hsotg, hs_req);
1779 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1780 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1781 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1783 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1787 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1788 * @hsotg: The driver state
1789 * @idx: The index for the endpoint (0..15)
1790 * @dir_in: Set if this is an IN endpoint
1792 * Process and clear any interrupt pending for an individual endpoint
1794 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1797 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1798 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1799 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1800 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1804 ints = readl(hsotg->regs + epint_reg);
1805 ctrl = readl(hsotg->regs + epctl_reg);
1807 /* Clear endpoint interrupts */
1808 writel(ints, hsotg->regs + epint_reg);
1810 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1811 __func__, idx, dir_in ? "in" : "out", ints);
1813 if (ints & DXEPINT_XFERCOMPL) {
1814 if (hs_ep->isochronous && hs_ep->interval == 1) {
1815 if (ctrl & DXEPCTL_EOFRNUM)
1816 ctrl |= DXEPCTL_SETEVENFR;
1818 ctrl |= DXEPCTL_SETODDFR;
1819 writel(ctrl, hsotg->regs + epctl_reg);
1823 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1824 __func__, readl(hsotg->regs + epctl_reg),
1825 readl(hsotg->regs + epsiz_reg));
1828 * we get OutDone from the FIFO, so we only need to look
1829 * at completing IN requests here
1832 s3c_hsotg_complete_in(hsotg, hs_ep);
1834 if (idx == 0 && !hs_ep->req)
1835 s3c_hsotg_enqueue_setup(hsotg);
1836 } else if (using_dma(hsotg)) {
1838 * We're using DMA, we need to fire an OutDone here
1839 * as we ignore the RXFIFO.
1842 s3c_hsotg_handle_outdone(hsotg, idx, false);
1846 if (ints & DXEPINT_EPDISBLD) {
1847 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1850 int epctl = readl(hsotg->regs + epctl_reg);
1852 s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
1854 if ((epctl & DXEPCTL_STALL) &&
1855 (epctl & DXEPCTL_EPTYPE_BULK)) {
1856 int dctl = readl(hsotg->regs + DCTL);
1858 dctl |= DCTL_CGNPINNAK;
1859 writel(dctl, hsotg->regs + DCTL);
1864 if (ints & DXEPINT_AHBERR)
1865 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1867 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
1868 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1870 if (using_dma(hsotg) && idx == 0) {
1872 * this is the notification we've received a
1873 * setup packet. In non-DMA mode we'd get this
1874 * from the RXFIFO, instead we need to process
1881 s3c_hsotg_handle_outdone(hsotg, 0, true);
1885 if (ints & DXEPINT_BACK2BACKSETUP)
1886 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1888 if (dir_in && !hs_ep->isochronous) {
1889 /* not sure if this is important, but we'll clear it anyway */
1890 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
1891 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1895 /* this probably means something bad is happening */
1896 if (ints & DIEPMSK_INTKNEPMISMSK) {
1897 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1901 /* FIFO has space or is empty (see GAHBCFG) */
1902 if (hsotg->dedicated_fifos &&
1903 ints & DIEPMSK_TXFIFOEMPTY) {
1904 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
1906 if (!using_dma(hsotg))
1907 s3c_hsotg_trytx(hsotg, hs_ep);
1913 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1914 * @hsotg: The device state.
1916 * Handle updating the device settings after the enumeration phase has
1919 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1921 u32 dsts = readl(hsotg->regs + DSTS);
1922 int ep0_mps = 0, ep_mps = 8;
1925 * This should signal the finish of the enumeration phase
1926 * of the USB handshaking, so we should now know what rate
1930 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1933 * note, since we're limited by the size of transfer on EP0, and
1934 * it seems IN transfers must be a even number of packets we do
1935 * not advertise a 64byte MPS on EP0.
1938 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1939 switch (dsts & DSTS_ENUMSPD_MASK) {
1940 case DSTS_ENUMSPD_FS:
1941 case DSTS_ENUMSPD_FS48:
1942 hsotg->gadget.speed = USB_SPEED_FULL;
1943 ep0_mps = EP0_MPS_LIMIT;
1947 case DSTS_ENUMSPD_HS:
1948 hsotg->gadget.speed = USB_SPEED_HIGH;
1949 ep0_mps = EP0_MPS_LIMIT;
1953 case DSTS_ENUMSPD_LS:
1954 hsotg->gadget.speed = USB_SPEED_LOW;
1956 * note, we don't actually support LS in this driver at the
1957 * moment, and the documentation seems to imply that it isn't
1958 * supported by the PHYs on some of the devices.
1962 dev_info(hsotg->dev, "new device is %s\n",
1963 usb_speed_string(hsotg->gadget.speed));
1966 * we should now know the maximum packet size for an
1967 * endpoint, so set the endpoints to a default value.
1972 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1973 for (i = 1; i < hsotg->num_of_eps; i++)
1974 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1977 /* ensure after enumeration our EP0 is active */
1979 s3c_hsotg_enqueue_setup(hsotg);
1981 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1982 readl(hsotg->regs + DIEPCTL0),
1983 readl(hsotg->regs + DOEPCTL0));
1987 * kill_all_requests - remove all requests from the endpoint's queue
1988 * @hsotg: The device state.
1989 * @ep: The endpoint the requests may be on.
1990 * @result: The result code to use.
1991 * @force: Force removal of any current requests
1993 * Go through the requests on the given endpoint and mark them
1994 * completed with the given result code.
1996 static void kill_all_requests(struct s3c_hsotg *hsotg,
1997 struct s3c_hsotg_ep *ep,
1998 int result, bool force)
2000 struct s3c_hsotg_req *req, *treq;
2003 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2005 * currently, we can't do much about an already
2006 * running request on an in endpoint
2009 if (ep->req == req && ep->dir_in && !force)
2012 s3c_hsotg_complete_request(hsotg, ep, req,
2015 if (!hsotg->dedicated_fifos)
2017 size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2018 if (size < ep->fifo_size)
2019 s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2023 * s3c_hsotg_disconnect - disconnect service
2024 * @hsotg: The device state.
2026 * The device has been disconnected. Remove all current
2027 * transactions and signal the gadget driver that this
2030 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2034 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2035 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2037 call_gadget(hsotg, disconnect);
2041 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2042 * @hsotg: The device state:
2043 * @periodic: True if this is a periodic FIFO interrupt
2045 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2047 struct s3c_hsotg_ep *ep;
2050 /* look through for any more data to transmit */
2052 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2053 ep = &hsotg->eps[epno];
2058 if ((periodic && !ep->periodic) ||
2059 (!periodic && ep->periodic))
2062 ret = s3c_hsotg_trytx(hsotg, ep);
2068 /* IRQ flags which will trigger a retry around the IRQ loop */
2069 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2074 * s3c_hsotg_corereset - issue softreset to the core
2075 * @hsotg: The device state
2077 * Issue a soft reset to the core, and await the core finishing it.
2079 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2084 dev_dbg(hsotg->dev, "resetting core\n");
2086 /* issue soft reset */
2087 writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
2091 grstctl = readl(hsotg->regs + GRSTCTL);
2092 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
2094 if (grstctl & GRSTCTL_CSFTRST) {
2095 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2102 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2104 if (timeout-- < 0) {
2105 dev_info(hsotg->dev,
2106 "%s: reset failed, GRSTCTL=%08x\n",
2111 if (!(grstctl & GRSTCTL_AHBIDLE))
2114 break; /* reset done */
2117 dev_dbg(hsotg->dev, "reset successful\n");
2122 * s3c_hsotg_core_init - issue softreset to the core
2123 * @hsotg: The device state
2125 * Issue a soft reset to the core, and await the core finishing it.
2127 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2129 s3c_hsotg_corereset(hsotg);
2132 * we must now enable ep0 ready for host detection and then
2133 * set configuration.
2136 /* set the PLL on, remove the HNP/SRP and set the PHY */
2137 writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2138 (0x5 << 10), hsotg->regs + GUSBCFG);
2140 s3c_hsotg_init_fifo(hsotg);
2142 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2144 writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2146 /* Clear any pending OTG interrupts */
2147 writel(0xffffffff, hsotg->regs + GOTGINT);
2149 /* Clear any pending interrupts */
2150 writel(0xffffffff, hsotg->regs + GINTSTS);
2152 writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2153 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2154 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2155 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2156 GINTSTS_USBSUSP | GINTSTS_WKUPINT,
2157 hsotg->regs + GINTMSK);
2159 if (using_dma(hsotg))
2160 writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2161 GAHBCFG_HBSTLEN_INCR4,
2162 hsotg->regs + GAHBCFG);
2164 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL |
2165 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2166 GAHBCFG_GLBL_INTR_EN,
2167 hsotg->regs + GAHBCFG);
2170 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2171 * when we have no data to transfer. Otherwise we get being flooded by
2175 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY |
2176 DIEPMSK_INTKNTXFEMPMSK : 0) |
2177 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2178 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2179 DIEPMSK_INTKNEPMISMSK,
2180 hsotg->regs + DIEPMSK);
2183 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2184 * DMA mode we may need this.
2186 writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2187 DIEPMSK_TIMEOUTMSK) : 0) |
2188 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2190 hsotg->regs + DOEPMSK);
2192 writel(0, hsotg->regs + DAINTMSK);
2194 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2195 readl(hsotg->regs + DIEPCTL0),
2196 readl(hsotg->regs + DOEPCTL0));
2198 /* enable in and out endpoint interrupts */
2199 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2202 * Enable the RXFIFO when in slave mode, as this is how we collect
2203 * the data. In DMA mode, we get events from the FIFO but also
2204 * things we cannot process, so do not use it.
2206 if (!using_dma(hsotg))
2207 s3c_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2209 /* Enable interrupts for EP0 in and out */
2210 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2211 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2213 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2214 udelay(10); /* see openiboot */
2215 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2217 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2220 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2221 * writing to the EPCTL register..
2224 /* set to read 1 8byte packet */
2225 writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2226 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2228 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2229 DXEPCTL_CNAK | DXEPCTL_EPENA |
2231 hsotg->regs + DOEPCTL0);
2233 /* enable, but don't activate EP0in */
2234 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2235 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2237 s3c_hsotg_enqueue_setup(hsotg);
2239 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2240 readl(hsotg->regs + DIEPCTL0),
2241 readl(hsotg->regs + DOEPCTL0));
2243 /* clear global NAKs */
2244 writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK,
2245 hsotg->regs + DCTL);
2247 /* must be at-least 3ms to allow bus to see disconnect */
2250 /* remove the soft-disconnect and let's go */
2251 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2255 * s3c_hsotg_irq - handle device interrupt
2256 * @irq: The IRQ number triggered
2257 * @pw: The pw value when registered the handler.
2259 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2261 struct s3c_hsotg *hsotg = pw;
2262 int retry_count = 8;
2266 spin_lock(&hsotg->lock);
2268 gintsts = readl(hsotg->regs + GINTSTS);
2269 gintmsk = readl(hsotg->regs + GINTMSK);
2271 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2272 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2276 if (gintsts & GINTSTS_OTGINT) {
2277 u32 otgint = readl(hsotg->regs + GOTGINT);
2279 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2281 writel(otgint, hsotg->regs + GOTGINT);
2284 if (gintsts & GINTSTS_SESSREQINT) {
2285 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2286 writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
2289 if (gintsts & GINTSTS_ENUMDONE) {
2290 writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2292 s3c_hsotg_irq_enumdone(hsotg);
2295 if (gintsts & GINTSTS_CONIDSTSCHNG) {
2296 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2297 readl(hsotg->regs + DSTS),
2298 readl(hsotg->regs + GOTGCTL));
2300 writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
2303 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2304 u32 daint = readl(hsotg->regs + DAINT);
2305 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2306 u32 daint_out, daint_in;
2310 daint_out = daint >> DAINT_OUTEP_SHIFT;
2311 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2313 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2315 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2317 s3c_hsotg_epint(hsotg, ep, 0);
2320 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2322 s3c_hsotg_epint(hsotg, ep, 1);
2326 if (gintsts & GINTSTS_USBRST) {
2328 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2330 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2331 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2332 readl(hsotg->regs + GNPTXSTS));
2334 writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2336 if (usb_status & GOTGCTL_BSESVLD) {
2337 if (time_after(jiffies, hsotg->last_rst +
2338 msecs_to_jiffies(200))) {
2340 kill_all_requests(hsotg, &hsotg->eps[0],
2343 s3c_hsotg_core_init(hsotg);
2344 hsotg->last_rst = jiffies;
2349 /* check both FIFOs */
2351 if (gintsts & GINTSTS_NPTXFEMP) {
2352 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2355 * Disable the interrupt to stop it happening again
2356 * unless one of these endpoint routines decides that
2357 * it needs re-enabling
2360 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2361 s3c_hsotg_irq_fifoempty(hsotg, false);
2364 if (gintsts & GINTSTS_PTXFEMP) {
2365 dev_dbg(hsotg->dev, "PTxFEmp\n");
2367 /* See note in GINTSTS_NPTxFEmp */
2369 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2370 s3c_hsotg_irq_fifoempty(hsotg, true);
2373 if (gintsts & GINTSTS_RXFLVL) {
2375 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2376 * we need to retry s3c_hsotg_handle_rx if this is still
2380 s3c_hsotg_handle_rx(hsotg);
2383 if (gintsts & GINTSTS_MODEMIS) {
2384 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2385 writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
2388 if (gintsts & GINTSTS_USBSUSP) {
2389 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2390 writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
2392 call_gadget(hsotg, suspend);
2395 if (gintsts & GINTSTS_WKUPINT) {
2396 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2397 writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
2399 call_gadget(hsotg, resume);
2402 if (gintsts & GINTSTS_ERLYSUSP) {
2403 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2404 writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2408 * these next two seem to crop-up occasionally causing the core
2409 * to shutdown the USB transfer, so try clearing them and logging
2413 if (gintsts & GINTSTS_GOUTNAKEFF) {
2414 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2416 writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
2418 s3c_hsotg_dump(hsotg);
2421 if (gintsts & GINTSTS_GINNAKEFF) {
2422 dev_info(hsotg->dev, "GINNakEff triggered\n");
2424 writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2426 s3c_hsotg_dump(hsotg);
2430 * if we've had fifo events, we should try and go around the
2431 * loop again to see if there's any point in returning yet.
2434 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2437 spin_unlock(&hsotg->lock);
2443 * s3c_hsotg_ep_enable - enable the given endpoint
2444 * @ep: The USB endpint to configure
2445 * @desc: The USB endpoint descriptor to configure with.
2447 * This is called from the USB gadget code's usb_ep_enable().
2449 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2450 const struct usb_endpoint_descriptor *desc)
2452 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2453 struct s3c_hsotg *hsotg = hs_ep->parent;
2454 unsigned long flags;
2455 int index = hs_ep->index;
2464 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2465 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2466 desc->wMaxPacketSize, desc->bInterval);
2468 /* not to be called for EP0 */
2469 WARN_ON(index == 0);
2471 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2472 if (dir_in != hs_ep->dir_in) {
2473 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2477 mps = usb_endpoint_maxp(desc);
2479 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2481 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2482 epctrl = readl(hsotg->regs + epctrl_reg);
2484 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2485 __func__, epctrl, epctrl_reg);
2487 spin_lock_irqsave(&hsotg->lock, flags);
2489 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2490 epctrl |= DXEPCTL_MPS(mps);
2493 * mark the endpoint as active, otherwise the core may ignore
2494 * transactions entirely for this endpoint
2496 epctrl |= DXEPCTL_USBACTEP;
2499 * set the NAK status on the endpoint, otherwise we might try and
2500 * do something with data that we've yet got a request to process
2501 * since the RXFIFO will take data for an endpoint even if the
2502 * size register hasn't been set.
2505 epctrl |= DXEPCTL_SNAK;
2507 /* update the endpoint state */
2508 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2510 /* default, set to non-periodic */
2511 hs_ep->isochronous = 0;
2512 hs_ep->periodic = 0;
2514 hs_ep->interval = desc->bInterval;
2516 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2517 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2519 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2520 case USB_ENDPOINT_XFER_ISOC:
2521 epctrl |= DXEPCTL_EPTYPE_ISO;
2522 epctrl |= DXEPCTL_SETEVENFR;
2523 hs_ep->isochronous = 1;
2525 hs_ep->periodic = 1;
2528 case USB_ENDPOINT_XFER_BULK:
2529 epctrl |= DXEPCTL_EPTYPE_BULK;
2532 case USB_ENDPOINT_XFER_INT:
2534 hs_ep->periodic = 1;
2536 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2539 case USB_ENDPOINT_XFER_CONTROL:
2540 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2545 * if the hardware has dedicated fifos, we must give each IN EP
2546 * a unique tx-fifo even if it is non-periodic.
2548 if (dir_in && hsotg->dedicated_fifos) {
2549 size = hs_ep->ep.maxpacket*hs_ep->mc;
2550 for (i = 1; i <= 8; ++i) {
2551 if (hsotg->fifo_map & (1<<i))
2553 val = readl(hsotg->regs + DPTXFSIZN(i));
2554 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2557 hsotg->fifo_map |= 1<<i;
2559 epctrl |= DXEPCTL_TXFNUM(i);
2560 hs_ep->fifo_index = i;
2561 hs_ep->fifo_size = val;
2568 /* for non control endpoints, set PID to D0 */
2570 epctrl |= DXEPCTL_SETD0PID;
2572 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2575 writel(epctrl, hsotg->regs + epctrl_reg);
2576 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2577 __func__, readl(hsotg->regs + epctrl_reg));
2579 /* enable the endpoint interrupt */
2580 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2582 spin_unlock_irqrestore(&hsotg->lock, flags);
2587 * s3c_hsotg_ep_disable - disable given endpoint
2588 * @ep: The endpoint to disable.
2590 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2592 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2593 struct s3c_hsotg *hsotg = hs_ep->parent;
2594 int dir_in = hs_ep->dir_in;
2595 int index = hs_ep->index;
2596 unsigned long flags;
2600 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2602 if (ep == &hsotg->eps[0].ep) {
2603 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2607 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2609 spin_lock_irqsave(&hsotg->lock, flags);
2610 /* terminate all requests with shutdown */
2611 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2613 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2614 hs_ep->fifo_index = 0;
2615 hs_ep->fifo_size = 0;
2617 ctrl = readl(hsotg->regs + epctrl_reg);
2618 ctrl &= ~DXEPCTL_EPENA;
2619 ctrl &= ~DXEPCTL_USBACTEP;
2620 ctrl |= DXEPCTL_SNAK;
2622 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2623 writel(ctrl, hsotg->regs + epctrl_reg);
2625 /* disable endpoint interrupts */
2626 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2628 spin_unlock_irqrestore(&hsotg->lock, flags);
2633 * on_list - check request is on the given endpoint
2634 * @ep: The endpoint to check.
2635 * @test: The request to test if it is on the endpoint.
2637 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2639 struct s3c_hsotg_req *req, *treq;
2641 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2650 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2651 * @ep: The endpoint to dequeue.
2652 * @req: The request to be removed from a queue.
2654 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2656 struct s3c_hsotg_req *hs_req = our_req(req);
2657 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2658 struct s3c_hsotg *hs = hs_ep->parent;
2659 unsigned long flags;
2661 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2663 spin_lock_irqsave(&hs->lock, flags);
2665 if (!on_list(hs_ep, hs_req)) {
2666 spin_unlock_irqrestore(&hs->lock, flags);
2670 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2671 spin_unlock_irqrestore(&hs->lock, flags);
2677 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2678 * @ep: The endpoint to set halt.
2679 * @value: Set or unset the halt.
2681 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2683 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2684 struct s3c_hsotg *hs = hs_ep->parent;
2685 int index = hs_ep->index;
2690 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2694 s3c_hsotg_stall_ep0(hs);
2697 "%s: can't clear halt on ep0\n", __func__);
2701 /* write both IN and OUT control registers */
2703 epreg = DIEPCTL(index);
2704 epctl = readl(hs->regs + epreg);
2707 epctl |= DXEPCTL_STALL + DXEPCTL_SNAK;
2708 if (epctl & DXEPCTL_EPENA)
2709 epctl |= DXEPCTL_EPDIS;
2711 epctl &= ~DXEPCTL_STALL;
2712 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2713 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2714 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2715 epctl |= DXEPCTL_SETD0PID;
2718 writel(epctl, hs->regs + epreg);
2720 epreg = DOEPCTL(index);
2721 epctl = readl(hs->regs + epreg);
2724 epctl |= DXEPCTL_STALL;
2726 epctl &= ~DXEPCTL_STALL;
2727 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2728 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2729 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2730 epctl |= DXEPCTL_SETD0PID;
2733 writel(epctl, hs->regs + epreg);
2735 hs_ep->halted = value;
2741 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2742 * @ep: The endpoint to set halt.
2743 * @value: Set or unset the halt.
2745 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2747 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2748 struct s3c_hsotg *hs = hs_ep->parent;
2749 unsigned long flags = 0;
2752 spin_lock_irqsave(&hs->lock, flags);
2753 ret = s3c_hsotg_ep_sethalt(ep, value);
2754 spin_unlock_irqrestore(&hs->lock, flags);
2759 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2760 .enable = s3c_hsotg_ep_enable,
2761 .disable = s3c_hsotg_ep_disable,
2762 .alloc_request = s3c_hsotg_ep_alloc_request,
2763 .free_request = s3c_hsotg_ep_free_request,
2764 .queue = s3c_hsotg_ep_queue_lock,
2765 .dequeue = s3c_hsotg_ep_dequeue,
2766 .set_halt = s3c_hsotg_ep_sethalt_lock,
2767 /* note, don't believe we have any call for the fifo routines */
2771 * s3c_hsotg_phy_enable - enable platform phy dev
2772 * @hsotg: The driver state
2774 * A wrapper for platform code responsible for controlling
2775 * low-level USB code
2777 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2779 struct platform_device *pdev = to_platform_device(hsotg->dev);
2781 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2784 usb_phy_init(hsotg->uphy);
2785 else if (hsotg->plat && hsotg->plat->phy_init)
2786 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2788 phy_init(hsotg->phy);
2789 phy_power_on(hsotg->phy);
2794 * s3c_hsotg_phy_disable - disable platform phy dev
2795 * @hsotg: The driver state
2797 * A wrapper for platform code responsible for controlling
2798 * low-level USB code
2800 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2802 struct platform_device *pdev = to_platform_device(hsotg->dev);
2805 usb_phy_shutdown(hsotg->uphy);
2806 else if (hsotg->plat && hsotg->plat->phy_exit)
2807 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2809 phy_power_off(hsotg->phy);
2810 phy_exit(hsotg->phy);
2815 * s3c_hsotg_init - initalize the usb core
2816 * @hsotg: The driver state
2818 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2820 /* unmask subset of endpoint interrupts */
2822 writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2823 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
2824 hsotg->regs + DIEPMSK);
2826 writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
2827 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
2828 hsotg->regs + DOEPMSK);
2830 writel(0, hsotg->regs + DAINTMSK);
2832 /* Be in disconnected state until gadget is registered */
2833 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2836 /* post global nak until we're ready */
2837 writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK,
2838 hsotg->regs + DCTL);
2843 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2844 readl(hsotg->regs + GRXFSIZ),
2845 readl(hsotg->regs + GNPTXFSIZ));
2847 s3c_hsotg_init_fifo(hsotg);
2849 /* set the PLL on, remove the HNP/SRP and set the PHY */
2850 writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10),
2851 hsotg->regs + GUSBCFG);
2853 writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0,
2854 hsotg->regs + GAHBCFG);
2858 * s3c_hsotg_udc_start - prepare the udc for work
2859 * @gadget: The usb gadget state
2860 * @driver: The usb gadget driver
2862 * Perform initialization to prepare udc device and driver
2865 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2866 struct usb_gadget_driver *driver)
2868 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2872 pr_err("%s: called with no device\n", __func__);
2877 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2881 if (driver->max_speed < USB_SPEED_FULL)
2882 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2884 if (!driver->setup) {
2885 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2889 WARN_ON(hsotg->driver);
2891 driver->driver.bus = NULL;
2892 hsotg->driver = driver;
2893 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
2894 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2896 clk_enable(hsotg->clk);
2898 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
2901 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
2905 hsotg->last_rst = jiffies;
2906 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2910 hsotg->driver = NULL;
2915 * s3c_hsotg_udc_stop - stop the udc
2916 * @gadget: The usb gadget state
2917 * @driver: The usb gadget driver
2919 * Stop udc hw block and stay tunned for future transmissions
2921 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
2922 struct usb_gadget_driver *driver)
2924 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2925 unsigned long flags = 0;
2931 /* all endpoints should be shutdown */
2932 for (ep = 1; ep < hsotg->num_of_eps; ep++)
2933 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2935 spin_lock_irqsave(&hsotg->lock, flags);
2938 hsotg->driver = NULL;
2940 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2942 spin_unlock_irqrestore(&hsotg->lock, flags);
2944 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
2946 clk_disable(hsotg->clk);
2952 * s3c_hsotg_gadget_getframe - read the frame number
2953 * @gadget: The usb gadget state
2955 * Read the {micro} frame number
2957 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2959 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2963 * s3c_hsotg_pullup - connect/disconnect the USB PHY
2964 * @gadget: The usb gadget state
2965 * @is_on: Current state of the USB PHY
2967 * Connect/Disconnect the USB PHY pullup
2969 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
2971 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2972 unsigned long flags = 0;
2974 dev_dbg(hsotg->dev, "%s: is_on: %d\n", __func__, is_on);
2976 spin_lock_irqsave(&hsotg->lock, flags);
2978 s3c_hsotg_phy_enable(hsotg);
2979 clk_enable(hsotg->clk);
2980 s3c_hsotg_core_init(hsotg);
2982 clk_disable(hsotg->clk);
2983 s3c_hsotg_phy_disable(hsotg);
2986 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2987 spin_unlock_irqrestore(&hsotg->lock, flags);
2992 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2993 .get_frame = s3c_hsotg_gadget_getframe,
2994 .udc_start = s3c_hsotg_udc_start,
2995 .udc_stop = s3c_hsotg_udc_stop,
2996 .pullup = s3c_hsotg_pullup,
3000 * s3c_hsotg_initep - initialise a single endpoint
3001 * @hsotg: The device state.
3002 * @hs_ep: The endpoint to be initialised.
3003 * @epnum: The endpoint number
3005 * Initialise the given endpoint (as part of the probe and device state
3006 * creation) to give to the gadget driver. Setup the endpoint name, any
3007 * direction information and other state that may be required.
3009 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3010 struct s3c_hsotg_ep *hs_ep,
3017 else if ((epnum % 2) == 0) {
3024 hs_ep->index = epnum;
3026 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3028 INIT_LIST_HEAD(&hs_ep->queue);
3029 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3031 /* add to the list of endpoints known by the gadget driver */
3033 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3035 hs_ep->parent = hsotg;
3036 hs_ep->ep.name = hs_ep->name;
3037 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3038 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3041 * if we're using dma, we need to set the next-endpoint pointer
3042 * to be something valid.
3045 if (using_dma(hsotg)) {
3046 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3047 writel(next, hsotg->regs + DIEPCTL(epnum));
3048 writel(next, hsotg->regs + DOEPCTL(epnum));
3053 * s3c_hsotg_hw_cfg - read HW configuration registers
3054 * @param: The device state
3056 * Read the USB core HW configuration registers
3058 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3060 u32 cfg2, cfg3, cfg4;
3061 /* check hardware configuration */
3063 cfg2 = readl(hsotg->regs + 0x48);
3064 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3066 cfg3 = readl(hsotg->regs + 0x4C);
3067 hsotg->fifo_mem = (cfg3 >> 16);
3069 cfg4 = readl(hsotg->regs + 0x50);
3070 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3072 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3074 hsotg->dedicated_fifos ? "dedicated" : "shared",
3079 * s3c_hsotg_dump - dump state of the udc
3080 * @param: The device state
3082 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3085 struct device *dev = hsotg->dev;
3086 void __iomem *regs = hsotg->regs;
3090 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3091 readl(regs + DCFG), readl(regs + DCTL),
3092 readl(regs + DIEPMSK));
3094 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3095 readl(regs + GAHBCFG), readl(regs + 0x44));
3097 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3098 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3100 /* show periodic fifo settings */
3102 for (idx = 1; idx <= 15; idx++) {
3103 val = readl(regs + DPTXFSIZN(idx));
3104 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3105 val >> FIFOSIZE_DEPTH_SHIFT,
3106 val & FIFOSIZE_STARTADDR_MASK);
3109 for (idx = 0; idx < 15; idx++) {
3111 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3112 readl(regs + DIEPCTL(idx)),
3113 readl(regs + DIEPTSIZ(idx)),
3114 readl(regs + DIEPDMA(idx)));
3116 val = readl(regs + DOEPCTL(idx));
3118 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3119 idx, readl(regs + DOEPCTL(idx)),
3120 readl(regs + DOEPTSIZ(idx)),
3121 readl(regs + DOEPDMA(idx)));
3125 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3126 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3131 * state_show - debugfs: show overall driver and device state.
3132 * @seq: The seq file to write to.
3133 * @v: Unused parameter.
3135 * This debugfs entry shows the overall state of the hardware and
3136 * some general information about each of the endpoints available
3139 static int state_show(struct seq_file *seq, void *v)
3141 struct s3c_hsotg *hsotg = seq->private;
3142 void __iomem *regs = hsotg->regs;
3145 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3148 readl(regs + DSTS));
3150 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3151 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3153 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3154 readl(regs + GINTMSK),
3155 readl(regs + GINTSTS));
3157 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3158 readl(regs + DAINTMSK),
3159 readl(regs + DAINT));
3161 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3162 readl(regs + GNPTXSTS),
3163 readl(regs + GRXSTSR));
3165 seq_puts(seq, "\nEndpoint status:\n");
3167 for (idx = 0; idx < 15; idx++) {
3170 in = readl(regs + DIEPCTL(idx));
3171 out = readl(regs + DOEPCTL(idx));
3173 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3176 in = readl(regs + DIEPTSIZ(idx));
3177 out = readl(regs + DOEPTSIZ(idx));
3179 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3182 seq_puts(seq, "\n");
3188 static int state_open(struct inode *inode, struct file *file)
3190 return single_open(file, state_show, inode->i_private);
3193 static const struct file_operations state_fops = {
3194 .owner = THIS_MODULE,
3197 .llseek = seq_lseek,
3198 .release = single_release,
3202 * fifo_show - debugfs: show the fifo information
3203 * @seq: The seq_file to write data to.
3204 * @v: Unused parameter.
3206 * Show the FIFO information for the overall fifo and all the
3207 * periodic transmission FIFOs.
3209 static int fifo_show(struct seq_file *seq, void *v)
3211 struct s3c_hsotg *hsotg = seq->private;
3212 void __iomem *regs = hsotg->regs;
3216 seq_puts(seq, "Non-periodic FIFOs:\n");
3217 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3219 val = readl(regs + GNPTXFSIZ);
3220 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3221 val >> FIFOSIZE_DEPTH_SHIFT,
3222 val & FIFOSIZE_DEPTH_MASK);
3224 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3226 for (idx = 1; idx <= 15; idx++) {
3227 val = readl(regs + DPTXFSIZN(idx));
3229 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3230 val >> FIFOSIZE_DEPTH_SHIFT,
3231 val & FIFOSIZE_STARTADDR_MASK);
3237 static int fifo_open(struct inode *inode, struct file *file)
3239 return single_open(file, fifo_show, inode->i_private);
3242 static const struct file_operations fifo_fops = {
3243 .owner = THIS_MODULE,
3246 .llseek = seq_lseek,
3247 .release = single_release,
3251 static const char *decode_direction(int is_in)
3253 return is_in ? "in" : "out";
3257 * ep_show - debugfs: show the state of an endpoint.
3258 * @seq: The seq_file to write data to.
3259 * @v: Unused parameter.
3261 * This debugfs entry shows the state of the given endpoint (one is
3262 * registered for each available).
3264 static int ep_show(struct seq_file *seq, void *v)
3266 struct s3c_hsotg_ep *ep = seq->private;
3267 struct s3c_hsotg *hsotg = ep->parent;
3268 struct s3c_hsotg_req *req;
3269 void __iomem *regs = hsotg->regs;
3270 int index = ep->index;
3271 int show_limit = 15;
3272 unsigned long flags;
3274 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3275 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3277 /* first show the register state */
3279 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3280 readl(regs + DIEPCTL(index)),
3281 readl(regs + DOEPCTL(index)));
3283 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3284 readl(regs + DIEPDMA(index)),
3285 readl(regs + DOEPDMA(index)));
3287 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3288 readl(regs + DIEPINT(index)),
3289 readl(regs + DOEPINT(index)));
3291 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3292 readl(regs + DIEPTSIZ(index)),
3293 readl(regs + DOEPTSIZ(index)));
3295 seq_puts(seq, "\n");
3296 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3297 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3299 seq_printf(seq, "request list (%p,%p):\n",
3300 ep->queue.next, ep->queue.prev);
3302 spin_lock_irqsave(&hsotg->lock, flags);
3304 list_for_each_entry(req, &ep->queue, queue) {
3305 if (--show_limit < 0) {
3306 seq_puts(seq, "not showing more requests...\n");
3310 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3311 req == ep->req ? '*' : ' ',
3312 req, req->req.length, req->req.buf);
3313 seq_printf(seq, "%d done, res %d\n",
3314 req->req.actual, req->req.status);
3317 spin_unlock_irqrestore(&hsotg->lock, flags);
3322 static int ep_open(struct inode *inode, struct file *file)
3324 return single_open(file, ep_show, inode->i_private);
3327 static const struct file_operations ep_fops = {
3328 .owner = THIS_MODULE,
3331 .llseek = seq_lseek,
3332 .release = single_release,
3336 * s3c_hsotg_create_debug - create debugfs directory and files
3337 * @hsotg: The driver state
3339 * Create the debugfs files to allow the user to get information
3340 * about the state of the system. The directory name is created
3341 * with the same name as the device itself, in case we end up
3342 * with multiple blocks in future systems.
3344 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3346 struct dentry *root;
3349 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3350 hsotg->debug_root = root;
3352 dev_err(hsotg->dev, "cannot create debug root\n");
3356 /* create general state file */
3358 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3359 hsotg, &state_fops);
3361 if (IS_ERR(hsotg->debug_file))
3362 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3364 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3367 if (IS_ERR(hsotg->debug_fifo))
3368 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3370 /* create one file for each endpoint */
3372 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3373 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3375 ep->debugfs = debugfs_create_file(ep->name, 0444,
3376 root, ep, &ep_fops);
3378 if (IS_ERR(ep->debugfs))
3379 dev_err(hsotg->dev, "failed to create %s debug file\n",
3385 * s3c_hsotg_delete_debug - cleanup debugfs entries
3386 * @hsotg: The driver state
3388 * Cleanup (remove) the debugfs files for use on module exit.
3390 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3394 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3395 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3396 debugfs_remove(ep->debugfs);
3399 debugfs_remove(hsotg->debug_file);
3400 debugfs_remove(hsotg->debug_fifo);
3401 debugfs_remove(hsotg->debug_root);
3405 * s3c_hsotg_probe - probe function for hsotg driver
3406 * @pdev: The platform information for the driver
3409 static int s3c_hsotg_probe(struct platform_device *pdev)
3411 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3413 struct usb_phy *uphy;
3414 struct device *dev = &pdev->dev;
3415 struct s3c_hsotg_ep *eps;
3416 struct s3c_hsotg *hsotg;
3417 struct resource *res;
3422 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3426 /* Set default UTMI width */
3427 hsotg->phyif = GUSBCFG_PHYIF16;
3430 * Attempt to find a generic PHY, then look for an old style
3431 * USB PHY, finally fall back to pdata
3433 phy = devm_phy_get(&pdev->dev, "usb2-phy");
3435 uphy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3437 /* Fallback for pdata */
3438 plat = dev_get_platdata(&pdev->dev);
3441 "no platform data or transceiver defined\n");
3442 return -EPROBE_DEFER;
3450 * If using the generic PHY framework, check if the PHY bus
3451 * width is 8-bit and set the phyif appropriately.
3453 if (phy_get_bus_width(phy) == 8)
3454 hsotg->phyif = GUSBCFG_PHYIF8;
3459 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3460 if (IS_ERR(hsotg->clk)) {
3461 dev_err(dev, "cannot get otg clock\n");
3462 return PTR_ERR(hsotg->clk);
3465 platform_set_drvdata(pdev, hsotg);
3467 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3469 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3470 if (IS_ERR(hsotg->regs)) {
3471 ret = PTR_ERR(hsotg->regs);
3475 ret = platform_get_irq(pdev, 0);
3477 dev_err(dev, "cannot find IRQ\n");
3481 spin_lock_init(&hsotg->lock);
3485 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3487 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3488 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3489 hsotg->gadget.name = dev_name(dev);
3491 /* reset the system */
3493 clk_prepare_enable(hsotg->clk);
3497 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3498 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3500 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3503 dev_err(dev, "failed to request supplies: %d\n", ret);
3507 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3511 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3515 /* usb phy enable */
3516 s3c_hsotg_phy_enable(hsotg);
3518 s3c_hsotg_corereset(hsotg);
3519 s3c_hsotg_hw_cfg(hsotg);
3520 s3c_hsotg_init(hsotg);
3522 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3523 dev_name(dev), hsotg);
3525 s3c_hsotg_phy_disable(hsotg);
3526 clk_disable_unprepare(hsotg->clk);
3527 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3529 dev_err(dev, "cannot claim IRQ\n");
3533 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3535 if (hsotg->num_of_eps == 0) {
3536 dev_err(dev, "wrong number of EPs (zero)\n");
3541 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3550 /* setup endpoint information */
3552 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3553 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3555 /* allocate EP0 request */
3557 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3559 if (!hsotg->ctrl_req) {
3560 dev_err(dev, "failed to allocate ctrl req\n");
3565 /* initialise the endpoints now the core has been initialised */
3566 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3567 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3569 /* disable power and clock */
3571 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3574 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3578 s3c_hsotg_phy_disable(hsotg);
3580 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3584 s3c_hsotg_create_debug(hsotg);
3586 s3c_hsotg_dump(hsotg);
3593 s3c_hsotg_phy_disable(hsotg);
3595 clk_disable_unprepare(hsotg->clk);
3601 * s3c_hsotg_remove - remove function for hsotg driver
3602 * @pdev: The platform information for the driver
3604 static int s3c_hsotg_remove(struct platform_device *pdev)
3606 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3608 usb_del_gadget_udc(&hsotg->gadget);
3610 s3c_hsotg_delete_debug(hsotg);
3612 if (hsotg->driver) {
3613 /* should have been done already by driver model core */
3614 usb_gadget_unregister_driver(hsotg->driver);
3617 clk_disable_unprepare(hsotg->clk);
3622 static int s3c_hsotg_suspend(struct platform_device *pdev, pm_message_t state)
3624 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3625 unsigned long flags;
3629 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3630 hsotg->driver->driver.name);
3632 spin_lock_irqsave(&hsotg->lock, flags);
3633 s3c_hsotg_disconnect(hsotg);
3634 s3c_hsotg_phy_disable(hsotg);
3635 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3636 spin_unlock_irqrestore(&hsotg->lock, flags);
3638 if (hsotg->driver) {
3640 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3641 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3643 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3645 clk_disable(hsotg->clk);
3651 static int s3c_hsotg_resume(struct platform_device *pdev)
3653 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3654 unsigned long flags;
3657 if (hsotg->driver) {
3658 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3659 hsotg->driver->driver.name);
3661 clk_enable(hsotg->clk);
3662 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3666 spin_lock_irqsave(&hsotg->lock, flags);
3667 hsotg->last_rst = jiffies;
3668 s3c_hsotg_phy_enable(hsotg);
3669 s3c_hsotg_core_init(hsotg);
3670 spin_unlock_irqrestore(&hsotg->lock, flags);
3676 static const struct of_device_id s3c_hsotg_of_ids[] = {
3677 { .compatible = "samsung,s3c6400-hsotg", },
3678 { .compatible = "snps,dwc2", },
3681 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3684 static struct platform_driver s3c_hsotg_driver = {
3686 .name = "s3c-hsotg",
3687 .owner = THIS_MODULE,
3688 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3690 .probe = s3c_hsotg_probe,
3691 .remove = s3c_hsotg_remove,
3692 .suspend = s3c_hsotg_suspend,
3693 .resume = s3c_hsotg_resume,
3696 module_platform_driver(s3c_hsotg_driver);
3698 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3699 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3700 MODULE_LICENSE("GPL");
3701 MODULE_ALIAS("platform:s3c-hsotg");