2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/of_platform.h>
31 #include <linux/phy/phy.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/phy.h>
36 #include <linux/platform_data/s3c-hsotg.h>
41 /* conversion functions */
42 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
44 return container_of(req, struct dwc2_hsotg_req, req);
47 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
49 return container_of(ep, struct dwc2_hsotg_ep, ep);
52 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
54 return container_of(gadget, struct dwc2_hsotg, gadget);
57 static inline void __orr32(void __iomem *ptr, u32 val)
59 dwc2_writel(dwc2_readl(ptr) | val, ptr);
62 static inline void __bic32(void __iomem *ptr, u32 val)
64 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
67 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
68 u32 ep_index, u32 dir_in)
71 return hsotg->eps_in[ep_index];
73 return hsotg->eps_out[ep_index];
76 /* forward declaration of functions */
77 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
80 * using_dma - return the DMA status of the driver.
81 * @hsotg: The driver state.
83 * Return true if we're using DMA.
85 * Currently, we have the DMA support code worked into everywhere
86 * that needs it, but the AMBA DMA implementation in the hardware can
87 * only DMA from 32bit aligned addresses. This means that gadgets such
88 * as the CDC Ethernet cannot work as they often pass packets which are
91 * Unfortunately the choice to use DMA or not is global to the controller
92 * and seems to be only settable when the controller is being put through
93 * a core reset. This means we either need to fix the gadgets to take
94 * account of DMA alignment, or add bounce buffers (yuerk).
96 * g_using_dma is set depending on dts flag.
98 static inline bool using_dma(struct dwc2_hsotg *hsotg)
100 return hsotg->g_using_dma;
104 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
105 * @hsotg: The device state
106 * @ints: A bitmask of the interrupts to enable
108 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
110 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
113 new_gsintmsk = gsintmsk | ints;
115 if (new_gsintmsk != gsintmsk) {
116 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
117 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
122 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
123 * @hsotg: The device state
124 * @ints: A bitmask of the interrupts to enable
126 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
128 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
131 new_gsintmsk = gsintmsk & ~ints;
133 if (new_gsintmsk != gsintmsk)
134 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
138 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
139 * @hsotg: The device state
140 * @ep: The endpoint index
141 * @dir_in: True if direction is in.
142 * @en: The enable value, true to enable
144 * Set or clear the mask for an individual endpoint's interrupt
147 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
148 unsigned int ep, unsigned int dir_in,
158 local_irq_save(flags);
159 daint = dwc2_readl(hsotg->regs + DAINTMSK);
164 dwc2_writel(daint, hsotg->regs + DAINTMSK);
165 local_irq_restore(flags);
169 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
170 * @hsotg: The device instance.
172 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
179 /* Reset fifo map if not correctly cleared during previous session */
180 WARN_ON(hsotg->fifo_map);
183 /* set RX/NPTX FIFO sizes */
184 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
185 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
186 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
187 hsotg->regs + GNPTXFSIZ);
190 * arange all the rest of the TX FIFOs, as some versions of this
191 * block have overlapping default addresses. This also ensures
192 * that if the settings have been changed, then they are set to
196 /* start at the end of the GNPTXFSIZ, rounded up */
197 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
200 * Configure fifos sizes from provided configuration and assign
201 * them to endpoints dynamically according to maxpacket size value of
204 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
205 if (!hsotg->g_tx_fifo_sz[ep])
208 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
209 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
210 "insufficient fifo memory");
211 addr += hsotg->g_tx_fifo_sz[ep];
213 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
217 * according to p428 of the design guide, we need to ensure that
218 * all fifos are flushed before continuing
221 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
222 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
224 /* wait until the fifos are both flushed */
227 val = dwc2_readl(hsotg->regs + GRSTCTL);
229 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
232 if (--timeout == 0) {
234 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
242 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
246 * @ep: USB endpoint to allocate request for.
247 * @flags: Allocation flags
249 * Allocate a new USB request structure appropriate for the specified endpoint
251 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
254 struct dwc2_hsotg_req *req;
256 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
260 INIT_LIST_HEAD(&req->queue);
266 * is_ep_periodic - return true if the endpoint is in periodic mode.
267 * @hs_ep: The endpoint to query.
269 * Returns true if the endpoint is in periodic mode, meaning it is being
270 * used for an Interrupt or ISO transfer.
272 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
274 return hs_ep->periodic;
278 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
279 * @hsotg: The device state.
280 * @hs_ep: The endpoint for the request
281 * @hs_req: The request being processed.
283 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
284 * of a request to ensure the buffer is ready for access by the caller.
286 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
287 struct dwc2_hsotg_ep *hs_ep,
288 struct dwc2_hsotg_req *hs_req)
290 struct usb_request *req = &hs_req->req;
292 /* ignore this if we're not moving any data */
293 if (hs_req->req.length == 0)
296 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
300 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
301 * @hsotg: The controller state.
302 * @hs_ep: The endpoint we're going to write for.
303 * @hs_req: The request to write data for.
305 * This is called when the TxFIFO has some space in it to hold a new
306 * transmission and we have something to give it. The actual setup of
307 * the data size is done elsewhere, so all we have to do is to actually
310 * The return value is zero if there is more space (or nothing was done)
311 * otherwise -ENOSPC is returned if the FIFO space was used up.
313 * This routine is only needed for PIO
315 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
316 struct dwc2_hsotg_ep *hs_ep,
317 struct dwc2_hsotg_req *hs_req)
319 bool periodic = is_ep_periodic(hs_ep);
320 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
321 int buf_pos = hs_req->req.actual;
322 int to_write = hs_ep->size_loaded;
328 to_write -= (buf_pos - hs_ep->last_load);
330 /* if there's nothing to write, get out early */
334 if (periodic && !hsotg->dedicated_fifos) {
335 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
340 * work out how much data was loaded so we can calculate
341 * how much data is left in the fifo.
344 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
347 * if shared fifo, we cannot write anything until the
348 * previous data has been completely sent.
350 if (hs_ep->fifo_load != 0) {
351 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
355 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
357 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
359 /* how much of the data has moved */
360 size_done = hs_ep->size_loaded - size_left;
362 /* how much data is left in the fifo */
363 can_write = hs_ep->fifo_load - size_done;
364 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
365 __func__, can_write);
367 can_write = hs_ep->fifo_size - can_write;
368 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
369 __func__, can_write);
371 if (can_write <= 0) {
372 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
375 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
376 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
381 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
383 "%s: no queue slots available (0x%08x)\n",
386 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
390 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
391 can_write *= 4; /* fifo size is in 32bit quantities. */
394 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
396 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
397 __func__, gnptxsts, can_write, to_write, max_transfer);
400 * limit to 512 bytes of data, it seems at least on the non-periodic
401 * FIFO, requests of >512 cause the endpoint to get stuck with a
402 * fragment of the end of the transfer in it.
404 if (can_write > 512 && !periodic)
408 * limit the write to one max-packet size worth of data, but allow
409 * the transfer to return that it did not run out of fifo space
412 if (to_write > max_transfer) {
413 to_write = max_transfer;
415 /* it's needed only when we do not use dedicated fifos */
416 if (!hsotg->dedicated_fifos)
417 dwc2_hsotg_en_gsint(hsotg,
418 periodic ? GINTSTS_PTXFEMP :
422 /* see if we can write data */
424 if (to_write > can_write) {
425 to_write = can_write;
426 pkt_round = to_write % max_transfer;
429 * Round the write down to an
430 * exact number of packets.
432 * Note, we do not currently check to see if we can ever
433 * write a full packet or not to the FIFO.
437 to_write -= pkt_round;
440 * enable correct FIFO interrupt to alert us when there
444 /* it's needed only when we do not use dedicated fifos */
445 if (!hsotg->dedicated_fifos)
446 dwc2_hsotg_en_gsint(hsotg,
447 periodic ? GINTSTS_PTXFEMP :
451 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
452 to_write, hs_req->req.length, can_write, buf_pos);
457 hs_req->req.actual = buf_pos + to_write;
458 hs_ep->total_data += to_write;
461 hs_ep->fifo_load += to_write;
463 to_write = DIV_ROUND_UP(to_write, 4);
464 data = hs_req->req.buf + buf_pos;
466 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
468 return (to_write >= can_write) ? -ENOSPC : 0;
472 * get_ep_limit - get the maximum data legnth for this endpoint
473 * @hs_ep: The endpoint
475 * Return the maximum data that can be queued in one go on a given endpoint
476 * so that transfers that are too long can be split.
478 static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
480 int index = hs_ep->index;
485 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
486 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
490 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
495 /* we made the constant loading easier above by using +1 */
500 * constrain by packet count if maxpkts*pktsize is greater
501 * than the length register size.
504 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
505 maxsize = maxpkt * hs_ep->ep.maxpacket;
511 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
512 * @hsotg: The controller state.
513 * @hs_ep: The endpoint to process a request for
514 * @hs_req: The request to start.
515 * @continuing: True if we are doing more for the current request.
517 * Start the given request running by setting the endpoint registers
518 * appropriately, and writing any data to the FIFOs.
520 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
521 struct dwc2_hsotg_ep *hs_ep,
522 struct dwc2_hsotg_req *hs_req,
525 struct usb_request *ureq = &hs_req->req;
526 int index = hs_ep->index;
527 int dir_in = hs_ep->dir_in;
537 if (hs_ep->req && !continuing) {
538 dev_err(hsotg->dev, "%s: active request\n", __func__);
541 } else if (hs_ep->req != hs_req && continuing) {
543 "%s: continue different req\n", __func__);
549 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
550 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
552 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
553 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
554 hs_ep->dir_in ? "in" : "out");
556 /* If endpoint is stalled, we will restart request later */
557 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
559 if (ctrl & DXEPCTL_STALL) {
560 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
564 length = ureq->length - ureq->actual;
565 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
566 ureq->length, ureq->actual);
568 maxreq = get_ep_limit(hs_ep);
569 if (length > maxreq) {
570 int round = maxreq % hs_ep->ep.maxpacket;
572 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
573 __func__, length, maxreq, round);
575 /* round down to multiple of packets */
583 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
585 packets = 1; /* send one packet if length is zero. */
587 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
588 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
592 if (dir_in && index != 0)
593 if (hs_ep->isochronous)
594 epsize = DXEPTSIZ_MC(packets);
596 epsize = DXEPTSIZ_MC(1);
601 * zero length packet should be programmed on its own and should not
602 * be counted in DIEPTSIZ.PktCnt with other packets.
604 if (dir_in && ureq->zero && !continuing) {
605 /* Test if zlp is actually required. */
606 if ((ureq->length >= hs_ep->ep.maxpacket) &&
607 !(ureq->length % hs_ep->ep.maxpacket))
611 epsize |= DXEPTSIZ_PKTCNT(packets);
612 epsize |= DXEPTSIZ_XFERSIZE(length);
614 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
615 __func__, packets, length, ureq->length, epsize, epsize_reg);
617 /* store the request as the current one we're doing */
620 /* write size / packets */
621 dwc2_writel(epsize, hsotg->regs + epsize_reg);
623 if (using_dma(hsotg) && !continuing) {
624 unsigned int dma_reg;
627 * write DMA address to control register, buffer already
628 * synced by dwc2_hsotg_ep_queue().
631 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
632 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
634 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
635 __func__, &ureq->dma, dma_reg);
638 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
639 ctrl |= DXEPCTL_USBACTEP;
641 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
643 /* For Setup request do not clear NAK */
644 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
645 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
647 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
648 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
651 * set these, it seems that DMA support increments past the end
652 * of the packet buffer so we need to calculate the length from
655 hs_ep->size_loaded = length;
656 hs_ep->last_load = ureq->actual;
658 if (dir_in && !using_dma(hsotg)) {
659 /* set these anyway, we may need them for non-periodic in */
660 hs_ep->fifo_load = 0;
662 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
666 * clear the INTknTXFEmpMsk when we start request, more as a aide
667 * to debugging to see what is going on.
670 dwc2_writel(DIEPMSK_INTKNTXFEMPMSK,
671 hsotg->regs + DIEPINT(index));
674 * Note, trying to clear the NAK here causes problems with transmit
675 * on the S3C6400 ending up with the TXFIFO becoming full.
678 /* check ep is enabled */
679 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
681 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
682 index, dwc2_readl(hsotg->regs + epctrl_reg));
684 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
685 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
687 /* enable ep interrupts */
688 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
692 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
693 * @hsotg: The device state.
694 * @hs_ep: The endpoint the request is on.
695 * @req: The request being processed.
697 * We've been asked to queue a request, so ensure that the memory buffer
698 * is correctly setup for DMA. If we've been passed an extant DMA address
699 * then ensure the buffer has been synced to memory. If our buffer has no
700 * DMA memory, then we map the memory and mark our request to allow us to
701 * cleanup on completion.
703 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
704 struct dwc2_hsotg_ep *hs_ep,
705 struct usb_request *req)
707 struct dwc2_hsotg_req *hs_req = our_req(req);
710 /* if the length is zero, ignore the DMA data */
711 if (hs_req->req.length == 0)
714 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
721 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
722 __func__, req->buf, req->length);
727 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
728 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
730 void *req_buf = hs_req->req.buf;
732 /* If dma is not being used or buffer is aligned */
733 if (!using_dma(hsotg) || !((long)req_buf & 3))
736 WARN_ON(hs_req->saved_req_buf);
738 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
739 hs_ep->ep.name, req_buf, hs_req->req.length);
741 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
742 if (!hs_req->req.buf) {
743 hs_req->req.buf = req_buf;
745 "%s: unable to allocate memory for bounce buffer\n",
750 /* Save actual buffer */
751 hs_req->saved_req_buf = req_buf;
754 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
758 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
759 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
761 /* If dma is not being used or buffer was aligned */
762 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
765 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
766 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
768 /* Copy data from bounce buffer on successful out transfer */
769 if (!hs_ep->dir_in && !hs_req->req.status)
770 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
773 /* Free bounce buffer */
774 kfree(hs_req->req.buf);
776 hs_req->req.buf = hs_req->saved_req_buf;
777 hs_req->saved_req_buf = NULL;
780 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
783 struct dwc2_hsotg_req *hs_req = our_req(req);
784 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
785 struct dwc2_hsotg *hs = hs_ep->parent;
789 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
790 ep->name, req, req->length, req->buf, req->no_interrupt,
791 req->zero, req->short_not_ok);
793 /* Prevent new request submission when controller is suspended */
794 if (hs->lx_state == DWC2_L2) {
795 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
800 /* initialise status of the request */
801 INIT_LIST_HEAD(&hs_req->queue);
803 req->status = -EINPROGRESS;
805 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
809 /* if we're using DMA, sync the buffers as necessary */
811 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
816 first = list_empty(&hs_ep->queue);
817 list_add_tail(&hs_req->queue, &hs_ep->queue);
820 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
825 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
828 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
829 struct dwc2_hsotg *hs = hs_ep->parent;
830 unsigned long flags = 0;
833 spin_lock_irqsave(&hs->lock, flags);
834 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
835 spin_unlock_irqrestore(&hs->lock, flags);
840 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
841 struct usb_request *req)
843 struct dwc2_hsotg_req *hs_req = our_req(req);
849 * dwc2_hsotg_complete_oursetup - setup completion callback
850 * @ep: The endpoint the request was on.
851 * @req: The request completed.
853 * Called on completion of any requests the driver itself
854 * submitted that need cleaning up.
856 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
857 struct usb_request *req)
859 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
860 struct dwc2_hsotg *hsotg = hs_ep->parent;
862 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
864 dwc2_hsotg_ep_free_request(ep, req);
868 * ep_from_windex - convert control wIndex value to endpoint
869 * @hsotg: The driver state.
870 * @windex: The control request wIndex field (in host order).
872 * Convert the given wIndex into a pointer to an driver endpoint
873 * structure, or return NULL if it is not a valid endpoint.
875 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
878 struct dwc2_hsotg_ep *ep;
879 int dir = (windex & USB_DIR_IN) ? 1 : 0;
880 int idx = windex & 0x7F;
885 if (idx > hsotg->num_of_eps)
888 ep = index_to_ep(hsotg, idx, dir);
890 if (idx && ep->dir_in != dir)
897 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
898 * @hsotg: The driver state.
899 * @testmode: requested usb test mode
900 * Enable usb Test Mode requested by the Host.
902 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
904 int dctl = dwc2_readl(hsotg->regs + DCTL);
906 dctl &= ~DCTL_TSTCTL_MASK;
913 dctl |= testmode << DCTL_TSTCTL_SHIFT;
918 dwc2_writel(dctl, hsotg->regs + DCTL);
923 * dwc2_hsotg_send_reply - send reply to control request
924 * @hsotg: The device state
926 * @buff: Buffer for request
927 * @length: Length of reply.
929 * Create a request and queue it on the given endpoint. This is useful as
930 * an internal method of sending replies to certain control requests, etc.
932 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
933 struct dwc2_hsotg_ep *ep,
937 struct usb_request *req;
940 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
942 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
943 hsotg->ep0_reply = req;
945 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
949 req->buf = hsotg->ep0_buff;
950 req->length = length;
952 * zero flag is for sending zlp in DATA IN stage. It has no impact on
956 req->complete = dwc2_hsotg_complete_oursetup;
959 memcpy(req->buf, buff, length);
961 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
963 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
971 * dwc2_hsotg_process_req_status - process request GET_STATUS
972 * @hsotg: The device state
973 * @ctrl: USB control request
975 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
976 struct usb_ctrlrequest *ctrl)
978 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
979 struct dwc2_hsotg_ep *ep;
983 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
986 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
990 switch (ctrl->bRequestType & USB_RECIP_MASK) {
991 case USB_RECIP_DEVICE:
992 reply = cpu_to_le16(0); /* bit 0 => self powered,
993 * bit 1 => remote wakeup */
996 case USB_RECIP_INTERFACE:
997 /* currently, the data result should be zero */
998 reply = cpu_to_le16(0);
1001 case USB_RECIP_ENDPOINT:
1002 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1006 reply = cpu_to_le16(ep->halted ? 1 : 0);
1013 if (le16_to_cpu(ctrl->wLength) != 2)
1016 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1018 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1025 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1028 * get_ep_head - return the first request on the endpoint
1029 * @hs_ep: The controller endpoint to get
1031 * Get the first request on the endpoint.
1033 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1035 if (list_empty(&hs_ep->queue))
1038 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1042 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1043 * @hsotg: The device state
1044 * @ctrl: USB control request
1046 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1047 struct usb_ctrlrequest *ctrl)
1049 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1050 struct dwc2_hsotg_req *hs_req;
1052 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1053 struct dwc2_hsotg_ep *ep;
1060 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1061 __func__, set ? "SET" : "CLEAR");
1063 wValue = le16_to_cpu(ctrl->wValue);
1064 wIndex = le16_to_cpu(ctrl->wIndex);
1065 recip = ctrl->bRequestType & USB_RECIP_MASK;
1068 case USB_RECIP_DEVICE:
1070 case USB_DEVICE_TEST_MODE:
1071 if ((wIndex & 0xff) != 0)
1076 hsotg->test_mode = wIndex >> 8;
1077 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1080 "%s: failed to send reply\n", __func__);
1089 case USB_RECIP_ENDPOINT:
1090 ep = ep_from_windex(hsotg, wIndex);
1092 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1098 case USB_ENDPOINT_HALT:
1099 halted = ep->halted;
1101 dwc2_hsotg_ep_sethalt(&ep->ep, set);
1103 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1106 "%s: failed to send reply\n", __func__);
1111 * we have to complete all requests for ep if it was
1112 * halted, and the halt was cleared by CLEAR_FEATURE
1115 if (!set && halted) {
1117 * If we have request in progress,
1123 list_del_init(&hs_req->queue);
1124 if (hs_req->req.complete) {
1125 spin_unlock(&hsotg->lock);
1126 usb_gadget_giveback_request(
1127 &ep->ep, &hs_req->req);
1128 spin_lock(&hsotg->lock);
1132 /* If we have pending request, then start it */
1134 restart = !list_empty(&ep->queue);
1136 hs_req = get_ep_head(ep);
1137 dwc2_hsotg_start_req(hsotg, ep,
1155 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1158 * dwc2_hsotg_stall_ep0 - stall ep0
1159 * @hsotg: The device state
1161 * Set stall for ep0 as response for setup request.
1163 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1165 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1169 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1170 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1173 * DxEPCTL_Stall will be cleared by EP once it has
1174 * taken effect, so no need to clear later.
1177 ctrl = dwc2_readl(hsotg->regs + reg);
1178 ctrl |= DXEPCTL_STALL;
1179 ctrl |= DXEPCTL_CNAK;
1180 dwc2_writel(ctrl, hsotg->regs + reg);
1183 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1184 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1187 * complete won't be called, so we enqueue
1188 * setup request here
1190 dwc2_hsotg_enqueue_setup(hsotg);
1194 * dwc2_hsotg_process_control - process a control request
1195 * @hsotg: The device state
1196 * @ctrl: The control request received
1198 * The controller has received the SETUP phase of a control request, and
1199 * needs to work out what to do next (and whether to pass it on to the
1202 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1203 struct usb_ctrlrequest *ctrl)
1205 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1209 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1210 ctrl->bRequest, ctrl->bRequestType,
1211 ctrl->wValue, ctrl->wLength);
1213 if (ctrl->wLength == 0) {
1215 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1216 } else if (ctrl->bRequestType & USB_DIR_IN) {
1218 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1221 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1224 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1225 switch (ctrl->bRequest) {
1226 case USB_REQ_SET_ADDRESS:
1227 hsotg->connected = 1;
1228 dcfg = dwc2_readl(hsotg->regs + DCFG);
1229 dcfg &= ~DCFG_DEVADDR_MASK;
1230 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1231 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1232 dwc2_writel(dcfg, hsotg->regs + DCFG);
1234 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1236 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1239 case USB_REQ_GET_STATUS:
1240 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1243 case USB_REQ_CLEAR_FEATURE:
1244 case USB_REQ_SET_FEATURE:
1245 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1250 /* as a fallback, try delivering it to the driver to deal with */
1252 if (ret == 0 && hsotg->driver) {
1253 spin_unlock(&hsotg->lock);
1254 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1255 spin_lock(&hsotg->lock);
1257 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1261 * the request is either unhandlable, or is not formatted correctly
1262 * so respond with a STALL for the status stage to indicate failure.
1266 dwc2_hsotg_stall_ep0(hsotg);
1270 * dwc2_hsotg_complete_setup - completion of a setup transfer
1271 * @ep: The endpoint the request was on.
1272 * @req: The request completed.
1274 * Called on completion of any requests the driver itself submitted for
1277 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1278 struct usb_request *req)
1280 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1281 struct dwc2_hsotg *hsotg = hs_ep->parent;
1283 if (req->status < 0) {
1284 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1288 spin_lock(&hsotg->lock);
1289 if (req->actual == 0)
1290 dwc2_hsotg_enqueue_setup(hsotg);
1292 dwc2_hsotg_process_control(hsotg, req->buf);
1293 spin_unlock(&hsotg->lock);
1297 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1298 * @hsotg: The device state.
1300 * Enqueue a request on EP0 if necessary to received any SETUP packets
1301 * received from the host.
1303 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1305 struct usb_request *req = hsotg->ctrl_req;
1306 struct dwc2_hsotg_req *hs_req = our_req(req);
1309 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1313 req->buf = hsotg->ctrl_buff;
1314 req->complete = dwc2_hsotg_complete_setup;
1316 if (!list_empty(&hs_req->queue)) {
1317 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1321 hsotg->eps_out[0]->dir_in = 0;
1322 hsotg->eps_out[0]->send_zlp = 0;
1323 hsotg->ep0_state = DWC2_EP0_SETUP;
1325 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1327 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1329 * Don't think there's much we can do other than watch the
1335 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1336 struct dwc2_hsotg_ep *hs_ep)
1339 u8 index = hs_ep->index;
1340 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1341 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1344 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1347 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1350 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1351 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1354 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1355 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1356 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1357 ctrl |= DXEPCTL_USBACTEP;
1358 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1362 * dwc2_hsotg_complete_request - complete a request given to us
1363 * @hsotg: The device state.
1364 * @hs_ep: The endpoint the request was on.
1365 * @hs_req: The request to complete.
1366 * @result: The result code (0 => Ok, otherwise errno)
1368 * The given request has finished, so call the necessary completion
1369 * if it has one and then look to see if we can start a new request
1372 * Note, expects the ep to already be locked as appropriate.
1374 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1375 struct dwc2_hsotg_ep *hs_ep,
1376 struct dwc2_hsotg_req *hs_req,
1382 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1386 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1387 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1390 * only replace the status if we've not already set an error
1391 * from a previous transaction
1394 if (hs_req->req.status == -EINPROGRESS)
1395 hs_req->req.status = result;
1397 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1400 list_del_init(&hs_req->queue);
1402 if (using_dma(hsotg))
1403 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1406 * call the complete request with the locks off, just in case the
1407 * request tries to queue more work for this endpoint.
1410 if (hs_req->req.complete) {
1411 spin_unlock(&hsotg->lock);
1412 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1413 spin_lock(&hsotg->lock);
1417 * Look to see if there is anything else to do. Note, the completion
1418 * of the previous request may have caused a new request to be started
1419 * so be careful when doing this.
1422 if (!hs_ep->req && result >= 0) {
1423 restart = !list_empty(&hs_ep->queue);
1425 hs_req = get_ep_head(hs_ep);
1426 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1432 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1433 * @hsotg: The device state.
1434 * @ep_idx: The endpoint index for the data
1435 * @size: The size of data in the fifo, in bytes
1437 * The FIFO status shows there is data to read from the FIFO for a given
1438 * endpoint, so sort out whether we need to read the data into a request
1439 * that has been made for that endpoint.
1441 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1443 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1444 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1445 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1452 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1456 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1457 __func__, size, ep_idx, epctl);
1459 /* dump the data from the FIFO, we've nothing we can do */
1460 for (ptr = 0; ptr < size; ptr += 4)
1461 (void)dwc2_readl(fifo);
1467 read_ptr = hs_req->req.actual;
1468 max_req = hs_req->req.length - read_ptr;
1470 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1471 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1473 if (to_read > max_req) {
1475 * more data appeared than we where willing
1476 * to deal with in this request.
1479 /* currently we don't deal this */
1483 hs_ep->total_data += to_read;
1484 hs_req->req.actual += to_read;
1485 to_read = DIV_ROUND_UP(to_read, 4);
1488 * note, we might over-write the buffer end by 3 bytes depending on
1489 * alignment of the data.
1491 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1495 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1496 * @hsotg: The device instance
1497 * @dir_in: If IN zlp
1499 * Generate a zero-length IN packet request for terminating a SETUP
1502 * Note, since we don't write any data to the TxFIFO, then it is
1503 * currently believed that we do not need to wait for any space in
1506 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1508 /* eps_out[0] is used in both directions */
1509 hsotg->eps_out[0]->dir_in = dir_in;
1510 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1512 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1516 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1517 * @hsotg: The device instance
1518 * @epnum: The endpoint received from
1520 * The RXFIFO has delivered an OutDone event, which means that the data
1521 * transfer for an OUT endpoint has been completed, either by a short
1522 * packet or by the finish of a transfer.
1524 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1526 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1527 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1528 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1529 struct usb_request *req = &hs_req->req;
1530 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1534 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1538 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1539 dev_dbg(hsotg->dev, "zlp packet received\n");
1540 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1541 dwc2_hsotg_enqueue_setup(hsotg);
1545 if (using_dma(hsotg)) {
1549 * Calculate the size of the transfer by checking how much
1550 * is left in the endpoint size register and then working it
1551 * out from the amount we loaded for the transfer.
1553 * We need to do this as DMA pointers are always 32bit aligned
1554 * so may overshoot/undershoot the transfer.
1557 size_done = hs_ep->size_loaded - size_left;
1558 size_done += hs_ep->last_load;
1560 req->actual = size_done;
1563 /* if there is more request to do, schedule new transfer */
1564 if (req->actual < req->length && size_left == 0) {
1565 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1569 if (req->actual < req->length && req->short_not_ok) {
1570 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1571 __func__, req->actual, req->length);
1574 * todo - what should we return here? there's no one else
1575 * even bothering to check the status.
1579 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1580 /* Move to STATUS IN */
1581 dwc2_hsotg_ep0_zlp(hsotg, true);
1585 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1589 * dwc2_hsotg_read_frameno - read current frame number
1590 * @hsotg: The device instance
1592 * Return the current frame number
1594 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1598 dsts = dwc2_readl(hsotg->regs + DSTS);
1599 dsts &= DSTS_SOFFN_MASK;
1600 dsts >>= DSTS_SOFFN_SHIFT;
1606 * dwc2_hsotg_handle_rx - RX FIFO has data
1607 * @hsotg: The device instance
1609 * The IRQ handler has detected that the RX FIFO has some data in it
1610 * that requires processing, so find out what is in there and do the
1613 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1614 * chunks, so if you have x packets received on an endpoint you'll get x
1615 * FIFO events delivered, each with a packet's worth of data in it.
1617 * When using DMA, we should not be processing events from the RXFIFO
1618 * as the actual data should be sent to the memory directly and we turn
1619 * on the completion interrupts to get notifications of transfer completion.
1621 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1623 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1624 u32 epnum, status, size;
1626 WARN_ON(using_dma(hsotg));
1628 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1629 status = grxstsr & GRXSTS_PKTSTS_MASK;
1631 size = grxstsr & GRXSTS_BYTECNT_MASK;
1632 size >>= GRXSTS_BYTECNT_SHIFT;
1634 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1635 __func__, grxstsr, size, epnum);
1637 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1638 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1639 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1642 case GRXSTS_PKTSTS_OUTDONE:
1643 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1644 dwc2_hsotg_read_frameno(hsotg));
1646 if (!using_dma(hsotg))
1647 dwc2_hsotg_handle_outdone(hsotg, epnum);
1650 case GRXSTS_PKTSTS_SETUPDONE:
1652 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1653 dwc2_hsotg_read_frameno(hsotg),
1654 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1656 * Call dwc2_hsotg_handle_outdone here if it was not called from
1657 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1658 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1660 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1661 dwc2_hsotg_handle_outdone(hsotg, epnum);
1664 case GRXSTS_PKTSTS_OUTRX:
1665 dwc2_hsotg_rx_data(hsotg, epnum, size);
1668 case GRXSTS_PKTSTS_SETUPRX:
1670 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1671 dwc2_hsotg_read_frameno(hsotg),
1672 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1674 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1676 dwc2_hsotg_rx_data(hsotg, epnum, size);
1680 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1683 dwc2_hsotg_dump(hsotg);
1689 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1690 * @mps: The maximum packet size in bytes.
1692 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1696 return D0EPCTL_MPS_64;
1698 return D0EPCTL_MPS_32;
1700 return D0EPCTL_MPS_16;
1702 return D0EPCTL_MPS_8;
1705 /* bad max packet size, warn and return invalid result */
1711 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1712 * @hsotg: The driver state.
1713 * @ep: The index number of the endpoint
1714 * @mps: The maximum packet size in bytes
1716 * Configure the maximum packet size for the given endpoint, updating
1717 * the hardware control registers to reflect this.
1719 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1720 unsigned int ep, unsigned int mps, unsigned int dir_in)
1722 struct dwc2_hsotg_ep *hs_ep;
1723 void __iomem *regs = hsotg->regs;
1728 hs_ep = index_to_ep(hsotg, ep, dir_in);
1733 /* EP0 is a special case */
1734 mpsval = dwc2_hsotg_ep0_mps(mps);
1737 hs_ep->ep.maxpacket = mps;
1740 mpsval = mps & DXEPCTL_MPS_MASK;
1743 mcval = ((mps >> 11) & 0x3) + 1;
1747 hs_ep->ep.maxpacket = mpsval;
1751 reg = dwc2_readl(regs + DIEPCTL(ep));
1752 reg &= ~DXEPCTL_MPS_MASK;
1754 dwc2_writel(reg, regs + DIEPCTL(ep));
1756 reg = dwc2_readl(regs + DOEPCTL(ep));
1757 reg &= ~DXEPCTL_MPS_MASK;
1759 dwc2_writel(reg, regs + DOEPCTL(ep));
1765 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1769 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1770 * @hsotg: The driver state
1771 * @idx: The index for the endpoint (0..15)
1773 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1778 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1779 hsotg->regs + GRSTCTL);
1781 /* wait until the fifo is flushed */
1785 val = dwc2_readl(hsotg->regs + GRSTCTL);
1787 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1790 if (--timeout == 0) {
1792 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1802 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1803 * @hsotg: The driver state
1804 * @hs_ep: The driver endpoint to check.
1806 * Check to see if there is a request that has data to send, and if so
1807 * make an attempt to write data into the FIFO.
1809 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1810 struct dwc2_hsotg_ep *hs_ep)
1812 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1814 if (!hs_ep->dir_in || !hs_req) {
1816 * if request is not enqueued, we disable interrupts
1817 * for endpoints, excepting ep0
1819 if (hs_ep->index != 0)
1820 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1825 if (hs_req->req.actual < hs_req->req.length) {
1826 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1828 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1835 * dwc2_hsotg_complete_in - complete IN transfer
1836 * @hsotg: The device state.
1837 * @hs_ep: The endpoint that has just completed.
1839 * An IN transfer has been completed, update the transfer's state and then
1840 * call the relevant completion routines.
1842 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1843 struct dwc2_hsotg_ep *hs_ep)
1845 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1846 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1847 int size_left, size_done;
1850 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1854 /* Finish ZLP handling for IN EP0 transactions */
1855 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1856 dev_dbg(hsotg->dev, "zlp packet sent\n");
1857 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1858 if (hsotg->test_mode) {
1861 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1863 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1865 dwc2_hsotg_stall_ep0(hsotg);
1869 dwc2_hsotg_enqueue_setup(hsotg);
1874 * Calculate the size of the transfer by checking how much is left
1875 * in the endpoint size register and then working it out from
1876 * the amount we loaded for the transfer.
1878 * We do this even for DMA, as the transfer may have incremented
1879 * past the end of the buffer (DMA transfers are always 32bit
1883 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1885 size_done = hs_ep->size_loaded - size_left;
1886 size_done += hs_ep->last_load;
1888 if (hs_req->req.actual != size_done)
1889 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1890 __func__, hs_req->req.actual, size_done);
1892 hs_req->req.actual = size_done;
1893 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1894 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1896 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1897 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1898 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1902 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1903 if (hs_ep->send_zlp) {
1904 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1905 hs_ep->send_zlp = 0;
1906 /* transfer will be completed on next complete interrupt */
1910 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1911 /* Move to STATUS OUT */
1912 dwc2_hsotg_ep0_zlp(hsotg, false);
1916 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1920 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
1921 * @hsotg: The driver state
1922 * @idx: The index for the endpoint (0..15)
1923 * @dir_in: Set if this is an IN endpoint
1925 * Process and clear any interrupt pending for an individual endpoint
1927 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
1930 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
1931 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1932 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1933 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1937 ints = dwc2_readl(hsotg->regs + epint_reg);
1938 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1940 /* Clear endpoint interrupts */
1941 dwc2_writel(ints, hsotg->regs + epint_reg);
1944 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
1945 __func__, idx, dir_in ? "in" : "out");
1949 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1950 __func__, idx, dir_in ? "in" : "out", ints);
1952 /* Don't process XferCompl interrupt if it is a setup packet */
1953 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
1954 ints &= ~DXEPINT_XFERCOMPL;
1956 if (ints & DXEPINT_XFERCOMPL) {
1957 if (hs_ep->isochronous && hs_ep->interval == 1) {
1958 if (ctrl & DXEPCTL_EOFRNUM)
1959 ctrl |= DXEPCTL_SETEVENFR;
1961 ctrl |= DXEPCTL_SETODDFR;
1962 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1966 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
1967 __func__, dwc2_readl(hsotg->regs + epctl_reg),
1968 dwc2_readl(hsotg->regs + epsiz_reg));
1971 * we get OutDone from the FIFO, so we only need to look
1972 * at completing IN requests here
1975 dwc2_hsotg_complete_in(hsotg, hs_ep);
1977 if (idx == 0 && !hs_ep->req)
1978 dwc2_hsotg_enqueue_setup(hsotg);
1979 } else if (using_dma(hsotg)) {
1981 * We're using DMA, we need to fire an OutDone here
1982 * as we ignore the RXFIFO.
1985 dwc2_hsotg_handle_outdone(hsotg, idx);
1989 if (ints & DXEPINT_EPDISBLD) {
1990 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1993 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
1995 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
1997 if ((epctl & DXEPCTL_STALL) &&
1998 (epctl & DXEPCTL_EPTYPE_BULK)) {
1999 int dctl = dwc2_readl(hsotg->regs + DCTL);
2001 dctl |= DCTL_CGNPINNAK;
2002 dwc2_writel(dctl, hsotg->regs + DCTL);
2007 if (ints & DXEPINT_AHBERR)
2008 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2010 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2011 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2013 if (using_dma(hsotg) && idx == 0) {
2015 * this is the notification we've received a
2016 * setup packet. In non-DMA mode we'd get this
2017 * from the RXFIFO, instead we need to process
2024 dwc2_hsotg_handle_outdone(hsotg, 0);
2028 if (ints & DXEPINT_BACK2BACKSETUP)
2029 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2031 if (dir_in && !hs_ep->isochronous) {
2032 /* not sure if this is important, but we'll clear it anyway */
2033 if (ints & DIEPMSK_INTKNTXFEMPMSK) {
2034 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2038 /* this probably means something bad is happening */
2039 if (ints & DIEPMSK_INTKNEPMISMSK) {
2040 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2044 /* FIFO has space or is empty (see GAHBCFG) */
2045 if (hsotg->dedicated_fifos &&
2046 ints & DIEPMSK_TXFIFOEMPTY) {
2047 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2049 if (!using_dma(hsotg))
2050 dwc2_hsotg_trytx(hsotg, hs_ep);
2056 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2057 * @hsotg: The device state.
2059 * Handle updating the device settings after the enumeration phase has
2062 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2064 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2065 int ep0_mps = 0, ep_mps = 8;
2068 * This should signal the finish of the enumeration phase
2069 * of the USB handshaking, so we should now know what rate
2073 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2076 * note, since we're limited by the size of transfer on EP0, and
2077 * it seems IN transfers must be a even number of packets we do
2078 * not advertise a 64byte MPS on EP0.
2081 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2082 switch (dsts & DSTS_ENUMSPD_MASK) {
2083 case DSTS_ENUMSPD_FS:
2084 case DSTS_ENUMSPD_FS48:
2085 hsotg->gadget.speed = USB_SPEED_FULL;
2086 ep0_mps = EP0_MPS_LIMIT;
2090 case DSTS_ENUMSPD_HS:
2091 hsotg->gadget.speed = USB_SPEED_HIGH;
2092 ep0_mps = EP0_MPS_LIMIT;
2096 case DSTS_ENUMSPD_LS:
2097 hsotg->gadget.speed = USB_SPEED_LOW;
2099 * note, we don't actually support LS in this driver at the
2100 * moment, and the documentation seems to imply that it isn't
2101 * supported by the PHYs on some of the devices.
2105 dev_info(hsotg->dev, "new device is %s\n",
2106 usb_speed_string(hsotg->gadget.speed));
2109 * we should now know the maximum packet size for an
2110 * endpoint, so set the endpoints to a default value.
2115 /* Initialize ep0 for both in and out directions */
2116 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2117 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2118 for (i = 1; i < hsotg->num_of_eps; i++) {
2119 if (hsotg->eps_in[i])
2120 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2121 if (hsotg->eps_out[i])
2122 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2126 /* ensure after enumeration our EP0 is active */
2128 dwc2_hsotg_enqueue_setup(hsotg);
2130 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2131 dwc2_readl(hsotg->regs + DIEPCTL0),
2132 dwc2_readl(hsotg->regs + DOEPCTL0));
2136 * kill_all_requests - remove all requests from the endpoint's queue
2137 * @hsotg: The device state.
2138 * @ep: The endpoint the requests may be on.
2139 * @result: The result code to use.
2141 * Go through the requests on the given endpoint and mark them
2142 * completed with the given result code.
2144 static void kill_all_requests(struct dwc2_hsotg *hsotg,
2145 struct dwc2_hsotg_ep *ep,
2148 struct dwc2_hsotg_req *req, *treq;
2153 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2154 dwc2_hsotg_complete_request(hsotg, ep, req,
2157 if (!hsotg->dedicated_fifos)
2159 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2160 if (size < ep->fifo_size)
2161 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2165 * dwc2_hsotg_disconnect - disconnect service
2166 * @hsotg: The device state.
2168 * The device has been disconnected. Remove all current
2169 * transactions and signal the gadget driver that this
2172 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2176 if (!hsotg->connected)
2179 hsotg->connected = 0;
2180 hsotg->test_mode = 0;
2182 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2183 if (hsotg->eps_in[ep])
2184 kill_all_requests(hsotg, hsotg->eps_in[ep],
2186 if (hsotg->eps_out[ep])
2187 kill_all_requests(hsotg, hsotg->eps_out[ep],
2191 call_gadget(hsotg, disconnect);
2192 hsotg->lx_state = DWC2_L3;
2196 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2197 * @hsotg: The device state:
2198 * @periodic: True if this is a periodic FIFO interrupt
2200 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2202 struct dwc2_hsotg_ep *ep;
2205 /* look through for any more data to transmit */
2206 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2207 ep = index_to_ep(hsotg, epno, 1);
2215 if ((periodic && !ep->periodic) ||
2216 (!periodic && ep->periodic))
2219 ret = dwc2_hsotg_trytx(hsotg, ep);
2225 /* IRQ flags which will trigger a retry around the IRQ loop */
2226 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2231 * dwc2_hsotg_corereset - issue softreset to the core
2232 * @hsotg: The device state
2234 * Issue a soft reset to the core, and await the core finishing it.
2236 static int dwc2_hsotg_corereset(struct dwc2_hsotg *hsotg)
2241 dev_dbg(hsotg->dev, "resetting core\n");
2243 /* issue soft reset */
2244 dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL);
2248 grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
2249 } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0);
2251 if (grstctl & GRSTCTL_CSFTRST) {
2252 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2259 u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL);
2261 if (timeout-- < 0) {
2262 dev_info(hsotg->dev,
2263 "%s: reset failed, GRSTCTL=%08x\n",
2268 if (!(grstctl & GRSTCTL_AHBIDLE))
2271 break; /* reset done */
2274 dev_dbg(hsotg->dev, "reset successful\n");
2279 * dwc2_hsotg_core_init - issue softreset to the core
2280 * @hsotg: The device state
2282 * Issue a soft reset to the core, and await the core finishing it.
2284 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2290 dwc2_hsotg_corereset(hsotg);
2293 * we must now enable ep0 ready for host detection and then
2294 * set configuration.
2297 /* set the PLL on, remove the HNP/SRP and set the PHY */
2298 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2299 dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2300 (val << GUSBCFG_USBTRDTIM_SHIFT), hsotg->regs + GUSBCFG);
2302 dwc2_hsotg_init_fifo(hsotg);
2305 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2307 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2309 /* Clear any pending OTG interrupts */
2310 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2312 /* Clear any pending interrupts */
2313 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2315 dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2316 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2317 GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST |
2318 GINTSTS_RESETDET | GINTSTS_ENUMDONE |
2319 GINTSTS_OTGINT | GINTSTS_USBSUSP |
2321 hsotg->regs + GINTMSK);
2323 if (using_dma(hsotg))
2324 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2325 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2326 hsotg->regs + GAHBCFG);
2328 dwc2_writel(((hsotg->dedicated_fifos) ?
2329 (GAHBCFG_NP_TXF_EMP_LVL |
2330 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2331 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2334 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2335 * when we have no data to transfer. Otherwise we get being flooded by
2339 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2340 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2341 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2342 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2343 DIEPMSK_INTKNEPMISMSK,
2344 hsotg->regs + DIEPMSK);
2347 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2348 * DMA mode we may need this.
2350 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2351 DIEPMSK_TIMEOUTMSK) : 0) |
2352 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2354 hsotg->regs + DOEPMSK);
2356 dwc2_writel(0, hsotg->regs + DAINTMSK);
2358 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2359 dwc2_readl(hsotg->regs + DIEPCTL0),
2360 dwc2_readl(hsotg->regs + DOEPCTL0));
2362 /* enable in and out endpoint interrupts */
2363 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2366 * Enable the RXFIFO when in slave mode, as this is how we collect
2367 * the data. In DMA mode, we get events from the FIFO but also
2368 * things we cannot process, so do not use it.
2370 if (!using_dma(hsotg))
2371 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2373 /* Enable interrupts for EP0 in and out */
2374 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2375 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2377 if (!is_usb_reset) {
2378 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2379 udelay(10); /* see openiboot */
2380 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2383 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2386 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2387 * writing to the EPCTL register..
2390 /* set to read 1 8byte packet */
2391 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2392 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2394 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2395 DXEPCTL_CNAK | DXEPCTL_EPENA |
2397 hsotg->regs + DOEPCTL0);
2399 /* enable, but don't activate EP0in */
2400 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2401 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2403 dwc2_hsotg_enqueue_setup(hsotg);
2405 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2406 dwc2_readl(hsotg->regs + DIEPCTL0),
2407 dwc2_readl(hsotg->regs + DOEPCTL0));
2409 /* clear global NAKs */
2410 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2412 val |= DCTL_SFTDISCON;
2413 __orr32(hsotg->regs + DCTL, val);
2415 /* must be at-least 3ms to allow bus to see disconnect */
2418 hsotg->last_rst = jiffies;
2419 hsotg->lx_state = DWC2_L0;
2422 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2424 /* set the soft-disconnect bit */
2425 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2428 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2430 /* remove the soft-disconnect and let's go */
2431 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2435 * dwc2_hsotg_irq - handle device interrupt
2436 * @irq: The IRQ number triggered
2437 * @pw: The pw value when registered the handler.
2439 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2441 struct dwc2_hsotg *hsotg = pw;
2442 int retry_count = 8;
2446 spin_lock(&hsotg->lock);
2448 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2449 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2451 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2452 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2456 if (gintsts & GINTSTS_ENUMDONE) {
2457 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2459 dwc2_hsotg_irq_enumdone(hsotg);
2462 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2463 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2464 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2465 u32 daint_out, daint_in;
2469 daint_out = daint >> DAINT_OUTEP_SHIFT;
2470 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2472 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2474 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2475 ep++, daint_out >>= 1) {
2477 dwc2_hsotg_epint(hsotg, ep, 0);
2480 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2481 ep++, daint_in >>= 1) {
2483 dwc2_hsotg_epint(hsotg, ep, 1);
2487 if (gintsts & GINTSTS_RESETDET) {
2488 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2490 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2492 /* This event must be used only if controller is suspended */
2493 if (hsotg->lx_state == DWC2_L2) {
2494 dwc2_exit_hibernation(hsotg, true);
2495 hsotg->lx_state = DWC2_L0;
2499 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2501 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2503 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2504 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2505 dwc2_readl(hsotg->regs + GNPTXSTS));
2507 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2509 /* Report disconnection if it is not already done. */
2510 dwc2_hsotg_disconnect(hsotg);
2512 if (usb_status & GOTGCTL_BSESVLD) {
2513 if (time_after(jiffies, hsotg->last_rst +
2514 msecs_to_jiffies(200))) {
2516 kill_all_requests(hsotg, hsotg->eps_out[0],
2519 dwc2_hsotg_core_init_disconnected(hsotg, true);
2524 /* check both FIFOs */
2526 if (gintsts & GINTSTS_NPTXFEMP) {
2527 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2530 * Disable the interrupt to stop it happening again
2531 * unless one of these endpoint routines decides that
2532 * it needs re-enabling
2535 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2536 dwc2_hsotg_irq_fifoempty(hsotg, false);
2539 if (gintsts & GINTSTS_PTXFEMP) {
2540 dev_dbg(hsotg->dev, "PTxFEmp\n");
2542 /* See note in GINTSTS_NPTxFEmp */
2544 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2545 dwc2_hsotg_irq_fifoempty(hsotg, true);
2548 if (gintsts & GINTSTS_RXFLVL) {
2550 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2551 * we need to retry dwc2_hsotg_handle_rx if this is still
2555 dwc2_hsotg_handle_rx(hsotg);
2558 if (gintsts & GINTSTS_ERLYSUSP) {
2559 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2560 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2564 * these next two seem to crop-up occasionally causing the core
2565 * to shutdown the USB transfer, so try clearing them and logging
2569 if (gintsts & GINTSTS_GOUTNAKEFF) {
2570 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2572 dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL);
2574 dwc2_hsotg_dump(hsotg);
2577 if (gintsts & GINTSTS_GINNAKEFF) {
2578 dev_info(hsotg->dev, "GINNakEff triggered\n");
2580 dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL);
2582 dwc2_hsotg_dump(hsotg);
2586 * if we've had fifo events, we should try and go around the
2587 * loop again to see if there's any point in returning yet.
2590 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2593 spin_unlock(&hsotg->lock);
2599 * dwc2_hsotg_ep_enable - enable the given endpoint
2600 * @ep: The USB endpint to configure
2601 * @desc: The USB endpoint descriptor to configure with.
2603 * This is called from the USB gadget code's usb_ep_enable().
2605 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2606 const struct usb_endpoint_descriptor *desc)
2608 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2609 struct dwc2_hsotg *hsotg = hs_ep->parent;
2610 unsigned long flags;
2611 unsigned int index = hs_ep->index;
2615 unsigned int dir_in;
2616 unsigned int i, val, size;
2620 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2621 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2622 desc->wMaxPacketSize, desc->bInterval);
2624 /* not to be called for EP0 */
2625 WARN_ON(index == 0);
2627 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2628 if (dir_in != hs_ep->dir_in) {
2629 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2633 mps = usb_endpoint_maxp(desc);
2635 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2637 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2638 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2640 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2641 __func__, epctrl, epctrl_reg);
2643 spin_lock_irqsave(&hsotg->lock, flags);
2645 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2646 epctrl |= DXEPCTL_MPS(mps);
2649 * mark the endpoint as active, otherwise the core may ignore
2650 * transactions entirely for this endpoint
2652 epctrl |= DXEPCTL_USBACTEP;
2655 * set the NAK status on the endpoint, otherwise we might try and
2656 * do something with data that we've yet got a request to process
2657 * since the RXFIFO will take data for an endpoint even if the
2658 * size register hasn't been set.
2661 epctrl |= DXEPCTL_SNAK;
2663 /* update the endpoint state */
2664 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2666 /* default, set to non-periodic */
2667 hs_ep->isochronous = 0;
2668 hs_ep->periodic = 0;
2670 hs_ep->interval = desc->bInterval;
2672 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2673 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2675 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2676 case USB_ENDPOINT_XFER_ISOC:
2677 epctrl |= DXEPCTL_EPTYPE_ISO;
2678 epctrl |= DXEPCTL_SETEVENFR;
2679 hs_ep->isochronous = 1;
2681 hs_ep->periodic = 1;
2684 case USB_ENDPOINT_XFER_BULK:
2685 epctrl |= DXEPCTL_EPTYPE_BULK;
2688 case USB_ENDPOINT_XFER_INT:
2690 hs_ep->periodic = 1;
2692 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2695 case USB_ENDPOINT_XFER_CONTROL:
2696 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2700 /* If fifo is already allocated for this ep */
2701 if (hs_ep->fifo_index) {
2702 size = hs_ep->ep.maxpacket * hs_ep->mc;
2703 /* If bigger fifo is required deallocate current one */
2704 if (size > hs_ep->fifo_size) {
2705 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2706 hs_ep->fifo_index = 0;
2707 hs_ep->fifo_size = 0;
2712 * if the hardware has dedicated fifos, we must give each IN EP
2713 * a unique tx-fifo even if it is non-periodic.
2715 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2717 u32 fifo_size = UINT_MAX;
2718 size = hs_ep->ep.maxpacket*hs_ep->mc;
2719 for (i = 1; i < hsotg->num_of_eps; ++i) {
2720 if (hsotg->fifo_map & (1<<i))
2722 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2723 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2726 /* Search for smallest acceptable fifo */
2727 if (val < fifo_size) {
2734 "%s: No suitable fifo found\n", __func__);
2738 hsotg->fifo_map |= 1 << fifo_index;
2739 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2740 hs_ep->fifo_index = fifo_index;
2741 hs_ep->fifo_size = fifo_size;
2744 /* for non control endpoints, set PID to D0 */
2746 epctrl |= DXEPCTL_SETD0PID;
2748 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2751 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2752 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2753 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2755 /* enable the endpoint interrupt */
2756 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2759 spin_unlock_irqrestore(&hsotg->lock, flags);
2764 * dwc2_hsotg_ep_disable - disable given endpoint
2765 * @ep: The endpoint to disable.
2767 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2769 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2770 struct dwc2_hsotg *hsotg = hs_ep->parent;
2771 int dir_in = hs_ep->dir_in;
2772 int index = hs_ep->index;
2773 unsigned long flags;
2777 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2779 if (ep == &hsotg->eps_out[0]->ep) {
2780 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2784 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2786 spin_lock_irqsave(&hsotg->lock, flags);
2788 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2789 hs_ep->fifo_index = 0;
2790 hs_ep->fifo_size = 0;
2792 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2793 ctrl &= ~DXEPCTL_EPENA;
2794 ctrl &= ~DXEPCTL_USBACTEP;
2795 ctrl |= DXEPCTL_SNAK;
2797 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2798 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2800 /* disable endpoint interrupts */
2801 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2803 /* terminate all requests with shutdown */
2804 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2806 spin_unlock_irqrestore(&hsotg->lock, flags);
2811 * on_list - check request is on the given endpoint
2812 * @ep: The endpoint to check.
2813 * @test: The request to test if it is on the endpoint.
2815 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2817 struct dwc2_hsotg_req *req, *treq;
2819 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2828 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
2829 * @ep: The endpoint to dequeue.
2830 * @req: The request to be removed from a queue.
2832 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2834 struct dwc2_hsotg_req *hs_req = our_req(req);
2835 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2836 struct dwc2_hsotg *hs = hs_ep->parent;
2837 unsigned long flags;
2839 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2841 spin_lock_irqsave(&hs->lock, flags);
2843 if (!on_list(hs_ep, hs_req)) {
2844 spin_unlock_irqrestore(&hs->lock, flags);
2848 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2849 spin_unlock_irqrestore(&hs->lock, flags);
2855 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
2856 * @ep: The endpoint to set halt.
2857 * @value: Set or unset the halt.
2859 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2861 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2862 struct dwc2_hsotg *hs = hs_ep->parent;
2863 int index = hs_ep->index;
2868 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2872 dwc2_hsotg_stall_ep0(hs);
2875 "%s: can't clear halt on ep0\n", __func__);
2879 if (hs_ep->dir_in) {
2880 epreg = DIEPCTL(index);
2881 epctl = dwc2_readl(hs->regs + epreg);
2884 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
2885 if (epctl & DXEPCTL_EPENA)
2886 epctl |= DXEPCTL_EPDIS;
2888 epctl &= ~DXEPCTL_STALL;
2889 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2890 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2891 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2892 epctl |= DXEPCTL_SETD0PID;
2894 dwc2_writel(epctl, hs->regs + epreg);
2897 epreg = DOEPCTL(index);
2898 epctl = dwc2_readl(hs->regs + epreg);
2901 epctl |= DXEPCTL_STALL;
2903 epctl &= ~DXEPCTL_STALL;
2904 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
2905 if (xfertype == DXEPCTL_EPTYPE_BULK ||
2906 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
2907 epctl |= DXEPCTL_SETD0PID;
2909 dwc2_writel(epctl, hs->regs + epreg);
2912 hs_ep->halted = value;
2918 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2919 * @ep: The endpoint to set halt.
2920 * @value: Set or unset the halt.
2922 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2924 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2925 struct dwc2_hsotg *hs = hs_ep->parent;
2926 unsigned long flags = 0;
2929 spin_lock_irqsave(&hs->lock, flags);
2930 ret = dwc2_hsotg_ep_sethalt(ep, value);
2931 spin_unlock_irqrestore(&hs->lock, flags);
2936 static struct usb_ep_ops dwc2_hsotg_ep_ops = {
2937 .enable = dwc2_hsotg_ep_enable,
2938 .disable = dwc2_hsotg_ep_disable,
2939 .alloc_request = dwc2_hsotg_ep_alloc_request,
2940 .free_request = dwc2_hsotg_ep_free_request,
2941 .queue = dwc2_hsotg_ep_queue_lock,
2942 .dequeue = dwc2_hsotg_ep_dequeue,
2943 .set_halt = dwc2_hsotg_ep_sethalt_lock,
2944 /* note, don't believe we have any call for the fifo routines */
2948 * dwc2_hsotg_phy_enable - enable platform phy dev
2949 * @hsotg: The driver state
2951 * A wrapper for platform code responsible for controlling
2952 * low-level USB code
2954 static void dwc2_hsotg_phy_enable(struct dwc2_hsotg *hsotg)
2956 struct platform_device *pdev = to_platform_device(hsotg->dev);
2958 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2961 usb_phy_init(hsotg->uphy);
2962 else if (hsotg->plat && hsotg->plat->phy_init)
2963 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2965 phy_init(hsotg->phy);
2966 phy_power_on(hsotg->phy);
2971 * dwc2_hsotg_phy_disable - disable platform phy dev
2972 * @hsotg: The driver state
2974 * A wrapper for platform code responsible for controlling
2975 * low-level USB code
2977 static void dwc2_hsotg_phy_disable(struct dwc2_hsotg *hsotg)
2979 struct platform_device *pdev = to_platform_device(hsotg->dev);
2982 usb_phy_shutdown(hsotg->uphy);
2983 else if (hsotg->plat && hsotg->plat->phy_exit)
2984 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2986 phy_power_off(hsotg->phy);
2987 phy_exit(hsotg->phy);
2992 * dwc2_hsotg_init - initalize the usb core
2993 * @hsotg: The driver state
2995 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
2998 /* unmask subset of endpoint interrupts */
3000 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3001 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3002 hsotg->regs + DIEPMSK);
3004 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3005 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3006 hsotg->regs + DOEPMSK);
3008 dwc2_writel(0, hsotg->regs + DAINTMSK);
3010 /* Be in disconnected state until gadget is registered */
3011 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3015 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3016 dwc2_readl(hsotg->regs + GRXFSIZ),
3017 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3019 dwc2_hsotg_init_fifo(hsotg);
3021 /* set the PLL on, remove the HNP/SRP and set the PHY */
3022 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3023 dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3024 (trdtim << GUSBCFG_USBTRDTIM_SHIFT),
3025 hsotg->regs + GUSBCFG);
3027 if (using_dma(hsotg))
3028 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3032 * dwc2_hsotg_udc_start - prepare the udc for work
3033 * @gadget: The usb gadget state
3034 * @driver: The usb gadget driver
3036 * Perform initialization to prepare udc device and driver
3039 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3040 struct usb_gadget_driver *driver)
3042 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3043 unsigned long flags;
3047 pr_err("%s: called with no device\n", __func__);
3052 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3056 if (driver->max_speed < USB_SPEED_FULL)
3057 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3059 if (!driver->setup) {
3060 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3064 mutex_lock(&hsotg->init_mutex);
3065 WARN_ON(hsotg->driver);
3067 driver->driver.bus = NULL;
3068 hsotg->driver = driver;
3069 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3070 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3072 clk_enable(hsotg->clk);
3074 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3077 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3081 dwc2_hsotg_phy_enable(hsotg);
3082 if (!IS_ERR_OR_NULL(hsotg->uphy))
3083 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3085 spin_lock_irqsave(&hsotg->lock, flags);
3086 dwc2_hsotg_init(hsotg);
3087 dwc2_hsotg_core_init_disconnected(hsotg, false);
3089 spin_unlock_irqrestore(&hsotg->lock, flags);
3091 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3093 mutex_unlock(&hsotg->init_mutex);
3098 mutex_unlock(&hsotg->init_mutex);
3099 hsotg->driver = NULL;
3104 * dwc2_hsotg_udc_stop - stop the udc
3105 * @gadget: The usb gadget state
3106 * @driver: The usb gadget driver
3108 * Stop udc hw block and stay tunned for future transmissions
3110 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3112 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3113 unsigned long flags = 0;
3119 mutex_lock(&hsotg->init_mutex);
3121 /* all endpoints should be shutdown */
3122 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3123 if (hsotg->eps_in[ep])
3124 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3125 if (hsotg->eps_out[ep])
3126 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3129 spin_lock_irqsave(&hsotg->lock, flags);
3131 hsotg->driver = NULL;
3132 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3135 spin_unlock_irqrestore(&hsotg->lock, flags);
3137 if (!IS_ERR_OR_NULL(hsotg->uphy))
3138 otg_set_peripheral(hsotg->uphy->otg, NULL);
3139 dwc2_hsotg_phy_disable(hsotg);
3141 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3143 clk_disable(hsotg->clk);
3145 mutex_unlock(&hsotg->init_mutex);
3151 * dwc2_hsotg_gadget_getframe - read the frame number
3152 * @gadget: The usb gadget state
3154 * Read the {micro} frame number
3156 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3158 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3162 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3163 * @gadget: The usb gadget state
3164 * @is_on: Current state of the USB PHY
3166 * Connect/Disconnect the USB PHY pullup
3168 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3170 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3171 unsigned long flags = 0;
3173 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3176 /* Don't modify pullup state while in host mode */
3177 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3178 hsotg->enabled = is_on;
3182 mutex_lock(&hsotg->init_mutex);
3183 spin_lock_irqsave(&hsotg->lock, flags);
3185 clk_enable(hsotg->clk);
3187 dwc2_hsotg_core_init_disconnected(hsotg, false);
3188 dwc2_hsotg_core_connect(hsotg);
3190 dwc2_hsotg_core_disconnect(hsotg);
3191 dwc2_hsotg_disconnect(hsotg);
3193 clk_disable(hsotg->clk);
3196 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3197 spin_unlock_irqrestore(&hsotg->lock, flags);
3198 mutex_unlock(&hsotg->init_mutex);
3203 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3205 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3206 unsigned long flags;
3208 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3209 spin_lock_irqsave(&hsotg->lock, flags);
3212 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3214 * If controller is hibernated, it must exit from hibernation
3215 * before being initialized
3217 if (hsotg->lx_state == DWC2_L2)
3218 dwc2_exit_hibernation(hsotg, false);
3220 /* Kill any ep0 requests as controller will be reinitialized */
3221 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3222 dwc2_hsotg_core_init_disconnected(hsotg, false);
3224 dwc2_hsotg_core_connect(hsotg);
3226 dwc2_hsotg_core_disconnect(hsotg);
3227 dwc2_hsotg_disconnect(hsotg);
3230 spin_unlock_irqrestore(&hsotg->lock, flags);
3235 * dwc2_hsotg_vbus_draw - report bMaxPower field
3236 * @gadget: The usb gadget state
3237 * @mA: Amount of current
3239 * Report how much power the device may consume to the phy.
3241 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3243 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3245 if (IS_ERR_OR_NULL(hsotg->uphy))
3247 return usb_phy_set_power(hsotg->uphy, mA);
3250 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3251 .get_frame = dwc2_hsotg_gadget_getframe,
3252 .udc_start = dwc2_hsotg_udc_start,
3253 .udc_stop = dwc2_hsotg_udc_stop,
3254 .pullup = dwc2_hsotg_pullup,
3255 .vbus_session = dwc2_hsotg_vbus_session,
3256 .vbus_draw = dwc2_hsotg_vbus_draw,
3260 * dwc2_hsotg_initep - initialise a single endpoint
3261 * @hsotg: The device state.
3262 * @hs_ep: The endpoint to be initialised.
3263 * @epnum: The endpoint number
3265 * Initialise the given endpoint (as part of the probe and device state
3266 * creation) to give to the gadget driver. Setup the endpoint name, any
3267 * direction information and other state that may be required.
3269 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3270 struct dwc2_hsotg_ep *hs_ep,
3283 hs_ep->dir_in = dir_in;
3284 hs_ep->index = epnum;
3286 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3288 INIT_LIST_HEAD(&hs_ep->queue);
3289 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3291 /* add to the list of endpoints known by the gadget driver */
3293 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3295 hs_ep->parent = hsotg;
3296 hs_ep->ep.name = hs_ep->name;
3297 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3298 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3301 hs_ep->ep.caps.type_control = true;
3303 hs_ep->ep.caps.type_iso = true;
3304 hs_ep->ep.caps.type_bulk = true;
3305 hs_ep->ep.caps.type_int = true;
3309 hs_ep->ep.caps.dir_in = true;
3311 hs_ep->ep.caps.dir_out = true;
3314 * if we're using dma, we need to set the next-endpoint pointer
3315 * to be something valid.
3318 if (using_dma(hsotg)) {
3319 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3321 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3323 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3328 * dwc2_hsotg_hw_cfg - read HW configuration registers
3329 * @param: The device state
3331 * Read the USB core HW configuration registers
3333 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3339 /* check hardware configuration */
3341 cfg = dwc2_readl(hsotg->regs + GHWCFG2);
3342 hsotg->num_of_eps = (cfg >> GHWCFG2_NUM_DEV_EP_SHIFT) & 0xF;
3344 hsotg->num_of_eps++;
3346 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3348 if (!hsotg->eps_in[0])
3350 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3351 hsotg->eps_out[0] = hsotg->eps_in[0];
3353 cfg = dwc2_readl(hsotg->regs + GHWCFG1);
3354 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3356 /* Direction in or both */
3357 if (!(ep_type & 2)) {
3358 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3359 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3360 if (!hsotg->eps_in[i])
3363 /* Direction out or both */
3364 if (!(ep_type & 1)) {
3365 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3366 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3367 if (!hsotg->eps_out[i])
3372 cfg = dwc2_readl(hsotg->regs + GHWCFG3);
3373 hsotg->fifo_mem = (cfg >> GHWCFG3_DFIFO_DEPTH_SHIFT);
3375 cfg = dwc2_readl(hsotg->regs + GHWCFG4);
3376 hsotg->dedicated_fifos = (cfg >> GHWCFG4_DED_FIFO_SHIFT) & 1;
3378 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3380 hsotg->dedicated_fifos ? "dedicated" : "shared",
3386 * dwc2_hsotg_dump - dump state of the udc
3387 * @param: The device state
3389 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3392 struct device *dev = hsotg->dev;
3393 void __iomem *regs = hsotg->regs;
3397 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3398 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3399 dwc2_readl(regs + DIEPMSK));
3401 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3402 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3404 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3405 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3407 /* show periodic fifo settings */
3409 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3410 val = dwc2_readl(regs + DPTXFSIZN(idx));
3411 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3412 val >> FIFOSIZE_DEPTH_SHIFT,
3413 val & FIFOSIZE_STARTADDR_MASK);
3416 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3418 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3419 dwc2_readl(regs + DIEPCTL(idx)),
3420 dwc2_readl(regs + DIEPTSIZ(idx)),
3421 dwc2_readl(regs + DIEPDMA(idx)));
3423 val = dwc2_readl(regs + DOEPCTL(idx));
3425 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3426 idx, dwc2_readl(regs + DOEPCTL(idx)),
3427 dwc2_readl(regs + DOEPTSIZ(idx)),
3428 dwc2_readl(regs + DOEPDMA(idx)));
3432 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3433 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3438 static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3440 struct device_node *np = hsotg->dev->of_node;
3444 /* Enable dma if requested in device tree */
3445 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3448 * Register TX periodic fifo size per endpoint.
3449 * EP0 is excluded since it has no fifo configuration.
3451 if (!of_find_property(np, "g-tx-fifo-size", &len))
3456 /* Read tx fifo sizes other than ep0 */
3457 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3458 &hsotg->g_tx_fifo_sz[1], len))
3464 /* Make remaining TX fifos unavailable */
3465 if (len < MAX_EPS_CHANNELS) {
3466 for (i = len; i < MAX_EPS_CHANNELS; i++)
3467 hsotg->g_tx_fifo_sz[i] = 0;
3471 /* Register RX fifo size */
3472 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3474 /* Register NPTX fifo size */
3475 of_property_read_u32(np, "g-np-tx-fifo-size",
3476 &hsotg->g_np_g_tx_fifo_sz);
3479 static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3483 * dwc2_gadget_init - init function for gadget
3484 * @dwc2: The data structure for the DWC2 driver.
3485 * @irq: The IRQ number for the controller.
3487 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3489 struct device *dev = hsotg->dev;
3490 struct dwc2_hsotg_plat *plat = dev->platform_data;
3494 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3496 /* Set default UTMI width */
3497 hsotg->phyif = GUSBCFG_PHYIF16;
3499 dwc2_hsotg_of_probe(hsotg);
3501 /* Initialize to legacy fifo configuration values */
3502 hsotg->g_rx_fifo_sz = 2048;
3503 hsotg->g_np_g_tx_fifo_sz = 1024;
3504 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3505 /* Device tree specific probe */
3506 dwc2_hsotg_of_probe(hsotg);
3507 /* Dump fifo information */
3508 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3509 hsotg->g_np_g_tx_fifo_sz);
3510 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3511 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3512 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3513 hsotg->g_tx_fifo_sz[i]);
3515 * If platform probe couldn't find a generic PHY or an old style
3516 * USB PHY, fall back to pdata
3518 if (IS_ERR_OR_NULL(hsotg->phy) && IS_ERR_OR_NULL(hsotg->uphy)) {
3519 plat = dev_get_platdata(dev);
3522 "no platform data or transceiver defined\n");
3523 return -EPROBE_DEFER;
3526 } else if (hsotg->phy) {
3528 * If using the generic PHY framework, check if the PHY bus
3529 * width is 8-bit and set the phyif appropriately.
3531 if (phy_get_bus_width(hsotg->phy) == 8)
3532 hsotg->phyif = GUSBCFG_PHYIF8;
3535 hsotg->clk = devm_clk_get(dev, "otg");
3536 if (IS_ERR(hsotg->clk)) {
3538 dev_dbg(dev, "cannot get otg clock\n");
3541 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3542 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3543 hsotg->gadget.name = dev_name(dev);
3544 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3545 hsotg->gadget.is_otg = 1;
3546 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3547 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3549 /* reset the system */
3551 ret = clk_prepare_enable(hsotg->clk);
3553 dev_err(dev, "failed to enable otg clk\n");
3560 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3561 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
3563 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3566 dev_err(dev, "failed to request supplies: %d\n", ret);
3570 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3574 dev_err(dev, "failed to enable supplies: %d\n", ret);
3578 /* usb phy enable */
3579 dwc2_hsotg_phy_enable(hsotg);
3582 * Force Device mode before initialization.
3583 * This allows correctly configuring fifo for device mode.
3585 __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEHOSTMODE);
3586 __orr32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
3589 * According to Synopsys databook, this sleep is needed for the force
3590 * device mode to take effect.
3594 dwc2_hsotg_corereset(hsotg);
3595 ret = dwc2_hsotg_hw_cfg(hsotg);
3597 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3601 dwc2_hsotg_init(hsotg);
3603 /* Switch back to default configuration */
3604 __bic32(hsotg->regs + GUSBCFG, GUSBCFG_FORCEDEVMODE);
3606 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3607 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3608 if (!hsotg->ctrl_buff) {
3609 dev_err(dev, "failed to allocate ctrl request buff\n");
3614 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3615 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3616 if (!hsotg->ep0_buff) {
3617 dev_err(dev, "failed to allocate ctrl reply buff\n");
3622 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3623 dev_name(hsotg->dev), hsotg);
3625 dwc2_hsotg_phy_disable(hsotg);
3626 clk_disable_unprepare(hsotg->clk);
3627 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3629 dev_err(dev, "cannot claim IRQ for gadget\n");
3633 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3635 if (hsotg->num_of_eps == 0) {
3636 dev_err(dev, "wrong number of EPs (zero)\n");
3641 /* setup endpoint information */
3643 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3644 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3646 /* allocate EP0 request */
3648 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3650 if (!hsotg->ctrl_req) {
3651 dev_err(dev, "failed to allocate ctrl req\n");
3656 /* initialise the endpoints now the core has been initialised */
3657 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3658 if (hsotg->eps_in[epnum])
3659 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3661 if (hsotg->eps_out[epnum])
3662 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3666 /* disable power and clock */
3667 dwc2_hsotg_phy_disable(hsotg);
3669 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3672 dev_err(dev, "failed to disable supplies: %d\n", ret);
3676 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3680 dwc2_hsotg_dump(hsotg);
3685 dwc2_hsotg_phy_disable(hsotg);
3687 clk_disable_unprepare(hsotg->clk);
3693 * dwc2_hsotg_remove - remove function for hsotg driver
3694 * @pdev: The platform information for the driver
3696 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3698 usb_del_gadget_udc(&hsotg->gadget);
3699 clk_disable_unprepare(hsotg->clk);
3704 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3706 unsigned long flags;
3709 if (hsotg->lx_state != DWC2_L0)
3712 mutex_lock(&hsotg->init_mutex);
3714 if (hsotg->driver) {
3717 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3718 hsotg->driver->driver.name);
3720 spin_lock_irqsave(&hsotg->lock, flags);
3722 dwc2_hsotg_core_disconnect(hsotg);
3723 dwc2_hsotg_disconnect(hsotg);
3724 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3725 spin_unlock_irqrestore(&hsotg->lock, flags);
3727 dwc2_hsotg_phy_disable(hsotg);
3729 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3730 if (hsotg->eps_in[ep])
3731 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3732 if (hsotg->eps_out[ep])
3733 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3736 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3738 clk_disable(hsotg->clk);
3741 mutex_unlock(&hsotg->init_mutex);
3746 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3748 unsigned long flags;
3751 if (hsotg->lx_state == DWC2_L2)
3754 mutex_lock(&hsotg->init_mutex);
3756 if (hsotg->driver) {
3757 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3758 hsotg->driver->driver.name);
3760 clk_enable(hsotg->clk);
3761 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3764 dwc2_hsotg_phy_enable(hsotg);
3766 spin_lock_irqsave(&hsotg->lock, flags);
3767 dwc2_hsotg_core_init_disconnected(hsotg, false);
3769 dwc2_hsotg_core_connect(hsotg);
3770 spin_unlock_irqrestore(&hsotg->lock, flags);
3772 mutex_unlock(&hsotg->init_mutex);