2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
58 * dwc2_dump_channel_info() - Prints the state of a host channel
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
63 * Must be called with interrupt disabled and spinlock held
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
72 int num_channels = hsotg->core_params->host_channels;
83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
119 #endif /* VERBOSE_DEBUG */
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
126 * Must be called with interrupt disabled and spinlock held
128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
151 /* The list hasn't been initialized yet */
154 spin_lock_irqsave(&hsotg->lock, flags);
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
172 spin_unlock_irqrestore(&hsotg->lock, flags);
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
181 * Must be called with interrupt disabled and spinlock held
183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
196 * @hsotg: Pointer to struct dwc2_hsotg
198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
208 hprt0 = dwc2_read_hprt0(hsotg);
210 dwc2_writel(hprt0, hsotg->regs + HPRT0);
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
217 /* Must be called with interrupt disabled and spinlock held */
218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
231 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
235 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
244 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
248 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
260 /* All channels have been freed, mark them available */
261 if (hsotg->core_params->uframe_sched > 0) {
262 hsotg->available_host_channels =
263 hsotg->core_params->host_channels;
265 hsotg->non_periodic_channels = 0;
266 hsotg->periodic_channels = 0;
271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
273 * @hsotg: Pointer to struct dwc2_hsotg
275 * Must be called with interrupt disabled and spinlock held
277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
281 /* Set status flags for the hub driver */
282 hsotg->flags.b.port_connect_status_change = 1;
283 hsotg->flags.b.port_connect_status = 0;
286 * Shutdown any transfers in process by clearing the Tx FIFO Empty
287 * interrupt mask and status bits and disabling subsequent host
288 * channel interrupts.
290 intr = dwc2_readl(hsotg->regs + GINTMSK);
291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
292 dwc2_writel(intr, hsotg->regs + GINTMSK);
293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
294 dwc2_writel(intr, hsotg->regs + GINTSTS);
297 * Turn off the vbus power only if the core has transitioned to device
298 * mode. If still in host mode, need to keep power on to detect a
301 if (dwc2_is_device_mode(hsotg)) {
302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
304 dwc2_writel(0, hsotg->regs + HPRT0);
307 dwc2_disable_host_interrupts(hsotg);
310 /* Respond with an error status to all URBs in the schedule */
311 dwc2_kill_all_urbs(hsotg);
313 if (dwc2_is_host_mode(hsotg))
314 /* Clean up any host channels that were in use */
315 dwc2_hcd_cleanup_channels(hsotg);
317 dwc2_host_disconnect(hsotg);
321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
323 * @hsotg: Pointer to struct dwc2_hsotg
325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
327 if (hsotg->lx_state == DWC2_L2) {
328 hsotg->flags.b.port_suspend_change = 1;
329 usb_hcd_resume_root_hub(hsotg->priv);
331 hsotg->flags.b.port_l1_change = 1;
336 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
338 * @hsotg: Pointer to struct dwc2_hsotg
340 * Must be called with interrupt disabled and spinlock held
342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
344 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
347 * The root hub should be disconnected before this function is called.
348 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
349 * and the QH lists (via ..._hcd_endpoint_disable).
352 /* Turn off all host-specific interrupts */
353 dwc2_disable_host_interrupts(hsotg);
355 /* Turn off the vbus power */
356 dev_dbg(hsotg->dev, "PortPower off\n");
357 dwc2_writel(0, hsotg->regs + HPRT0);
360 /* Caller must hold driver lock */
361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
362 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
363 struct dwc2_qtd *qtd)
369 if (!hsotg->flags.b.port_connect_status) {
370 /* No longer connected */
371 dev_err(hsotg->dev, "Not connected\n");
375 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
377 /* Some configurations cannot support LS traffic on a FS root port */
378 if ((dev_speed == USB_SPEED_LOW) &&
379 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
380 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
381 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
382 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
384 if (prtspd == HPRT0_SPD_FULL_SPEED)
391 dwc2_hcd_qtd_init(qtd, urb);
392 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
395 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
400 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
401 if (!(intr_mask & GINTSTS_SOF)) {
402 enum dwc2_transaction_type tr_type;
404 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
405 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
407 * Do not schedule SG transactions until qtd has
408 * URB_GIVEBACK_ASAP set
412 tr_type = dwc2_hcd_select_transactions(hsotg);
413 if (tr_type != DWC2_TRANSACTION_NONE)
414 dwc2_hcd_queue_transactions(hsotg, tr_type);
420 /* Must be called with interrupt disabled and spinlock held */
421 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
422 struct dwc2_hcd_urb *urb)
425 struct dwc2_qtd *urb_qtd;
429 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
435 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
441 if (urb_qtd->in_process && qh->channel) {
442 dwc2_dump_channel_info(hsotg, qh->channel);
444 /* The QTD is in process (it has been assigned to a channel) */
445 if (hsotg->flags.b.port_connect_status)
447 * If still connected (i.e. in host mode), halt the
448 * channel so it can be used for other transfers. If
449 * no longer connected, the host registers can't be
450 * written to halt the channel since the core is in
453 dwc2_hc_halt(hsotg, qh->channel,
454 DWC2_HC_XFER_URB_DEQUEUE);
458 * Free the QTD and clean up the associated QH. Leave the QH in the
459 * schedule if it has any remaining QTDs.
461 if (hsotg->core_params->dma_desc_enable <= 0) {
462 u8 in_process = urb_qtd->in_process;
464 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
466 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
468 } else if (list_empty(&qh->qtd_list)) {
469 dwc2_hcd_qh_unlink(hsotg, qh);
472 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
478 /* Must NOT be called with interrupt disabled or spinlock held */
479 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
480 struct usb_host_endpoint *ep, int retry)
482 struct dwc2_qtd *qtd, *qtd_tmp;
487 spin_lock_irqsave(&hsotg->lock, flags);
495 while (!list_empty(&qh->qtd_list) && retry--) {
498 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
503 spin_unlock_irqrestore(&hsotg->lock, flags);
504 usleep_range(20000, 40000);
505 spin_lock_irqsave(&hsotg->lock, flags);
513 dwc2_hcd_qh_unlink(hsotg, qh);
515 /* Free each QTD in the QH's QTD list */
516 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
517 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
520 spin_unlock_irqrestore(&hsotg->lock, flags);
521 dwc2_hcd_qh_free(hsotg, qh);
527 spin_unlock_irqrestore(&hsotg->lock, flags);
532 /* Must be called with interrupt disabled and spinlock held */
533 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
534 struct usb_host_endpoint *ep)
536 struct dwc2_qh *qh = ep->hcpriv;
541 qh->data_toggle = DWC2_HC_PID_DATA0;
547 * Initializes dynamic portions of the DWC_otg HCD state
549 * Must be called with interrupt disabled and spinlock held
551 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
553 struct dwc2_host_chan *chan, *chan_tmp;
557 hsotg->flags.d32 = 0;
558 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
560 if (hsotg->core_params->uframe_sched > 0) {
561 hsotg->available_host_channels =
562 hsotg->core_params->host_channels;
564 hsotg->non_periodic_channels = 0;
565 hsotg->periodic_channels = 0;
569 * Put all channels in the free channel list and clean up channel
572 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
574 list_del_init(&chan->hc_list_entry);
576 num_channels = hsotg->core_params->host_channels;
577 for (i = 0; i < num_channels; i++) {
578 chan = hsotg->hc_ptr_array[i];
579 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
580 dwc2_hc_cleanup(hsotg, chan);
583 /* Initialize the DWC core for host mode operation */
584 dwc2_core_host_init(hsotg);
587 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
588 struct dwc2_host_chan *chan,
589 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
591 int hub_addr, hub_port;
594 chan->xact_pos = qtd->isoc_split_pos;
595 chan->complete_split = qtd->complete_split;
596 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
597 chan->hub_addr = (u8)hub_addr;
598 chan->hub_port = (u8)hub_port;
601 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
602 struct dwc2_host_chan *chan,
603 struct dwc2_qtd *qtd, void *bufptr)
605 struct dwc2_hcd_urb *urb = qtd->urb;
606 struct dwc2_hcd_iso_packet_desc *frame_desc;
608 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
609 case USB_ENDPOINT_XFER_CONTROL:
610 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
612 switch (qtd->control_phase) {
613 case DWC2_CONTROL_SETUP:
614 dev_vdbg(hsotg->dev, " Control setup transaction\n");
617 chan->data_pid_start = DWC2_HC_PID_SETUP;
618 if (hsotg->core_params->dma_enable > 0)
619 chan->xfer_dma = urb->setup_dma;
621 chan->xfer_buf = urb->setup_packet;
626 case DWC2_CONTROL_DATA:
627 dev_vdbg(hsotg->dev, " Control data transaction\n");
628 chan->data_pid_start = qtd->data_toggle;
631 case DWC2_CONTROL_STATUS:
633 * Direction is opposite of data direction or IN if no
636 dev_vdbg(hsotg->dev, " Control status transaction\n");
637 if (urb->length == 0)
641 dwc2_hcd_is_pipe_out(&urb->pipe_info);
644 chan->data_pid_start = DWC2_HC_PID_DATA1;
646 if (hsotg->core_params->dma_enable > 0)
647 chan->xfer_dma = hsotg->status_buf_dma;
649 chan->xfer_buf = hsotg->status_buf;
655 case USB_ENDPOINT_XFER_BULK:
656 chan->ep_type = USB_ENDPOINT_XFER_BULK;
659 case USB_ENDPOINT_XFER_INT:
660 chan->ep_type = USB_ENDPOINT_XFER_INT;
663 case USB_ENDPOINT_XFER_ISOC:
664 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
665 if (hsotg->core_params->dma_desc_enable > 0)
668 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
669 frame_desc->status = 0;
671 if (hsotg->core_params->dma_enable > 0) {
672 chan->xfer_dma = urb->dma;
673 chan->xfer_dma += frame_desc->offset +
674 qtd->isoc_split_offset;
676 chan->xfer_buf = urb->buf;
677 chan->xfer_buf += frame_desc->offset +
678 qtd->isoc_split_offset;
681 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
683 /* For non-dword aligned buffers */
684 if (hsotg->core_params->dma_enable > 0 &&
685 (chan->xfer_dma & 0x3))
686 bufptr = (u8 *)urb->buf + frame_desc->offset +
687 qtd->isoc_split_offset;
691 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
692 if (chan->xfer_len <= 188)
693 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
695 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
703 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
704 struct dwc2_host_chan *chan,
705 struct dwc2_hcd_urb *urb, void *bufptr)
711 if (!qh->dw_align_buf) {
712 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
713 buf_size = hsotg->core_params->max_transfer_size;
715 /* 3072 = 3 max-size Isoc packets */
718 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
719 if (!qh->dw_align_buf)
721 qh->dw_align_buf_size = buf_size;
724 if (chan->xfer_len) {
725 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
729 if (usb_urb->transfer_flags &
730 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
731 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
732 hcd = dwc2_hsotg_to_hcd(hsotg);
733 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
736 memcpy(qh->dw_align_buf, bufptr,
739 dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
743 qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
744 qh->dw_align_buf, qh->dw_align_buf_size,
745 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
746 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
747 dev_err(hsotg->dev, "can't map align_buf\n");
752 chan->align_buf = qh->dw_align_buf_dma;
757 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
758 * channel and initializes the host channel to perform the transactions. The
759 * host channel is removed from the free list.
761 * @hsotg: The HCD state structure
762 * @qh: Transactions from the first QTD for this QH are selected and assigned
763 * to a free host channel
765 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
767 struct dwc2_host_chan *chan;
768 struct dwc2_hcd_urb *urb;
769 struct dwc2_qtd *qtd;
773 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
775 if (list_empty(&qh->qtd_list)) {
776 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
780 if (list_empty(&hsotg->free_hc_list)) {
781 dev_dbg(hsotg->dev, "No free channel to assign\n");
785 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
788 /* Remove host channel from free list */
789 list_del_init(&chan->hc_list_entry);
791 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
797 * Use usb_pipedevice to determine device address. This address is
798 * 0 before the SET_ADDRESS command and the correct address afterward.
800 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
801 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
802 chan->speed = qh->dev_speed;
803 chan->max_packet = dwc2_max_packet(qh->maxp);
805 chan->xfer_started = 0;
806 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
807 chan->error_state = (qtd->error_count > 0);
808 chan->halt_on_queue = 0;
809 chan->halt_pending = 0;
813 * The following values may be modified in the transfer type section
814 * below. The xfer_len value may be reduced when the transfer is
815 * started to accommodate the max widths of the XferSize and PktCnt
816 * fields in the HCTSIZn register.
819 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
823 chan->do_ping = qh->ping_state;
825 chan->data_pid_start = qh->data_toggle;
826 chan->multi_count = 1;
828 if (urb->actual_length > urb->length &&
829 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
830 urb->actual_length = urb->length;
832 if (hsotg->core_params->dma_enable > 0) {
833 chan->xfer_dma = urb->dma + urb->actual_length;
835 /* For non-dword aligned case */
836 if (hsotg->core_params->dma_desc_enable <= 0 &&
837 (chan->xfer_dma & 0x3))
838 bufptr = (u8 *)urb->buf + urb->actual_length;
840 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
843 chan->xfer_len = urb->length - urb->actual_length;
844 chan->xfer_count = 0;
846 /* Set the split attributes if required */
848 dwc2_hc_init_split(hsotg, chan, qtd, urb);
852 /* Set the transfer attributes */
853 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
855 /* Non DWORD-aligned buffer case */
857 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
858 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
860 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
862 /* Add channel back to free list */
864 chan->multi_count = 0;
865 list_add_tail(&chan->hc_list_entry,
866 &hsotg->free_hc_list);
875 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
876 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
878 * This value may be modified when the transfer is started
879 * to reflect the actual transfer length
881 chan->multi_count = dwc2_hb_mult(qh->maxp);
883 if (hsotg->core_params->dma_desc_enable > 0)
884 chan->desc_list_addr = qh->desc_list_dma;
886 dwc2_hc_init(hsotg, chan);
893 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
894 * schedule and assigns them to available host channels. Called from the HCD
895 * interrupt handler functions.
897 * @hsotg: The HCD state structure
899 * Return: The types of new transactions that were assigned to host channels
901 enum dwc2_transaction_type dwc2_hcd_select_transactions(
902 struct dwc2_hsotg *hsotg)
904 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
905 struct list_head *qh_ptr;
909 #ifdef DWC2_DEBUG_SOF
910 dev_vdbg(hsotg->dev, " Select Transactions\n");
913 /* Process entries in the periodic ready list */
914 qh_ptr = hsotg->periodic_sched_ready.next;
915 while (qh_ptr != &hsotg->periodic_sched_ready) {
916 if (list_empty(&hsotg->free_hc_list))
918 if (hsotg->core_params->uframe_sched > 0) {
919 if (hsotg->available_host_channels <= 1)
921 hsotg->available_host_channels--;
923 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
924 if (dwc2_assign_and_init_hc(hsotg, qh))
928 * Move the QH from the periodic ready schedule to the
929 * periodic assigned schedule
931 qh_ptr = qh_ptr->next;
932 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
933 ret_val = DWC2_TRANSACTION_PERIODIC;
937 * Process entries in the inactive portion of the non-periodic
938 * schedule. Some free host channels may not be used if they are
939 * reserved for periodic transfers.
941 num_channels = hsotg->core_params->host_channels;
942 qh_ptr = hsotg->non_periodic_sched_inactive.next;
943 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
944 if (hsotg->core_params->uframe_sched <= 0 &&
945 hsotg->non_periodic_channels >= num_channels -
946 hsotg->periodic_channels)
948 if (list_empty(&hsotg->free_hc_list))
950 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
951 if (hsotg->core_params->uframe_sched > 0) {
952 if (hsotg->available_host_channels < 1)
954 hsotg->available_host_channels--;
957 if (dwc2_assign_and_init_hc(hsotg, qh))
961 * Move the QH from the non-periodic inactive schedule to the
962 * non-periodic active schedule
964 qh_ptr = qh_ptr->next;
965 list_move(&qh->qh_list_entry,
966 &hsotg->non_periodic_sched_active);
968 if (ret_val == DWC2_TRANSACTION_NONE)
969 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
971 ret_val = DWC2_TRANSACTION_ALL;
973 if (hsotg->core_params->uframe_sched <= 0)
974 hsotg->non_periodic_channels++;
981 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
982 * a host channel associated with either a periodic or non-periodic transfer
984 * @hsotg: The HCD state structure
985 * @chan: Host channel descriptor associated with either a periodic or
986 * non-periodic transfer
987 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
988 * for periodic transfers or the non-periodic Tx FIFO
989 * for non-periodic transfers
991 * Return: 1 if a request is queued and more requests may be needed to
992 * complete the transfer, 0 if no more requests are required for this
993 * transfer, -1 if there is insufficient space in the Tx FIFO
995 * This function assumes that there is space available in the appropriate
996 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
997 * it checks whether space is available in the appropriate Tx FIFO.
999 * Must be called with interrupt disabled and spinlock held
1001 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1002 struct dwc2_host_chan *chan,
1003 u16 fifo_dwords_avail)
1007 if (hsotg->core_params->dma_enable > 0) {
1008 if (hsotg->core_params->dma_desc_enable > 0) {
1009 if (!chan->xfer_started ||
1010 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1011 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1012 chan->qh->ping_state = 0;
1014 } else if (!chan->xfer_started) {
1015 dwc2_hc_start_transfer(hsotg, chan);
1016 chan->qh->ping_state = 0;
1018 } else if (chan->halt_pending) {
1019 /* Don't queue a request if the channel has been halted */
1020 } else if (chan->halt_on_queue) {
1021 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1022 } else if (chan->do_ping) {
1023 if (!chan->xfer_started)
1024 dwc2_hc_start_transfer(hsotg, chan);
1025 } else if (!chan->ep_is_in ||
1026 chan->data_pid_start == DWC2_HC_PID_SETUP) {
1027 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1028 if (!chan->xfer_started) {
1029 dwc2_hc_start_transfer(hsotg, chan);
1032 retval = dwc2_hc_continue_transfer(hsotg, chan);
1038 if (!chan->xfer_started) {
1039 dwc2_hc_start_transfer(hsotg, chan);
1042 retval = dwc2_hc_continue_transfer(hsotg, chan);
1050 * Processes periodic channels for the next frame and queues transactions for
1051 * these channels to the DWC_otg controller. After queueing transactions, the
1052 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1053 * to queue as Periodic Tx FIFO or request queue space becomes available.
1054 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1056 * Must be called with interrupt disabled and spinlock held
1058 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1060 struct list_head *qh_ptr;
1066 int no_queue_space = 0;
1067 int no_fifo_space = 0;
1071 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1073 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1074 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1075 TXSTS_QSPCAVAIL_SHIFT;
1076 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1077 TXSTS_FSPCAVAIL_SHIFT;
1080 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1082 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1086 qh_ptr = hsotg->periodic_sched_assigned.next;
1087 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1088 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1089 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1090 TXSTS_QSPCAVAIL_SHIFT;
1091 if (qspcavail == 0) {
1096 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1098 qh_ptr = qh_ptr->next;
1102 /* Make sure EP's TT buffer is clean before queueing qtds */
1103 if (qh->tt_buffer_dirty) {
1104 qh_ptr = qh_ptr->next;
1109 * Set a flag if we're queuing high-bandwidth in slave mode.
1110 * The flag prevents any halts to get into the request queue in
1111 * the middle of multiple high-bandwidth packets getting queued.
1113 if (hsotg->core_params->dma_enable <= 0 &&
1114 qh->channel->multi_count > 1)
1115 hsotg->queuing_high_bandwidth = 1;
1117 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1118 TXSTS_FSPCAVAIL_SHIFT;
1119 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1126 * In Slave mode, stay on the current transfer until there is
1127 * nothing more to do or the high-bandwidth request count is
1128 * reached. In DMA mode, only need to queue one request. The
1129 * controller automatically handles multiple packets for
1130 * high-bandwidth transfers.
1132 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1133 qh->channel->requests == qh->channel->multi_count) {
1134 qh_ptr = qh_ptr->next;
1136 * Move the QH from the periodic assigned schedule to
1137 * the periodic queued schedule
1139 list_move(&qh->qh_list_entry,
1140 &hsotg->periodic_sched_queued);
1142 /* done queuing high bandwidth */
1143 hsotg->queuing_high_bandwidth = 0;
1147 if (hsotg->core_params->dma_enable <= 0) {
1148 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1149 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1150 TXSTS_QSPCAVAIL_SHIFT;
1151 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1152 TXSTS_FSPCAVAIL_SHIFT;
1154 dev_vdbg(hsotg->dev,
1155 " P Tx Req Queue Space Avail (after queue): %d\n",
1157 dev_vdbg(hsotg->dev,
1158 " P Tx FIFO Space Avail (after queue): %d\n",
1162 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1163 no_queue_space || no_fifo_space) {
1165 * May need to queue more transactions as the request
1166 * queue or Tx FIFO empties. Enable the periodic Tx
1167 * FIFO empty interrupt. (Always use the half-empty
1168 * level to ensure that new requests are loaded as
1169 * soon as possible.)
1171 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1172 gintmsk |= GINTSTS_PTXFEMP;
1173 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1176 * Disable the Tx FIFO empty interrupt since there are
1177 * no more transactions that need to be queued right
1178 * now. This function is called from interrupt
1179 * handlers to queue more transactions as transfer
1182 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1183 gintmsk &= ~GINTSTS_PTXFEMP;
1184 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1190 * Processes active non-periodic channels and queues transactions for these
1191 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1192 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1193 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1194 * FIFO Empty interrupt is disabled.
1196 * Must be called with interrupt disabled and spinlock held
1198 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1200 struct list_head *orig_qh_ptr;
1207 int no_queue_space = 0;
1208 int no_fifo_space = 0;
1211 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1213 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1214 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1215 TXSTS_QSPCAVAIL_SHIFT;
1216 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1217 TXSTS_FSPCAVAIL_SHIFT;
1218 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1220 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1224 * Keep track of the starting point. Skip over the start-of-list
1227 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1228 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1229 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1232 * Process once through the active list or until no more space is
1233 * available in the request queue or the Tx FIFO
1236 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1237 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1238 TXSTS_QSPCAVAIL_SHIFT;
1239 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1244 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1249 /* Make sure EP's TT buffer is clean before queueing qtds */
1250 if (qh->tt_buffer_dirty)
1253 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1254 TXSTS_FSPCAVAIL_SHIFT;
1255 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1259 } else if (status < 0) {
1264 /* Advance to next QH, skipping start-of-list entry */
1265 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1266 if (hsotg->non_periodic_qh_ptr ==
1267 &hsotg->non_periodic_sched_active)
1268 hsotg->non_periodic_qh_ptr =
1269 hsotg->non_periodic_qh_ptr->next;
1270 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1272 if (hsotg->core_params->dma_enable <= 0) {
1273 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1274 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1275 TXSTS_QSPCAVAIL_SHIFT;
1276 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1277 TXSTS_FSPCAVAIL_SHIFT;
1278 dev_vdbg(hsotg->dev,
1279 " NP Tx Req Queue Space Avail (after queue): %d\n",
1281 dev_vdbg(hsotg->dev,
1282 " NP Tx FIFO Space Avail (after queue): %d\n",
1285 if (more_to_do || no_queue_space || no_fifo_space) {
1287 * May need to queue more transactions as the request
1288 * queue or Tx FIFO empties. Enable the non-periodic
1289 * Tx FIFO empty interrupt. (Always use the half-empty
1290 * level to ensure that new requests are loaded as
1291 * soon as possible.)
1293 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1294 gintmsk |= GINTSTS_NPTXFEMP;
1295 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1298 * Disable the Tx FIFO empty interrupt since there are
1299 * no more transactions that need to be queued right
1300 * now. This function is called from interrupt
1301 * handlers to queue more transactions as transfer
1304 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1305 gintmsk &= ~GINTSTS_NPTXFEMP;
1306 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1312 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1313 * and queues transactions for these channels to the DWC_otg controller. Called
1314 * from the HCD interrupt handler functions.
1316 * @hsotg: The HCD state structure
1317 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1320 * Must be called with interrupt disabled and spinlock held
1322 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1323 enum dwc2_transaction_type tr_type)
1325 #ifdef DWC2_DEBUG_SOF
1326 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1328 /* Process host channels associated with periodic transfers */
1329 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1330 tr_type == DWC2_TRANSACTION_ALL) &&
1331 !list_empty(&hsotg->periodic_sched_assigned))
1332 dwc2_process_periodic_channels(hsotg);
1334 /* Process host channels associated with non-periodic transfers */
1335 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1336 tr_type == DWC2_TRANSACTION_ALL) {
1337 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1338 dwc2_process_non_periodic_channels(hsotg);
1341 * Ensure NP Tx FIFO empty interrupt is disabled when
1342 * there are no non-periodic transfers to process
1344 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1346 gintmsk &= ~GINTSTS_NPTXFEMP;
1347 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1352 static void dwc2_conn_id_status_change(struct work_struct *work)
1354 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1359 dev_dbg(hsotg->dev, "%s()\n", __func__);
1361 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1362 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1363 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1364 !!(gotgctl & GOTGCTL_CONID_B));
1366 /* B-Device connector (Device Mode) */
1367 if (gotgctl & GOTGCTL_CONID_B) {
1368 /* Wait for switch to device mode */
1369 dev_dbg(hsotg->dev, "connId B\n");
1370 while (!dwc2_is_device_mode(hsotg)) {
1371 dev_info(hsotg->dev,
1372 "Waiting for Peripheral Mode, Mode=%s\n",
1373 dwc2_is_host_mode(hsotg) ? "Host" :
1375 usleep_range(20000, 40000);
1381 "Connection id status change timed out\n");
1382 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1383 dwc2_core_init(hsotg, false, -1);
1384 dwc2_enable_global_interrupts(hsotg);
1385 dwc2_hsotg_core_init_disconnected(hsotg, false);
1386 dwc2_hsotg_core_connect(hsotg);
1388 /* A-Device connector (Host Mode) */
1389 dev_dbg(hsotg->dev, "connId A\n");
1390 while (!dwc2_is_host_mode(hsotg)) {
1391 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1392 dwc2_is_host_mode(hsotg) ?
1393 "Host" : "Peripheral");
1394 usleep_range(20000, 40000);
1400 "Connection id status change timed out\n");
1401 hsotg->op_state = OTG_STATE_A_HOST;
1403 /* Initialize the Core for Host mode */
1404 dwc2_core_init(hsotg, false, -1);
1405 dwc2_enable_global_interrupts(hsotg);
1406 dwc2_hcd_start(hsotg);
1410 static void dwc2_wakeup_detected(unsigned long data)
1412 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1415 dev_dbg(hsotg->dev, "%s()\n", __func__);
1418 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1419 * so that OPT tests pass with all PHYs.)
1421 hprt0 = dwc2_read_hprt0(hsotg);
1422 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1423 hprt0 &= ~HPRT0_RES;
1424 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1425 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1426 dwc2_readl(hsotg->regs + HPRT0));
1428 hsotg->bus_suspended = 0;
1429 dwc2_hcd_rem_wakeup(hsotg);
1431 /* Change to L0 state */
1432 hsotg->lx_state = DWC2_L0;
1435 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1437 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1439 return hcd->self.b_hnp_enable;
1442 /* Must NOT be called with interrupt disabled or spinlock held */
1443 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1445 unsigned long flags;
1450 dev_dbg(hsotg->dev, "%s()\n", __func__);
1452 spin_lock_irqsave(&hsotg->lock, flags);
1454 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1455 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1456 gotgctl |= GOTGCTL_HSTSETHNPEN;
1457 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1458 hsotg->op_state = OTG_STATE_A_SUSPEND;
1461 hprt0 = dwc2_read_hprt0(hsotg);
1462 hprt0 |= HPRT0_SUSP;
1463 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1465 hsotg->bus_suspended = 1;
1468 * If hibernation is supported, Phy clock will be suspended
1469 * after registers are backuped.
1471 if (!hsotg->core_params->hibernation) {
1472 /* Suspend the Phy Clock */
1473 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1474 pcgctl |= PCGCTL_STOPPCLK;
1475 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1479 /* For HNP the bus must be suspended for at least 200ms */
1480 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1481 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1482 pcgctl &= ~PCGCTL_STOPPCLK;
1483 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1485 spin_unlock_irqrestore(&hsotg->lock, flags);
1487 usleep_range(200000, 250000);
1489 spin_unlock_irqrestore(&hsotg->lock, flags);
1493 /* Must NOT be called with interrupt disabled or spinlock held */
1494 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1496 unsigned long flags;
1501 * If hibernation is supported, Phy clock is already resumed
1502 * after registers restore.
1504 if (!hsotg->core_params->hibernation) {
1505 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1506 pcgctl &= ~PCGCTL_STOPPCLK;
1507 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1508 usleep_range(20000, 40000);
1511 spin_lock_irqsave(&hsotg->lock, flags);
1512 hprt0 = dwc2_read_hprt0(hsotg);
1514 hprt0 &= ~HPRT0_SUSP;
1515 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1516 spin_unlock_irqrestore(&hsotg->lock, flags);
1518 msleep(USB_RESUME_TIMEOUT);
1520 spin_lock_irqsave(&hsotg->lock, flags);
1521 hprt0 = dwc2_read_hprt0(hsotg);
1522 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
1523 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1524 hsotg->bus_suspended = 0;
1525 spin_unlock_irqrestore(&hsotg->lock, flags);
1528 /* Handles hub class-specific requests */
1529 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1530 u16 wvalue, u16 windex, char *buf, u16 wlength)
1532 struct usb_hub_descriptor *hub_desc;
1540 case ClearHubFeature:
1541 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1544 case C_HUB_LOCAL_POWER:
1545 case C_HUB_OVER_CURRENT:
1546 /* Nothing required here */
1552 "ClearHubFeature request %1xh unknown\n",
1557 case ClearPortFeature:
1558 if (wvalue != USB_PORT_FEAT_L1)
1559 if (!windex || windex > 1)
1562 case USB_PORT_FEAT_ENABLE:
1564 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1565 hprt0 = dwc2_read_hprt0(hsotg);
1567 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1570 case USB_PORT_FEAT_SUSPEND:
1572 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1574 if (hsotg->bus_suspended)
1575 dwc2_port_resume(hsotg);
1578 case USB_PORT_FEAT_POWER:
1580 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1581 hprt0 = dwc2_read_hprt0(hsotg);
1582 hprt0 &= ~HPRT0_PWR;
1583 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1586 case USB_PORT_FEAT_INDICATOR:
1588 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1589 /* Port indicator not supported */
1592 case USB_PORT_FEAT_C_CONNECTION:
1594 * Clears driver's internal Connect Status Change flag
1597 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1598 hsotg->flags.b.port_connect_status_change = 0;
1601 case USB_PORT_FEAT_C_RESET:
1602 /* Clears driver's internal Port Reset Change flag */
1604 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1605 hsotg->flags.b.port_reset_change = 0;
1608 case USB_PORT_FEAT_C_ENABLE:
1610 * Clears the driver's internal Port Enable/Disable
1614 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1615 hsotg->flags.b.port_enable_change = 0;
1618 case USB_PORT_FEAT_C_SUSPEND:
1620 * Clears the driver's internal Port Suspend Change
1621 * flag, which is set when resume signaling on the host
1625 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1626 hsotg->flags.b.port_suspend_change = 0;
1629 case USB_PORT_FEAT_C_PORT_L1:
1631 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1632 hsotg->flags.b.port_l1_change = 0;
1635 case USB_PORT_FEAT_C_OVER_CURRENT:
1637 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1638 hsotg->flags.b.port_over_current_change = 0;
1644 "ClearPortFeature request %1xh unknown or unsupported\n",
1649 case GetHubDescriptor:
1650 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1651 hub_desc = (struct usb_hub_descriptor *)buf;
1652 hub_desc->bDescLength = 9;
1653 hub_desc->bDescriptorType = USB_DT_HUB;
1654 hub_desc->bNbrPorts = 1;
1655 hub_desc->wHubCharacteristics =
1656 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1657 HUB_CHAR_INDV_PORT_OCPM);
1658 hub_desc->bPwrOn2PwrGood = 1;
1659 hub_desc->bHubContrCurrent = 0;
1660 hub_desc->u.hs.DeviceRemovable[0] = 0;
1661 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1665 dev_dbg(hsotg->dev, "GetHubStatus\n");
1670 dev_vdbg(hsotg->dev,
1671 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1673 if (!windex || windex > 1)
1677 if (hsotg->flags.b.port_connect_status_change)
1678 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1679 if (hsotg->flags.b.port_enable_change)
1680 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1681 if (hsotg->flags.b.port_suspend_change)
1682 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1683 if (hsotg->flags.b.port_l1_change)
1684 port_status |= USB_PORT_STAT_C_L1 << 16;
1685 if (hsotg->flags.b.port_reset_change)
1686 port_status |= USB_PORT_STAT_C_RESET << 16;
1687 if (hsotg->flags.b.port_over_current_change) {
1688 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1689 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1692 if (!hsotg->flags.b.port_connect_status) {
1694 * The port is disconnected, which means the core is
1695 * either in device mode or it soon will be. Just
1696 * return 0's for the remainder of the port status
1697 * since the port register can't be read if the core
1698 * is in device mode.
1700 *(__le32 *)buf = cpu_to_le32(port_status);
1704 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1705 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
1707 if (hprt0 & HPRT0_CONNSTS)
1708 port_status |= USB_PORT_STAT_CONNECTION;
1709 if (hprt0 & HPRT0_ENA)
1710 port_status |= USB_PORT_STAT_ENABLE;
1711 if (hprt0 & HPRT0_SUSP)
1712 port_status |= USB_PORT_STAT_SUSPEND;
1713 if (hprt0 & HPRT0_OVRCURRACT)
1714 port_status |= USB_PORT_STAT_OVERCURRENT;
1715 if (hprt0 & HPRT0_RST)
1716 port_status |= USB_PORT_STAT_RESET;
1717 if (hprt0 & HPRT0_PWR)
1718 port_status |= USB_PORT_STAT_POWER;
1720 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1721 if (speed == HPRT0_SPD_HIGH_SPEED)
1722 port_status |= USB_PORT_STAT_HIGH_SPEED;
1723 else if (speed == HPRT0_SPD_LOW_SPEED)
1724 port_status |= USB_PORT_STAT_LOW_SPEED;
1726 if (hprt0 & HPRT0_TSTCTL_MASK)
1727 port_status |= USB_PORT_STAT_TEST;
1728 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1730 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1731 *(__le32 *)buf = cpu_to_le32(port_status);
1735 dev_dbg(hsotg->dev, "SetHubFeature\n");
1736 /* No HUB features supported */
1739 case SetPortFeature:
1740 dev_dbg(hsotg->dev, "SetPortFeature\n");
1741 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1744 if (!hsotg->flags.b.port_connect_status) {
1746 * The port is disconnected, which means the core is
1747 * either in device mode or it soon will be. Just
1748 * return without doing anything since the port
1749 * register can't be written if the core is in device
1756 case USB_PORT_FEAT_SUSPEND:
1758 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1759 if (windex != hsotg->otg_port)
1761 dwc2_port_suspend(hsotg, windex);
1764 case USB_PORT_FEAT_POWER:
1766 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1767 hprt0 = dwc2_read_hprt0(hsotg);
1769 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1772 case USB_PORT_FEAT_RESET:
1773 hprt0 = dwc2_read_hprt0(hsotg);
1775 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1776 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1777 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1778 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1779 /* ??? Original driver does this */
1780 dwc2_writel(0, hsotg->regs + PCGCTL);
1782 hprt0 = dwc2_read_hprt0(hsotg);
1783 /* Clear suspend bit if resetting from suspend state */
1784 hprt0 &= ~HPRT0_SUSP;
1787 * When B-Host the Port reset bit is set in the Start
1788 * HCD Callback function, so that the reset is started
1789 * within 1ms of the HNP success interrupt
1791 if (!dwc2_hcd_is_b_host(hsotg)) {
1792 hprt0 |= HPRT0_PWR | HPRT0_RST;
1794 "In host mode, hprt0=%08x\n", hprt0);
1795 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1798 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1799 usleep_range(50000, 70000);
1800 hprt0 &= ~HPRT0_RST;
1801 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1802 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1805 case USB_PORT_FEAT_INDICATOR:
1807 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1811 case USB_PORT_FEAT_TEST:
1812 hprt0 = dwc2_read_hprt0(hsotg);
1814 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1815 hprt0 &= ~HPRT0_TSTCTL_MASK;
1816 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
1817 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1823 "SetPortFeature %1xh unknown or unsupported\n",
1833 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1834 typereq, windex, wvalue);
1841 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1848 retval = (hsotg->flags.b.port_connect_status_change ||
1849 hsotg->flags.b.port_reset_change ||
1850 hsotg->flags.b.port_enable_change ||
1851 hsotg->flags.b.port_suspend_change ||
1852 hsotg->flags.b.port_over_current_change);
1856 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1857 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1858 hsotg->flags.b.port_connect_status_change);
1859 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1860 hsotg->flags.b.port_reset_change);
1861 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1862 hsotg->flags.b.port_enable_change);
1863 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1864 hsotg->flags.b.port_suspend_change);
1865 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1866 hsotg->flags.b.port_over_current_change);
1872 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1874 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
1876 #ifdef DWC2_DEBUG_SOF
1877 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1878 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1880 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1883 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1885 return hsotg->op_state == OTG_STATE_B_HOST;
1888 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1892 struct dwc2_hcd_urb *urb;
1893 u32 size = sizeof(*urb) + iso_desc_count *
1894 sizeof(struct dwc2_hcd_iso_packet_desc);
1896 urb = kzalloc(size, mem_flags);
1898 urb->packet_count = iso_desc_count;
1902 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1903 struct dwc2_hcd_urb *urb, u8 dev_addr,
1904 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1907 ep_type == USB_ENDPOINT_XFER_BULK ||
1908 ep_type == USB_ENDPOINT_XFER_CONTROL)
1909 dev_vdbg(hsotg->dev,
1910 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1911 dev_addr, ep_num, ep_dir, ep_type, mps);
1912 urb->pipe_info.dev_addr = dev_addr;
1913 urb->pipe_info.ep_num = ep_num;
1914 urb->pipe_info.pipe_type = ep_type;
1915 urb->pipe_info.pipe_dir = ep_dir;
1916 urb->pipe_info.mps = mps;
1920 * NOTE: This function will be removed once the peripheral controller code
1921 * is integrated and the driver is stable
1923 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1926 struct dwc2_host_chan *chan;
1927 struct dwc2_hcd_urb *urb;
1928 struct dwc2_qtd *qtd;
1934 num_channels = hsotg->core_params->host_channels;
1935 dev_dbg(hsotg->dev, "\n");
1937 "************************************************************\n");
1938 dev_dbg(hsotg->dev, "HCD State:\n");
1939 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1941 for (i = 0; i < num_channels; i++) {
1942 chan = hsotg->hc_ptr_array[i];
1943 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1945 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1946 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1947 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1948 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1949 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1950 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1951 chan->data_pid_start);
1952 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1953 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1954 chan->xfer_started);
1955 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1956 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1957 (unsigned long)chan->xfer_dma);
1958 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1959 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1960 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1961 chan->halt_on_queue);
1962 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1963 chan->halt_pending);
1964 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1965 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1966 dev_dbg(hsotg->dev, " complete_split: %d\n",
1967 chan->complete_split);
1968 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
1969 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
1970 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
1971 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
1972 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
1974 if (chan->xfer_started) {
1975 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1977 hfnum = dwc2_readl(hsotg->regs + HFNUM);
1978 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1979 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
1980 hcint = dwc2_readl(hsotg->regs + HCINT(i));
1981 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
1982 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
1983 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
1984 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
1985 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
1986 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
1989 if (!(chan->xfer_started && chan->qh))
1992 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1993 if (!qtd->in_process)
1996 dev_dbg(hsotg->dev, " URB Info:\n");
1997 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
2001 " Dev: %d, EP: %d %s\n",
2002 dwc2_hcd_get_dev_addr(&urb->pipe_info),
2003 dwc2_hcd_get_ep_num(&urb->pipe_info),
2004 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
2007 " Max packet size: %d\n",
2008 dwc2_hcd_get_mps(&urb->pipe_info));
2010 " transfer_buffer: %p\n",
2013 " transfer_dma: %08lx\n",
2014 (unsigned long)urb->dma);
2016 " transfer_buffer_length: %d\n",
2018 dev_dbg(hsotg->dev, " actual_length: %d\n",
2019 urb->actual_length);
2024 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
2025 hsotg->non_periodic_channels);
2026 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
2027 hsotg->periodic_channels);
2028 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
2029 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2030 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
2031 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2032 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
2033 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2034 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2035 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
2036 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2037 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
2038 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2039 dwc2_hcd_dump_frrem(hsotg);
2040 dwc2_dump_global_registers(hsotg);
2041 dwc2_dump_host_registers(hsotg);
2043 "************************************************************\n");
2044 dev_dbg(hsotg->dev, "\n");
2049 * NOTE: This function will be removed once the peripheral controller code
2050 * is integrated and the driver is stable
2052 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2054 #ifdef DWC2_DUMP_FRREM
2055 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2056 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2057 hsotg->frrem_samples, hsotg->frrem_accum,
2058 hsotg->frrem_samples > 0 ?
2059 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2060 dev_dbg(hsotg->dev, "\n");
2061 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2062 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2063 hsotg->hfnum_7_samples,
2064 hsotg->hfnum_7_frrem_accum,
2065 hsotg->hfnum_7_samples > 0 ?
2066 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2067 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2068 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2069 hsotg->hfnum_0_samples,
2070 hsotg->hfnum_0_frrem_accum,
2071 hsotg->hfnum_0_samples > 0 ?
2072 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2073 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2074 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2075 hsotg->hfnum_other_samples,
2076 hsotg->hfnum_other_frrem_accum,
2077 hsotg->hfnum_other_samples > 0 ?
2078 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2080 dev_dbg(hsotg->dev, "\n");
2081 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2082 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2083 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2084 hsotg->hfnum_7_samples_a > 0 ?
2085 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2086 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2087 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2088 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2089 hsotg->hfnum_0_samples_a > 0 ?
2090 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2091 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2092 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2093 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2094 hsotg->hfnum_other_samples_a > 0 ?
2095 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2097 dev_dbg(hsotg->dev, "\n");
2098 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2099 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2100 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2101 hsotg->hfnum_7_samples_b > 0 ?
2102 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2103 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2104 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2105 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2106 (hsotg->hfnum_0_samples_b > 0) ?
2107 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2108 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2109 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2110 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2111 (hsotg->hfnum_other_samples_b > 0) ?
2112 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2117 struct wrapper_priv_data {
2118 struct dwc2_hsotg *hsotg;
2121 /* Gets the dwc2_hsotg from a usb_hcd */
2122 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2124 struct wrapper_priv_data *p;
2126 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2130 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2132 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2134 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2136 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2137 _dwc2_hcd_start(hcd);
2140 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2142 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2144 hcd->self.is_b_host = 0;
2147 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2150 struct urb *urb = context;
2153 *hub_addr = urb->dev->tt->hub->devnum;
2156 *hub_port = urb->dev->ttport;
2159 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2161 struct urb *urb = context;
2163 return urb->dev->speed;
2166 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2169 struct usb_bus *bus = hcd_to_bus(hcd);
2172 bus->bandwidth_allocated += bw / urb->interval;
2173 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2174 bus->bandwidth_isoc_reqs++;
2176 bus->bandwidth_int_reqs++;
2179 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2182 struct usb_bus *bus = hcd_to_bus(hcd);
2185 bus->bandwidth_allocated -= bw / urb->interval;
2186 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2187 bus->bandwidth_isoc_reqs--;
2189 bus->bandwidth_int_reqs--;
2193 * Sets the final status of an URB and returns it to the upper layer. Any
2194 * required cleanup of the URB is performed.
2196 * Must be called with interrupt disabled and spinlock held
2198 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2205 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2210 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2214 urb = qtd->urb->priv;
2216 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2220 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2223 dev_vdbg(hsotg->dev,
2224 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2225 __func__, urb, usb_pipedevice(urb->pipe),
2226 usb_pipeendpoint(urb->pipe),
2227 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2228 urb->actual_length);
2231 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2232 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2233 for (i = 0; i < urb->number_of_packets; ++i) {
2234 urb->iso_frame_desc[i].actual_length =
2235 dwc2_hcd_urb_get_iso_desc_actual_length(
2237 urb->iso_frame_desc[i].status =
2238 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2242 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2243 for (i = 0; i < urb->number_of_packets; i++)
2244 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2245 i, urb->iso_frame_desc[i].status);
2248 urb->status = status;
2250 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2251 urb->actual_length < urb->transfer_buffer_length)
2252 urb->status = -EREMOTEIO;
2255 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2256 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2257 struct usb_host_endpoint *ep = urb->ep;
2260 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2261 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2265 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2270 spin_unlock(&hsotg->lock);
2271 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2272 spin_lock(&hsotg->lock);
2276 * Work queue function for starting the HCD when A-Cable is connected
2278 static void dwc2_hcd_start_func(struct work_struct *work)
2280 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2283 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2284 dwc2_host_start(hsotg);
2288 * Reset work queue function
2290 static void dwc2_hcd_reset_func(struct work_struct *work)
2292 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2296 dev_dbg(hsotg->dev, "USB RESET function called\n");
2297 hprt0 = dwc2_read_hprt0(hsotg);
2298 hprt0 &= ~HPRT0_RST;
2299 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2300 hsotg->flags.b.port_reset_change = 1;
2304 * =========================================================================
2305 * Linux HC Driver Functions
2306 * =========================================================================
2310 * Initializes the DWC_otg controller and its root hub and prepares it for host
2311 * mode operation. Activates the root port. Returns 0 on success and a negative
2312 * error code on failure.
2314 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2316 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2317 struct usb_bus *bus = hcd_to_bus(hcd);
2318 unsigned long flags;
2320 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2322 spin_lock_irqsave(&hsotg->lock, flags);
2323 hsotg->lx_state = DWC2_L0;
2324 hcd->state = HC_STATE_RUNNING;
2325 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2327 if (dwc2_is_device_mode(hsotg)) {
2328 spin_unlock_irqrestore(&hsotg->lock, flags);
2329 return 0; /* why 0 ?? */
2332 dwc2_hcd_reinit(hsotg);
2334 /* Initialize and connect root hub if one is not already attached */
2335 if (bus->root_hub) {
2336 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2337 /* Inform the HUB driver to resume */
2338 usb_hcd_resume_root_hub(hcd);
2341 spin_unlock_irqrestore(&hsotg->lock, flags);
2346 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2349 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2351 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2352 unsigned long flags;
2354 /* Turn off all host-specific interrupts */
2355 dwc2_disable_host_interrupts(hsotg);
2357 /* Wait for interrupt processing to finish */
2358 synchronize_irq(hcd->irq);
2360 spin_lock_irqsave(&hsotg->lock, flags);
2361 /* Ensure hcd is disconnected */
2362 dwc2_hcd_disconnect(hsotg);
2363 dwc2_hcd_stop(hsotg);
2364 hsotg->lx_state = DWC2_L3;
2365 hcd->state = HC_STATE_HALT;
2366 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2367 spin_unlock_irqrestore(&hsotg->lock, flags);
2369 usleep_range(1000, 3000);
2372 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2374 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2375 unsigned long flags;
2379 spin_lock_irqsave(&hsotg->lock, flags);
2381 if (hsotg->lx_state != DWC2_L0)
2384 if (!HCD_HW_ACCESSIBLE(hcd))
2387 if (!hsotg->core_params->hibernation)
2388 goto skip_power_saving;
2391 * Drive USB suspend and disable port Power
2392 * if usb bus is not suspended.
2394 if (!hsotg->bus_suspended) {
2395 hprt0 = dwc2_read_hprt0(hsotg);
2396 hprt0 |= HPRT0_SUSP;
2397 hprt0 &= ~HPRT0_PWR;
2398 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2401 /* Enter hibernation */
2402 ret = dwc2_enter_hibernation(hsotg);
2404 if (ret != -ENOTSUPP)
2406 "enter hibernation failed\n");
2407 goto skip_power_saving;
2410 /* Ask phy to be suspended */
2411 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2412 spin_unlock_irqrestore(&hsotg->lock, flags);
2413 usb_phy_set_suspend(hsotg->uphy, true);
2414 spin_lock_irqsave(&hsotg->lock, flags);
2417 /* After entering hibernation, hardware is no more accessible */
2418 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2421 hsotg->lx_state = DWC2_L2;
2423 spin_unlock_irqrestore(&hsotg->lock, flags);
2428 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2430 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2431 unsigned long flags;
2434 spin_lock_irqsave(&hsotg->lock, flags);
2436 if (hsotg->lx_state != DWC2_L2)
2439 if (!hsotg->core_params->hibernation) {
2440 hsotg->lx_state = DWC2_L0;
2445 * Set HW accessible bit before powering on the controller
2446 * since an interrupt may rise.
2448 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2451 * Enable power if not already done.
2452 * This must not be spinlocked since duration
2453 * of this call is unknown.
2455 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2456 spin_unlock_irqrestore(&hsotg->lock, flags);
2457 usb_phy_set_suspend(hsotg->uphy, false);
2458 spin_lock_irqsave(&hsotg->lock, flags);
2461 /* Exit hibernation */
2462 ret = dwc2_exit_hibernation(hsotg, true);
2463 if (ret && (ret != -ENOTSUPP))
2464 dev_err(hsotg->dev, "exit hibernation failed\n");
2466 hsotg->lx_state = DWC2_L0;
2468 spin_unlock_irqrestore(&hsotg->lock, flags);
2470 if (hsotg->bus_suspended) {
2471 spin_lock_irqsave(&hsotg->lock, flags);
2472 hsotg->flags.b.port_suspend_change = 1;
2473 spin_unlock_irqrestore(&hsotg->lock, flags);
2474 dwc2_port_resume(hsotg);
2476 /* Wait for controller to correctly update D+/D- level */
2477 usleep_range(3000, 5000);
2480 * Clear Port Enable and Port Status changes.
2481 * Enable Port Power.
2483 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
2484 HPRT0_ENACHG, hsotg->regs + HPRT0);
2485 /* Wait for controller to detect Port Connect */
2486 usleep_range(5000, 7000);
2491 spin_unlock_irqrestore(&hsotg->lock, flags);
2496 /* Returns the current frame number */
2497 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2499 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2501 return dwc2_hcd_get_frame_number(hsotg);
2504 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2507 #ifdef VERBOSE_DEBUG
2508 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2512 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2513 dev_vdbg(hsotg->dev, " Device address: %d\n",
2514 usb_pipedevice(urb->pipe));
2515 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2516 usb_pipeendpoint(urb->pipe),
2517 usb_pipein(urb->pipe) ? "IN" : "OUT");
2519 switch (usb_pipetype(urb->pipe)) {
2521 pipetype = "CONTROL";
2526 case PIPE_INTERRUPT:
2527 pipetype = "INTERRUPT";
2529 case PIPE_ISOCHRONOUS:
2530 pipetype = "ISOCHRONOUS";
2533 pipetype = "UNKNOWN";
2537 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2538 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2541 switch (urb->dev->speed) {
2542 case USB_SPEED_HIGH:
2545 case USB_SPEED_FULL:
2556 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2557 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2558 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2559 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2560 urb->transfer_buffer_length);
2561 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2562 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2563 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2564 urb->setup_packet, (unsigned long)urb->setup_dma);
2565 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2567 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2570 for (i = 0; i < urb->number_of_packets; i++) {
2571 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2572 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2573 urb->iso_frame_desc[i].offset,
2574 urb->iso_frame_desc[i].length);
2581 * Starts processing a USB transfer request specified by a USB Request Block
2582 * (URB). mem_flags indicates the type of memory allocation to use while
2583 * processing this URB.
2585 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2588 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2589 struct usb_host_endpoint *ep = urb->ep;
2590 struct dwc2_hcd_urb *dwc2_urb;
2593 int alloc_bandwidth = 0;
2597 unsigned long flags;
2599 bool qh_allocated = false;
2600 struct dwc2_qtd *qtd;
2603 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2604 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2610 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2611 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2612 spin_lock_irqsave(&hsotg->lock, flags);
2613 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2614 alloc_bandwidth = 1;
2615 spin_unlock_irqrestore(&hsotg->lock, flags);
2618 switch (usb_pipetype(urb->pipe)) {
2620 ep_type = USB_ENDPOINT_XFER_CONTROL;
2622 case PIPE_ISOCHRONOUS:
2623 ep_type = USB_ENDPOINT_XFER_ISOC;
2626 ep_type = USB_ENDPOINT_XFER_BULK;
2628 case PIPE_INTERRUPT:
2629 ep_type = USB_ENDPOINT_XFER_INT;
2632 dev_warn(hsotg->dev, "Wrong ep type\n");
2635 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2640 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2641 usb_pipeendpoint(urb->pipe), ep_type,
2642 usb_pipein(urb->pipe),
2643 usb_maxpacket(urb->dev, urb->pipe,
2644 !(usb_pipein(urb->pipe))));
2646 buf = urb->transfer_buffer;
2648 if (hcd->self.uses_dma) {
2649 if (!buf && (urb->transfer_dma & 3)) {
2651 "%s: unaligned transfer with no transfer_buffer",
2658 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2659 tflags |= URB_GIVEBACK_ASAP;
2660 if (urb->transfer_flags & URB_ZERO_PACKET)
2661 tflags |= URB_SEND_ZERO_PACKET;
2663 dwc2_urb->priv = urb;
2664 dwc2_urb->buf = buf;
2665 dwc2_urb->dma = urb->transfer_dma;
2666 dwc2_urb->length = urb->transfer_buffer_length;
2667 dwc2_urb->setup_packet = urb->setup_packet;
2668 dwc2_urb->setup_dma = urb->setup_dma;
2669 dwc2_urb->flags = tflags;
2670 dwc2_urb->interval = urb->interval;
2671 dwc2_urb->status = -EINPROGRESS;
2673 for (i = 0; i < urb->number_of_packets; ++i)
2674 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2675 urb->iso_frame_desc[i].offset,
2676 urb->iso_frame_desc[i].length);
2678 urb->hcpriv = dwc2_urb;
2679 qh = (struct dwc2_qh *) ep->hcpriv;
2680 /* Create QH for the endpoint if it doesn't exist */
2682 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2688 qh_allocated = true;
2691 qtd = kzalloc(sizeof(*qtd), mem_flags);
2697 spin_lock_irqsave(&hsotg->lock, flags);
2698 retval = usb_hcd_link_urb_to_ep(hcd, urb);
2702 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
2706 if (alloc_bandwidth) {
2707 dwc2_allocate_bus_bandwidth(hcd,
2708 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2712 spin_unlock_irqrestore(&hsotg->lock, flags);
2717 dwc2_urb->priv = NULL;
2718 usb_hcd_unlink_urb_from_ep(hcd, urb);
2720 spin_unlock_irqrestore(&hsotg->lock, flags);
2725 struct dwc2_qtd *qtd2, *qtd2_tmp;
2728 dwc2_hcd_qh_unlink(hsotg, qh);
2729 /* Free each QTD in the QH's QTD list */
2730 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2732 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2733 dwc2_hcd_qh_free(hsotg, qh);
2742 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2744 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2747 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2749 unsigned long flags;
2751 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2752 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2754 spin_lock_irqsave(&hsotg->lock, flags);
2756 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2761 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2765 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2767 usb_hcd_unlink_urb_from_ep(hcd, urb);
2772 /* Higher layer software sets URB status */
2773 spin_unlock(&hsotg->lock);
2774 usb_hcd_giveback_urb(hcd, urb, status);
2775 spin_lock(&hsotg->lock);
2777 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2778 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2780 spin_unlock_irqrestore(&hsotg->lock, flags);
2786 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2787 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2788 * must already be dequeued.
2790 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2791 struct usb_host_endpoint *ep)
2793 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2796 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2797 ep->desc.bEndpointAddress, ep->hcpriv);
2798 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2802 * Resets endpoint specific parameter values, in current version used to reset
2803 * the data toggle (as a WA). This function can be called from usb_clear_halt
2806 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2807 struct usb_host_endpoint *ep)
2809 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2810 unsigned long flags;
2813 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2814 ep->desc.bEndpointAddress);
2816 spin_lock_irqsave(&hsotg->lock, flags);
2817 dwc2_hcd_endpoint_reset(hsotg, ep);
2818 spin_unlock_irqrestore(&hsotg->lock, flags);
2822 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2823 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2826 * This function is called by the USB core when an interrupt occurs
2828 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2830 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2832 return dwc2_handle_hcd_intr(hsotg);
2836 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2837 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2838 * is the status change indicator for the single root port. Returns 1 if either
2839 * change indicator is 1, otherwise returns 0.
2841 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2843 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2845 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2849 /* Handles hub class-specific requests */
2850 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2851 u16 windex, char *buf, u16 wlength)
2853 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2854 wvalue, windex, buf, wlength);
2858 /* Handles hub TT buffer clear completions */
2859 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2860 struct usb_host_endpoint *ep)
2862 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2864 unsigned long flags;
2870 spin_lock_irqsave(&hsotg->lock, flags);
2871 qh->tt_buffer_dirty = 0;
2873 if (hsotg->flags.b.port_connect_status)
2874 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2876 spin_unlock_irqrestore(&hsotg->lock, flags);
2879 static struct hc_driver dwc2_hc_driver = {
2880 .description = "dwc2_hsotg",
2881 .product_desc = "DWC OTG Controller",
2882 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2884 .irq = _dwc2_hcd_irq,
2885 .flags = HCD_MEMORY | HCD_USB2,
2887 .start = _dwc2_hcd_start,
2888 .stop = _dwc2_hcd_stop,
2889 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2890 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2891 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2892 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2893 .get_frame_number = _dwc2_hcd_get_frame_number,
2895 .hub_status_data = _dwc2_hcd_hub_status_data,
2896 .hub_control = _dwc2_hcd_hub_control,
2897 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2899 .bus_suspend = _dwc2_hcd_suspend,
2900 .bus_resume = _dwc2_hcd_resume,
2904 * Frees secondary storage associated with the dwc2_hsotg structure contained
2905 * in the struct usb_hcd field
2907 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2913 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2915 /* Free memory for QH/QTD lists */
2916 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2917 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2918 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2919 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2920 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2921 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2923 /* Free memory for the host channels */
2924 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2925 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2928 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2930 hsotg->hc_ptr_array[i] = NULL;
2935 if (hsotg->core_params->dma_enable > 0) {
2936 if (hsotg->status_buf) {
2937 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2939 hsotg->status_buf_dma);
2940 hsotg->status_buf = NULL;
2943 kfree(hsotg->status_buf);
2944 hsotg->status_buf = NULL;
2947 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
2949 /* Disable all interrupts */
2950 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2951 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2952 dwc2_writel(0, hsotg->regs + GINTMSK);
2954 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2955 dctl = dwc2_readl(hsotg->regs + DCTL);
2956 dctl |= DCTL_SFTDISCON;
2957 dwc2_writel(dctl, hsotg->regs + DCTL);
2960 if (hsotg->wq_otg) {
2961 if (!cancel_work_sync(&hsotg->wf_otg))
2962 flush_workqueue(hsotg->wq_otg);
2963 destroy_workqueue(hsotg->wq_otg);
2966 del_timer(&hsotg->wkp_timer);
2969 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2971 /* Turn off all host-specific interrupts */
2972 dwc2_disable_host_interrupts(hsotg);
2974 dwc2_hcd_free(hsotg);
2978 * Initializes the HCD. This function allocates memory for and initializes the
2979 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2980 * USB bus with the core and calls the hc_driver->start() function. It returns
2981 * a negative error on failure.
2983 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
2985 struct usb_hcd *hcd;
2986 struct dwc2_host_chan *channel;
2988 int i, num_channels;
2994 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2998 hcfg = dwc2_readl(hsotg->regs + HCFG);
2999 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
3001 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3002 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
3003 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3004 if (!hsotg->frame_num_array)
3006 hsotg->last_frame_num_array = kzalloc(
3007 sizeof(*hsotg->last_frame_num_array) *
3008 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3009 if (!hsotg->last_frame_num_array)
3011 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
3014 /* Check if the bus driver or platform code has setup a dma_mask */
3015 if (hsotg->core_params->dma_enable > 0 &&
3016 hsotg->dev->dma_mask == NULL) {
3017 dev_warn(hsotg->dev,
3018 "dma_mask not set, disabling DMA\n");
3019 hsotg->core_params->dma_enable = 0;
3020 hsotg->core_params->dma_desc_enable = 0;
3023 /* Set device flags indicating whether the HCD supports DMA */
3024 if (hsotg->core_params->dma_enable > 0) {
3025 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3026 dev_warn(hsotg->dev, "can't set DMA mask\n");
3027 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3028 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
3031 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
3035 if (hsotg->core_params->dma_enable <= 0)
3036 hcd->self.uses_dma = 0;
3040 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
3044 * Disable the global interrupt until all the interrupt handlers are
3047 dwc2_disable_global_interrupts(hsotg);
3049 /* Initialize the DWC_otg core, and select the Phy type */
3050 retval = dwc2_core_init(hsotg, true, irq);
3054 /* Create new workqueue and init work */
3056 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
3057 if (!hsotg->wq_otg) {
3058 dev_err(hsotg->dev, "Failed to create workqueue\n");
3061 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
3063 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
3064 (unsigned long)hsotg);
3066 /* Initialize the non-periodic schedule */
3067 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
3068 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
3070 /* Initialize the periodic schedule */
3071 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
3072 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
3073 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
3074 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
3077 * Create a host channel descriptor for each host channel implemented
3078 * in the controller. Initialize the channel descriptor array.
3080 INIT_LIST_HEAD(&hsotg->free_hc_list);
3081 num_channels = hsotg->core_params->host_channels;
3082 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
3084 for (i = 0; i < num_channels; i++) {
3085 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3086 if (channel == NULL)
3088 channel->hc_num = i;
3089 hsotg->hc_ptr_array[i] = channel;
3092 if (hsotg->core_params->uframe_sched > 0)
3093 dwc2_hcd_init_usecs(hsotg);
3095 /* Initialize hsotg start work */
3096 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
3098 /* Initialize port reset work */
3099 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
3102 * Allocate space for storing data on status transactions. Normally no
3103 * data is sent, but this space acts as a bit bucket. This must be
3104 * done after usb_add_hcd since that function allocates the DMA buffer
3107 if (hsotg->core_params->dma_enable > 0)
3108 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
3109 DWC2_HCD_STATUS_BUF_SIZE,
3110 &hsotg->status_buf_dma, GFP_KERNEL);
3112 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
3115 if (!hsotg->status_buf)
3118 hsotg->otg_port = 1;
3119 hsotg->frame_list = NULL;
3120 hsotg->frame_list_dma = 0;
3121 hsotg->periodic_qh_count = 0;
3123 /* Initiate lx_state to L3 disconnected state */
3124 hsotg->lx_state = DWC2_L3;
3126 hcd->self.otg_port = hsotg->otg_port;
3128 /* Don't support SG list at this point */
3129 hcd->self.sg_tablesize = 0;
3131 if (!IS_ERR_OR_NULL(hsotg->uphy))
3132 otg_set_host(hsotg->uphy->otg, &hcd->self);
3135 * Finish generic HCD initialization and start the HCD. This function
3136 * allocates the DMA buffer pool, registers the USB bus, requests the
3137 * IRQ line, and calls hcd_start method.
3139 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
3143 device_wakeup_enable(hcd->self.controller);
3145 dwc2_hcd_dump_state(hsotg);
3147 dwc2_enable_global_interrupts(hsotg);
3152 dwc2_hcd_release(hsotg);
3156 kfree(hsotg->core_params);
3158 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3159 kfree(hsotg->last_frame_num_array);
3160 kfree(hsotg->frame_num_array);
3163 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
3169 * Frees memory and resources associated with the HCD and deregisters the bus.
3171 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
3173 struct usb_hcd *hcd;
3175 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
3177 hcd = dwc2_hsotg_to_hcd(hsotg);
3178 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
3181 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3186 if (!IS_ERR_OR_NULL(hsotg->uphy))
3187 otg_set_host(hsotg->uphy->otg, NULL);
3189 usb_remove_hcd(hcd);
3191 dwc2_hcd_release(hsotg);
3194 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3195 kfree(hsotg->last_frame_num_array);
3196 kfree(hsotg->frame_num_array);