2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
58 * dwc2_dump_channel_info() - Prints the state of a host channel
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
63 * Must be called with interrupt disabled and spinlock held
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
72 int num_channels = hsotg->core_params->host_channels;
83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
119 #endif /* VERBOSE_DEBUG */
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
126 * Must be called with interrupt disabled and spinlock held
128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
151 /* The list hasn't been initialized yet */
154 spin_lock_irqsave(&hsotg->lock, flags);
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
172 spin_unlock_irqrestore(&hsotg->lock, flags);
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
181 * Must be called with interrupt disabled and spinlock held
183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
196 * @hsotg: Pointer to struct dwc2_hsotg
198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
208 hprt0 = dwc2_read_hprt0(hsotg);
210 writel(hprt0, hsotg->regs + HPRT0);
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
217 /* Must be called with interrupt disabled and spinlock held */
218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
231 hcchar = readl(hsotg->regs + HCCHAR(i));
232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
235 writel(hcchar, hsotg->regs + HCCHAR(i));
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
244 hcchar = readl(hsotg->regs + HCCHAR(i));
245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
248 writel(hcchar, hsotg->regs + HCCHAR(i));
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
260 /* All channels have been freed, mark them available */
261 if (hsotg->core_params->uframe_sched > 0) {
262 hsotg->available_host_channels =
263 hsotg->core_params->host_channels;
265 hsotg->non_periodic_channels = 0;
266 hsotg->periodic_channels = 0;
271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
273 * @hsotg: Pointer to struct dwc2_hsotg
275 * Must be called with interrupt disabled and spinlock held
277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
281 /* Set status flags for the hub driver */
282 hsotg->flags.b.port_connect_status_change = 1;
283 hsotg->flags.b.port_connect_status = 0;
286 * Shutdown any transfers in process by clearing the Tx FIFO Empty
287 * interrupt mask and status bits and disabling subsequent host
288 * channel interrupts.
290 intr = readl(hsotg->regs + GINTMSK);
291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
292 writel(intr, hsotg->regs + GINTMSK);
293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
294 writel(intr, hsotg->regs + GINTSTS);
297 * Turn off the vbus power only if the core has transitioned to device
298 * mode. If still in host mode, need to keep power on to detect a
301 if (dwc2_is_device_mode(hsotg)) {
302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
304 writel(0, hsotg->regs + HPRT0);
307 dwc2_disable_host_interrupts(hsotg);
310 /* Respond with an error status to all URBs in the schedule */
311 dwc2_kill_all_urbs(hsotg);
313 if (dwc2_is_host_mode(hsotg))
314 /* Clean up any host channels that were in use */
315 dwc2_hcd_cleanup_channels(hsotg);
317 dwc2_host_disconnect(hsotg);
321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
323 * @hsotg: Pointer to struct dwc2_hsotg
325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
327 if (hsotg->lx_state == DWC2_L2) {
328 hsotg->flags.b.port_suspend_change = 1;
329 usb_hcd_resume_root_hub(hsotg->priv);
331 hsotg->flags.b.port_l1_change = 1;
336 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
338 * @hsotg: Pointer to struct dwc2_hsotg
340 * Must be called with interrupt disabled and spinlock held
342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
344 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
347 * The root hub should be disconnected before this function is called.
348 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
349 * and the QH lists (via ..._hcd_endpoint_disable).
352 /* Turn off all host-specific interrupts */
353 dwc2_disable_host_interrupts(hsotg);
355 /* Turn off the vbus power */
356 dev_dbg(hsotg->dev, "PortPower off\n");
357 writel(0, hsotg->regs + HPRT0);
360 /* Caller must hold driver lock */
361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
362 struct dwc2_hcd_urb *urb, void **ep_handle,
365 struct dwc2_qtd *qtd;
370 if (!hsotg->flags.b.port_connect_status) {
371 /* No longer connected */
372 dev_err(hsotg->dev, "Not connected\n");
376 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
378 /* Some configurations cannot support LS traffic on a FS root port */
379 if ((dev_speed == USB_SPEED_LOW) &&
380 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
381 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
382 u32 hprt0 = readl(hsotg->regs + HPRT0);
383 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
385 if (prtspd == HPRT0_SPD_FULL_SPEED)
389 qtd = kzalloc(sizeof(*qtd), mem_flags);
393 dwc2_hcd_qtd_init(qtd, urb);
394 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
398 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
404 intr_mask = readl(hsotg->regs + GINTMSK);
405 if (!(intr_mask & GINTSTS_SOF)) {
406 enum dwc2_transaction_type tr_type;
408 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
409 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
411 * Do not schedule SG transactions until qtd has
412 * URB_GIVEBACK_ASAP set
416 tr_type = dwc2_hcd_select_transactions(hsotg);
417 if (tr_type != DWC2_TRANSACTION_NONE)
418 dwc2_hcd_queue_transactions(hsotg, tr_type);
424 /* Must be called with interrupt disabled and spinlock held */
425 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
426 struct dwc2_hcd_urb *urb)
429 struct dwc2_qtd *urb_qtd;
433 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
439 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
445 if (urb_qtd->in_process && qh->channel) {
446 dwc2_dump_channel_info(hsotg, qh->channel);
448 /* The QTD is in process (it has been assigned to a channel) */
449 if (hsotg->flags.b.port_connect_status)
451 * If still connected (i.e. in host mode), halt the
452 * channel so it can be used for other transfers. If
453 * no longer connected, the host registers can't be
454 * written to halt the channel since the core is in
457 dwc2_hc_halt(hsotg, qh->channel,
458 DWC2_HC_XFER_URB_DEQUEUE);
462 * Free the QTD and clean up the associated QH. Leave the QH in the
463 * schedule if it has any remaining QTDs.
465 if (hsotg->core_params->dma_desc_enable <= 0) {
466 u8 in_process = urb_qtd->in_process;
468 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
470 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
472 } else if (list_empty(&qh->qtd_list)) {
473 dwc2_hcd_qh_unlink(hsotg, qh);
476 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
482 /* Must NOT be called with interrupt disabled or spinlock held */
483 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
484 struct usb_host_endpoint *ep, int retry)
486 struct dwc2_qtd *qtd, *qtd_tmp;
491 spin_lock_irqsave(&hsotg->lock, flags);
499 while (!list_empty(&qh->qtd_list) && retry--) {
502 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
507 spin_unlock_irqrestore(&hsotg->lock, flags);
508 usleep_range(20000, 40000);
509 spin_lock_irqsave(&hsotg->lock, flags);
517 dwc2_hcd_qh_unlink(hsotg, qh);
519 /* Free each QTD in the QH's QTD list */
520 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
521 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
524 spin_unlock_irqrestore(&hsotg->lock, flags);
525 dwc2_hcd_qh_free(hsotg, qh);
531 spin_unlock_irqrestore(&hsotg->lock, flags);
536 /* Must be called with interrupt disabled and spinlock held */
537 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
538 struct usb_host_endpoint *ep)
540 struct dwc2_qh *qh = ep->hcpriv;
545 qh->data_toggle = DWC2_HC_PID_DATA0;
551 * Initializes dynamic portions of the DWC_otg HCD state
553 * Must be called with interrupt disabled and spinlock held
555 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
557 struct dwc2_host_chan *chan, *chan_tmp;
561 hsotg->flags.d32 = 0;
562 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
564 if (hsotg->core_params->uframe_sched > 0) {
565 hsotg->available_host_channels =
566 hsotg->core_params->host_channels;
568 hsotg->non_periodic_channels = 0;
569 hsotg->periodic_channels = 0;
573 * Put all channels in the free channel list and clean up channel
576 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
578 list_del_init(&chan->hc_list_entry);
580 num_channels = hsotg->core_params->host_channels;
581 for (i = 0; i < num_channels; i++) {
582 chan = hsotg->hc_ptr_array[i];
583 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
584 dwc2_hc_cleanup(hsotg, chan);
587 /* Initialize the DWC core for host mode operation */
588 dwc2_core_host_init(hsotg);
591 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
592 struct dwc2_host_chan *chan,
593 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
595 int hub_addr, hub_port;
598 chan->xact_pos = qtd->isoc_split_pos;
599 chan->complete_split = qtd->complete_split;
600 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
601 chan->hub_addr = (u8)hub_addr;
602 chan->hub_port = (u8)hub_port;
605 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
606 struct dwc2_host_chan *chan,
607 struct dwc2_qtd *qtd, void *bufptr)
609 struct dwc2_hcd_urb *urb = qtd->urb;
610 struct dwc2_hcd_iso_packet_desc *frame_desc;
612 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
613 case USB_ENDPOINT_XFER_CONTROL:
614 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
616 switch (qtd->control_phase) {
617 case DWC2_CONTROL_SETUP:
618 dev_vdbg(hsotg->dev, " Control setup transaction\n");
621 chan->data_pid_start = DWC2_HC_PID_SETUP;
622 if (hsotg->core_params->dma_enable > 0)
623 chan->xfer_dma = urb->setup_dma;
625 chan->xfer_buf = urb->setup_packet;
630 case DWC2_CONTROL_DATA:
631 dev_vdbg(hsotg->dev, " Control data transaction\n");
632 chan->data_pid_start = qtd->data_toggle;
635 case DWC2_CONTROL_STATUS:
637 * Direction is opposite of data direction or IN if no
640 dev_vdbg(hsotg->dev, " Control status transaction\n");
641 if (urb->length == 0)
645 dwc2_hcd_is_pipe_out(&urb->pipe_info);
648 chan->data_pid_start = DWC2_HC_PID_DATA1;
650 if (hsotg->core_params->dma_enable > 0)
651 chan->xfer_dma = hsotg->status_buf_dma;
653 chan->xfer_buf = hsotg->status_buf;
659 case USB_ENDPOINT_XFER_BULK:
660 chan->ep_type = USB_ENDPOINT_XFER_BULK;
663 case USB_ENDPOINT_XFER_INT:
664 chan->ep_type = USB_ENDPOINT_XFER_INT;
667 case USB_ENDPOINT_XFER_ISOC:
668 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
669 if (hsotg->core_params->dma_desc_enable > 0)
672 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
673 frame_desc->status = 0;
675 if (hsotg->core_params->dma_enable > 0) {
676 chan->xfer_dma = urb->dma;
677 chan->xfer_dma += frame_desc->offset +
678 qtd->isoc_split_offset;
680 chan->xfer_buf = urb->buf;
681 chan->xfer_buf += frame_desc->offset +
682 qtd->isoc_split_offset;
685 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
687 /* For non-dword aligned buffers */
688 if (hsotg->core_params->dma_enable > 0 &&
689 (chan->xfer_dma & 0x3))
690 bufptr = (u8 *)urb->buf + frame_desc->offset +
691 qtd->isoc_split_offset;
695 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
696 if (chan->xfer_len <= 188)
697 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
699 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
707 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
708 struct dwc2_host_chan *chan,
709 struct dwc2_hcd_urb *urb, void *bufptr)
715 if (!qh->dw_align_buf) {
716 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
717 buf_size = hsotg->core_params->max_transfer_size;
719 /* 3072 = 3 max-size Isoc packets */
722 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
723 if (!qh->dw_align_buf)
725 qh->dw_align_buf_size = buf_size;
728 if (chan->xfer_len) {
729 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
733 if (usb_urb->transfer_flags &
734 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
735 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
736 hcd = dwc2_hsotg_to_hcd(hsotg);
737 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
740 memcpy(qh->dw_align_buf, bufptr,
743 dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
747 qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
748 qh->dw_align_buf, qh->dw_align_buf_size,
749 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
750 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
751 dev_err(hsotg->dev, "can't map align_buf\n");
756 chan->align_buf = qh->dw_align_buf_dma;
761 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
762 * channel and initializes the host channel to perform the transactions. The
763 * host channel is removed from the free list.
765 * @hsotg: The HCD state structure
766 * @qh: Transactions from the first QTD for this QH are selected and assigned
767 * to a free host channel
769 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
771 struct dwc2_host_chan *chan;
772 struct dwc2_hcd_urb *urb;
773 struct dwc2_qtd *qtd;
777 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
779 if (list_empty(&qh->qtd_list)) {
780 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
784 if (list_empty(&hsotg->free_hc_list)) {
785 dev_dbg(hsotg->dev, "No free channel to assign\n");
789 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
792 /* Remove host channel from free list */
793 list_del_init(&chan->hc_list_entry);
795 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
801 * Use usb_pipedevice to determine device address. This address is
802 * 0 before the SET_ADDRESS command and the correct address afterward.
804 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
805 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
806 chan->speed = qh->dev_speed;
807 chan->max_packet = dwc2_max_packet(qh->maxp);
809 chan->xfer_started = 0;
810 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
811 chan->error_state = (qtd->error_count > 0);
812 chan->halt_on_queue = 0;
813 chan->halt_pending = 0;
817 * The following values may be modified in the transfer type section
818 * below. The xfer_len value may be reduced when the transfer is
819 * started to accommodate the max widths of the XferSize and PktCnt
820 * fields in the HCTSIZn register.
823 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
827 chan->do_ping = qh->ping_state;
829 chan->data_pid_start = qh->data_toggle;
830 chan->multi_count = 1;
832 if (urb->actual_length > urb->length &&
833 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
834 urb->actual_length = urb->length;
836 if (hsotg->core_params->dma_enable > 0) {
837 chan->xfer_dma = urb->dma + urb->actual_length;
839 /* For non-dword aligned case */
840 if (hsotg->core_params->dma_desc_enable <= 0 &&
841 (chan->xfer_dma & 0x3))
842 bufptr = (u8 *)urb->buf + urb->actual_length;
844 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
847 chan->xfer_len = urb->length - urb->actual_length;
848 chan->xfer_count = 0;
850 /* Set the split attributes if required */
852 dwc2_hc_init_split(hsotg, chan, qtd, urb);
856 /* Set the transfer attributes */
857 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
859 /* Non DWORD-aligned buffer case */
861 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
862 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
864 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
866 /* Add channel back to free list */
868 chan->multi_count = 0;
869 list_add_tail(&chan->hc_list_entry,
870 &hsotg->free_hc_list);
879 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
880 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
882 * This value may be modified when the transfer is started
883 * to reflect the actual transfer length
885 chan->multi_count = dwc2_hb_mult(qh->maxp);
887 if (hsotg->core_params->dma_desc_enable > 0)
888 chan->desc_list_addr = qh->desc_list_dma;
890 dwc2_hc_init(hsotg, chan);
897 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
898 * schedule and assigns them to available host channels. Called from the HCD
899 * interrupt handler functions.
901 * @hsotg: The HCD state structure
903 * Return: The types of new transactions that were assigned to host channels
905 enum dwc2_transaction_type dwc2_hcd_select_transactions(
906 struct dwc2_hsotg *hsotg)
908 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
909 struct list_head *qh_ptr;
913 #ifdef DWC2_DEBUG_SOF
914 dev_vdbg(hsotg->dev, " Select Transactions\n");
917 /* Process entries in the periodic ready list */
918 qh_ptr = hsotg->periodic_sched_ready.next;
919 while (qh_ptr != &hsotg->periodic_sched_ready) {
920 if (list_empty(&hsotg->free_hc_list))
922 if (hsotg->core_params->uframe_sched > 0) {
923 if (hsotg->available_host_channels <= 1)
925 hsotg->available_host_channels--;
927 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
928 if (dwc2_assign_and_init_hc(hsotg, qh))
932 * Move the QH from the periodic ready schedule to the
933 * periodic assigned schedule
935 qh_ptr = qh_ptr->next;
936 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
937 ret_val = DWC2_TRANSACTION_PERIODIC;
941 * Process entries in the inactive portion of the non-periodic
942 * schedule. Some free host channels may not be used if they are
943 * reserved for periodic transfers.
945 num_channels = hsotg->core_params->host_channels;
946 qh_ptr = hsotg->non_periodic_sched_inactive.next;
947 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
948 if (hsotg->core_params->uframe_sched <= 0 &&
949 hsotg->non_periodic_channels >= num_channels -
950 hsotg->periodic_channels)
952 if (list_empty(&hsotg->free_hc_list))
954 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
955 if (hsotg->core_params->uframe_sched > 0) {
956 if (hsotg->available_host_channels < 1)
958 hsotg->available_host_channels--;
961 if (dwc2_assign_and_init_hc(hsotg, qh))
965 * Move the QH from the non-periodic inactive schedule to the
966 * non-periodic active schedule
968 qh_ptr = qh_ptr->next;
969 list_move(&qh->qh_list_entry,
970 &hsotg->non_periodic_sched_active);
972 if (ret_val == DWC2_TRANSACTION_NONE)
973 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
975 ret_val = DWC2_TRANSACTION_ALL;
977 if (hsotg->core_params->uframe_sched <= 0)
978 hsotg->non_periodic_channels++;
985 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
986 * a host channel associated with either a periodic or non-periodic transfer
988 * @hsotg: The HCD state structure
989 * @chan: Host channel descriptor associated with either a periodic or
990 * non-periodic transfer
991 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
992 * for periodic transfers or the non-periodic Tx FIFO
993 * for non-periodic transfers
995 * Return: 1 if a request is queued and more requests may be needed to
996 * complete the transfer, 0 if no more requests are required for this
997 * transfer, -1 if there is insufficient space in the Tx FIFO
999 * This function assumes that there is space available in the appropriate
1000 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
1001 * it checks whether space is available in the appropriate Tx FIFO.
1003 * Must be called with interrupt disabled and spinlock held
1005 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1006 struct dwc2_host_chan *chan,
1007 u16 fifo_dwords_avail)
1011 if (hsotg->core_params->dma_enable > 0) {
1012 if (hsotg->core_params->dma_desc_enable > 0) {
1013 if (!chan->xfer_started ||
1014 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1015 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1016 chan->qh->ping_state = 0;
1018 } else if (!chan->xfer_started) {
1019 dwc2_hc_start_transfer(hsotg, chan);
1020 chan->qh->ping_state = 0;
1022 } else if (chan->halt_pending) {
1023 /* Don't queue a request if the channel has been halted */
1024 } else if (chan->halt_on_queue) {
1025 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1026 } else if (chan->do_ping) {
1027 if (!chan->xfer_started)
1028 dwc2_hc_start_transfer(hsotg, chan);
1029 } else if (!chan->ep_is_in ||
1030 chan->data_pid_start == DWC2_HC_PID_SETUP) {
1031 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1032 if (!chan->xfer_started) {
1033 dwc2_hc_start_transfer(hsotg, chan);
1036 retval = dwc2_hc_continue_transfer(hsotg, chan);
1042 if (!chan->xfer_started) {
1043 dwc2_hc_start_transfer(hsotg, chan);
1046 retval = dwc2_hc_continue_transfer(hsotg, chan);
1054 * Processes periodic channels for the next frame and queues transactions for
1055 * these channels to the DWC_otg controller. After queueing transactions, the
1056 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1057 * to queue as Periodic Tx FIFO or request queue space becomes available.
1058 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1060 * Must be called with interrupt disabled and spinlock held
1062 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1064 struct list_head *qh_ptr;
1070 int no_queue_space = 0;
1071 int no_fifo_space = 0;
1075 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1077 tx_status = readl(hsotg->regs + HPTXSTS);
1078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1079 TXSTS_QSPCAVAIL_SHIFT;
1080 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1081 TXSTS_FSPCAVAIL_SHIFT;
1084 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1086 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1090 qh_ptr = hsotg->periodic_sched_assigned.next;
1091 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1092 tx_status = readl(hsotg->regs + HPTXSTS);
1093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1094 TXSTS_QSPCAVAIL_SHIFT;
1095 if (qspcavail == 0) {
1100 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1102 qh_ptr = qh_ptr->next;
1106 /* Make sure EP's TT buffer is clean before queueing qtds */
1107 if (qh->tt_buffer_dirty) {
1108 qh_ptr = qh_ptr->next;
1113 * Set a flag if we're queuing high-bandwidth in slave mode.
1114 * The flag prevents any halts to get into the request queue in
1115 * the middle of multiple high-bandwidth packets getting queued.
1117 if (hsotg->core_params->dma_enable <= 0 &&
1118 qh->channel->multi_count > 1)
1119 hsotg->queuing_high_bandwidth = 1;
1121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1122 TXSTS_FSPCAVAIL_SHIFT;
1123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1130 * In Slave mode, stay on the current transfer until there is
1131 * nothing more to do or the high-bandwidth request count is
1132 * reached. In DMA mode, only need to queue one request. The
1133 * controller automatically handles multiple packets for
1134 * high-bandwidth transfers.
1136 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1137 qh->channel->requests == qh->channel->multi_count) {
1138 qh_ptr = qh_ptr->next;
1140 * Move the QH from the periodic assigned schedule to
1141 * the periodic queued schedule
1143 list_move(&qh->qh_list_entry,
1144 &hsotg->periodic_sched_queued);
1146 /* done queuing high bandwidth */
1147 hsotg->queuing_high_bandwidth = 0;
1151 if (hsotg->core_params->dma_enable <= 0) {
1152 tx_status = readl(hsotg->regs + HPTXSTS);
1153 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1154 TXSTS_QSPCAVAIL_SHIFT;
1155 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1156 TXSTS_FSPCAVAIL_SHIFT;
1158 dev_vdbg(hsotg->dev,
1159 " P Tx Req Queue Space Avail (after queue): %d\n",
1161 dev_vdbg(hsotg->dev,
1162 " P Tx FIFO Space Avail (after queue): %d\n",
1166 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1167 no_queue_space || no_fifo_space) {
1169 * May need to queue more transactions as the request
1170 * queue or Tx FIFO empties. Enable the periodic Tx
1171 * FIFO empty interrupt. (Always use the half-empty
1172 * level to ensure that new requests are loaded as
1173 * soon as possible.)
1175 gintmsk = readl(hsotg->regs + GINTMSK);
1176 gintmsk |= GINTSTS_PTXFEMP;
1177 writel(gintmsk, hsotg->regs + GINTMSK);
1180 * Disable the Tx FIFO empty interrupt since there are
1181 * no more transactions that need to be queued right
1182 * now. This function is called from interrupt
1183 * handlers to queue more transactions as transfer
1186 gintmsk = readl(hsotg->regs + GINTMSK);
1187 gintmsk &= ~GINTSTS_PTXFEMP;
1188 writel(gintmsk, hsotg->regs + GINTMSK);
1194 * Processes active non-periodic channels and queues transactions for these
1195 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1196 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1197 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1198 * FIFO Empty interrupt is disabled.
1200 * Must be called with interrupt disabled and spinlock held
1202 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1204 struct list_head *orig_qh_ptr;
1211 int no_queue_space = 0;
1212 int no_fifo_space = 0;
1215 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1217 tx_status = readl(hsotg->regs + GNPTXSTS);
1218 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1219 TXSTS_QSPCAVAIL_SHIFT;
1220 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1221 TXSTS_FSPCAVAIL_SHIFT;
1222 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1224 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1228 * Keep track of the starting point. Skip over the start-of-list
1231 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1232 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1233 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1236 * Process once through the active list or until no more space is
1237 * available in the request queue or the Tx FIFO
1240 tx_status = readl(hsotg->regs + GNPTXSTS);
1241 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1242 TXSTS_QSPCAVAIL_SHIFT;
1243 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1248 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1253 /* Make sure EP's TT buffer is clean before queueing qtds */
1254 if (qh->tt_buffer_dirty)
1257 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1258 TXSTS_FSPCAVAIL_SHIFT;
1259 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1263 } else if (status < 0) {
1268 /* Advance to next QH, skipping start-of-list entry */
1269 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1270 if (hsotg->non_periodic_qh_ptr ==
1271 &hsotg->non_periodic_sched_active)
1272 hsotg->non_periodic_qh_ptr =
1273 hsotg->non_periodic_qh_ptr->next;
1274 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1276 if (hsotg->core_params->dma_enable <= 0) {
1277 tx_status = readl(hsotg->regs + GNPTXSTS);
1278 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1279 TXSTS_QSPCAVAIL_SHIFT;
1280 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1281 TXSTS_FSPCAVAIL_SHIFT;
1282 dev_vdbg(hsotg->dev,
1283 " NP Tx Req Queue Space Avail (after queue): %d\n",
1285 dev_vdbg(hsotg->dev,
1286 " NP Tx FIFO Space Avail (after queue): %d\n",
1289 if (more_to_do || no_queue_space || no_fifo_space) {
1291 * May need to queue more transactions as the request
1292 * queue or Tx FIFO empties. Enable the non-periodic
1293 * Tx FIFO empty interrupt. (Always use the half-empty
1294 * level to ensure that new requests are loaded as
1295 * soon as possible.)
1297 gintmsk = readl(hsotg->regs + GINTMSK);
1298 gintmsk |= GINTSTS_NPTXFEMP;
1299 writel(gintmsk, hsotg->regs + GINTMSK);
1302 * Disable the Tx FIFO empty interrupt since there are
1303 * no more transactions that need to be queued right
1304 * now. This function is called from interrupt
1305 * handlers to queue more transactions as transfer
1308 gintmsk = readl(hsotg->regs + GINTMSK);
1309 gintmsk &= ~GINTSTS_NPTXFEMP;
1310 writel(gintmsk, hsotg->regs + GINTMSK);
1316 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1317 * and queues transactions for these channels to the DWC_otg controller. Called
1318 * from the HCD interrupt handler functions.
1320 * @hsotg: The HCD state structure
1321 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1324 * Must be called with interrupt disabled and spinlock held
1326 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1327 enum dwc2_transaction_type tr_type)
1329 #ifdef DWC2_DEBUG_SOF
1330 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1332 /* Process host channels associated with periodic transfers */
1333 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1334 tr_type == DWC2_TRANSACTION_ALL) &&
1335 !list_empty(&hsotg->periodic_sched_assigned))
1336 dwc2_process_periodic_channels(hsotg);
1338 /* Process host channels associated with non-periodic transfers */
1339 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1340 tr_type == DWC2_TRANSACTION_ALL) {
1341 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1342 dwc2_process_non_periodic_channels(hsotg);
1345 * Ensure NP Tx FIFO empty interrupt is disabled when
1346 * there are no non-periodic transfers to process
1348 u32 gintmsk = readl(hsotg->regs + GINTMSK);
1350 gintmsk &= ~GINTSTS_NPTXFEMP;
1351 writel(gintmsk, hsotg->regs + GINTMSK);
1356 static void dwc2_conn_id_status_change(struct work_struct *work)
1358 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1363 dev_dbg(hsotg->dev, "%s()\n", __func__);
1365 gotgctl = readl(hsotg->regs + GOTGCTL);
1366 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1367 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1368 !!(gotgctl & GOTGCTL_CONID_B));
1370 /* B-Device connector (Device Mode) */
1371 if (gotgctl & GOTGCTL_CONID_B) {
1372 /* Wait for switch to device mode */
1373 dev_dbg(hsotg->dev, "connId B\n");
1374 while (!dwc2_is_device_mode(hsotg)) {
1375 dev_info(hsotg->dev,
1376 "Waiting for Peripheral Mode, Mode=%s\n",
1377 dwc2_is_host_mode(hsotg) ? "Host" :
1379 usleep_range(20000, 40000);
1385 "Connection id status change timed out\n");
1386 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1387 dwc2_core_init(hsotg, false, -1);
1388 dwc2_enable_global_interrupts(hsotg);
1389 s3c_hsotg_core_init_disconnected(hsotg, false);
1390 s3c_hsotg_core_connect(hsotg);
1392 /* A-Device connector (Host Mode) */
1393 dev_dbg(hsotg->dev, "connId A\n");
1394 while (!dwc2_is_host_mode(hsotg)) {
1395 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1396 dwc2_is_host_mode(hsotg) ?
1397 "Host" : "Peripheral");
1398 usleep_range(20000, 40000);
1404 "Connection id status change timed out\n");
1405 hsotg->op_state = OTG_STATE_A_HOST;
1407 /* Initialize the Core for Host mode */
1408 dwc2_core_init(hsotg, false, -1);
1409 dwc2_enable_global_interrupts(hsotg);
1410 dwc2_hcd_start(hsotg);
1414 static void dwc2_wakeup_detected(unsigned long data)
1416 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1419 dev_dbg(hsotg->dev, "%s()\n", __func__);
1422 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1423 * so that OPT tests pass with all PHYs.)
1425 hprt0 = dwc2_read_hprt0(hsotg);
1426 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1427 hprt0 &= ~HPRT0_RES;
1428 writel(hprt0, hsotg->regs + HPRT0);
1429 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1430 readl(hsotg->regs + HPRT0));
1432 dwc2_hcd_rem_wakeup(hsotg);
1434 /* Change to L0 state */
1435 hsotg->lx_state = DWC2_L0;
1438 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1440 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1442 return hcd->self.b_hnp_enable;
1445 /* Must NOT be called with interrupt disabled or spinlock held */
1446 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1448 unsigned long flags;
1453 dev_dbg(hsotg->dev, "%s()\n", __func__);
1455 spin_lock_irqsave(&hsotg->lock, flags);
1457 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1458 gotgctl = readl(hsotg->regs + GOTGCTL);
1459 gotgctl |= GOTGCTL_HSTSETHNPEN;
1460 writel(gotgctl, hsotg->regs + GOTGCTL);
1461 hsotg->op_state = OTG_STATE_A_SUSPEND;
1464 hprt0 = dwc2_read_hprt0(hsotg);
1465 hprt0 |= HPRT0_SUSP;
1466 writel(hprt0, hsotg->regs + HPRT0);
1468 /* Update lx_state */
1469 hsotg->lx_state = DWC2_L2;
1471 /* Suspend the Phy Clock */
1472 pcgctl = readl(hsotg->regs + PCGCTL);
1473 pcgctl |= PCGCTL_STOPPCLK;
1474 writel(pcgctl, hsotg->regs + PCGCTL);
1477 /* For HNP the bus must be suspended for at least 200ms */
1478 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1479 pcgctl = readl(hsotg->regs + PCGCTL);
1480 pcgctl &= ~PCGCTL_STOPPCLK;
1481 writel(pcgctl, hsotg->regs + PCGCTL);
1483 spin_unlock_irqrestore(&hsotg->lock, flags);
1485 usleep_range(200000, 250000);
1487 spin_unlock_irqrestore(&hsotg->lock, flags);
1491 /* Handles hub class-specific requests */
1492 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1493 u16 wvalue, u16 windex, char *buf, u16 wlength)
1495 struct usb_hub_descriptor *hub_desc;
1503 case ClearHubFeature:
1504 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1507 case C_HUB_LOCAL_POWER:
1508 case C_HUB_OVER_CURRENT:
1509 /* Nothing required here */
1515 "ClearHubFeature request %1xh unknown\n",
1520 case ClearPortFeature:
1521 if (wvalue != USB_PORT_FEAT_L1)
1522 if (!windex || windex > 1)
1525 case USB_PORT_FEAT_ENABLE:
1527 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1528 hprt0 = dwc2_read_hprt0(hsotg);
1530 writel(hprt0, hsotg->regs + HPRT0);
1533 case USB_PORT_FEAT_SUSPEND:
1535 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1536 writel(0, hsotg->regs + PCGCTL);
1537 usleep_range(20000, 40000);
1539 hprt0 = dwc2_read_hprt0(hsotg);
1541 writel(hprt0, hsotg->regs + HPRT0);
1542 hprt0 &= ~HPRT0_SUSP;
1543 msleep(USB_RESUME_TIMEOUT);
1545 hprt0 &= ~HPRT0_RES;
1546 writel(hprt0, hsotg->regs + HPRT0);
1549 case USB_PORT_FEAT_POWER:
1551 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1552 hprt0 = dwc2_read_hprt0(hsotg);
1553 hprt0 &= ~HPRT0_PWR;
1554 writel(hprt0, hsotg->regs + HPRT0);
1557 case USB_PORT_FEAT_INDICATOR:
1559 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1560 /* Port indicator not supported */
1563 case USB_PORT_FEAT_C_CONNECTION:
1565 * Clears driver's internal Connect Status Change flag
1568 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1569 hsotg->flags.b.port_connect_status_change = 0;
1572 case USB_PORT_FEAT_C_RESET:
1573 /* Clears driver's internal Port Reset Change flag */
1575 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1576 hsotg->flags.b.port_reset_change = 0;
1579 case USB_PORT_FEAT_C_ENABLE:
1581 * Clears the driver's internal Port Enable/Disable
1585 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1586 hsotg->flags.b.port_enable_change = 0;
1589 case USB_PORT_FEAT_C_SUSPEND:
1591 * Clears the driver's internal Port Suspend Change
1592 * flag, which is set when resume signaling on the host
1596 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1597 hsotg->flags.b.port_suspend_change = 0;
1600 case USB_PORT_FEAT_C_PORT_L1:
1602 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1603 hsotg->flags.b.port_l1_change = 0;
1606 case USB_PORT_FEAT_C_OVER_CURRENT:
1608 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1609 hsotg->flags.b.port_over_current_change = 0;
1615 "ClearPortFeature request %1xh unknown or unsupported\n",
1620 case GetHubDescriptor:
1621 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1622 hub_desc = (struct usb_hub_descriptor *)buf;
1623 hub_desc->bDescLength = 9;
1624 hub_desc->bDescriptorType = USB_DT_HUB;
1625 hub_desc->bNbrPorts = 1;
1626 hub_desc->wHubCharacteristics =
1627 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1628 HUB_CHAR_INDV_PORT_OCPM);
1629 hub_desc->bPwrOn2PwrGood = 1;
1630 hub_desc->bHubContrCurrent = 0;
1631 hub_desc->u.hs.DeviceRemovable[0] = 0;
1632 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1636 dev_dbg(hsotg->dev, "GetHubStatus\n");
1641 dev_vdbg(hsotg->dev,
1642 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1644 if (!windex || windex > 1)
1648 if (hsotg->flags.b.port_connect_status_change)
1649 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1650 if (hsotg->flags.b.port_enable_change)
1651 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1652 if (hsotg->flags.b.port_suspend_change)
1653 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1654 if (hsotg->flags.b.port_l1_change)
1655 port_status |= USB_PORT_STAT_C_L1 << 16;
1656 if (hsotg->flags.b.port_reset_change)
1657 port_status |= USB_PORT_STAT_C_RESET << 16;
1658 if (hsotg->flags.b.port_over_current_change) {
1659 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1660 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1663 if (!hsotg->flags.b.port_connect_status) {
1665 * The port is disconnected, which means the core is
1666 * either in device mode or it soon will be. Just
1667 * return 0's for the remainder of the port status
1668 * since the port register can't be read if the core
1669 * is in device mode.
1671 *(__le32 *)buf = cpu_to_le32(port_status);
1675 hprt0 = readl(hsotg->regs + HPRT0);
1676 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
1678 if (hprt0 & HPRT0_CONNSTS)
1679 port_status |= USB_PORT_STAT_CONNECTION;
1680 if (hprt0 & HPRT0_ENA)
1681 port_status |= USB_PORT_STAT_ENABLE;
1682 if (hprt0 & HPRT0_SUSP)
1683 port_status |= USB_PORT_STAT_SUSPEND;
1684 if (hprt0 & HPRT0_OVRCURRACT)
1685 port_status |= USB_PORT_STAT_OVERCURRENT;
1686 if (hprt0 & HPRT0_RST)
1687 port_status |= USB_PORT_STAT_RESET;
1688 if (hprt0 & HPRT0_PWR)
1689 port_status |= USB_PORT_STAT_POWER;
1691 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1692 if (speed == HPRT0_SPD_HIGH_SPEED)
1693 port_status |= USB_PORT_STAT_HIGH_SPEED;
1694 else if (speed == HPRT0_SPD_LOW_SPEED)
1695 port_status |= USB_PORT_STAT_LOW_SPEED;
1697 if (hprt0 & HPRT0_TSTCTL_MASK)
1698 port_status |= USB_PORT_STAT_TEST;
1699 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1701 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1702 *(__le32 *)buf = cpu_to_le32(port_status);
1706 dev_dbg(hsotg->dev, "SetHubFeature\n");
1707 /* No HUB features supported */
1710 case SetPortFeature:
1711 dev_dbg(hsotg->dev, "SetPortFeature\n");
1712 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1715 if (!hsotg->flags.b.port_connect_status) {
1717 * The port is disconnected, which means the core is
1718 * either in device mode or it soon will be. Just
1719 * return without doing anything since the port
1720 * register can't be written if the core is in device
1727 case USB_PORT_FEAT_SUSPEND:
1729 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1730 if (windex != hsotg->otg_port)
1732 dwc2_port_suspend(hsotg, windex);
1735 case USB_PORT_FEAT_POWER:
1737 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1738 hprt0 = dwc2_read_hprt0(hsotg);
1740 writel(hprt0, hsotg->regs + HPRT0);
1743 case USB_PORT_FEAT_RESET:
1744 hprt0 = dwc2_read_hprt0(hsotg);
1746 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1747 pcgctl = readl(hsotg->regs + PCGCTL);
1748 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1749 writel(pcgctl, hsotg->regs + PCGCTL);
1750 /* ??? Original driver does this */
1751 writel(0, hsotg->regs + PCGCTL);
1753 hprt0 = dwc2_read_hprt0(hsotg);
1754 /* Clear suspend bit if resetting from suspend state */
1755 hprt0 &= ~HPRT0_SUSP;
1758 * When B-Host the Port reset bit is set in the Start
1759 * HCD Callback function, so that the reset is started
1760 * within 1ms of the HNP success interrupt
1762 if (!dwc2_hcd_is_b_host(hsotg)) {
1763 hprt0 |= HPRT0_PWR | HPRT0_RST;
1765 "In host mode, hprt0=%08x\n", hprt0);
1766 writel(hprt0, hsotg->regs + HPRT0);
1769 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1770 usleep_range(50000, 70000);
1771 hprt0 &= ~HPRT0_RST;
1772 writel(hprt0, hsotg->regs + HPRT0);
1773 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1776 case USB_PORT_FEAT_INDICATOR:
1778 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1782 case USB_PORT_FEAT_TEST:
1783 hprt0 = dwc2_read_hprt0(hsotg);
1785 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1786 hprt0 &= ~HPRT0_TSTCTL_MASK;
1787 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
1788 writel(hprt0, hsotg->regs + HPRT0);
1794 "SetPortFeature %1xh unknown or unsupported\n",
1804 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1805 typereq, windex, wvalue);
1812 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1819 retval = (hsotg->flags.b.port_connect_status_change ||
1820 hsotg->flags.b.port_reset_change ||
1821 hsotg->flags.b.port_enable_change ||
1822 hsotg->flags.b.port_suspend_change ||
1823 hsotg->flags.b.port_over_current_change);
1827 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1828 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1829 hsotg->flags.b.port_connect_status_change);
1830 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1831 hsotg->flags.b.port_reset_change);
1832 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1833 hsotg->flags.b.port_enable_change);
1834 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1835 hsotg->flags.b.port_suspend_change);
1836 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1837 hsotg->flags.b.port_over_current_change);
1843 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1845 u32 hfnum = readl(hsotg->regs + HFNUM);
1847 #ifdef DWC2_DEBUG_SOF
1848 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1849 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1851 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1854 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1856 return hsotg->op_state == OTG_STATE_B_HOST;
1859 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1863 struct dwc2_hcd_urb *urb;
1864 u32 size = sizeof(*urb) + iso_desc_count *
1865 sizeof(struct dwc2_hcd_iso_packet_desc);
1867 urb = kzalloc(size, mem_flags);
1869 urb->packet_count = iso_desc_count;
1873 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1874 struct dwc2_hcd_urb *urb, u8 dev_addr,
1875 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1878 ep_type == USB_ENDPOINT_XFER_BULK ||
1879 ep_type == USB_ENDPOINT_XFER_CONTROL)
1880 dev_vdbg(hsotg->dev,
1881 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1882 dev_addr, ep_num, ep_dir, ep_type, mps);
1883 urb->pipe_info.dev_addr = dev_addr;
1884 urb->pipe_info.ep_num = ep_num;
1885 urb->pipe_info.pipe_type = ep_type;
1886 urb->pipe_info.pipe_dir = ep_dir;
1887 urb->pipe_info.mps = mps;
1891 * NOTE: This function will be removed once the peripheral controller code
1892 * is integrated and the driver is stable
1894 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1897 struct dwc2_host_chan *chan;
1898 struct dwc2_hcd_urb *urb;
1899 struct dwc2_qtd *qtd;
1905 num_channels = hsotg->core_params->host_channels;
1906 dev_dbg(hsotg->dev, "\n");
1908 "************************************************************\n");
1909 dev_dbg(hsotg->dev, "HCD State:\n");
1910 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1912 for (i = 0; i < num_channels; i++) {
1913 chan = hsotg->hc_ptr_array[i];
1914 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1916 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1917 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1918 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1919 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1920 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1921 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1922 chan->data_pid_start);
1923 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1924 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1925 chan->xfer_started);
1926 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1927 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1928 (unsigned long)chan->xfer_dma);
1929 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1930 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1931 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1932 chan->halt_on_queue);
1933 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1934 chan->halt_pending);
1935 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1936 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1937 dev_dbg(hsotg->dev, " complete_split: %d\n",
1938 chan->complete_split);
1939 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
1940 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
1941 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
1942 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
1943 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
1945 if (chan->xfer_started) {
1946 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1948 hfnum = readl(hsotg->regs + HFNUM);
1949 hcchar = readl(hsotg->regs + HCCHAR(i));
1950 hctsiz = readl(hsotg->regs + HCTSIZ(i));
1951 hcint = readl(hsotg->regs + HCINT(i));
1952 hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1953 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
1954 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
1955 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
1956 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
1957 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
1960 if (!(chan->xfer_started && chan->qh))
1963 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1964 if (!qtd->in_process)
1967 dev_dbg(hsotg->dev, " URB Info:\n");
1968 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
1972 " Dev: %d, EP: %d %s\n",
1973 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1974 dwc2_hcd_get_ep_num(&urb->pipe_info),
1975 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1978 " Max packet size: %d\n",
1979 dwc2_hcd_get_mps(&urb->pipe_info));
1981 " transfer_buffer: %p\n",
1984 " transfer_dma: %08lx\n",
1985 (unsigned long)urb->dma);
1987 " transfer_buffer_length: %d\n",
1989 dev_dbg(hsotg->dev, " actual_length: %d\n",
1990 urb->actual_length);
1995 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
1996 hsotg->non_periodic_channels);
1997 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
1998 hsotg->periodic_channels);
1999 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
2000 np_tx_status = readl(hsotg->regs + GNPTXSTS);
2001 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
2002 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2003 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
2004 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2005 p_tx_status = readl(hsotg->regs + HPTXSTS);
2006 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
2007 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2008 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
2009 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2010 dwc2_hcd_dump_frrem(hsotg);
2011 dwc2_dump_global_registers(hsotg);
2012 dwc2_dump_host_registers(hsotg);
2014 "************************************************************\n");
2015 dev_dbg(hsotg->dev, "\n");
2020 * NOTE: This function will be removed once the peripheral controller code
2021 * is integrated and the driver is stable
2023 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2025 #ifdef DWC2_DUMP_FRREM
2026 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2027 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2028 hsotg->frrem_samples, hsotg->frrem_accum,
2029 hsotg->frrem_samples > 0 ?
2030 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2031 dev_dbg(hsotg->dev, "\n");
2032 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2033 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2034 hsotg->hfnum_7_samples,
2035 hsotg->hfnum_7_frrem_accum,
2036 hsotg->hfnum_7_samples > 0 ?
2037 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2038 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2039 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2040 hsotg->hfnum_0_samples,
2041 hsotg->hfnum_0_frrem_accum,
2042 hsotg->hfnum_0_samples > 0 ?
2043 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2044 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2045 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2046 hsotg->hfnum_other_samples,
2047 hsotg->hfnum_other_frrem_accum,
2048 hsotg->hfnum_other_samples > 0 ?
2049 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2051 dev_dbg(hsotg->dev, "\n");
2052 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2053 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2054 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2055 hsotg->hfnum_7_samples_a > 0 ?
2056 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2057 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2058 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2059 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2060 hsotg->hfnum_0_samples_a > 0 ?
2061 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2062 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2063 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2064 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2065 hsotg->hfnum_other_samples_a > 0 ?
2066 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2068 dev_dbg(hsotg->dev, "\n");
2069 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2070 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2071 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2072 hsotg->hfnum_7_samples_b > 0 ?
2073 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2074 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2075 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2076 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2077 (hsotg->hfnum_0_samples_b > 0) ?
2078 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2079 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2080 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2081 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2082 (hsotg->hfnum_other_samples_b > 0) ?
2083 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2088 struct wrapper_priv_data {
2089 struct dwc2_hsotg *hsotg;
2092 /* Gets the dwc2_hsotg from a usb_hcd */
2093 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2095 struct wrapper_priv_data *p;
2097 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2101 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2103 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2105 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2107 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2108 _dwc2_hcd_start(hcd);
2111 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2113 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2115 hcd->self.is_b_host = 0;
2118 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2121 struct urb *urb = context;
2124 *hub_addr = urb->dev->tt->hub->devnum;
2127 *hub_port = urb->dev->ttport;
2130 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2132 struct urb *urb = context;
2134 return urb->dev->speed;
2137 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2140 struct usb_bus *bus = hcd_to_bus(hcd);
2143 bus->bandwidth_allocated += bw / urb->interval;
2144 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2145 bus->bandwidth_isoc_reqs++;
2147 bus->bandwidth_int_reqs++;
2150 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2153 struct usb_bus *bus = hcd_to_bus(hcd);
2156 bus->bandwidth_allocated -= bw / urb->interval;
2157 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2158 bus->bandwidth_isoc_reqs--;
2160 bus->bandwidth_int_reqs--;
2164 * Sets the final status of an URB and returns it to the upper layer. Any
2165 * required cleanup of the URB is performed.
2167 * Must be called with interrupt disabled and spinlock held
2169 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2176 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2181 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2185 urb = qtd->urb->priv;
2187 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2191 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2194 dev_vdbg(hsotg->dev,
2195 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2196 __func__, urb, usb_pipedevice(urb->pipe),
2197 usb_pipeendpoint(urb->pipe),
2198 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2199 urb->actual_length);
2201 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2202 for (i = 0; i < urb->number_of_packets; i++)
2203 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2204 i, urb->iso_frame_desc[i].status);
2207 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2208 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2209 for (i = 0; i < urb->number_of_packets; ++i) {
2210 urb->iso_frame_desc[i].actual_length =
2211 dwc2_hcd_urb_get_iso_desc_actual_length(
2213 urb->iso_frame_desc[i].status =
2214 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2218 urb->status = status;
2220 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2221 urb->actual_length < urb->transfer_buffer_length)
2222 urb->status = -EREMOTEIO;
2225 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2226 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2227 struct usb_host_endpoint *ep = urb->ep;
2230 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2231 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2235 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2240 spin_unlock(&hsotg->lock);
2241 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2242 spin_lock(&hsotg->lock);
2246 * Work queue function for starting the HCD when A-Cable is connected
2248 static void dwc2_hcd_start_func(struct work_struct *work)
2250 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2253 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2254 dwc2_host_start(hsotg);
2258 * Reset work queue function
2260 static void dwc2_hcd_reset_func(struct work_struct *work)
2262 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2266 dev_dbg(hsotg->dev, "USB RESET function called\n");
2267 hprt0 = dwc2_read_hprt0(hsotg);
2268 hprt0 &= ~HPRT0_RST;
2269 writel(hprt0, hsotg->regs + HPRT0);
2270 hsotg->flags.b.port_reset_change = 1;
2274 * =========================================================================
2275 * Linux HC Driver Functions
2276 * =========================================================================
2280 * Initializes the DWC_otg controller and its root hub and prepares it for host
2281 * mode operation. Activates the root port. Returns 0 on success and a negative
2282 * error code on failure.
2284 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2286 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2287 struct usb_bus *bus = hcd_to_bus(hcd);
2288 unsigned long flags;
2290 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2292 spin_lock_irqsave(&hsotg->lock, flags);
2294 hcd->state = HC_STATE_RUNNING;
2296 if (dwc2_is_device_mode(hsotg)) {
2297 spin_unlock_irqrestore(&hsotg->lock, flags);
2298 return 0; /* why 0 ?? */
2301 dwc2_hcd_reinit(hsotg);
2303 /* Initialize and connect root hub if one is not already attached */
2304 if (bus->root_hub) {
2305 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2306 /* Inform the HUB driver to resume */
2307 usb_hcd_resume_root_hub(hcd);
2310 spin_unlock_irqrestore(&hsotg->lock, flags);
2315 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2318 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2320 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2321 unsigned long flags;
2323 spin_lock_irqsave(&hsotg->lock, flags);
2324 dwc2_hcd_stop(hsotg);
2325 spin_unlock_irqrestore(&hsotg->lock, flags);
2327 usleep_range(1000, 3000);
2330 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2332 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2334 hsotg->lx_state = DWC2_L2;
2338 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2340 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2342 hsotg->lx_state = DWC2_L0;
2346 /* Returns the current frame number */
2347 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2349 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2351 return dwc2_hcd_get_frame_number(hsotg);
2354 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2357 #ifdef VERBOSE_DEBUG
2358 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2362 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2363 dev_vdbg(hsotg->dev, " Device address: %d\n",
2364 usb_pipedevice(urb->pipe));
2365 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2366 usb_pipeendpoint(urb->pipe),
2367 usb_pipein(urb->pipe) ? "IN" : "OUT");
2369 switch (usb_pipetype(urb->pipe)) {
2371 pipetype = "CONTROL";
2376 case PIPE_INTERRUPT:
2377 pipetype = "INTERRUPT";
2379 case PIPE_ISOCHRONOUS:
2380 pipetype = "ISOCHRONOUS";
2383 pipetype = "UNKNOWN";
2387 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2388 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2391 switch (urb->dev->speed) {
2392 case USB_SPEED_HIGH:
2395 case USB_SPEED_FULL:
2406 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2407 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2408 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2409 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2410 urb->transfer_buffer_length);
2411 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2412 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2413 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2414 urb->setup_packet, (unsigned long)urb->setup_dma);
2415 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2417 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2420 for (i = 0; i < urb->number_of_packets; i++) {
2421 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2422 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2423 urb->iso_frame_desc[i].offset,
2424 urb->iso_frame_desc[i].length);
2431 * Starts processing a USB transfer request specified by a USB Request Block
2432 * (URB). mem_flags indicates the type of memory allocation to use while
2433 * processing this URB.
2435 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2438 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2439 struct usb_host_endpoint *ep = urb->ep;
2440 struct dwc2_hcd_urb *dwc2_urb;
2443 int alloc_bandwidth = 0;
2447 unsigned long flags;
2450 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2451 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2457 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2458 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2459 spin_lock_irqsave(&hsotg->lock, flags);
2460 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2461 alloc_bandwidth = 1;
2462 spin_unlock_irqrestore(&hsotg->lock, flags);
2465 switch (usb_pipetype(urb->pipe)) {
2467 ep_type = USB_ENDPOINT_XFER_CONTROL;
2469 case PIPE_ISOCHRONOUS:
2470 ep_type = USB_ENDPOINT_XFER_ISOC;
2473 ep_type = USB_ENDPOINT_XFER_BULK;
2475 case PIPE_INTERRUPT:
2476 ep_type = USB_ENDPOINT_XFER_INT;
2479 dev_warn(hsotg->dev, "Wrong ep type\n");
2482 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2487 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2488 usb_pipeendpoint(urb->pipe), ep_type,
2489 usb_pipein(urb->pipe),
2490 usb_maxpacket(urb->dev, urb->pipe,
2491 !(usb_pipein(urb->pipe))));
2493 buf = urb->transfer_buffer;
2495 if (hcd->self.uses_dma) {
2496 if (!buf && (urb->transfer_dma & 3)) {
2498 "%s: unaligned transfer with no transfer_buffer",
2505 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2506 tflags |= URB_GIVEBACK_ASAP;
2507 if (urb->transfer_flags & URB_ZERO_PACKET)
2508 tflags |= URB_SEND_ZERO_PACKET;
2510 dwc2_urb->priv = urb;
2511 dwc2_urb->buf = buf;
2512 dwc2_urb->dma = urb->transfer_dma;
2513 dwc2_urb->length = urb->transfer_buffer_length;
2514 dwc2_urb->setup_packet = urb->setup_packet;
2515 dwc2_urb->setup_dma = urb->setup_dma;
2516 dwc2_urb->flags = tflags;
2517 dwc2_urb->interval = urb->interval;
2518 dwc2_urb->status = -EINPROGRESS;
2520 for (i = 0; i < urb->number_of_packets; ++i)
2521 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2522 urb->iso_frame_desc[i].offset,
2523 urb->iso_frame_desc[i].length);
2525 urb->hcpriv = dwc2_urb;
2527 spin_lock_irqsave(&hsotg->lock, flags);
2528 retval = usb_hcd_link_urb_to_ep(hcd, urb);
2532 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2536 if (alloc_bandwidth) {
2537 dwc2_allocate_bus_bandwidth(hcd,
2538 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2542 spin_unlock_irqrestore(&hsotg->lock, flags);
2547 dwc2_urb->priv = NULL;
2548 usb_hcd_unlink_urb_from_ep(hcd, urb);
2550 spin_unlock_irqrestore(&hsotg->lock, flags);
2559 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2561 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2564 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2566 unsigned long flags;
2568 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2569 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2571 spin_lock_irqsave(&hsotg->lock, flags);
2573 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2578 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2582 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2584 usb_hcd_unlink_urb_from_ep(hcd, urb);
2589 /* Higher layer software sets URB status */
2590 spin_unlock(&hsotg->lock);
2591 usb_hcd_giveback_urb(hcd, urb, status);
2592 spin_lock(&hsotg->lock);
2594 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2595 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2597 spin_unlock_irqrestore(&hsotg->lock, flags);
2603 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2604 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2605 * must already be dequeued.
2607 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2608 struct usb_host_endpoint *ep)
2610 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2613 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2614 ep->desc.bEndpointAddress, ep->hcpriv);
2615 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2619 * Resets endpoint specific parameter values, in current version used to reset
2620 * the data toggle (as a WA). This function can be called from usb_clear_halt
2623 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2624 struct usb_host_endpoint *ep)
2626 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2627 unsigned long flags;
2630 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2631 ep->desc.bEndpointAddress);
2633 spin_lock_irqsave(&hsotg->lock, flags);
2634 dwc2_hcd_endpoint_reset(hsotg, ep);
2635 spin_unlock_irqrestore(&hsotg->lock, flags);
2639 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2640 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2643 * This function is called by the USB core when an interrupt occurs
2645 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2647 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2649 return dwc2_handle_hcd_intr(hsotg);
2653 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2654 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2655 * is the status change indicator for the single root port. Returns 1 if either
2656 * change indicator is 1, otherwise returns 0.
2658 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2660 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2662 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2666 /* Handles hub class-specific requests */
2667 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2668 u16 windex, char *buf, u16 wlength)
2670 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2671 wvalue, windex, buf, wlength);
2675 /* Handles hub TT buffer clear completions */
2676 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2677 struct usb_host_endpoint *ep)
2679 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2681 unsigned long flags;
2687 spin_lock_irqsave(&hsotg->lock, flags);
2688 qh->tt_buffer_dirty = 0;
2690 if (hsotg->flags.b.port_connect_status)
2691 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2693 spin_unlock_irqrestore(&hsotg->lock, flags);
2696 static struct hc_driver dwc2_hc_driver = {
2697 .description = "dwc2_hsotg",
2698 .product_desc = "DWC OTG Controller",
2699 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2701 .irq = _dwc2_hcd_irq,
2702 .flags = HCD_MEMORY | HCD_USB2,
2704 .start = _dwc2_hcd_start,
2705 .stop = _dwc2_hcd_stop,
2706 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2707 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2708 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2709 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2710 .get_frame_number = _dwc2_hcd_get_frame_number,
2712 .hub_status_data = _dwc2_hcd_hub_status_data,
2713 .hub_control = _dwc2_hcd_hub_control,
2714 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2716 .bus_suspend = _dwc2_hcd_suspend,
2717 .bus_resume = _dwc2_hcd_resume,
2721 * Frees secondary storage associated with the dwc2_hsotg structure contained
2722 * in the struct usb_hcd field
2724 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2730 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2732 /* Free memory for QH/QTD lists */
2733 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2734 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2735 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2736 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2737 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2738 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2740 /* Free memory for the host channels */
2741 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2742 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2745 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2747 hsotg->hc_ptr_array[i] = NULL;
2752 if (hsotg->core_params->dma_enable > 0) {
2753 if (hsotg->status_buf) {
2754 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2756 hsotg->status_buf_dma);
2757 hsotg->status_buf = NULL;
2760 kfree(hsotg->status_buf);
2761 hsotg->status_buf = NULL;
2764 ahbcfg = readl(hsotg->regs + GAHBCFG);
2766 /* Disable all interrupts */
2767 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2768 writel(ahbcfg, hsotg->regs + GAHBCFG);
2769 writel(0, hsotg->regs + GINTMSK);
2771 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2772 dctl = readl(hsotg->regs + DCTL);
2773 dctl |= DCTL_SFTDISCON;
2774 writel(dctl, hsotg->regs + DCTL);
2777 if (hsotg->wq_otg) {
2778 if (!cancel_work_sync(&hsotg->wf_otg))
2779 flush_workqueue(hsotg->wq_otg);
2780 destroy_workqueue(hsotg->wq_otg);
2783 del_timer(&hsotg->wkp_timer);
2786 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2788 /* Turn off all host-specific interrupts */
2789 dwc2_disable_host_interrupts(hsotg);
2791 dwc2_hcd_free(hsotg);
2795 * Initializes the HCD. This function allocates memory for and initializes the
2796 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2797 * USB bus with the core and calls the hc_driver->start() function. It returns
2798 * a negative error on failure.
2800 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
2802 struct usb_hcd *hcd;
2803 struct dwc2_host_chan *channel;
2805 int i, num_channels;
2811 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2815 hcfg = readl(hsotg->regs + HCFG);
2816 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2818 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2819 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2820 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2821 if (!hsotg->frame_num_array)
2823 hsotg->last_frame_num_array = kzalloc(
2824 sizeof(*hsotg->last_frame_num_array) *
2825 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2826 if (!hsotg->last_frame_num_array)
2828 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2831 /* Check if the bus driver or platform code has setup a dma_mask */
2832 if (hsotg->core_params->dma_enable > 0 &&
2833 hsotg->dev->dma_mask == NULL) {
2834 dev_warn(hsotg->dev,
2835 "dma_mask not set, disabling DMA\n");
2836 hsotg->core_params->dma_enable = 0;
2837 hsotg->core_params->dma_desc_enable = 0;
2840 /* Set device flags indicating whether the HCD supports DMA */
2841 if (hsotg->core_params->dma_enable > 0) {
2842 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2843 dev_warn(hsotg->dev, "can't set DMA mask\n");
2844 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2845 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
2848 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2852 if (hsotg->core_params->dma_enable <= 0)
2853 hcd->self.uses_dma = 0;
2857 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2861 * Disable the global interrupt until all the interrupt handlers are
2864 dwc2_disable_global_interrupts(hsotg);
2866 /* Initialize the DWC_otg core, and select the Phy type */
2867 retval = dwc2_core_init(hsotg, true, irq);
2871 /* Create new workqueue and init work */
2873 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2874 if (!hsotg->wq_otg) {
2875 dev_err(hsotg->dev, "Failed to create workqueue\n");
2878 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2880 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2881 (unsigned long)hsotg);
2883 /* Initialize the non-periodic schedule */
2884 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2885 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2887 /* Initialize the periodic schedule */
2888 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2889 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2890 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2891 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2894 * Create a host channel descriptor for each host channel implemented
2895 * in the controller. Initialize the channel descriptor array.
2897 INIT_LIST_HEAD(&hsotg->free_hc_list);
2898 num_channels = hsotg->core_params->host_channels;
2899 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2901 for (i = 0; i < num_channels; i++) {
2902 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2903 if (channel == NULL)
2905 channel->hc_num = i;
2906 hsotg->hc_ptr_array[i] = channel;
2909 if (hsotg->core_params->uframe_sched > 0)
2910 dwc2_hcd_init_usecs(hsotg);
2912 /* Initialize hsotg start work */
2913 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2915 /* Initialize port reset work */
2916 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2919 * Allocate space for storing data on status transactions. Normally no
2920 * data is sent, but this space acts as a bit bucket. This must be
2921 * done after usb_add_hcd since that function allocates the DMA buffer
2924 if (hsotg->core_params->dma_enable > 0)
2925 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2926 DWC2_HCD_STATUS_BUF_SIZE,
2927 &hsotg->status_buf_dma, GFP_KERNEL);
2929 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2932 if (!hsotg->status_buf)
2935 hsotg->otg_port = 1;
2936 hsotg->frame_list = NULL;
2937 hsotg->frame_list_dma = 0;
2938 hsotg->periodic_qh_count = 0;
2940 /* Initiate lx_state to L3 disconnected state */
2941 hsotg->lx_state = DWC2_L3;
2943 hcd->self.otg_port = hsotg->otg_port;
2945 /* Don't support SG list at this point */
2946 hcd->self.sg_tablesize = 0;
2948 if (!IS_ERR_OR_NULL(hsotg->uphy))
2949 otg_set_host(hsotg->uphy->otg, &hcd->self);
2952 * Finish generic HCD initialization and start the HCD. This function
2953 * allocates the DMA buffer pool, registers the USB bus, requests the
2954 * IRQ line, and calls hcd_start method.
2956 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
2960 device_wakeup_enable(hcd->self.controller);
2962 dwc2_hcd_dump_state(hsotg);
2964 dwc2_enable_global_interrupts(hsotg);
2969 dwc2_hcd_release(hsotg);
2973 kfree(hsotg->core_params);
2975 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2976 kfree(hsotg->last_frame_num_array);
2977 kfree(hsotg->frame_num_array);
2980 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2986 * Frees memory and resources associated with the HCD and deregisters the bus.
2988 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2990 struct usb_hcd *hcd;
2992 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2994 hcd = dwc2_hsotg_to_hcd(hsotg);
2995 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2998 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3003 if (!IS_ERR_OR_NULL(hsotg->uphy))
3004 otg_set_host(hsotg->uphy->otg, NULL);
3006 usb_remove_hcd(hcd);
3008 dwc2_hcd_release(hsotg);
3011 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3012 kfree(hsotg->last_frame_num_array);
3013 kfree(hsotg->frame_num_array);