2 * hcd.h - DesignWare HS OTG Controller host-mode declarations
4 * Copyright (C) 2004-2013 Synopsys, Inc.
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36 #ifndef __DWC2_HCD_H__
37 #define __DWC2_HCD_H__
40 * This file contains the structures, constants, and interfaces for the
41 * Host Contoller Driver (HCD)
43 * The Host Controller Driver (HCD) is responsible for translating requests
44 * from the USB Driver into the appropriate actions on the DWC_otg controller.
45 * It isolates the USBD from the specifics of the controller by providing an
52 * struct dwc2_host_chan - Software host channel descriptor
54 * @hc_num: Host channel number, used for register address lookup
55 * @dev_addr: Address of the device
56 * @ep_num: Endpoint of the device
57 * @ep_is_in: Endpoint direction
58 * @speed: Device speed. One of the following values:
62 * @ep_type: Endpoint type. One of the following values:
63 * - USB_ENDPOINT_XFER_CONTROL: 0
64 * - USB_ENDPOINT_XFER_ISOC: 1
65 * - USB_ENDPOINT_XFER_BULK: 2
66 * - USB_ENDPOINT_XFER_INTR: 3
67 * @max_packet: Max packet size in bytes
68 * @data_pid_start: PID for initial transaction.
72 * 3: MDATA (non-Control EP),
74 * @multi_count: Number of additional periodic transactions per
76 * @xfer_buf: Pointer to current transfer buffer position
77 * @xfer_dma: DMA address of xfer_buf
78 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not
80 * @xfer_len: Total number of bytes to transfer
81 * @xfer_count: Number of bytes transferred so far
82 * @start_pkt_count: Packet count at start of transfer
83 * @xfer_started: True if the transfer has been started
84 * @ping: True if a PING request should be issued on this channel
85 * @error_state: True if the error count for this transaction is non-zero
86 * @halt_on_queue: True if this channel should be halted the next time a
87 * request is queued for the channel. This is necessary in
88 * slave mode if no request queue space is available when
89 * an attempt is made to halt the channel.
90 * @halt_pending: True if the host channel has been halted, but the core
91 * is not finished flushing queued requests
92 * @do_split: Enable split for the channel
93 * @complete_split: Enable complete split
94 * @hub_addr: Address of high speed hub for the split
95 * @hub_port: Port of the low/full speed device for the split
96 * @xact_pos: Split transaction position. One of the following values:
97 * - DWC2_HCSPLT_XACTPOS_MID
98 * - DWC2_HCSPLT_XACTPOS_BEGIN
99 * - DWC2_HCSPLT_XACTPOS_END
100 * - DWC2_HCSPLT_XACTPOS_ALL
101 * @requests: Number of requests issued for this channel since it was
102 * assigned to the current transfer (not counting PINGs)
103 * @schinfo: Scheduling micro-frame bitmap
104 * @ntd: Number of transfer descriptors for the transfer
105 * @halt_status: Reason for halting the host channel
106 * @hcint Contents of the HCINT register when the interrupt came
107 * @qh: QH for the transfer being processed by this channel
108 * @hc_list_entry: For linking to list of host channels
109 * @desc_list_addr: Current QH's descriptor list DMA address
110 * @desc_list_sz: Current QH's descriptor list size
112 * This structure represents the state of a single host channel when acting in
113 * host mode. It contains the data items needed to transfer packets to an
114 * endpoint via a host channel.
116 struct dwc2_host_chan {
124 unsigned max_packet:11;
125 unsigned data_pid_start:2;
126 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0
127 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2
128 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1
129 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA
130 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP
132 unsigned multi_count:2;
136 dma_addr_t align_buf;
150 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID
151 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END
152 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
153 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL
158 enum dwc2_halt_status halt_status;
161 struct list_head hc_list_entry;
162 dma_addr_t desc_list_addr;
166 struct dwc2_hcd_pipe_info {
174 struct dwc2_hcd_iso_packet_desc {
183 struct dwc2_hcd_urb {
185 struct dwc2_qtd *qtd;
189 dma_addr_t setup_dma;
197 struct dwc2_hcd_pipe_info pipe_info;
198 struct dwc2_hcd_iso_packet_desc iso_descs[0];
201 /* Phases for control transfers */
202 enum dwc2_control_phase {
208 /* Transaction types */
209 enum dwc2_transaction_type {
210 DWC2_TRANSACTION_NONE,
211 DWC2_TRANSACTION_PERIODIC,
212 DWC2_TRANSACTION_NON_PERIODIC,
213 DWC2_TRANSACTION_ALL,
217 * struct dwc2_qh - Software queue head structure
219 * @ep_type: Endpoint type. One of the following values:
220 * - USB_ENDPOINT_XFER_CONTROL
221 * - USB_ENDPOINT_XFER_BULK
222 * - USB_ENDPOINT_XFER_INT
223 * - USB_ENDPOINT_XFER_ISOC
224 * @ep_is_in: Endpoint direction
225 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor
226 * @dev_speed: Device speed. One of the following values:
230 * @data_toggle: Determines the PID of the next data packet for
231 * non-controltransfers. Ignored for control transfers.
232 * One of the following values:
233 * - DWC2_HC_PID_DATA0
234 * - DWC2_HC_PID_DATA1
235 * @ping_state: Ping state
236 * @do_split: Full/low speed endpoint on high-speed hub requires split
237 * @td_first: Index of first activated isochronous transfer descriptor
238 * @td_last: Index of last activated isochronous transfer descriptor
239 * @usecs: Bandwidth in microseconds per (micro)frame
240 * @interval: Interval between transfers in (micro)frames
241 * @sched_frame: (Micro)frame to initialize a periodic transfer.
242 * The transfer executes in the following (micro)frame.
243 * @frame_usecs: Internal variable used by the microframe scheduler
244 * @start_split_frame: (Micro)frame at which last start split was initialized
245 * @ntd: Actual number of transfer descriptors in a list
246 * @dw_align_buf: Used instead of original buffer if its physical address
247 * is not dword-aligned
248 * @dw_align_buf_size: Size of dw_align_buf
249 * @dw_align_buf_dma: DMA address for dw_align_buf
250 * @qtd_list: List of QTDs for this QH
251 * @channel: Host channel currently processing transfers for this QH
252 * @qh_list_entry: Entry for QH in either the periodic or non-periodic
254 * @desc_list: List of transfer descriptors
255 * @desc_list_dma: Physical address of desc_list
256 * @desc_list_sz: Size of descriptors list
257 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer
258 * descriptor and indicates original XferSize value for the
260 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending
262 * A Queue Head (QH) holds the static characteristics of an endpoint and
263 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
264 * be entered in either the non-periodic or periodic schedule.
280 u16 start_split_frame;
283 int dw_align_buf_size;
284 dma_addr_t dw_align_buf_dma;
285 struct list_head qtd_list;
286 struct dwc2_host_chan *channel;
287 struct list_head qh_list_entry;
288 struct dwc2_hcd_dma_desc *desc_list;
289 dma_addr_t desc_list_dma;
292 unsigned tt_buffer_dirty:1;
296 * struct dwc2_qtd - Software queue transfer descriptor (QTD)
298 * @control_phase: Current phase for control transfers (Setup, Data, or
300 * @in_process: Indicates if this QTD is currently processed by HW
301 * @data_toggle: Determines the PID of the next data packet for the
302 * data phase of control transfers. Ignored for other
303 * transfer types. One of the following values:
304 * - DWC2_HC_PID_DATA0
305 * - DWC2_HC_PID_DATA1
306 * @complete_split: Keeps track of the current split type for FS/LS
307 * endpoints on a HS Hub
308 * @isoc_split_pos: Position of the ISOC split in full/low speed
309 * @isoc_frame_index: Index of the next frame descriptor for an isochronous
310 * transfer. A frame descriptor describes the buffer
311 * position and length of the data to be transferred in the
312 * next scheduled (micro)frame of an isochronous transfer.
313 * It also holds status for that transaction. The frame
315 * @isoc_split_offset: Position of the ISOC split in the buffer for the
317 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
318 * @error_count: Holds the number of bus errors that have occurred for
319 * a transaction within this transfer
320 * @n_desc: Number of DMA descriptors for this QTD
321 * @isoc_frame_index_last: Last activated frame (packet) index, used in
322 * descriptor DMA mode only
323 * @urb: URB for this transfer
324 * @qh: Queue head for this QTD
325 * @qtd_list_entry: For linking to the QH's list of QTDs
327 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
328 * interrupt, or isochronous transfer. A single QTD is created for each URB
329 * (of one of these types) submitted to the HCD. The transfer associated with
330 * a QTD may require one or multiple transactions.
332 * A QTD is linked to a Queue Head, which is entered in either the
333 * non-periodic or periodic schedule for execution. When a QTD is chosen for
334 * execution, some or all of its transactions may be executed. After
335 * execution, the state of the QTD is updated. The QTD may be retired if all
336 * its transactions are complete or if an error occurred. Otherwise, it
337 * remains in the schedule so more transactions can be executed later.
340 enum dwc2_control_phase control_phase;
345 u16 isoc_frame_index;
346 u16 isoc_split_offset;
349 u32 ssplit_out_xfer_count;
352 u16 isoc_frame_index_last;
353 struct dwc2_hcd_urb *urb;
355 struct list_head qtd_list_entry;
359 struct hc_xfer_info {
360 struct dwc2_hsotg *hsotg;
361 struct dwc2_host_chan *chan;
365 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
366 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
368 return (struct usb_hcd *)hsotg->priv;
372 * Inline used to disable one channel interrupt. Channel interrupts are
373 * disabled when the channel is halted or released by the interrupt handler.
374 * There is no need to handle further interrupts of that type until the
375 * channel is re-assigned. In fact, subsequent handling may cause crashes
376 * because the channel structures are cleaned up when the channel is released.
378 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
380 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
383 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum));
387 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
388 * are read as 1, they won't clear when written back.
390 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
392 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
394 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
398 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
403 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
405 return pipe->pipe_type;
408 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe)
413 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
415 return pipe->dev_addr;
418 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
420 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
423 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
425 return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
428 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
430 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
433 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
435 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
438 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
440 return pipe->pipe_dir == USB_DIR_IN;
443 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
445 return !dwc2_hcd_is_pipe_in(pipe);
448 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq);
449 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
451 /* Transaction Execution Functions */
452 extern enum dwc2_transaction_type dwc2_hcd_select_transactions(
453 struct dwc2_hsotg *hsotg);
454 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
455 enum dwc2_transaction_type tr_type);
457 /* Schedule Queue Functions */
458 /* Implemented in hcd_queue.c */
459 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg);
460 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
461 struct dwc2_hcd_urb *urb,
463 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
464 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
465 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
466 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
469 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
470 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
473 /* Unlinks and frees a QTD */
474 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
475 struct dwc2_qtd *qtd,
478 list_del(&qtd->qtd_list_entry);
482 /* Descriptor DMA support functions */
483 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
485 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
486 struct dwc2_host_chan *chan, int chnum,
487 enum dwc2_halt_status halt_status);
489 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
491 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
493 /* Check if QH is non-periodic */
494 #define dwc2_qh_is_non_per(_qh_ptr_) \
495 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
496 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
498 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
499 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
500 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
501 static inline bool dbg_urb(struct urb *urb) { return true; }
502 static inline bool dbg_perio(void) { return true; }
503 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
504 static inline bool dbg_hc(struct dwc2_host_chan *hc)
506 return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
507 hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
510 static inline bool dbg_qh(struct dwc2_qh *qh)
512 return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
513 qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
516 static inline bool dbg_urb(struct urb *urb)
518 return usb_pipetype(urb->pipe) == PIPE_BULK ||
519 usb_pipetype(urb->pipe) == PIPE_CONTROL;
522 static inline bool dbg_perio(void) { return false; }
525 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */
526 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03))
528 /* Packet size for any kind of endpoint descriptor */
529 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff)
532 * Returns true if frame1 index is greater than frame2 index. The comparison
533 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
534 * frame number when the max index frame number is reached.
536 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
538 u16 diff = fr_idx1 - fr_idx2;
539 u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
541 return diff && !sign;
545 * Returns true if frame1 is less than or equal to frame2. The comparison is
546 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
547 * frame number when the max frame number is reached.
549 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
551 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
555 * Returns true if frame1 is greater than frame2. The comparison is done
556 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
557 * number when the max frame number is reached.
559 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
561 return (frame1 != frame2) &&
562 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
566 * Increments frame by the amount specified by inc. The addition is done
567 * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
569 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
571 return (frame + inc) & HFNUM_MAX_FRNUM;
574 static inline u16 dwc2_full_frame_num(u16 frame)
576 return (frame & HFNUM_MAX_FRNUM) >> 3;
579 static inline u16 dwc2_micro_frame_num(u16 frame)
585 * Returns the Core Interrupt Status register contents, ANDed with the Core
586 * Interrupt Mask register contents
588 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
590 return dwc2_readl(hsotg->regs + GINTSTS) &
591 dwc2_readl(hsotg->regs + GINTMSK);
594 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
596 return dwc2_urb->status;
599 static inline u32 dwc2_hcd_urb_get_actual_length(
600 struct dwc2_hcd_urb *dwc2_urb)
602 return dwc2_urb->actual_length;
605 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
607 return dwc2_urb->error_count;
610 static inline void dwc2_hcd_urb_set_iso_desc_params(
611 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
614 dwc2_urb->iso_descs[desc_num].offset = offset;
615 dwc2_urb->iso_descs[desc_num].length = length;
618 static inline u32 dwc2_hcd_urb_get_iso_desc_status(
619 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
621 return dwc2_urb->iso_descs[desc_num].status;
624 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
625 struct dwc2_hcd_urb *dwc2_urb, int desc_num)
627 return dwc2_urb->iso_descs[desc_num].actual_length;
630 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
631 struct usb_host_endpoint *ep)
633 struct dwc2_qh *qh = ep->hcpriv;
635 if (qh && !list_empty(&qh->qh_list_entry))
641 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
642 struct usb_host_endpoint *ep)
644 struct dwc2_qh *qh = ep->hcpriv;
654 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
655 struct dwc2_host_chan *chan, int chnum,
656 struct dwc2_qtd *qtd);
661 * dwc2_handle_hcd_intr() - Called on every hardware interrupt
663 * @hsotg: The DWC2 HCD
665 * Returns IRQ_HANDLED if interrupt is handled
666 * Return IRQ_NONE if interrupt is not handled
668 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
671 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
673 * @hsotg: The DWC2 HCD
675 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
678 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
681 * @hsotg: The DWC2 HCD
683 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
686 * dwc2_hcd_dump_state() - Dumps hsotg state
688 * @hsotg: The DWC2 HCD
690 * NOTE: This function will be removed once the peripheral controller code
691 * is integrated and the driver is stable
693 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
696 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF
698 * @hsotg: The DWC2 HCD
700 * This can be used to determine average interrupt latency. Frame remaining is
701 * also shown for start transfer and two additional sample points.
703 * NOTE: This function will be removed once the peripheral controller code
704 * is integrated and the driver is stable
706 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg);
711 #define URB_GIVEBACK_ASAP 0x1
712 #define URB_SEND_ZERO_PACKET 0x2
714 /* Host driver callbacks */
716 extern void dwc2_host_start(struct dwc2_hsotg *hsotg);
717 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg);
718 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
719 int *hub_addr, int *hub_port);
720 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
721 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
726 * Macro to sample the remaining PHY clocks left in the current frame. This
727 * may be used during debugging to determine the average time it takes to
728 * execute sections of code. There are two possible sample points, "a" and
729 * "b", so the _letter_ argument must be one of these values.
731 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
732 * example, "cat /sys/devices/lm0/hcd_frrem".
734 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \
736 struct hfnum_data _hfnum_; \
737 struct dwc2_qtd *_qtd_; \
739 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \
741 if (usb_pipeint(_qtd_->urb->pipe) && \
742 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \
743 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \
744 switch (_hfnum_.b.frnum & 0x7) { \
746 (_hcd_)->hfnum_7_samples_##_letter_++; \
747 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \
751 (_hcd_)->hfnum_0_samples_##_letter_++; \
752 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \
756 (_hcd_)->hfnum_other_samples_##_letter_++; \
757 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \
764 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0)
767 #endif /* __DWC2_HCD_H__ */