drivers/usb/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  59         u16 curr_frame_number = hsotg->frame_number;
  60
  61         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  62                 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
  63                     curr_frame_number) {
  64                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  65                                         curr_frame_number;
  66                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  67                                         hsotg->last_frame_num;
  68                         hsotg->frame_num_idx++;
  69                 }
  70         } else if (!hsotg->dumped_frame_num_array) {
  71                 int i;
  72
  73                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  74                 dev_info(hsotg->dev, "-----     ----------\n");
  75                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  76                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  77                                  hsotg->frame_num_array[i],
  78                                  hsotg->last_frame_num_array[i]);
  79                 }
  80                 hsotg->dumped_frame_num_array = 1;
  81         }
  82         hsotg->last_frame_num = curr_frame_number;
  83 #endif
  84 }
  85
  86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  87                                     struct dwc2_host_chan *chan,
  88                                     struct dwc2_qtd *qtd)
  89 {
  90         struct urb *usb_urb;
  91
  92         if (!chan->qh)
  93                 return;
  94
  95         if (chan->qh->dev_speed == USB_SPEED_HIGH)
  96                 return;
  97
  98         if (!qtd->urb)
  99                 return;
 100
 101         usb_urb = qtd->urb->priv;
 102         if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 103                 return;
 104
 105         if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 106                 chan->qh->tt_buffer_dirty = 1;
 107                 if (usb_hub_clear_tt_buffer(usb_urb))
 108                         /* Clear failed; let's hope things work anyway */
 109                         chan->qh->tt_buffer_dirty = 0;
 110         }
 111 }
 112
 113 /*
 114  * Handles the start-of-frame interrupt in host mode. Non-periodic
 115  * transactions may be queued to the DWC_otg controller for the current
 116  * (micro)frame. Periodic transactions may be queued to the controller
 117  * for the next (micro)frame.
 118  */
 119 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 120 {
 121         struct list_head *qh_entry;
 122         struct dwc2_qh *qh;
 123         enum dwc2_transaction_type tr_type;
 124
 125 #ifdef DEBUG_SOF
 126         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 127 #endif
 128
 129         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 130
 131         dwc2_track_missed_sofs(hsotg);
 132
 133         /* Determine whether any periodic QHs should be executed */
 134         qh_entry = hsotg->periodic_sched_inactive.next;
 135         while (qh_entry != &hsotg->periodic_sched_inactive) {
 136                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 137                 qh_entry = qh_entry->next;
 138                 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
 139                         /*
 140                          * Move QH to the ready list to be executed next
 141                          * (micro)frame
 142                          */
 143                         list_move(&qh->qh_list_entry,
 144                                   &hsotg->periodic_sched_ready);
 145         }
 146         tr_type = dwc2_hcd_select_transactions(hsotg);
 147         if (tr_type != DWC2_TRANSACTION_NONE)
 148                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 149
 150         /* Clear interrupt */
 151         dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 152 }
 153
 154 /*
 155  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 156  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 157  * memory if the DWC_otg controller is operating in Slave mode.
 158  */
 159 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 160 {
 161         u32 grxsts, chnum, bcnt, dpid, pktsts;
 162         struct dwc2_host_chan *chan;
 163
 164         if (dbg_perio())
 165                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 166
 167         grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
 168         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 169         chan = hsotg->hc_ptr_array[chnum];
 170         if (!chan) {
 171                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 172                 return;
 173         }
 174
 175         bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 176         dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 177         pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 178
 179         /* Packet Status */
 180         if (dbg_perio()) {
 181                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 182                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 183                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 184                          chan->data_pid_start);
 185                 dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 186         }
 187
 188         switch (pktsts) {
 189         case GRXSTS_PKTSTS_HCHIN:
 190                 /* Read the data into the host buffer */
 191                 if (bcnt > 0) {
 192                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 193
 194                         /* Update the HC fields for the next packet received */
 195                         chan->xfer_count += bcnt;
 196                         chan->xfer_buf += bcnt;
 197                 }
 198                 break;
 199         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 200         case GRXSTS_PKTSTS_DATATOGGLEERR:
 201         case GRXSTS_PKTSTS_HCHHALTED:
 202                 /* Handled in interrupt, just ignore data */
 203                 break;
 204         default:
 205                 dev_err(hsotg->dev,
 206                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 207                 break;
 208         }
 209 }
 210
 211 /*
 212  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 213  * data packets may be written to the FIFO for OUT transfers. More requests
 214  * may be written to the non-periodic request queue for IN transfers. This
 215  * interrupt is enabled only in Slave mode.
 216  */
 217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 218 {
 219         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 220         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 221 }
 222
 223 /*
 224  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 225  * packets may be written to the FIFO for OUT transfers. More requests may be
 226  * written to the periodic request queue for IN transfers. This interrupt is
 227  * enabled only in Slave mode.
 228  */
 229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 230 {
 231         if (dbg_perio())
 232                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 233         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 234 }
 235
 236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 237                               u32 *hprt0_modify)
 238 {
 239         struct dwc2_core_params *params = hsotg->core_params;
 240         int do_reset = 0;
 241         u32 usbcfg;
 242         u32 prtspd;
 243         u32 hcfg;
 244         u32 fslspclksel;
 245         u32 hfir;
 246
 247         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 248
 249         /* Every time when port enables calculate HFIR.FrInterval */
 250         hfir = dwc2_readl(hsotg->regs + HFIR);
 251         hfir &= ~HFIR_FRINT_MASK;
 252         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 253                 HFIR_FRINT_MASK;
 254         dwc2_writel(hfir, hsotg->regs + HFIR);
 255
 256         /* Check if we need to adjust the PHY clock speed for low power */
 257         if (!params->host_support_fs_ls_low_power) {
 258                 /* Port has been enabled, set the reset change flag */
 259                 hsotg->flags.b.port_reset_change = 1;
 260                 return;
 261         }
 262
 263         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 264         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 265
 266         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 267                 /* Low power */
 268                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 269                         /* Set PHY low power clock select for FS/LS devices */
 270                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 271                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 272                         do_reset = 1;
 273                 }
 274
 275                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 276                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 277                               HCFG_FSLSPCLKSEL_SHIFT;
 278
 279                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 280                     params->host_ls_low_power_phy_clk ==
 281                     DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 282                         /* 6 MHZ */
 283                         dev_vdbg(hsotg->dev,
 284                                  "FS_PHY programming HCFG to 6 MHz\n");
 285                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 286                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 287                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 288                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 289                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 290                                 do_reset = 1;
 291                         }
 292                 } else {
 293                         /* 48 MHZ */
 294                         dev_vdbg(hsotg->dev,
 295                                  "FS_PHY programming HCFG to 48 MHz\n");
 296                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 297                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 298                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 299                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 300                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 301                                 do_reset = 1;
 302                         }
 303                 }
 304         } else {
 305                 /* Not low power */
 306                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 307                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 308                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 309                         do_reset = 1;
 310                 }
 311         }
 312
 313         if (do_reset) {
 314                 *hprt0_modify |= HPRT0_RST;
 315                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 316                                    msecs_to_jiffies(60));
 317         } else {
 318                 /* Port has been enabled, set the reset change flag */
 319                 hsotg->flags.b.port_reset_change = 1;
 320         }
 321 }
 322
 323 /*
 324  * There are multiple conditions that can cause a port interrupt. This function
 325  * determines which interrupt conditions have occurred and handles them
 326  * appropriately.
 327  */
 328 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 329 {
 330         u32 hprt0;
 331         u32 hprt0_modify;
 332
 333         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 334
 335         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 336         hprt0_modify = hprt0;
 337
 338         /*
 339          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 340          * GINTSTS
 341          */
 342         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 343                           HPRT0_OVRCURRCHG);
 344
 345         /*
 346          * Port Connect Detected
 347          * Set flag and clear if detected
 348          */
 349         if (hprt0 & HPRT0_CONNDET) {
 350                 dev_vdbg(hsotg->dev,
 351                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 352                          hprt0);
 353                 if (hsotg->lx_state != DWC2_L0)
 354                         usb_hcd_resume_root_hub(hsotg->priv);
 355
 356                 hsotg->flags.b.port_connect_status_change = 1;
 357                 hsotg->flags.b.port_connect_status = 1;
 358                 hprt0_modify |= HPRT0_CONNDET;
 359
 360                 /*
 361                  * The Hub driver asserts a reset when it sees port connect
 362                  * status change flag
 363                  */
 364         }
 365
 366         /*
 367          * Port Enable Changed
 368          * Clear if detected - Set internal flag if disabled
 369          */
 370         if (hprt0 & HPRT0_ENACHG) {
 371                 dev_vdbg(hsotg->dev,
 372                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 373                          hprt0, !!(hprt0 & HPRT0_ENA));
 374                 hprt0_modify |= HPRT0_ENACHG;
 375                 if (hprt0 & HPRT0_ENA) {
 376                         hsotg->new_connection = true;
 377                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 378                 } else {
 379                         hsotg->flags.b.port_enable_change = 1;
 380                         if (hsotg->core_params->dma_desc_fs_enable) {
 381                                 u32 hcfg;
 382
 383                                 hsotg->core_params->dma_desc_enable = 0;
 384                                 hsotg->new_connection = false;
 385                                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 386                                 hcfg &= ~HCFG_DESCDMA;
 387                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 388                         }
 389                 }
 390         }
 391
 392         /* Overcurrent Change Interrupt */
 393         if (hprt0 & HPRT0_OVRCURRCHG) {
 394                 dev_vdbg(hsotg->dev,
 395                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 396                          hprt0);
 397                 hsotg->flags.b.port_over_current_change = 1;
 398                 hprt0_modify |= HPRT0_OVRCURRCHG;
 399         }
 400
 401         /* Clear Port Interrupts */
 402         dwc2_writel(hprt0_modify, hsotg->regs + HPRT0);
 403 }
 404
 405 /*
 406  * Gets the actual length of a transfer after the transfer halts. halt_status
 407  * holds the reason for the halt.
 408  *
 409  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 410  * is set to 1 upon return if less than the requested number of bytes were
 411  * transferred. short_read may also be NULL on entry, in which case it remains
 412  * unchanged.
 413  */
 414 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 415                                        struct dwc2_host_chan *chan, int chnum,
 416                                        struct dwc2_qtd *qtd,
 417                                        enum dwc2_halt_status halt_status,
 418                                        int *short_read)
 419 {
 420         u32 hctsiz, count, length;
 421
 422         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 423
 424         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 425                 if (chan->ep_is_in) {
 426                         count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 427                                 TSIZ_XFERSIZE_SHIFT;
 428                         length = chan->xfer_len - count;
 429                         if (short_read != NULL)
 430                                 *short_read = (count != 0);
 431                 } else if (chan->qh->do_split) {
 432                         length = qtd->ssplit_out_xfer_count;
 433                 } else {
 434                         length = chan->xfer_len;
 435                 }
 436         } else {
 437                 /*
 438                  * Must use the hctsiz.pktcnt field to determine how much data
 439                  * has been transferred. This field reflects the number of
 440                  * packets that have been transferred via the USB. This is
 441                  * always an integral number of packets if the transfer was
 442                  * halted before its normal completion. (Can't use the
 443                  * hctsiz.xfersize field because that reflects the number of
 444                  * bytes transferred via the AHB, not the USB).
 445                  */
 446                 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 447                 length = (chan->start_pkt_count - count) * chan->max_packet;
 448         }
 449
 450         return length;
 451 }
 452
 453 /**
 454  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 455  * Complete interrupt on the host channel. Updates the actual_length field
 456  * of the URB based on the number of bytes transferred via the host channel.
 457  * Sets the URB status if the data transfer is finished.
 458  *
 459  * Return: 1 if the data transfer specified by the URB is completely finished,
 460  * 0 otherwise
 461  */
 462 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 463                                  struct dwc2_host_chan *chan, int chnum,
 464                                  struct dwc2_hcd_urb *urb,
 465                                  struct dwc2_qtd *qtd)
 466 {
 467         u32 hctsiz;
 468         int xfer_done = 0;
 469         int short_read = 0;
 470         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 471                                                       DWC2_HC_XFER_COMPLETE,
 472                                                       &short_read);
 473
 474         if (urb->actual_length + xfer_length > urb->length) {
 475                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 476                 xfer_length = urb->length - urb->actual_length;
 477         }
 478
 479         /* Non DWORD-aligned buffer case handling */
 480         if (chan->align_buf && xfer_length) {
 481                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 482                 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 483                                 chan->qh->dw_align_buf_size,
 484                                 chan->ep_is_in ?
 485                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
 486                 if (chan->ep_is_in)
 487                         memcpy(urb->buf + urb->actual_length,
 488                                         chan->qh->dw_align_buf, xfer_length);
 489         }
 490
 491         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 492                  urb->actual_length, xfer_length);
 493         urb->actual_length += xfer_length;
 494
 495         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 496             (urb->flags & URB_SEND_ZERO_PACKET) &&
 497             urb->actual_length >= urb->length &&
 498             !(urb->length % chan->max_packet)) {
 499                 xfer_done = 0;
 500         } else if (short_read || urb->actual_length >= urb->length) {
 501                 xfer_done = 1;
 502                 urb->status = 0;
 503         }
 504
 505         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 506         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 507                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 508         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 509         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 510                  (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 511         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 512         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 513         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 514                  xfer_done);
 515
 516         return xfer_done;
 517 }
 518
 519 /*
 520  * Save the starting data toggle for the next transfer. The data toggle is
 521  * saved in the QH for non-control transfers and it's saved in the QTD for
 522  * control transfers.
 523  */
 524 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 525                                struct dwc2_host_chan *chan, int chnum,
 526                                struct dwc2_qtd *qtd)
 527 {
 528         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 529         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 530
 531         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 532                 if (pid == TSIZ_SC_MC_PID_DATA0)
 533                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 534                 else
 535                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 536         } else {
 537                 if (pid == TSIZ_SC_MC_PID_DATA0)
 538                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 539                 else
 540                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 541         }
 542 }
 543
 544 /**
 545  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 546  * the transfer is stopped for any reason. The fields of the current entry in
 547  * the frame descriptor array are set based on the transfer state and the input
 548  * halt_status. Completes the Isochronous URB if all the URB frames have been
 549  * completed.
 550  *
 551  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 552  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 553  */
 554 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 555                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 556                 int chnum, struct dwc2_qtd *qtd,
 557                 enum dwc2_halt_status halt_status)
 558 {
 559         struct dwc2_hcd_iso_packet_desc *frame_desc;
 560         struct dwc2_hcd_urb *urb = qtd->urb;
 561
 562         if (!urb)
 563                 return DWC2_HC_XFER_NO_HALT_STATUS;
 564
 565         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 566
 567         switch (halt_status) {
 568         case DWC2_HC_XFER_COMPLETE:
 569                 frame_desc->status = 0;
 570                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 571                                         chan, chnum, qtd, halt_status, NULL);
 572
 573                 /* Non DWORD-aligned buffer case handling */
 574                 if (chan->align_buf && frame_desc->actual_length) {
 575                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 576                                  __func__);
 577                         dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 578                                         chan->qh->dw_align_buf_size,
 579                                         chan->ep_is_in ?
 580                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 581                         if (chan->ep_is_in)
 582                                 memcpy(urb->buf + frame_desc->offset +
 583                                         qtd->isoc_split_offset,
 584                                         chan->qh->dw_align_buf,
 585                                         frame_desc->actual_length);
 586                 }
 587                 break;
 588         case DWC2_HC_XFER_FRAME_OVERRUN:
 589                 urb->error_count++;
 590                 if (chan->ep_is_in)
 591                         frame_desc->status = -ENOSR;
 592                 else
 593                         frame_desc->status = -ECOMM;
 594                 frame_desc->actual_length = 0;
 595                 break;
 596         case DWC2_HC_XFER_BABBLE_ERR:
 597                 urb->error_count++;
 598                 frame_desc->status = -EOVERFLOW;
 599                 /* Don't need to update actual_length in this case */
 600                 break;
 601         case DWC2_HC_XFER_XACT_ERR:
 602                 urb->error_count++;
 603                 frame_desc->status = -EPROTO;
 604                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 605                                         chan, chnum, qtd, halt_status, NULL);
 606
 607                 /* Non DWORD-aligned buffer case handling */
 608                 if (chan->align_buf && frame_desc->actual_length) {
 609                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 610                                  __func__);
 611                         dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 612                                         chan->qh->dw_align_buf_size,
 613                                         chan->ep_is_in ?
 614                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 615                         if (chan->ep_is_in)
 616                                 memcpy(urb->buf + frame_desc->offset +
 617                                         qtd->isoc_split_offset,
 618                                         chan->qh->dw_align_buf,
 619                                         frame_desc->actual_length);
 620                 }
 621
 622                 /* Skip whole frame */
 623                 if (chan->qh->do_split &&
 624                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 625                     hsotg->core_params->dma_enable > 0) {
 626                         qtd->complete_split = 0;
 627                         qtd->isoc_split_offset = 0;
 628                 }
 629
 630                 break;
 631         default:
 632                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 633                         halt_status);
 634                 break;
 635         }
 636
 637         if (++qtd->isoc_frame_index == urb->packet_count) {
 638                 /*
 639                  * urb->status is not used for isoc transfers. The individual
 640                  * frame_desc statuses are used instead.
 641                  */
 642                 dwc2_host_complete(hsotg, qtd, 0);
 643                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 644         } else {
 645                 halt_status = DWC2_HC_XFER_COMPLETE;
 646         }
 647
 648         return halt_status;
 649 }
 650
 651 /*
 652  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 653  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 654  * still linked to the QH, the QH is added to the end of the inactive
 655  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 656  * schedule if no more QTDs are linked to the QH.
 657  */
 658 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 659                                int free_qtd)
 660 {
 661         int continue_split = 0;
 662         struct dwc2_qtd *qtd;
 663
 664         if (dbg_qh(qh))
 665                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 666                          hsotg, qh, free_qtd);
 667
 668         if (list_empty(&qh->qtd_list)) {
 669                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 670                 goto no_qtd;
 671         }
 672
 673         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 674
 675         if (qtd->complete_split)
 676                 continue_split = 1;
 677         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 678                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 679                 continue_split = 1;
 680
 681         if (free_qtd) {
 682                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 683                 continue_split = 0;
 684         }
 685
 686 no_qtd:
 687         if (qh->channel)
 688                 qh->channel->align_buf = 0;
 689         qh->channel = NULL;
 690         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 691 }
 692
 693 /**
 694  * dwc2_release_channel() - Releases a host channel for use by other transfers
 695  *
 696  * @hsotg:       The HCD state structure
 697  * @chan:        The host channel to release
 698  * @qtd:         The QTD associated with the host channel. This QTD may be
 699  *               freed if the transfer is complete or an error has occurred.
 700  * @halt_status: Reason the channel is being released. This status
 701  *               determines the actions taken by this function.
 702  *
 703  * Also attempts to select and queue more transactions since at least one host
 704  * channel is available.
 705  */
 706 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 707                                  struct dwc2_host_chan *chan,
 708                                  struct dwc2_qtd *qtd,
 709                                  enum dwc2_halt_status halt_status)
 710 {
 711         enum dwc2_transaction_type tr_type;
 712         u32 haintmsk;
 713         int free_qtd = 0;
 714
 715         if (dbg_hc(chan))
 716                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 717                          __func__, chan->hc_num, halt_status);
 718
 719         switch (halt_status) {
 720         case DWC2_HC_XFER_URB_COMPLETE:
 721                 free_qtd = 1;
 722                 break;
 723         case DWC2_HC_XFER_AHB_ERR:
 724         case DWC2_HC_XFER_STALL:
 725         case DWC2_HC_XFER_BABBLE_ERR:
 726                 free_qtd = 1;
 727                 break;
 728         case DWC2_HC_XFER_XACT_ERR:
 729                 if (qtd && qtd->error_count >= 3) {
 730                         dev_vdbg(hsotg->dev,
 731                                  "  Complete URB with transaction error\n");
 732                         free_qtd = 1;
 733                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 734                 }
 735                 break;
 736         case DWC2_HC_XFER_URB_DEQUEUE:
 737                 /*
 738                  * The QTD has already been removed and the QH has been
 739                  * deactivated. Don't want to do anything except release the
 740                  * host channel and try to queue more transfers.
 741                  */
 742                 goto cleanup;
 743         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 744                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 745                 free_qtd = 1;
 746                 dwc2_host_complete(hsotg, qtd, -EIO);
 747                 break;
 748         case DWC2_HC_XFER_NO_HALT_STATUS:
 749         default:
 750                 break;
 751         }
 752
 753         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 754
 755 cleanup:
 756         /*
 757          * Release the host channel for use by other transfers. The cleanup
 758          * function clears the channel interrupt enables and conditions, so
 759          * there's no need to clear the Channel Halted interrupt separately.
 760          */
 761         if (!list_empty(&chan->hc_list_entry))
 762                 list_del(&chan->hc_list_entry);
 763         dwc2_hc_cleanup(hsotg, chan);
 764         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 765
 766         if (hsotg->core_params->uframe_sched > 0) {
 767                 hsotg->available_host_channels++;
 768         } else {
 769                 switch (chan->ep_type) {
 770                 case USB_ENDPOINT_XFER_CONTROL:
 771                 case USB_ENDPOINT_XFER_BULK:
 772                         hsotg->non_periodic_channels--;
 773                         break;
 774                 default:
 775                         /*
 776                          * Don't release reservations for periodic channels
 777                          * here. That's done when a periodic transfer is
 778                          * descheduled (i.e. when the QH is removed from the
 779                          * periodic schedule).
 780                          */
 781                         break;
 782                 }
 783         }
 784
 785         haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 786         haintmsk &= ~(1 << chan->hc_num);
 787         dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
 788
 789         /* Try to queue more transfers now that there's a free channel */
 790         tr_type = dwc2_hcd_select_transactions(hsotg);
 791         if (tr_type != DWC2_TRANSACTION_NONE)
 792                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 793 }
 794
 795 /*
 796  * Halts a host channel. If the channel cannot be halted immediately because
 797  * the request queue is full, this function ensures that the FIFO empty
 798  * interrupt for the appropriate queue is enabled so that the halt request can
 799  * be queued when there is space in the request queue.
 800  *
 801  * This function may also be called in DMA mode. In that case, the channel is
 802  * simply released since the core always halts the channel automatically in
 803  * DMA mode.
 804  */
 805 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 806                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 807                               enum dwc2_halt_status halt_status)
 808 {
 809         if (dbg_hc(chan))
 810                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 811
 812         if (hsotg->core_params->dma_enable > 0) {
 813                 if (dbg_hc(chan))
 814                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 815                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 816                 return;
 817         }
 818
 819         /* Slave mode processing */
 820         dwc2_hc_halt(hsotg, chan, halt_status);
 821
 822         if (chan->halt_on_queue) {
 823                 u32 gintmsk;
 824
 825                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 826                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 827                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 828                         dev_vdbg(hsotg->dev, "control/bulk\n");
 829                         /*
 830                          * Make sure the Non-periodic Tx FIFO empty interrupt
 831                          * is enabled so that the non-periodic schedule will
 832                          * be processed
 833                          */
 834                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 835                         gintmsk |= GINTSTS_NPTXFEMP;
 836                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 837                 } else {
 838                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 839                         /*
 840                          * Move the QH from the periodic queued schedule to
 841                          * the periodic assigned schedule. This allows the
 842                          * halt to be queued when the periodic schedule is
 843                          * processed.
 844                          */
 845                         list_move(&chan->qh->qh_list_entry,
 846                                   &hsotg->periodic_sched_assigned);
 847
 848                         /*
 849                          * Make sure the Periodic Tx FIFO Empty interrupt is
 850                          * enabled so that the periodic schedule will be
 851                          * processed
 852                          */
 853                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 854                         gintmsk |= GINTSTS_PTXFEMP;
 855                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 856                 }
 857         }
 858 }
 859
 860 /*
 861  * Performs common cleanup for non-periodic transfers after a Transfer
 862  * Complete interrupt. This function should be called after any endpoint type
 863  * specific handling is finished to release the host channel.
 864  */
 865 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 866                                             struct dwc2_host_chan *chan,
 867                                             int chnum, struct dwc2_qtd *qtd,
 868                                             enum dwc2_halt_status halt_status)
 869 {
 870         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 871
 872         qtd->error_count = 0;
 873
 874         if (chan->hcint & HCINTMSK_NYET) {
 875                 /*
 876                  * Got a NYET on the last transaction of the transfer. This
 877                  * means that the endpoint should be in the PING state at the
 878                  * beginning of the next transfer.
 879                  */
 880                 dev_vdbg(hsotg->dev, "got NYET\n");
 881                 chan->qh->ping_state = 1;
 882         }
 883
 884         /*
 885          * Always halt and release the host channel to make it available for
 886          * more transfers. There may still be more phases for a control
 887          * transfer or more data packets for a bulk transfer at this point,
 888          * but the host channel is still halted. A channel will be reassigned
 889          * to the transfer when the non-periodic schedule is processed after
 890          * the channel is released. This allows transactions to be queued
 891          * properly via dwc2_hcd_queue_transactions, which also enables the
 892          * Tx FIFO Empty interrupt if necessary.
 893          */
 894         if (chan->ep_is_in) {
 895                 /*
 896                  * IN transfers in Slave mode require an explicit disable to
 897                  * halt the channel. (In DMA mode, this call simply releases
 898                  * the channel.)
 899                  */
 900                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 901         } else {
 902                 /*
 903                  * The channel is automatically disabled by the core for OUT
 904                  * transfers in Slave mode
 905                  */
 906                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 907         }
 908 }
 909
 910 /*
 911  * Performs common cleanup for periodic transfers after a Transfer Complete
 912  * interrupt. This function should be called after any endpoint type specific
 913  * handling is finished to release the host channel.
 914  */
 915 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 916                                         struct dwc2_host_chan *chan, int chnum,
 917                                         struct dwc2_qtd *qtd,
 918                                         enum dwc2_halt_status halt_status)
 919 {
 920         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 921
 922         qtd->error_count = 0;
 923
 924         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 925                 /* Core halts channel in these cases */
 926                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 927         else
 928                 /* Flush any outstanding requests from the Tx queue */
 929                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 930 }
 931
 932 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 933                                        struct dwc2_host_chan *chan, int chnum,
 934                                        struct dwc2_qtd *qtd)
 935 {
 936         struct dwc2_hcd_iso_packet_desc *frame_desc;
 937         u32 len;
 938
 939         if (!qtd->urb)
 940                 return 0;
 941
 942         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 943         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 944                                           DWC2_HC_XFER_COMPLETE, NULL);
 945         if (!len) {
 946                 qtd->complete_split = 0;
 947                 qtd->isoc_split_offset = 0;
 948                 return 0;
 949         }
 950
 951         frame_desc->actual_length += len;
 952
 953         if (chan->align_buf) {
 954                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 955                 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 956                                 chan->qh->dw_align_buf_size, DMA_FROM_DEVICE);
 957                 memcpy(qtd->urb->buf + frame_desc->offset +
 958                        qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
 959         }
 960
 961         qtd->isoc_split_offset += len;
 962
 963         if (frame_desc->actual_length >= frame_desc->length) {
 964                 frame_desc->status = 0;
 965                 qtd->isoc_frame_index++;
 966                 qtd->complete_split = 0;
 967                 qtd->isoc_split_offset = 0;
 968         }
 969
 970         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 971                 dwc2_host_complete(hsotg, qtd, 0);
 972                 dwc2_release_channel(hsotg, chan, qtd,
 973                                      DWC2_HC_XFER_URB_COMPLETE);
 974         } else {
 975                 dwc2_release_channel(hsotg, chan, qtd,
 976                                      DWC2_HC_XFER_NO_HALT_STATUS);
 977         }
 978
 979         return 1;       /* Indicates that channel released */
 980 }
 981
 982 /*
 983  * Handles a host channel Transfer Complete interrupt. This handler may be
 984  * called in either DMA mode or Slave mode.
 985  */
 986 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 987                                   struct dwc2_host_chan *chan, int chnum,
 988                                   struct dwc2_qtd *qtd)
 989 {
 990         struct dwc2_hcd_urb *urb = qtd->urb;
 991         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 992         int pipe_type;
 993         int urb_xfer_done;
 994
 995         if (dbg_hc(chan))
 996                 dev_vdbg(hsotg->dev,
 997                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 998                          chnum);
 999
1000         if (!urb)
1001                 goto handle_xfercomp_done;
1002
1003         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1004
1005         if (hsotg->core_params->dma_desc_enable > 0) {
1006                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
1007                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
1008                         /* Do not disable the interrupt, just clear it */
1009                         return;
1010                 goto handle_xfercomp_done;
1011         }
1012
1013         /* Handle xfer complete on CSPLIT */
1014         if (chan->qh->do_split) {
1015                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1016                     hsotg->core_params->dma_enable > 0) {
1017                         if (qtd->complete_split &&
1018                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1019                                                         qtd))
1020                                 goto handle_xfercomp_done;
1021                 } else {
1022                         qtd->complete_split = 0;
1023                 }
1024         }
1025
1026         /* Update the QTD and URB states */
1027         switch (pipe_type) {
1028         case USB_ENDPOINT_XFER_CONTROL:
1029                 switch (qtd->control_phase) {
1030                 case DWC2_CONTROL_SETUP:
1031                         if (urb->length > 0)
1032                                 qtd->control_phase = DWC2_CONTROL_DATA;
1033                         else
1034                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1035                         dev_vdbg(hsotg->dev,
1036                                  "  Control setup transaction done\n");
1037                         halt_status = DWC2_HC_XFER_COMPLETE;
1038                         break;
1039                 case DWC2_CONTROL_DATA:
1040                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1041                                                               chnum, urb, qtd);
1042                         if (urb_xfer_done) {
1043                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1044                                 dev_vdbg(hsotg->dev,
1045                                          "  Control data transfer done\n");
1046                         } else {
1047                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1048                                                           qtd);
1049                         }
1050                         halt_status = DWC2_HC_XFER_COMPLETE;
1051                         break;
1052                 case DWC2_CONTROL_STATUS:
1053                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1054                         if (urb->status == -EINPROGRESS)
1055                                 urb->status = 0;
1056                         dwc2_host_complete(hsotg, qtd, urb->status);
1057                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1058                         break;
1059                 }
1060
1061                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1062                                                 halt_status);
1063                 break;
1064         case USB_ENDPOINT_XFER_BULK:
1065                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1066                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1067                                                       qtd);
1068                 if (urb_xfer_done) {
1069                         dwc2_host_complete(hsotg, qtd, urb->status);
1070                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1071                 } else {
1072                         halt_status = DWC2_HC_XFER_COMPLETE;
1073                 }
1074
1075                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1076                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1077                                                 halt_status);
1078                 break;
1079         case USB_ENDPOINT_XFER_INT:
1080                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1081                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1082                                                       qtd);
1083
1084                 /*
1085                  * Interrupt URB is done on the first transfer complete
1086                  * interrupt
1087                  */
1088                 if (urb_xfer_done) {
1089                         dwc2_host_complete(hsotg, qtd, urb->status);
1090                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1091                 } else {
1092                         halt_status = DWC2_HC_XFER_COMPLETE;
1093                 }
1094
1095                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1096                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1097                                             halt_status);
1098                 break;
1099         case USB_ENDPOINT_XFER_ISOC:
1100                 if (dbg_perio())
1101                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1102                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1103                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1104                                         chnum, qtd, DWC2_HC_XFER_COMPLETE);
1105                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1106                                             halt_status);
1107                 break;
1108         }
1109
1110 handle_xfercomp_done:
1111         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1112 }
1113
1114 /*
1115  * Handles a host channel STALL interrupt. This handler may be called in
1116  * either DMA mode or Slave mode.
1117  */
1118 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1119                                struct dwc2_host_chan *chan, int chnum,
1120                                struct dwc2_qtd *qtd)
1121 {
1122         struct dwc2_hcd_urb *urb = qtd->urb;
1123         int pipe_type;
1124
1125         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1126                 chnum);
1127
1128         if (hsotg->core_params->dma_desc_enable > 0) {
1129                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1130                                             DWC2_HC_XFER_STALL);
1131                 goto handle_stall_done;
1132         }
1133
1134         if (!urb)
1135                 goto handle_stall_halt;
1136
1137         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1138
1139         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1140                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1141
1142         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1143             pipe_type == USB_ENDPOINT_XFER_INT) {
1144                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1145                 /*
1146                  * USB protocol requires resetting the data toggle for bulk
1147                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1148                  * setup command is issued to the endpoint. Anticipate the
1149                  * CLEAR_FEATURE command since a STALL has occurred and reset
1150                  * the data toggle now.
1151                  */
1152                 chan->qh->data_toggle = 0;
1153         }
1154
1155 handle_stall_halt:
1156         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1157
1158 handle_stall_done:
1159         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1160 }
1161
1162 /*
1163  * Updates the state of the URB when a transfer has been stopped due to an
1164  * abnormal condition before the transfer completes. Modifies the
1165  * actual_length field of the URB to reflect the number of bytes that have
1166  * actually been transferred via the host channel.
1167  */
1168 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1169                                       struct dwc2_host_chan *chan, int chnum,
1170                                       struct dwc2_hcd_urb *urb,
1171                                       struct dwc2_qtd *qtd,
1172                                       enum dwc2_halt_status halt_status)
1173 {
1174         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1175                                                       qtd, halt_status, NULL);
1176         u32 hctsiz;
1177
1178         if (urb->actual_length + xfer_length > urb->length) {
1179                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1180                 xfer_length = urb->length - urb->actual_length;
1181         }
1182
1183         /* Non DWORD-aligned buffer case handling */
1184         if (chan->align_buf && xfer_length && chan->ep_is_in) {
1185                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1186                 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
1187                                 chan->qh->dw_align_buf_size,
1188                                 chan->ep_is_in ?
1189                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
1190                 if (chan->ep_is_in)
1191                         memcpy(urb->buf + urb->actual_length,
1192                                         chan->qh->dw_align_buf,
1193                                         xfer_length);
1194         }
1195
1196         urb->actual_length += xfer_length;
1197
1198         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1199         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1200                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1201         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1202                  chan->start_pkt_count);
1203         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1204                  (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1205         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1206         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1207                  xfer_length);
1208         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1209                  urb->actual_length);
1210         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1211                  urb->length);
1212 }
1213
1214 /*
1215  * Handles a host channel NAK interrupt. This handler may be called in either
1216  * DMA mode or Slave mode.
1217  */
1218 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1219                              struct dwc2_host_chan *chan, int chnum,
1220                              struct dwc2_qtd *qtd)
1221 {
1222         if (!qtd) {
1223                 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1224                 return;
1225         }
1226
1227         if (!qtd->urb) {
1228                 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1229                 return;
1230         }
1231
1232         if (dbg_hc(chan))
1233                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1234                          chnum);
1235
1236         /*
1237          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1238          * interrupt. Re-start the SSPLIT transfer.
1239          */
1240         if (chan->do_split) {
1241                 if (chan->complete_split)
1242                         qtd->error_count = 0;
1243                 qtd->complete_split = 0;
1244                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1245                 goto handle_nak_done;
1246         }
1247
1248         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1249         case USB_ENDPOINT_XFER_CONTROL:
1250         case USB_ENDPOINT_XFER_BULK:
1251                 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1252                         /*
1253                          * NAK interrupts are enabled on bulk/control IN
1254                          * transfers in DMA mode for the sole purpose of
1255                          * resetting the error count after a transaction error
1256                          * occurs. The core will continue transferring data.
1257                          */
1258                         qtd->error_count = 0;
1259                         break;
1260                 }
1261
1262                 /*
1263                  * NAK interrupts normally occur during OUT transfers in DMA
1264                  * or Slave mode. For IN transfers, more requests will be
1265                  * queued as request queue space is available.
1266                  */
1267                 qtd->error_count = 0;
1268
1269                 if (!chan->qh->ping_state) {
1270                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1271                                                   qtd, DWC2_HC_XFER_NAK);
1272                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1273
1274                         if (chan->speed == USB_SPEED_HIGH)
1275                                 chan->qh->ping_state = 1;
1276                 }
1277
1278                 /*
1279                  * Halt the channel so the transfer can be re-started from
1280                  * the appropriate point or the PING protocol will
1281                  * start/continue
1282                  */
1283                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1284                 break;
1285         case USB_ENDPOINT_XFER_INT:
1286                 qtd->error_count = 0;
1287                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1288                 break;
1289         case USB_ENDPOINT_XFER_ISOC:
1290                 /* Should never get called for isochronous transfers */
1291                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1292                 break;
1293         }
1294
1295 handle_nak_done:
1296         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1297 }
1298
1299 /*
1300  * Handles a host channel ACK interrupt. This interrupt is enabled when
1301  * performing the PING protocol in Slave mode, when errors occur during
1302  * either Slave mode or DMA mode, and during Start Split transactions.
1303  */
1304 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1305                              struct dwc2_host_chan *chan, int chnum,
1306                              struct dwc2_qtd *qtd)
1307 {
1308         struct dwc2_hcd_iso_packet_desc *frame_desc;
1309
1310         if (dbg_hc(chan))
1311                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1312                          chnum);
1313
1314         if (chan->do_split) {
1315                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1316                 if (!chan->ep_is_in &&
1317                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1318                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1319
1320                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1321                         qtd->complete_split = 1;
1322                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1323                 } else {
1324                         /* ISOC OUT */
1325                         switch (chan->xact_pos) {
1326                         case DWC2_HCSPLT_XACTPOS_ALL:
1327                                 break;
1328                         case DWC2_HCSPLT_XACTPOS_END:
1329                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1330                                 qtd->isoc_split_offset = 0;
1331                                 break;
1332                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1333                         case DWC2_HCSPLT_XACTPOS_MID:
1334                                 /*
1335                                  * For BEGIN or MID, calculate the length for
1336                                  * the next microframe to determine the correct
1337                                  * SSPLIT token, either MID or END
1338                                  */
1339                                 frame_desc = &qtd->urb->iso_descs[
1340                                                 qtd->isoc_frame_index];
1341                                 qtd->isoc_split_offset += 188;
1342
1343                                 if (frame_desc->length - qtd->isoc_split_offset
1344                                                         <= 188)
1345                                         qtd->isoc_split_pos =
1346                                                         DWC2_HCSPLT_XACTPOS_END;
1347                                 else
1348                                         qtd->isoc_split_pos =
1349                                                         DWC2_HCSPLT_XACTPOS_MID;
1350                                 break;
1351                         }
1352                 }
1353         } else {
1354                 qtd->error_count = 0;
1355
1356                 if (chan->qh->ping_state) {
1357                         chan->qh->ping_state = 0;
1358                         /*
1359                          * Halt the channel so the transfer can be re-started
1360                          * from the appropriate point. This only happens in
1361                          * Slave mode. In DMA mode, the ping_state is cleared
1362                          * when the transfer is started because the core
1363                          * automatically executes the PING, then the transfer.
1364                          */
1365                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1366                 }
1367         }
1368
1369         /*
1370          * If the ACK occurred when _not_ in the PING state, let the channel
1371          * continue transferring data after clearing the error count
1372          */
1373         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1374 }
1375
1376 /*
1377  * Handles a host channel NYET interrupt. This interrupt should only occur on
1378  * Bulk and Control OUT endpoints and for complete split transactions. If a
1379  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1380  * handled in the xfercomp interrupt handler, not here. This handler may be
1381  * called in either DMA mode or Slave mode.
1382  */
1383 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1384                               struct dwc2_host_chan *chan, int chnum,
1385                               struct dwc2_qtd *qtd)
1386 {
1387         if (dbg_hc(chan))
1388                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1389                          chnum);
1390
1391         /*
1392          * NYET on CSPLIT
1393          * re-do the CSPLIT immediately on non-periodic
1394          */
1395         if (chan->do_split && chan->complete_split) {
1396                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1397                     hsotg->core_params->dma_enable > 0) {
1398                         qtd->complete_split = 0;
1399                         qtd->isoc_split_offset = 0;
1400                         qtd->isoc_frame_index++;
1401                         if (qtd->urb &&
1402                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1403                                 dwc2_host_complete(hsotg, qtd, 0);
1404                                 dwc2_release_channel(hsotg, chan, qtd,
1405                                                      DWC2_HC_XFER_URB_COMPLETE);
1406                         } else {
1407                                 dwc2_release_channel(hsotg, chan, qtd,
1408                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1409                         }
1410                         goto handle_nyet_done;
1411                 }
1412
1413                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1414                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1415                         int frnum = dwc2_hcd_get_frame_number(hsotg);
1416
1417                         if (dwc2_full_frame_num(frnum) !=
1418                             dwc2_full_frame_num(chan->qh->sched_frame)) {
1419                                 /*
1420                                  * No longer in the same full speed frame.
1421                                  * Treat this as a transaction error.
1422                                  */
1423 #if 0
1424                                 /*
1425                                  * Todo: Fix system performance so this can
1426                                  * be treated as an error. Right now complete
1427                                  * splits cannot be scheduled precisely enough
1428                                  * due to other system activity, so this error
1429                                  * occurs regularly in Slave mode.
1430                                  */
1431                                 qtd->error_count++;
1432 #endif
1433                                 qtd->complete_split = 0;
1434                                 dwc2_halt_channel(hsotg, chan, qtd,
1435                                                   DWC2_HC_XFER_XACT_ERR);
1436                                 /* Todo: add support for isoc release */
1437                                 goto handle_nyet_done;
1438                         }
1439                 }
1440
1441                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1442                 goto handle_nyet_done;
1443         }
1444
1445         chan->qh->ping_state = 1;
1446         qtd->error_count = 0;
1447
1448         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1449                                   DWC2_HC_XFER_NYET);
1450         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1451
1452         /*
1453          * Halt the channel and re-start the transfer so the PING protocol
1454          * will start
1455          */
1456         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1457
1458 handle_nyet_done:
1459         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1460 }
1461
1462 /*
1463  * Handles a host channel babble interrupt. This handler may be called in
1464  * either DMA mode or Slave mode.
1465  */
1466 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1467                                 struct dwc2_host_chan *chan, int chnum,
1468                                 struct dwc2_qtd *qtd)
1469 {
1470         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1471                 chnum);
1472
1473         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1474
1475         if (hsotg->core_params->dma_desc_enable > 0) {
1476                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1477                                             DWC2_HC_XFER_BABBLE_ERR);
1478                 goto disable_int;
1479         }
1480
1481         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1482                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1483                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1484         } else {
1485                 enum dwc2_halt_status halt_status;
1486
1487                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1488                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1489                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1490         }
1491
1492 disable_int:
1493         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1494 }
1495
1496 /*
1497  * Handles a host channel AHB error interrupt. This handler is only called in
1498  * DMA mode.
1499  */
1500 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1501                                 struct dwc2_host_chan *chan, int chnum,
1502                                 struct dwc2_qtd *qtd)
1503 {
1504         struct dwc2_hcd_urb *urb = qtd->urb;
1505         char *pipetype, *speed;
1506         u32 hcchar;
1507         u32 hcsplt;
1508         u32 hctsiz;
1509         u32 hc_dma;
1510
1511         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1512                 chnum);
1513
1514         if (!urb)
1515                 goto handle_ahberr_halt;
1516
1517         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1518
1519         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1520         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1521         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1522         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1523
1524         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1525         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1526         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1527         dev_err(hsotg->dev, "  Device address: %d\n",
1528                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1529         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1530                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1531                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1532
1533         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1534         case USB_ENDPOINT_XFER_CONTROL:
1535                 pipetype = "CONTROL";
1536                 break;
1537         case USB_ENDPOINT_XFER_BULK:
1538                 pipetype = "BULK";
1539                 break;
1540         case USB_ENDPOINT_XFER_INT:
1541                 pipetype = "INTERRUPT";
1542                 break;
1543         case USB_ENDPOINT_XFER_ISOC:
1544                 pipetype = "ISOCHRONOUS";
1545                 break;
1546         default:
1547                 pipetype = "UNKNOWN";
1548                 break;
1549         }
1550
1551         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1552
1553         switch (chan->speed) {
1554         case USB_SPEED_HIGH:
1555                 speed = "HIGH";
1556                 break;
1557         case USB_SPEED_FULL:
1558                 speed = "FULL";
1559                 break;
1560         case USB_SPEED_LOW:
1561                 speed = "LOW";
1562                 break;
1563         default:
1564                 speed = "UNKNOWN";
1565                 break;
1566         }
1567
1568         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1569
1570         dev_err(hsotg->dev, "  Max packet size: %d\n",
1571                 dwc2_hcd_get_mps(&urb->pipe_info));
1572         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1573         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1574                 urb->buf, (unsigned long)urb->dma);
1575         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1576                 urb->setup_packet, (unsigned long)urb->setup_dma);
1577         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1578
1579         /* Core halts the channel for Descriptor DMA mode */
1580         if (hsotg->core_params->dma_desc_enable > 0) {
1581                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1582                                             DWC2_HC_XFER_AHB_ERR);
1583                 goto handle_ahberr_done;
1584         }
1585
1586         dwc2_host_complete(hsotg, qtd, -EIO);
1587
1588 handle_ahberr_halt:
1589         /*
1590          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1591          * write to the HCCHARn register in DMA mode to force the halt.
1592          */
1593         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1594
1595 handle_ahberr_done:
1596         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1597 }
1598
1599 /*
1600  * Handles a host channel transaction error interrupt. This handler may be
1601  * called in either DMA mode or Slave mode.
1602  */
1603 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1604                                  struct dwc2_host_chan *chan, int chnum,
1605                                  struct dwc2_qtd *qtd)
1606 {
1607         dev_dbg(hsotg->dev,
1608                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1609
1610         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1611
1612         if (hsotg->core_params->dma_desc_enable > 0) {
1613                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1614                                             DWC2_HC_XFER_XACT_ERR);
1615                 goto handle_xacterr_done;
1616         }
1617
1618         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1619         case USB_ENDPOINT_XFER_CONTROL:
1620         case USB_ENDPOINT_XFER_BULK:
1621                 qtd->error_count++;
1622                 if (!chan->qh->ping_state) {
1623
1624                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1625                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1626                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1627                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1628                                 chan->qh->ping_state = 1;
1629                 }
1630
1631                 /*
1632                  * Halt the channel so the transfer can be re-started from
1633                  * the appropriate point or the PING protocol will start
1634                  */
1635                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1636                 break;
1637         case USB_ENDPOINT_XFER_INT:
1638                 qtd->error_count++;
1639                 if (chan->do_split && chan->complete_split)
1640                         qtd->complete_split = 0;
1641                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1642                 break;
1643         case USB_ENDPOINT_XFER_ISOC:
1644                 {
1645                         enum dwc2_halt_status halt_status;
1646
1647                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1648                                         chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1649                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1650                 }
1651                 break;
1652         }
1653
1654 handle_xacterr_done:
1655         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1656 }
1657
1658 /*
1659  * Handles a host channel frame overrun interrupt. This handler may be called
1660  * in either DMA mode or Slave mode.
1661  */
1662 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1663                                   struct dwc2_host_chan *chan, int chnum,
1664                                   struct dwc2_qtd *qtd)
1665 {
1666         enum dwc2_halt_status halt_status;
1667
1668         if (dbg_hc(chan))
1669                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1670                         chnum);
1671
1672         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1673
1674         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1675         case USB_ENDPOINT_XFER_CONTROL:
1676         case USB_ENDPOINT_XFER_BULK:
1677                 break;
1678         case USB_ENDPOINT_XFER_INT:
1679                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1680                 break;
1681         case USB_ENDPOINT_XFER_ISOC:
1682                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1683                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1684                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1685                 break;
1686         }
1687
1688         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1689 }
1690
1691 /*
1692  * Handles a host channel data toggle error interrupt. This handler may be
1693  * called in either DMA mode or Slave mode.
1694  */
1695 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1696                                     struct dwc2_host_chan *chan, int chnum,
1697                                     struct dwc2_qtd *qtd)
1698 {
1699         dev_dbg(hsotg->dev,
1700                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1701
1702         if (chan->ep_is_in)
1703                 qtd->error_count = 0;
1704         else
1705                 dev_err(hsotg->dev,
1706                         "Data Toggle Error on OUT transfer, channel %d\n",
1707                         chnum);
1708
1709         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1710         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1711 }
1712
1713 /*
1714  * For debug only. It checks that a valid halt status is set and that
1715  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1716  * taken and a warning is issued.
1717  *
1718  * Return: true if halt status is ok, false otherwise
1719  */
1720 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1721                                 struct dwc2_host_chan *chan, int chnum,
1722                                 struct dwc2_qtd *qtd)
1723 {
1724 #ifdef DEBUG
1725         u32 hcchar;
1726         u32 hctsiz;
1727         u32 hcintmsk;
1728         u32 hcsplt;
1729
1730         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1731                 /*
1732                  * This code is here only as a check. This condition should
1733                  * never happen. Ignore the halt if it does occur.
1734                  */
1735                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1736                 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1737                 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1738                 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1739                 dev_dbg(hsotg->dev,
1740                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1741                          __func__);
1742                 dev_dbg(hsotg->dev,
1743                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1744                         chnum, hcchar, hctsiz);
1745                 dev_dbg(hsotg->dev,
1746                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1747                         chan->hcint, hcintmsk, hcsplt);
1748                 if (qtd)
1749                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1750                                 qtd->complete_split);
1751                 dev_warn(hsotg->dev,
1752                          "%s: no halt status, channel %d, ignoring interrupt\n",
1753                          __func__, chnum);
1754                 return false;
1755         }
1756
1757         /*
1758          * This code is here only as a check. hcchar.chdis should never be set
1759          * when the halt interrupt occurs. Halt the channel again if it does
1760          * occur.
1761          */
1762         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1763         if (hcchar & HCCHAR_CHDIS) {
1764                 dev_warn(hsotg->dev,
1765                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1766                          __func__, hcchar);
1767                 chan->halt_pending = 0;
1768                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1769                 return false;
1770         }
1771 #endif
1772
1773         return true;
1774 }
1775
1776 /*
1777  * Handles a host Channel Halted interrupt in DMA mode. This handler
1778  * determines the reason the channel halted and proceeds accordingly.
1779  */
1780 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1781                                     struct dwc2_host_chan *chan, int chnum,
1782                                     struct dwc2_qtd *qtd)
1783 {
1784         u32 hcintmsk;
1785         int out_nak_enh = 0;
1786
1787         if (dbg_hc(chan))
1788                 dev_vdbg(hsotg->dev,
1789                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1790                          chnum);
1791
1792         /*
1793          * For core with OUT NAK enhancement, the flow for high-speed
1794          * CONTROL/BULK OUT is handled a little differently
1795          */
1796         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1797                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1798                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1799                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1800                         out_nak_enh = 1;
1801                 }
1802         }
1803
1804         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1805             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1806              hsotg->core_params->dma_desc_enable <= 0)) {
1807                 if (hsotg->core_params->dma_desc_enable > 0)
1808                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1809                                                     chan->halt_status);
1810                 else
1811                         /*
1812                          * Just release the channel. A dequeue can happen on a
1813                          * transfer timeout. In the case of an AHB Error, the
1814                          * channel was forced to halt because there's no way to
1815                          * gracefully recover.
1816                          */
1817                         dwc2_release_channel(hsotg, chan, qtd,
1818                                              chan->halt_status);
1819                 return;
1820         }
1821
1822         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1823
1824         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1825                 /*
1826                  * Todo: This is here because of a possible hardware bug. Spec
1827                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1828                  * interrupt w/ACK bit set should occur, but I only see the
1829                  * XFERCOMP bit, even with it masked out. This is a workaround
1830                  * for that behavior. Should fix this when hardware is fixed.
1831                  */
1832                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1833                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1834                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1835         } else if (chan->hcint & HCINTMSK_STALL) {
1836                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1837         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1838                    hsotg->core_params->dma_desc_enable <= 0) {
1839                 if (out_nak_enh) {
1840                         if (chan->hcint &
1841                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1842                                 dev_vdbg(hsotg->dev,
1843                                          "XactErr with NYET/NAK/ACK\n");
1844                                 qtd->error_count = 0;
1845                         } else {
1846                                 dev_vdbg(hsotg->dev,
1847                                          "XactErr without NYET/NAK/ACK\n");
1848                         }
1849                 }
1850
1851                 /*
1852                  * Must handle xacterr before nak or ack. Could get a xacterr
1853                  * at the same time as either of these on a BULK/CONTROL OUT
1854                  * that started with a PING. The xacterr takes precedence.
1855                  */
1856                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1857         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1858                    hsotg->core_params->dma_desc_enable > 0) {
1859                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1860         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1861                    hsotg->core_params->dma_desc_enable > 0) {
1862                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1863         } else if (chan->hcint & HCINTMSK_BBLERR) {
1864                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1865         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1866                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1867         } else if (!out_nak_enh) {
1868                 if (chan->hcint & HCINTMSK_NYET) {
1869                         /*
1870                          * Must handle nyet before nak or ack. Could get a nyet
1871                          * at the same time as either of those on a BULK/CONTROL
1872                          * OUT that started with a PING. The nyet takes
1873                          * precedence.
1874                          */
1875                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1876                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1877                            !(hcintmsk & HCINTMSK_NAK)) {
1878                         /*
1879                          * If nak is not masked, it's because a non-split IN
1880                          * transfer is in an error state. In that case, the nak
1881                          * is handled by the nak interrupt handler, not here.
1882                          * Handle nak here for BULK/CONTROL OUT transfers, which
1883                          * halt on a NAK to allow rewinding the buffer pointer.
1884                          */
1885                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1886                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1887                            !(hcintmsk & HCINTMSK_ACK)) {
1888                         /*
1889                          * If ack is not masked, it's because a non-split IN
1890                          * transfer is in an error state. In that case, the ack
1891                          * is handled by the ack interrupt handler, not here.
1892                          * Handle ack here for split transfers. Start splits
1893                          * halt on ACK.
1894                          */
1895                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1896                 } else {
1897                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1898                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1899                                 /*
1900                                  * A periodic transfer halted with no other
1901                                  * channel interrupts set. Assume it was halted
1902                                  * by the core because it could not be completed
1903                                  * in its scheduled (micro)frame.
1904                                  */
1905                                 dev_dbg(hsotg->dev,
1906                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1907                                         __func__, chnum);
1908                                 dwc2_halt_channel(hsotg, chan, qtd,
1909                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1910                         } else {
1911                                 dev_err(hsotg->dev,
1912                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1913                                         __func__, chnum);
1914                                 dev_err(hsotg->dev,
1915                                         "hcint 0x%08x, intsts 0x%08x\n",
1916                                         chan->hcint,
1917                                         dwc2_readl(hsotg->regs + GINTSTS));
1918                                 goto error;
1919                         }
1920                 }
1921         } else {
1922                 dev_info(hsotg->dev,
1923                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1924                          chan->hcint);
1925 error:
1926                 /* Failthrough: use 3-strikes rule */
1927                 qtd->error_count++;
1928                 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1929                                           qtd, DWC2_HC_XFER_XACT_ERR);
1930                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1931                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1932         }
1933 }
1934
1935 /*
1936  * Handles a host channel Channel Halted interrupt
1937  *
1938  * In slave mode, this handler is called only when the driver specifically
1939  * requests a halt. This occurs during handling other host channel interrupts
1940  * (e.g. nak, xacterr, stall, nyet, etc.).
1941  *
1942  * In DMA mode, this is the interrupt that occurs when the core has finished
1943  * processing a transfer on a channel. Other host channel interrupts (except
1944  * ahberr) are disabled in DMA mode.
1945  */
1946 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1947                                 struct dwc2_host_chan *chan, int chnum,
1948                                 struct dwc2_qtd *qtd)
1949 {
1950         if (dbg_hc(chan))
1951                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1952                          chnum);
1953
1954         if (hsotg->core_params->dma_enable > 0) {
1955                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1956         } else {
1957                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1958                         return;
1959                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1960         }
1961 }
1962
1963 /*
1964  * Check if the given qtd is still the top of the list (and thus valid).
1965  *
1966  * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1967  * the qtd from the top of the list, this will return false (otherwise true).
1968  */
1969 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1970 {
1971         struct dwc2_qtd *cur_head;
1972
1973         if (qh == NULL)
1974                 return false;
1975
1976         cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1977                                     qtd_list_entry);
1978         return (cur_head == qtd);
1979 }
1980
1981 /* Handles interrupt for a specific Host Channel */
1982 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1983 {
1984         struct dwc2_qtd *qtd;
1985         struct dwc2_host_chan *chan;
1986         u32 hcint, hcintmsk;
1987
1988         chan = hsotg->hc_ptr_array[chnum];
1989
1990         hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1991         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1992         if (!chan) {
1993                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1994                 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1995                 return;
1996         }
1997
1998         if (dbg_hc(chan)) {
1999                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2000                          chnum);
2001                 dev_vdbg(hsotg->dev,
2002                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2003                          hcint, hcintmsk, hcint & hcintmsk);
2004         }
2005
2006         dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2007         chan->hcint = hcint;
2008         hcint &= hcintmsk;
2009
2010         /*
2011          * If the channel was halted due to a dequeue, the qtd list might
2012          * be empty or at least the first entry will not be the active qtd.
2013          * In this case, take a shortcut and just release the channel.
2014          */
2015         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2016                 /*
2017                  * If the channel was halted, this should be the only
2018                  * interrupt unmasked
2019                  */
2020                 WARN_ON(hcint != HCINTMSK_CHHLTD);
2021                 if (hsotg->core_params->dma_desc_enable > 0)
2022                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2023                                                     chan->halt_status);
2024                 else
2025                         dwc2_release_channel(hsotg, chan, NULL,
2026                                              chan->halt_status);
2027                 return;
2028         }
2029
2030         if (list_empty(&chan->qh->qtd_list)) {
2031                 /*
2032                  * TODO: Will this ever happen with the
2033                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
2034                  */
2035                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2036                         chnum);
2037                 dev_dbg(hsotg->dev,
2038                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2039                         chan->hcint, hcintmsk, hcint);
2040                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2041                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2042                 chan->hcint = 0;
2043                 return;
2044         }
2045
2046         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2047                                qtd_list_entry);
2048
2049         if (hsotg->core_params->dma_enable <= 0) {
2050                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2051                         hcint &= ~HCINTMSK_CHHLTD;
2052         }
2053
2054         if (hcint & HCINTMSK_XFERCOMPL) {
2055                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2056                 /*
2057                  * If NYET occurred at same time as Xfer Complete, the NYET is
2058                  * handled by the Xfer Complete interrupt handler. Don't want
2059                  * to call the NYET interrupt handler in this case.
2060                  */
2061                 hcint &= ~HCINTMSK_NYET;
2062         }
2063
2064         if (hcint & HCINTMSK_CHHLTD) {
2065                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2066                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2067                         goto exit;
2068         }
2069         if (hcint & HCINTMSK_AHBERR) {
2070                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2071                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2072                         goto exit;
2073         }
2074         if (hcint & HCINTMSK_STALL) {
2075                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2076                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2077                         goto exit;
2078         }
2079         if (hcint & HCINTMSK_NAK) {
2080                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2081                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2082                         goto exit;
2083         }
2084         if (hcint & HCINTMSK_ACK) {
2085                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2086                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2087                         goto exit;
2088         }
2089         if (hcint & HCINTMSK_NYET) {
2090                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2091                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2092                         goto exit;
2093         }
2094         if (hcint & HCINTMSK_XACTERR) {
2095                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2096                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2097                         goto exit;
2098         }
2099         if (hcint & HCINTMSK_BBLERR) {
2100                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2101                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2102                         goto exit;
2103         }
2104         if (hcint & HCINTMSK_FRMOVRUN) {
2105                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2106                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2107                         goto exit;
2108         }
2109         if (hcint & HCINTMSK_DATATGLERR) {
2110                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2111                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2112                         goto exit;
2113         }
2114
2115 exit:
2116         chan->hcint = 0;
2117 }
2118
2119 /*
2120  * This interrupt indicates that one or more host channels has a pending
2121  * interrupt. There are multiple conditions that can cause each host channel
2122  * interrupt. This function determines which conditions have occurred for each
2123  * host channel interrupt and handles them appropriately.
2124  */
2125 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2126 {
2127         u32 haint;
2128         int i;
2129
2130         haint = dwc2_readl(hsotg->regs + HAINT);
2131         if (dbg_perio()) {
2132                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2133
2134                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2135         }
2136
2137         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2138                 if (haint & (1 << i))
2139                         dwc2_hc_n_intr(hsotg, i);
2140         }
2141 }
2142
2143 /* This function handles interrupts for the HCD */
2144 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2145 {
2146         u32 gintsts, dbg_gintsts;
2147         irqreturn_t retval = IRQ_NONE;
2148
2149         if (!dwc2_is_controller_alive(hsotg)) {
2150                 dev_warn(hsotg->dev, "Controller is dead\n");
2151                 return retval;
2152         }
2153
2154         spin_lock(&hsotg->lock);
2155
2156         /* Check if HOST Mode */
2157         if (dwc2_is_host_mode(hsotg)) {
2158                 gintsts = dwc2_read_core_intr(hsotg);
2159                 if (!gintsts) {
2160                         spin_unlock(&hsotg->lock);
2161                         return retval;
2162                 }
2163
2164                 retval = IRQ_HANDLED;
2165
2166                 dbg_gintsts = gintsts;
2167 #ifndef DEBUG_SOF
2168                 dbg_gintsts &= ~GINTSTS_SOF;
2169 #endif
2170                 if (!dbg_perio())
2171                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2172                                          GINTSTS_PTXFEMP);
2173
2174                 /* Only print if there are any non-suppressed interrupts left */
2175                 if (dbg_gintsts)
2176                         dev_vdbg(hsotg->dev,
2177                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2178                                  gintsts);
2179
2180                 if (gintsts & GINTSTS_SOF)
2181                         dwc2_sof_intr(hsotg);
2182                 if (gintsts & GINTSTS_RXFLVL)
2183                         dwc2_rx_fifo_level_intr(hsotg);
2184                 if (gintsts & GINTSTS_NPTXFEMP)
2185                         dwc2_np_tx_fifo_empty_intr(hsotg);
2186                 if (gintsts & GINTSTS_PRTINT)
2187                         dwc2_port_intr(hsotg);
2188                 if (gintsts & GINTSTS_HCHINT)
2189                         dwc2_hc_intr(hsotg);
2190                 if (gintsts & GINTSTS_PTXFEMP)
2191                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2192
2193                 if (dbg_gintsts) {
2194                         dev_vdbg(hsotg->dev,
2195                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2196                         dev_vdbg(hsotg->dev,
2197                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2198                                  dwc2_readl(hsotg->regs + GINTSTS),
2199                                  dwc2_readl(hsotg->regs + GINTMSK));
2200                 }
2201         }
2202
2203         spin_unlock(&hsotg->lock);
2204
2205         return retval;
2206 }