2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
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11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
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15 * 3. The names of the above-listed copyright holders may not be used
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17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors for Host mode
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
47 #include <linux/slab.h>
48 #include <linux/usb.h>
50 #include <linux/usb/hcd.h>
51 #include <linux/usb/ch11.h>
57 * dwc2_qh_init() - Initializes a QH structure
59 * @hsotg: The HCD state structure for the DWC OTG controller
61 * @urb: Holds the information about the device/endpoint needed to initialize
64 #define SCHEDULE_SLOP 10
65 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
66 struct dwc2_hcd_urb *urb)
68 int dev_speed, hub_addr, hub_port;
71 dev_vdbg(hsotg->dev, "%s()\n", __func__);
74 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
75 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
77 qh->data_toggle = DWC2_HC_PID_DATA0;
78 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
79 INIT_LIST_HEAD(&qh->qtd_list);
80 INIT_LIST_HEAD(&qh->qh_list_entry);
82 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */
83 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
85 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
87 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
88 hub_addr != 0 && hub_addr != 1) {
90 "QH init: EP %d: TT found at hub addr %d, for port %d\n",
91 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
96 if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
97 qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
98 /* Compute scheduling parameters once and save them */
101 /* Todo: Account for split transfers in the bus time */
103 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
105 qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ?
106 USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
107 qh->ep_type == USB_ENDPOINT_XFER_ISOC,
110 /* Ensure frame_number corresponds to the reality */
111 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
112 /* Start in a slightly future (micro)frame */
113 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
115 qh->interval = urb->interval;
117 /* Increase interrupt polling rate for debugging */
118 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
121 hprt = dwc2_readl(hsotg->regs + HPRT0);
122 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
123 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
124 (dev_speed == USB_SPEED_LOW ||
125 dev_speed == USB_SPEED_FULL)) {
127 qh->sched_frame |= 0x7;
128 qh->start_split_frame = qh->sched_frame;
130 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval);
133 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
134 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
135 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
136 dwc2_hcd_get_dev_addr(&urb->pipe_info));
137 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
138 dwc2_hcd_get_ep_num(&urb->pipe_info),
139 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
141 qh->dev_speed = dev_speed;
157 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
159 switch (qh->ep_type) {
160 case USB_ENDPOINT_XFER_ISOC:
161 type = "isochronous";
163 case USB_ENDPOINT_XFER_INT:
166 case USB_ENDPOINT_XFER_CONTROL:
169 case USB_ENDPOINT_XFER_BULK:
177 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
179 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
180 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
182 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
188 * dwc2_hcd_qh_create() - Allocates and initializes a QH
190 * @hsotg: The HCD state structure for the DWC OTG controller
191 * @urb: Holds the information about the device/endpoint needed
192 * to initialize the QH
193 * @atomic_alloc: Flag to do atomic allocation if needed
195 * Return: Pointer to the newly allocated QH, or NULL on error
197 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
198 struct dwc2_hcd_urb *urb,
206 /* Allocate memory */
207 qh = kzalloc(sizeof(*qh), mem_flags);
211 dwc2_qh_init(hsotg, qh, urb);
213 if (hsotg->core_params->dma_desc_enable > 0 &&
214 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
215 dwc2_hcd_qh_free(hsotg, qh);
223 * dwc2_hcd_qh_free() - Frees the QH
225 * @hsotg: HCD instance
226 * @qh: The QH to free
228 * QH should already be removed from the list. QTD list should already be empty
229 * if called from URB Dequeue.
231 * Must NOT be called with interrupt disabled or spinlock held
233 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
236 dwc2_hcd_qh_free_ddma(hsotg, qh);
241 * dwc2_periodic_channel_available() - Checks that a channel is available for a
244 * @hsotg: The HCD state structure for the DWC OTG controller
246 * Return: 0 if successful, negative error code otherwise
248 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
251 * Currently assuming that there is a dedicated host channel for
252 * each periodic transaction plus at least one host channel for
253 * non-periodic transactions
258 num_channels = hsotg->core_params->host_channels;
259 if (hsotg->periodic_channels + hsotg->non_periodic_channels <
261 && hsotg->periodic_channels < num_channels - 1) {
265 "%s: Total channels: %d, Periodic: %d, "
266 "Non-periodic: %d\n", __func__, num_channels,
267 hsotg->periodic_channels, hsotg->non_periodic_channels);
275 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
276 * for the specified QH in the periodic schedule
278 * @hsotg: The HCD state structure for the DWC OTG controller
279 * @qh: QH containing periodic bandwidth required
281 * Return: 0 if successful, negative error code otherwise
283 * For simplicity, this calculation assumes that all the transfers in the
284 * periodic schedule may occur in the same (micro)frame
286 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
290 s16 max_claimed_usecs;
294 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
297 * Max periodic usecs is 80% x 125 usec = 100 usec
299 max_claimed_usecs = 100 - qh->usecs;
303 * Max periodic usecs is 90% x 1000 usec = 900 usec
305 max_claimed_usecs = 900 - qh->usecs;
308 if (hsotg->periodic_usecs > max_claimed_usecs) {
310 "%s: already claimed usecs %d, required usecs %d\n",
311 __func__, hsotg->periodic_usecs, qh->usecs);
319 * Microframe scheduler
320 * track the total use in hsotg->frame_usecs
321 * keep each qh use in qh->frame_usecs
322 * when surrendering the qh then donate the time back
324 static const unsigned short max_uframe_usecs[] = {
325 100, 100, 100, 100, 100, 100, 30, 0
328 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg)
332 for (i = 0; i < 8; i++)
333 hsotg->frame_usecs[i] = max_uframe_usecs[i];
336 static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
338 unsigned short utime = qh->usecs;
341 for (i = 0; i < 8; i++) {
342 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */
343 if (utime <= hsotg->frame_usecs[i]) {
344 hsotg->frame_usecs[i] -= utime;
345 qh->frame_usecs[i] += utime;
353 * use this for FS apps that can span multiple uframes
355 static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
357 unsigned short utime = qh->usecs;
358 unsigned short xtime;
364 for (i = 0; i < 8; i++) {
365 if (hsotg->frame_usecs[i] <= 0)
369 * we need n consecutive slots so use j as a start slot
370 * j plus j+1 must be enough time (for now)
372 xtime = hsotg->frame_usecs[i];
373 for (j = i + 1; j < 8; j++) {
375 * if we add this frame remaining time to xtime we may
376 * be OK, if not we need to test j for a complete frame
378 if (xtime + hsotg->frame_usecs[j] < utime) {
379 if (hsotg->frame_usecs[j] <
383 if (xtime >= utime) {
385 for (k = i; k < 8; k++) {
386 t_left -= hsotg->frame_usecs[k];
388 qh->frame_usecs[k] +=
389 hsotg->frame_usecs[k]
391 hsotg->frame_usecs[k] = -t_left;
394 qh->frame_usecs[k] +=
395 hsotg->frame_usecs[k];
396 hsotg->frame_usecs[k] = 0;
400 /* add the frame time to x time */
401 xtime += hsotg->frame_usecs[j];
402 /* we must have a fully available next frame or break */
404 hsotg->frame_usecs[j] == max_uframe_usecs[j])
411 static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
415 if (qh->dev_speed == USB_SPEED_HIGH) {
416 /* if this is a hs transaction we need a full frame */
417 ret = dwc2_find_single_uframe(hsotg, qh);
420 * if this is a fs transaction we may need a sequence
423 ret = dwc2_find_multi_uframe(hsotg, qh);
429 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
430 * host channel is large enough to handle the maximum data transfer in a single
431 * (micro)frame for a periodic transfer
433 * @hsotg: The HCD state structure for the DWC OTG controller
434 * @qh: QH for a periodic endpoint
436 * Return: 0 if successful, negative error code otherwise
438 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
442 u32 max_channel_xfer_size;
445 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
446 max_channel_xfer_size = hsotg->core_params->max_transfer_size;
448 if (max_xfer_size > max_channel_xfer_size) {
450 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
451 __func__, max_xfer_size, max_channel_xfer_size);
459 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
460 * the periodic schedule
462 * @hsotg: The HCD state structure for the DWC OTG controller
463 * @qh: QH for the periodic transfer. The QH should already contain the
464 * scheduling information.
466 * Return: 0 if successful, negative error code otherwise
468 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
472 if (hsotg->core_params->uframe_sched > 0) {
475 status = dwc2_find_uframe(hsotg, qh);
481 /* Set the new frame up */
483 qh->sched_frame &= ~0x7;
484 qh->sched_frame |= (frame & 7);
490 status = dwc2_periodic_channel_available(hsotg);
493 "%s: No host channel available for periodic transfer\n",
498 status = dwc2_check_periodic_bandwidth(hsotg, qh);
503 "%s: Insufficient periodic bandwidth for periodic transfer\n",
508 status = dwc2_check_max_xfer_size(hsotg, qh);
511 "%s: Channel max transfer size too small for periodic transfer\n",
516 if (hsotg->core_params->dma_desc_enable > 0)
517 /* Don't rely on SOF and start in ready schedule */
518 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
520 /* Always start in inactive schedule */
521 list_add_tail(&qh->qh_list_entry,
522 &hsotg->periodic_sched_inactive);
524 if (hsotg->core_params->uframe_sched <= 0)
525 /* Reserve periodic channel */
526 hsotg->periodic_channels++;
528 /* Update claimed usecs per (micro)frame */
529 hsotg->periodic_usecs += qh->usecs;
535 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
536 * from the periodic schedule
538 * @hsotg: The HCD state structure for the DWC OTG controller
539 * @qh: QH for the periodic transfer
541 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
546 list_del_init(&qh->qh_list_entry);
548 /* Update claimed usecs per (micro)frame */
549 hsotg->periodic_usecs -= qh->usecs;
551 if (hsotg->core_params->uframe_sched > 0) {
552 for (i = 0; i < 8; i++) {
553 hsotg->frame_usecs[i] += qh->frame_usecs[i];
554 qh->frame_usecs[i] = 0;
557 /* Release periodic channel reservation */
558 hsotg->periodic_channels--;
563 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
564 * schedule if it is not already in the schedule. If the QH is already in
565 * the schedule, no action is taken.
567 * @hsotg: The HCD state structure for the DWC OTG controller
570 * Return: 0 if successful, negative error code otherwise
572 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
578 dev_vdbg(hsotg->dev, "%s()\n", __func__);
580 if (!list_empty(&qh->qh_list_entry))
581 /* QH already in a schedule */
584 if (!dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number) &&
585 !hsotg->frame_number) {
587 "reset frame number counter\n");
588 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number,
592 /* Add the new QH to the appropriate schedule */
593 if (dwc2_qh_is_non_per(qh)) {
594 /* Always start in inactive schedule */
595 list_add_tail(&qh->qh_list_entry,
596 &hsotg->non_periodic_sched_inactive);
600 status = dwc2_schedule_periodic(hsotg, qh);
603 if (!hsotg->periodic_qh_count) {
604 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
605 intr_mask |= GINTSTS_SOF;
606 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
608 hsotg->periodic_qh_count++;
614 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
615 * schedule. Memory is not freed.
617 * @hsotg: The HCD state structure
618 * @qh: QH to remove from schedule
620 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
624 dev_vdbg(hsotg->dev, "%s()\n", __func__);
626 if (list_empty(&qh->qh_list_entry))
627 /* QH is not in a schedule */
630 if (dwc2_qh_is_non_per(qh)) {
631 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
632 hsotg->non_periodic_qh_ptr =
633 hsotg->non_periodic_qh_ptr->next;
634 list_del_init(&qh->qh_list_entry);
638 dwc2_deschedule_periodic(hsotg, qh);
639 hsotg->periodic_qh_count--;
640 if (!hsotg->periodic_qh_count) {
641 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
642 intr_mask &= ~GINTSTS_SOF;
643 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
648 * Schedule the next continuing periodic split transfer
650 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
651 struct dwc2_qh *qh, u16 frame_number,
652 int sched_next_periodic_split)
656 if (sched_next_periodic_split) {
657 qh->sched_frame = frame_number;
658 incr = dwc2_frame_num_inc(qh->start_split_frame, 1);
659 if (dwc2_frame_num_le(frame_number, incr)) {
661 * Allow one frame to elapse after start split
662 * microframe before scheduling complete split, but
663 * DON'T if we are doing the next start split in the
664 * same frame for an ISOC out
666 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
669 dwc2_frame_num_inc(qh->sched_frame, 1);
673 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame,
675 if (dwc2_frame_num_le(qh->sched_frame, frame_number))
676 qh->sched_frame = frame_number;
677 qh->sched_frame |= 0x7;
678 qh->start_split_frame = qh->sched_frame;
683 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
684 * non-periodic schedule. The QH is added to the inactive non-periodic
685 * schedule if any QTDs are still attached to the QH.
687 * For periodic QHs, the QH is removed from the periodic queued schedule. If
688 * there are any QTDs still attached to the QH, the QH is added to either the
689 * periodic inactive schedule or the periodic ready schedule and its next
690 * scheduled frame is calculated. The QH is placed in the ready schedule if
691 * the scheduled frame has been reached already. Otherwise it's placed in the
692 * inactive schedule. If there are no QTDs attached to the QH, the QH is
693 * completely removed from the periodic schedule.
695 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
696 int sched_next_periodic_split)
701 dev_vdbg(hsotg->dev, "%s()\n", __func__);
703 if (dwc2_qh_is_non_per(qh)) {
704 dwc2_hcd_qh_unlink(hsotg, qh);
705 if (!list_empty(&qh->qtd_list))
706 /* Add back to inactive non-periodic schedule */
707 dwc2_hcd_qh_add(hsotg, qh);
711 frame_number = dwc2_hcd_get_frame_number(hsotg);
714 dwc2_sched_periodic_split(hsotg, qh, frame_number,
715 sched_next_periodic_split);
717 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame,
719 if (dwc2_frame_num_le(qh->sched_frame, frame_number))
720 qh->sched_frame = frame_number;
723 if (list_empty(&qh->qtd_list)) {
724 dwc2_hcd_qh_unlink(hsotg, qh);
728 * Remove from periodic_sched_queued and move to
731 if ((hsotg->core_params->uframe_sched > 0 &&
732 dwc2_frame_num_le(qh->sched_frame, frame_number)) ||
733 (hsotg->core_params->uframe_sched <= 0 &&
734 qh->sched_frame == frame_number))
735 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
737 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive);
741 * dwc2_hcd_qtd_init() - Initializes a QTD structure
743 * @qtd: The QTD to initialize
744 * @urb: The associated URB
746 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
749 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
750 USB_ENDPOINT_XFER_CONTROL) {
752 * The only time the QTD data toggle is used is on the data
753 * phase of control transfers. This phase always starts with
756 qtd->data_toggle = DWC2_HC_PID_DATA1;
757 qtd->control_phase = DWC2_CONTROL_SETUP;
761 qtd->complete_split = 0;
762 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
763 qtd->isoc_split_offset = 0;
766 /* Store the qtd ptr in the urb to reference the QTD */
771 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
772 * Caller must hold driver lock.
774 * @hsotg: The DWC HCD structure
775 * @qtd: The QTD to add
776 * @qh: Queue head to add qtd to
778 * Return: 0 if successful, negative error code otherwise
780 * If the QH to which the QTD is added is not currently scheduled, it is placed
781 * into the proper schedule based on its EP type.
783 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
789 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
794 retval = dwc2_hcd_qh_add(hsotg, qh);
799 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);