2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the functions to manage Queue Heads and Queue
39 * Transfer Descriptors for Host mode
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
47 #include <linux/slab.h>
48 #include <linux/usb.h>
50 #include <linux/usb/hcd.h>
51 #include <linux/usb/ch11.h>
56 /* Wait this long before releasing periodic reservation */
57 #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
60 * dwc2_do_unreserve() - Actually release the periodic reservation
62 * This function actually releases the periodic bandwidth that was reserved
65 * @hsotg: The HCD state structure for the DWC OTG controller
66 * @qh: QH for the periodic transfer.
68 static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
70 assert_spin_locked(&hsotg->lock);
72 WARN_ON(!qh->unreserve_pending);
74 /* No more unreserve pending--we're doing it */
75 qh->unreserve_pending = false;
77 if (WARN_ON(!list_empty(&qh->qh_list_entry)))
78 list_del_init(&qh->qh_list_entry);
80 /* Update claimed usecs per (micro)frame */
81 hsotg->periodic_usecs -= qh->host_us;
83 if (hsotg->core_params->uframe_sched > 0) {
86 for (i = 0; i < 8; i++) {
87 hsotg->frame_usecs[i] += qh->frame_usecs[i];
88 qh->frame_usecs[i] = 0;
91 /* Release periodic channel reservation */
92 hsotg->periodic_channels--;
97 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
99 * According to the kernel doc for usb_submit_urb() (specifically the part about
100 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
101 * long as a device driver keeps submitting. Since we're using HCD_BH to give
102 * back the URB we need to give the driver a little bit of time before we
103 * release the reservation. This worker is called after the appropriate
106 * @work: Pointer to a qh unreserve_work.
108 static void dwc2_unreserve_timer_fn(unsigned long data)
110 struct dwc2_qh *qh = (struct dwc2_qh *)data;
111 struct dwc2_hsotg *hsotg = qh->hsotg;
115 * Wait for the lock, or for us to be scheduled again. We
116 * could be scheduled again if:
117 * - We started executing but didn't get the lock yet.
118 * - A new reservation came in, but cancel didn't take effect
119 * because we already started executing.
120 * - The timer has been kicked again.
121 * In that case cancel and wait for the next call.
123 while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
124 if (timer_pending(&qh->unreserve_timer))
129 * Might be no more unreserve pending if:
130 * - We started executing but didn't get the lock yet.
131 * - A new reservation came in, but cancel didn't take effect
132 * because we already started executing.
134 * We can't put this in the loop above because unreserve_pending needs
135 * to be accessed under lock, so we can only check it once we got the
138 if (qh->unreserve_pending)
139 dwc2_do_unreserve(hsotg, qh);
141 spin_unlock_irqrestore(&hsotg->lock, flags);
145 * dwc2_qh_init() - Initializes a QH structure
147 * @hsotg: The HCD state structure for the DWC OTG controller
148 * @qh: The QH to init
149 * @urb: Holds the information about the device/endpoint needed to initialize
152 #define SCHEDULE_SLOP 10
153 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
154 struct dwc2_hcd_urb *urb)
156 int dev_speed, hub_addr, hub_port;
159 dev_vdbg(hsotg->dev, "%s()\n", __func__);
163 setup_timer(&qh->unreserve_timer, dwc2_unreserve_timer_fn,
165 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
166 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
168 qh->data_toggle = DWC2_HC_PID_DATA0;
169 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info);
170 INIT_LIST_HEAD(&qh->qtd_list);
171 INIT_LIST_HEAD(&qh->qh_list_entry);
173 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */
174 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
176 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
178 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) &&
179 hub_addr != 0 && hub_addr != 1) {
181 "QH init: EP %d: TT found at hub addr %d, for port %d\n",
182 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr,
187 if (qh->ep_type == USB_ENDPOINT_XFER_INT ||
188 qh->ep_type == USB_ENDPOINT_XFER_ISOC) {
189 /* Compute scheduling parameters once and save them */
192 /* Todo: Account for split transfers in the bus time */
194 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp);
196 qh->host_us = NS_TO_US(usb_calc_bus_time(qh->do_split ?
197 USB_SPEED_HIGH : dev_speed, qh->ep_is_in,
198 qh->ep_type == USB_ENDPOINT_XFER_ISOC,
201 /* Ensure frame_number corresponds to the reality */
202 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
203 /* Start in a slightly future (micro)frame */
204 qh->next_active_frame = dwc2_frame_num_inc(hsotg->frame_number,
206 qh->host_interval = urb->interval;
207 dwc2_sch_dbg(hsotg, "QH=%p init nxt=%04x, fn=%04x, int=%#x\n",
208 qh, qh->next_active_frame, hsotg->frame_number,
211 /* Increase interrupt polling rate for debugging */
212 if (qh->ep_type == USB_ENDPOINT_XFER_INT)
213 qh->host_interval = 8;
215 hprt = dwc2_readl(hsotg->regs + HPRT0);
216 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
217 if (prtspd == HPRT0_SPD_HIGH_SPEED &&
218 (dev_speed == USB_SPEED_LOW ||
219 dev_speed == USB_SPEED_FULL)) {
220 qh->host_interval *= 8;
221 qh->next_active_frame |= 0x7;
222 qh->start_split_frame = qh->next_active_frame;
224 "QH=%p init*8 nxt=%04x, fn=%04x, int=%#x\n",
225 qh, qh->next_active_frame,
226 hsotg->frame_number, qh->host_interval);
229 dev_dbg(hsotg->dev, "interval=%d\n", qh->host_interval);
232 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n");
233 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh);
234 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n",
235 dwc2_hcd_get_dev_addr(&urb->pipe_info));
236 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n",
237 dwc2_hcd_get_ep_num(&urb->pipe_info),
238 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
240 qh->dev_speed = dev_speed;
256 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed);
258 switch (qh->ep_type) {
259 case USB_ENDPOINT_XFER_ISOC:
260 type = "isochronous";
262 case USB_ENDPOINT_XFER_INT:
265 case USB_ENDPOINT_XFER_CONTROL:
268 case USB_ENDPOINT_XFER_BULK:
276 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type);
278 if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
279 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n",
281 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n",
287 * dwc2_hcd_qh_create() - Allocates and initializes a QH
289 * @hsotg: The HCD state structure for the DWC OTG controller
290 * @urb: Holds the information about the device/endpoint needed
291 * to initialize the QH
292 * @atomic_alloc: Flag to do atomic allocation if needed
294 * Return: Pointer to the newly allocated QH, or NULL on error
296 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
297 struct dwc2_hcd_urb *urb,
305 /* Allocate memory */
306 qh = kzalloc(sizeof(*qh), mem_flags);
310 dwc2_qh_init(hsotg, qh, urb);
312 if (hsotg->core_params->dma_desc_enable > 0 &&
313 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
314 dwc2_hcd_qh_free(hsotg, qh);
322 * dwc2_hcd_qh_free() - Frees the QH
324 * @hsotg: HCD instance
325 * @qh: The QH to free
327 * QH should already be removed from the list. QTD list should already be empty
328 * if called from URB Dequeue.
330 * Must NOT be called with interrupt disabled or spinlock held
332 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
334 /* Make sure any unreserve work is finished. */
335 if (del_timer_sync(&qh->unreserve_timer)) {
338 spin_lock_irqsave(&hsotg->lock, flags);
339 dwc2_do_unreserve(hsotg, qh);
340 spin_unlock_irqrestore(&hsotg->lock, flags);
344 dwc2_hcd_qh_free_ddma(hsotg, qh);
349 * dwc2_periodic_channel_available() - Checks that a channel is available for a
352 * @hsotg: The HCD state structure for the DWC OTG controller
354 * Return: 0 if successful, negative error code otherwise
356 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
359 * Currently assuming that there is a dedicated host channel for
360 * each periodic transaction plus at least one host channel for
361 * non-periodic transactions
366 num_channels = hsotg->core_params->host_channels;
367 if (hsotg->periodic_channels + hsotg->non_periodic_channels <
369 && hsotg->periodic_channels < num_channels - 1) {
373 "%s: Total channels: %d, Periodic: %d, "
374 "Non-periodic: %d\n", __func__, num_channels,
375 hsotg->periodic_channels, hsotg->non_periodic_channels);
383 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
384 * for the specified QH in the periodic schedule
386 * @hsotg: The HCD state structure for the DWC OTG controller
387 * @qh: QH containing periodic bandwidth required
389 * Return: 0 if successful, negative error code otherwise
391 * For simplicity, this calculation assumes that all the transfers in the
392 * periodic schedule may occur in the same (micro)frame
394 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
398 s16 max_claimed_usecs;
402 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
405 * Max periodic usecs is 80% x 125 usec = 100 usec
407 max_claimed_usecs = 100 - qh->host_us;
411 * Max periodic usecs is 90% x 1000 usec = 900 usec
413 max_claimed_usecs = 900 - qh->host_us;
416 if (hsotg->periodic_usecs > max_claimed_usecs) {
418 "%s: already claimed usecs %d, required usecs %d\n",
419 __func__, hsotg->periodic_usecs, qh->host_us);
427 * Microframe scheduler
428 * track the total use in hsotg->frame_usecs
429 * keep each qh use in qh->frame_usecs
430 * when surrendering the qh then donate the time back
432 static const unsigned short max_uframe_usecs[] = {
433 100, 100, 100, 100, 100, 100, 30, 0
436 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg)
440 for (i = 0; i < 8; i++)
441 hsotg->frame_usecs[i] = max_uframe_usecs[i];
444 static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
446 unsigned short utime = qh->host_us;
449 for (i = 0; i < 8; i++) {
450 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */
451 if (utime <= hsotg->frame_usecs[i]) {
452 hsotg->frame_usecs[i] -= utime;
453 qh->frame_usecs[i] += utime;
461 * use this for FS apps that can span multiple uframes
463 static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
465 unsigned short utime = qh->host_us;
466 unsigned short xtime;
472 for (i = 0; i < 8; i++) {
473 if (hsotg->frame_usecs[i] <= 0)
477 * we need n consecutive slots so use j as a start slot
478 * j plus j+1 must be enough time (for now)
480 xtime = hsotg->frame_usecs[i];
481 for (j = i + 1; j < 8; j++) {
483 * if we add this frame remaining time to xtime we may
484 * be OK, if not we need to test j for a complete frame
486 if (xtime + hsotg->frame_usecs[j] < utime) {
487 if (hsotg->frame_usecs[j] <
491 if (xtime >= utime) {
493 for (k = i; k < 8; k++) {
494 t_left -= hsotg->frame_usecs[k];
496 qh->frame_usecs[k] +=
497 hsotg->frame_usecs[k]
499 hsotg->frame_usecs[k] = -t_left;
502 qh->frame_usecs[k] +=
503 hsotg->frame_usecs[k];
504 hsotg->frame_usecs[k] = 0;
508 /* add the frame time to x time */
509 xtime += hsotg->frame_usecs[j];
510 /* we must have a fully available next frame or break */
512 hsotg->frame_usecs[j] == max_uframe_usecs[j])
519 static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
523 if (qh->dev_speed == USB_SPEED_HIGH) {
524 /* if this is a hs transaction we need a full frame */
525 ret = dwc2_find_single_uframe(hsotg, qh);
528 * if this is a fs transaction we may need a sequence
531 ret = dwc2_find_multi_uframe(hsotg, qh);
537 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
538 * host channel is large enough to handle the maximum data transfer in a single
539 * (micro)frame for a periodic transfer
541 * @hsotg: The HCD state structure for the DWC OTG controller
542 * @qh: QH for a periodic endpoint
544 * Return: 0 if successful, negative error code otherwise
546 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
550 u32 max_channel_xfer_size;
553 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp);
554 max_channel_xfer_size = hsotg->core_params->max_transfer_size;
556 if (max_xfer_size > max_channel_xfer_size) {
558 "%s: Periodic xfer length %d > max xfer length for channel %d\n",
559 __func__, max_xfer_size, max_channel_xfer_size);
567 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
568 * the periodic schedule
570 * @hsotg: The HCD state structure for the DWC OTG controller
571 * @qh: QH for the periodic transfer. The QH should already contain the
572 * scheduling information.
574 * Return: 0 if successful, negative error code otherwise
576 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
580 status = dwc2_check_max_xfer_size(hsotg, qh);
583 "%s: Channel max transfer size too small for periodic transfer\n",
588 /* Cancel pending unreserve; if canceled OK, unreserve was pending */
589 if (del_timer(&qh->unreserve_timer))
590 WARN_ON(!qh->unreserve_pending);
593 * Only need to reserve if there's not an unreserve pending, since if an
594 * unreserve is pending then by definition our old reservation is still
595 * valid. Unreserve might still be pending even if we didn't cancel if
596 * dwc2_unreserve_timer_fn() already started. Code in the timer handles
599 if (!qh->unreserve_pending) {
600 if (hsotg->core_params->uframe_sched > 0) {
603 status = dwc2_find_uframe(hsotg, qh);
609 /* Set the new frame up */
611 qh->next_active_frame &= ~0x7;
612 qh->next_active_frame |= (frame & 7);
614 "QH=%p sched_p nxt=%04x, uf=%d\n",
615 qh, qh->next_active_frame, frame);
621 status = dwc2_periodic_channel_available(hsotg);
624 "%s: No host channel available for periodic transfer\n",
629 status = dwc2_check_periodic_bandwidth(hsotg, qh);
634 "%s: Insufficient periodic bandwidth for periodic transfer\n",
639 if (hsotg->core_params->uframe_sched <= 0)
640 /* Reserve periodic channel */
641 hsotg->periodic_channels++;
643 /* Update claimed usecs per (micro)frame */
644 hsotg->periodic_usecs += qh->host_us;
647 qh->unreserve_pending = 0;
649 if (hsotg->core_params->dma_desc_enable > 0)
650 /* Don't rely on SOF and start in ready schedule */
651 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
653 /* Always start in inactive schedule */
654 list_add_tail(&qh->qh_list_entry,
655 &hsotg->periodic_sched_inactive);
661 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
662 * from the periodic schedule
664 * @hsotg: The HCD state structure for the DWC OTG controller
665 * @qh: QH for the periodic transfer
667 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
672 assert_spin_locked(&hsotg->lock);
675 * Schedule the unreserve to happen in a little bit. Cases here:
676 * - Unreserve worker might be sitting there waiting to grab the lock.
677 * In this case it will notice it's been schedule again and will
679 * - Unreserve worker might not be scheduled.
681 * We should never already be scheduled since dwc2_schedule_periodic()
682 * should have canceled the scheduled unreserve timer (hence the
683 * warning on did_modify).
685 * We add + 1 to the timer to guarantee that at least 1 jiffy has
686 * passed (otherwise if the jiffy counter might tick right after we
687 * read it and we'll get no delay).
689 did_modify = mod_timer(&qh->unreserve_timer,
690 jiffies + DWC2_UNRESERVE_DELAY + 1);
692 qh->unreserve_pending = 1;
694 list_del_init(&qh->qh_list_entry);
698 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
699 * schedule if it is not already in the schedule. If the QH is already in
700 * the schedule, no action is taken.
702 * @hsotg: The HCD state structure for the DWC OTG controller
705 * Return: 0 if successful, negative error code otherwise
707 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
713 dev_vdbg(hsotg->dev, "%s()\n", __func__);
715 if (!list_empty(&qh->qh_list_entry))
716 /* QH already in a schedule */
719 if (!dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number) &&
720 !hsotg->frame_number) {
724 "reset frame number counter\n");
725 new_frame = dwc2_frame_num_inc(hsotg->frame_number,
728 dwc2_sch_vdbg(hsotg, "QH=%p reset nxt=%04x=>%04x\n",
729 qh, qh->next_active_frame, new_frame);
730 qh->next_active_frame = new_frame;
733 /* Add the new QH to the appropriate schedule */
734 if (dwc2_qh_is_non_per(qh)) {
735 /* Always start in inactive schedule */
736 list_add_tail(&qh->qh_list_entry,
737 &hsotg->non_periodic_sched_inactive);
741 status = dwc2_schedule_periodic(hsotg, qh);
744 if (!hsotg->periodic_qh_count) {
745 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
746 intr_mask |= GINTSTS_SOF;
747 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
749 hsotg->periodic_qh_count++;
755 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
756 * schedule. Memory is not freed.
758 * @hsotg: The HCD state structure
759 * @qh: QH to remove from schedule
761 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
765 dev_vdbg(hsotg->dev, "%s()\n", __func__);
767 if (list_empty(&qh->qh_list_entry))
768 /* QH is not in a schedule */
771 if (dwc2_qh_is_non_per(qh)) {
772 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
773 hsotg->non_periodic_qh_ptr =
774 hsotg->non_periodic_qh_ptr->next;
775 list_del_init(&qh->qh_list_entry);
779 dwc2_deschedule_periodic(hsotg, qh);
780 hsotg->periodic_qh_count--;
781 if (!hsotg->periodic_qh_count) {
782 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
783 intr_mask &= ~GINTSTS_SOF;
784 dwc2_writel(intr_mask, hsotg->regs + GINTMSK);
789 * Schedule the next continuing periodic split transfer
791 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg,
792 struct dwc2_qh *qh, u16 frame_number,
793 int sched_next_periodic_split)
796 u16 old_frame = qh->next_active_frame;
798 if (sched_next_periodic_split) {
799 qh->next_active_frame = frame_number;
800 incr = dwc2_frame_num_inc(qh->start_split_frame, 1);
801 if (dwc2_frame_num_le(frame_number, incr)) {
803 * Allow one frame to elapse after start split
804 * microframe before scheduling complete split, but
805 * DON'T if we are doing the next start split in the
806 * same frame for an ISOC out
808 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
810 qh->next_active_frame = dwc2_frame_num_inc(
811 qh->next_active_frame, 1);
815 qh->next_active_frame =
816 dwc2_frame_num_inc(qh->start_split_frame,
818 if (dwc2_frame_num_le(qh->next_active_frame, frame_number))
819 qh->next_active_frame = frame_number;
820 qh->next_active_frame |= 0x7;
821 qh->start_split_frame = qh->next_active_frame;
824 dwc2_sch_vdbg(hsotg, "QH=%p next(%d) fn=%04x, nxt=%04x=>%04x (%+d)\n",
825 qh, sched_next_periodic_split, frame_number, old_frame,
826 qh->next_active_frame,
827 dwc2_frame_num_dec(qh->next_active_frame, old_frame));
831 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
832 * non-periodic schedule. The QH is added to the inactive non-periodic
833 * schedule if any QTDs are still attached to the QH.
835 * For periodic QHs, the QH is removed from the periodic queued schedule. If
836 * there are any QTDs still attached to the QH, the QH is added to either the
837 * periodic inactive schedule or the periodic ready schedule and its next
838 * scheduled frame is calculated. The QH is placed in the ready schedule if
839 * the scheduled frame has been reached already. Otherwise it's placed in the
840 * inactive schedule. If there are no QTDs attached to the QH, the QH is
841 * completely removed from the periodic schedule.
843 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
844 int sched_next_periodic_split)
849 dev_vdbg(hsotg->dev, "%s()\n", __func__);
851 if (dwc2_qh_is_non_per(qh)) {
852 dwc2_hcd_qh_unlink(hsotg, qh);
853 if (!list_empty(&qh->qtd_list))
854 /* Add back to inactive non-periodic schedule */
855 dwc2_hcd_qh_add(hsotg, qh);
859 frame_number = dwc2_hcd_get_frame_number(hsotg);
862 dwc2_sched_periodic_split(hsotg, qh, frame_number,
863 sched_next_periodic_split);
865 qh->next_active_frame = dwc2_frame_num_inc(
866 qh->next_active_frame, qh->host_interval);
867 if (dwc2_frame_num_le(qh->next_active_frame, frame_number))
868 qh->next_active_frame = frame_number;
871 if (list_empty(&qh->qtd_list)) {
872 dwc2_hcd_qh_unlink(hsotg, qh);
876 * Remove from periodic_sched_queued and move to
879 if ((hsotg->core_params->uframe_sched > 0 &&
880 dwc2_frame_num_le(qh->next_active_frame, frame_number)) ||
881 (hsotg->core_params->uframe_sched <= 0 &&
882 qh->next_active_frame == frame_number))
883 list_move_tail(&qh->qh_list_entry,
884 &hsotg->periodic_sched_ready);
886 list_move_tail(&qh->qh_list_entry,
887 &hsotg->periodic_sched_inactive);
891 * dwc2_hcd_qtd_init() - Initializes a QTD structure
893 * @qtd: The QTD to initialize
894 * @urb: The associated URB
896 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
899 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
900 USB_ENDPOINT_XFER_CONTROL) {
902 * The only time the QTD data toggle is used is on the data
903 * phase of control transfers. This phase always starts with
906 qtd->data_toggle = DWC2_HC_PID_DATA1;
907 qtd->control_phase = DWC2_CONTROL_SETUP;
911 qtd->complete_split = 0;
912 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
913 qtd->isoc_split_offset = 0;
916 /* Store the qtd ptr in the urb to reference the QTD */
921 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
922 * Caller must hold driver lock.
924 * @hsotg: The DWC HCD structure
925 * @qtd: The QTD to add
926 * @qh: Queue head to add qtd to
928 * Return: 0 if successful, negative error code otherwise
930 * If the QH to which the QTD is added is not currently scheduled, it is placed
931 * into the proper schedule based on its EP type.
933 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
939 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
944 retval = dwc2_hcd_qh_add(hsotg, qh);
949 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);