drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_bcm2835 = {
  58         .otg_cap                        = 0,    /* HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .dma_desc_fs_enable             = 0,
  63         .speed                          = 0,    /* High Speed */
  64         .enable_dynamic_fifo            = 1,
  65         .en_multiple_tx_fifo            = 1,
  66         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  67         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
  68         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
  69         .max_transfer_size              = 65535,
  70         .max_packet_count               = 511,
  71         .host_channels                  = 8,
  72         .phy_type                       = 1,    /* UTMI */
  73         .phy_utmi_width                 = 8,    /* 8 bits */
  74         .phy_ulpi_ddr                   = 0,    /* Single */
  75         .phy_ulpi_ext_vbus              = 0,
  76         .i2c_enable                     = 0,
  77         .ulpi_fs_ls                     = 0,
  78         .host_support_fs_ls_low_power   = 0,
  79         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  80         .ts_dline                       = 0,
  81         .reload_ctl                     = 0,
  82         .ahbcfg                         = 0x10,
  83         .uframe_sched                   = 0,
  84         .external_id_pin_ctl            = -1,
  85         .hibernation                    = -1,
  86 };
  87
  88 static const struct dwc2_core_params params_rk3066 = {
  89         .otg_cap                        = 2,    /* non-HNP/non-SRP */
  90         .otg_ver                        = -1,
  91         .dma_enable                     = -1,
  92         .dma_desc_enable                = 0,
  93         .dma_desc_fs_enable             = 0,
  94         .speed                          = -1,
  95         .enable_dynamic_fifo            = 1,
  96         .en_multiple_tx_fifo            = -1,
  97         .host_rx_fifo_size              = 520,  /* 520 DWORDs */
  98         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
  99         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
 100         .max_transfer_size              = 65535,
 101         .max_packet_count               = -1,
 102         .host_channels                  = -1,
 103         .phy_type                       = -1,
 104         .phy_utmi_width                 = -1,
 105         .phy_ulpi_ddr                   = -1,
 106         .phy_ulpi_ext_vbus              = -1,
 107         .i2c_enable                     = -1,
 108         .ulpi_fs_ls                     = -1,
 109         .host_support_fs_ls_low_power   = -1,
 110         .host_ls_low_power_phy_clk      = -1,
 111         .ts_dline                       = -1,
 112         .reload_ctl                     = -1,
 113         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 114                                           GAHBCFG_HBSTLEN_SHIFT,
 115         .uframe_sched                   = -1,
 116         .external_id_pin_ctl            = -1,
 117         .hibernation                    = -1,
 118 };
 119
 120 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 121 {
 122         struct platform_device *pdev = to_platform_device(hsotg->dev);
 123         int ret;
 124
 125         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 126                                     hsotg->supplies);
 127         if (ret)
 128                 return ret;
 129
 130         if (hsotg->clk) {
 131                 ret = clk_prepare_enable(hsotg->clk);
 132                 if (ret)
 133                         return ret;
 134         }
 135
 136         if (hsotg->uphy)
 137                 ret = usb_phy_init(hsotg->uphy);
 138         else if (hsotg->plat && hsotg->plat->phy_init)
 139                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 140         else {
 141                 ret = phy_power_on(hsotg->phy);
 142                 if (ret == 0)
 143                         ret = phy_init(hsotg->phy);
 144         }
 145
 146         return ret;
 147 }
 148
 149 /**
 150  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 151  * @hsotg: The driver state
 152  *
 153  * A wrapper for platform code responsible for controlling
 154  * low-level USB platform resources (phy, clock, regulators)
 155  */
 156 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 157 {
 158         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 159
 160         if (ret == 0)
 161                 hsotg->ll_hw_enabled = true;
 162         return ret;
 163 }
 164
 165 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 166 {
 167         struct platform_device *pdev = to_platform_device(hsotg->dev);
 168         int ret = 0;
 169
 170         if (hsotg->uphy)
 171                 usb_phy_shutdown(hsotg->uphy);
 172         else if (hsotg->plat && hsotg->plat->phy_exit)
 173                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 174         else {
 175                 ret = phy_exit(hsotg->phy);
 176                 if (ret == 0)
 177                         ret = phy_power_off(hsotg->phy);
 178         }
 179         if (ret)
 180                 return ret;
 181
 182         if (hsotg->clk)
 183                 clk_disable_unprepare(hsotg->clk);
 184
 185         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 186                                      hsotg->supplies);
 187
 188         return ret;
 189 }
 190
 191 /**
 192  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 193  * @hsotg: The driver state
 194  *
 195  * A wrapper for platform code responsible for controlling
 196  * low-level USB platform resources (phy, clock, regulators)
 197  */
 198 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 199 {
 200         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 201
 202         if (ret == 0)
 203                 hsotg->ll_hw_enabled = false;
 204         return ret;
 205 }
 206
 207 /* Only used to reset usb phy at interrupter runtime */
 208 static void dwc2_reset_phy_work(struct work_struct *data)
 209 {
 210         struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
 211                         phy_rst_work);
 212         phy_reset(hsotg->phy);
 213 }
 214
 215 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 216 {
 217         int i, ret;
 218
 219         /* Set default UTMI width */
 220         hsotg->phyif = GUSBCFG_PHYIF16;
 221
 222         /*
 223          * Attempt to find a generic PHY, then look for an old style
 224          * USB PHY and then fall back to pdata
 225          */
 226         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 227         if (IS_ERR(hsotg->phy)) {
 228                 ret = PTR_ERR(hsotg->phy);
 229                 switch (ret) {
 230                 case -ENODEV:
 231                 case -ENOSYS:
 232                         hsotg->phy = NULL;
 233                         break;
 234                 case -EPROBE_DEFER:
 235                         return ret;
 236                 default:
 237                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 238                         return ret;
 239                 }
 240         }
 241         INIT_WORK(&hsotg->phy_rst_work, dwc2_reset_phy_work);
 242
 243         if (!hsotg->phy) {
 244                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 245                 if (IS_ERR(hsotg->uphy)) {
 246                         ret = PTR_ERR(hsotg->uphy);
 247                         switch (ret) {
 248                         case -ENODEV:
 249                         case -ENXIO:
 250                                 hsotg->uphy = NULL;
 251                                 break;
 252                         case -EPROBE_DEFER:
 253                                 return ret;
 254                         default:
 255                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 256                                         ret);
 257                                 return ret;
 258                         }
 259                 }
 260         }
 261
 262         hsotg->plat = dev_get_platdata(hsotg->dev);
 263
 264         if (hsotg->phy) {
 265                 /*
 266                  * If using the generic PHY framework, check if the PHY bus
 267                  * width is 8-bit and set the phyif appropriately.
 268                  */
 269                 if (phy_get_bus_width(hsotg->phy) == 8)
 270                         hsotg->phyif = GUSBCFG_PHYIF8;
 271         }
 272
 273         /* Clock */
 274         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 275         if (IS_ERR(hsotg->clk)) {
 276                 hsotg->clk = NULL;
 277                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 278         }
 279
 280         /* Regulators */
 281         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 282                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 283
 284         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 285                                       hsotg->supplies);
 286         if (ret) {
 287                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 288                 return ret;
 289         }
 290         return 0;
 291 }
 292
 293 /**
 294  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 295  * DWC_otg driver
 296  *
 297  * @dev: Platform device
 298  *
 299  * This routine is called, for example, when the rmmod command is executed. The
 300  * device may or may not be electrically present. If it is present, the driver
 301  * stops device processing. Any resources used on behalf of this device are
 302  * freed.
 303  */
 304 static int dwc2_driver_remove(struct platform_device *dev)
 305 {
 306         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 307
 308         dwc2_debugfs_exit(hsotg);
 309         if (hsotg->hcd_enabled)
 310                 dwc2_hcd_remove(hsotg);
 311         if (hsotg->gadget_enabled)
 312                 dwc2_hsotg_remove(hsotg);
 313
 314         if (hsotg->ll_hw_enabled)
 315                 dwc2_lowlevel_hw_disable(hsotg);
 316
 317         return 0;
 318 }
 319
 320 static const struct of_device_id dwc2_of_match_table[] = {
 321         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 322         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 323         { .compatible = "snps,dwc2", .data = NULL },
 324         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 325         {},
 326 };
 327 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 328
 329 /**
 330  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 331  * driver
 332  *
 333  * @dev: Platform device
 334  *
 335  * This routine creates the driver components required to control the device
 336  * (core, HCD, and PCD) and initializes the device. The driver components are
 337  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 338  * in the device private data. This allows the driver to access the dwc2_hsotg
 339  * structure on subsequent calls to driver methods for this device.
 340  */
 341 static int dwc2_driver_probe(struct platform_device *dev)
 342 {
 343         const struct of_device_id *match;
 344         const struct dwc2_core_params *params;
 345         struct dwc2_core_params defparams;
 346         struct dwc2_hsotg *hsotg;
 347         struct resource *res;
 348         int retval;
 349         int irq;
 350
 351         match = of_match_device(dwc2_of_match_table, &dev->dev);
 352         if (match && match->data) {
 353                 params = match->data;
 354         } else {
 355                 /* Default all params to autodetect */
 356                 dwc2_set_all_params(&defparams, -1);
 357                 params = &defparams;
 358
 359                 /*
 360                  * Disable descriptor dma mode by default as the HW can support
 361                  * it, but does not support it for SPLIT transactions.
 362                  * Disable it for FS devices as well.
 363                  */
 364                 defparams.dma_desc_enable = 0;
 365                 defparams.dma_desc_fs_enable = 0;
 366         }
 367
 368         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 369         if (!hsotg)
 370                 return -ENOMEM;
 371
 372         hsotg->dev = &dev->dev;
 373
 374         /*
 375          * Use reasonable defaults so platforms don't have to provide these.
 376          */
 377         if (!dev->dev.dma_mask)
 378                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 379         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 380         if (retval)
 381                 return retval;
 382
 383         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 384         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 385         if (IS_ERR(hsotg->regs))
 386                 return PTR_ERR(hsotg->regs);
 387
 388         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 389                 (unsigned long)res->start, hsotg->regs);
 390
 391         hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
 392         if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
 393                         hsotg->dr_mode != USB_DR_MODE_HOST) {
 394                 hsotg->dr_mode = USB_DR_MODE_HOST;
 395                 dev_warn(hsotg->dev,
 396                         "Configuration mismatch. Forcing host mode\n");
 397         } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
 398                         hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 399                 hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
 400                 dev_warn(hsotg->dev,
 401                         "Configuration mismatch. Forcing peripheral mode\n");
 402         }
 403
 404         retval = dwc2_lowlevel_hw_init(hsotg);
 405         if (retval)
 406                 return retval;
 407
 408         spin_lock_init(&hsotg->lock);
 409
 410         hsotg->core_params = devm_kzalloc(&dev->dev,
 411                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 412         if (!hsotg->core_params)
 413                 return -ENOMEM;
 414
 415         dwc2_set_all_params(hsotg->core_params, -1);
 416
 417         irq = platform_get_irq(dev, 0);
 418         if (irq < 0) {
 419                 dev_err(&dev->dev, "missing IRQ resource\n");
 420                 return irq;
 421         }
 422
 423         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 424                 irq);
 425         retval = devm_request_irq(hsotg->dev, irq,
 426                                   dwc2_handle_common_intr, IRQF_SHARED,
 427                                   dev_name(hsotg->dev), hsotg);
 428         if (retval)
 429                 return retval;
 430
 431         retval = dwc2_lowlevel_hw_enable(hsotg);
 432         if (retval)
 433                 return retval;
 434
 435         /*
 436          * Reset before dwc2_get_hwparams() then it could get power-on real
 437          * reset value form registers.
 438          */
 439         dwc2_core_reset(hsotg);
 440
 441         /* Detect config values from hardware */
 442         retval = dwc2_get_hwparams(hsotg);
 443         if (retval)
 444                 goto error;
 445
 446         /* Validate parameter values */
 447         dwc2_set_parameters(hsotg, params);
 448
 449         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 450                 retval = dwc2_gadget_init(hsotg, irq);
 451                 if (retval)
 452                         goto error;
 453                 hsotg->gadget_enabled = 1;
 454         }
 455
 456         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 457                 retval = dwc2_hcd_init(hsotg, irq);
 458                 if (retval) {
 459                         if (hsotg->gadget_enabled)
 460                                 dwc2_hsotg_remove(hsotg);
 461                         goto error;
 462                 }
 463                 hsotg->hcd_enabled = 1;
 464         }
 465
 466         platform_set_drvdata(dev, hsotg);
 467
 468         dwc2_debugfs_init(hsotg);
 469
 470         /* Gadget code manages lowlevel hw on its own */
 471         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 472                 dwc2_lowlevel_hw_disable(hsotg);
 473
 474         return 0;
 475
 476 error:
 477         dwc2_lowlevel_hw_disable(hsotg);
 478         return retval;
 479 }
 480
 481 static int __maybe_unused dwc2_suspend(struct device *dev)
 482 {
 483         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 484         int ret = 0;
 485
 486         if (dwc2_is_device_mode(dwc2))
 487                 dwc2_hsotg_suspend(dwc2);
 488
 489         if (dwc2->ll_hw_enabled)
 490                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 491
 492         return ret;
 493 }
 494
 495 static int __maybe_unused dwc2_resume(struct device *dev)
 496 {
 497         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 498         int ret = 0;
 499
 500         if (dwc2->ll_hw_enabled) {
 501                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 502                 if (ret)
 503                         return ret;
 504         }
 505
 506         if (dwc2_is_device_mode(dwc2))
 507                 ret = dwc2_hsotg_resume(dwc2);
 508
 509         return ret;
 510 }
 511
 512 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 513         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 514 };
 515
 516 static struct platform_driver dwc2_platform_driver = {
 517         .driver = {
 518                 .name = dwc2_driver_name,
 519                 .of_match_table = dwc2_of_match_table,
 520                 .pm = &dwc2_dev_pm_ops,
 521         },
 522         .probe = dwc2_driver_probe,
 523         .remove = dwc2_driver_remove,
 524 };
 525
 526 module_platform_driver(dwc2_platform_driver);
 527
 528 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 529 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 530 MODULE_LICENSE("Dual BSD/GPL");