drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_bcm2835 = {
  58         .otg_cap                        = 0,    /* HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .speed                          = 0,    /* High Speed */
  63         .enable_dynamic_fifo            = 1,
  64         .en_multiple_tx_fifo            = 1,
  65         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  66         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
  67         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
  68         .max_transfer_size              = 65535,
  69         .max_packet_count               = 511,
  70         .host_channels                  = 8,
  71         .phy_type                       = 1,    /* UTMI */
  72         .phy_utmi_width                 = 8,    /* 8 bits */
  73         .phy_ulpi_ddr                   = 0,    /* Single */
  74         .phy_ulpi_ext_vbus              = 0,
  75         .i2c_enable                     = 0,
  76         .ulpi_fs_ls                     = 0,
  77         .host_support_fs_ls_low_power   = 0,
  78         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  79         .ts_dline                       = 0,
  80         .reload_ctl                     = 0,
  81         .ahbcfg                         = 0x10,
  82         .uframe_sched                   = 0,
  83         .external_id_pin_ctl            = -1,
  84         .hibernation                    = -1,
  85 };
  86
  87 static const struct dwc2_core_params params_rk3066 = {
  88         .otg_cap                        = 2,    /* non-HNP/non-SRP */
  89         .otg_ver                        = -1,
  90         .dma_enable                     = -1,
  91         .dma_desc_enable                = 0,
  92         .speed                          = -1,
  93         .enable_dynamic_fifo            = 1,
  94         .en_multiple_tx_fifo            = -1,
  95         .host_rx_fifo_size              = 520,  /* 520 DWORDs */
  96         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
  97         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
  98         .max_transfer_size              = 65535,
  99         .max_packet_count               = -1,
 100         .host_channels                  = -1,
 101         .phy_type                       = -1,
 102         .phy_utmi_width                 = -1,
 103         .phy_ulpi_ddr                   = -1,
 104         .phy_ulpi_ext_vbus              = -1,
 105         .i2c_enable                     = -1,
 106         .ulpi_fs_ls                     = -1,
 107         .host_support_fs_ls_low_power   = -1,
 108         .host_ls_low_power_phy_clk      = -1,
 109         .ts_dline                       = -1,
 110         .reload_ctl                     = -1,
 111         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 112                                           GAHBCFG_HBSTLEN_SHIFT,
 113         .uframe_sched                   = -1,
 114         .external_id_pin_ctl            = -1,
 115         .hibernation                    = -1,
 116 };
 117
 118 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 119 {
 120         struct platform_device *pdev = to_platform_device(hsotg->dev);
 121         int ret;
 122
 123         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 124                                     hsotg->supplies);
 125         if (ret)
 126                 return ret;
 127
 128         if (hsotg->clk) {
 129                 ret = clk_prepare_enable(hsotg->clk);
 130                 if (ret)
 131                         return ret;
 132         }
 133
 134         if (hsotg->uphy)
 135                 ret = usb_phy_init(hsotg->uphy);
 136         else if (hsotg->plat && hsotg->plat->phy_init)
 137                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 138         else {
 139                 ret = phy_power_on(hsotg->phy);
 140                 if (ret == 0)
 141                         ret = phy_init(hsotg->phy);
 142         }
 143
 144         return ret;
 145 }
 146
 147 /**
 148  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 149  * @hsotg: The driver state
 150  *
 151  * A wrapper for platform code responsible for controlling
 152  * low-level USB platform resources (phy, clock, regulators)
 153  */
 154 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 155 {
 156         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 157
 158         if (ret == 0)
 159                 hsotg->ll_hw_enabled = true;
 160         return ret;
 161 }
 162
 163 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 164 {
 165         struct platform_device *pdev = to_platform_device(hsotg->dev);
 166         int ret = 0;
 167
 168         if (hsotg->uphy)
 169                 usb_phy_shutdown(hsotg->uphy);
 170         else if (hsotg->plat && hsotg->plat->phy_exit)
 171                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 172         else {
 173                 ret = phy_exit(hsotg->phy);
 174                 if (ret == 0)
 175                         ret = phy_power_off(hsotg->phy);
 176         }
 177         if (ret)
 178                 return ret;
 179
 180         if (hsotg->clk)
 181                 clk_disable_unprepare(hsotg->clk);
 182
 183         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 184                                      hsotg->supplies);
 185
 186         return ret;
 187 }
 188
 189 /**
 190  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 191  * @hsotg: The driver state
 192  *
 193  * A wrapper for platform code responsible for controlling
 194  * low-level USB platform resources (phy, clock, regulators)
 195  */
 196 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 197 {
 198         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 199
 200         if (ret == 0)
 201                 hsotg->ll_hw_enabled = false;
 202         return ret;
 203 }
 204
 205 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 206 {
 207         int i, ret;
 208
 209         /* Set default UTMI width */
 210         hsotg->phyif = GUSBCFG_PHYIF16;
 211
 212         /*
 213          * Attempt to find a generic PHY, then look for an old style
 214          * USB PHY and then fall back to pdata
 215          */
 216         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 217         if (IS_ERR(hsotg->phy)) {
 218                 ret = PTR_ERR(hsotg->phy);
 219                 switch (ret) {
 220                 case -ENODEV:
 221                 case -ENOSYS:
 222                         hsotg->phy = NULL;
 223                         break;
 224                 case -EPROBE_DEFER:
 225                         return ret;
 226                 default:
 227                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 228                         return ret;
 229                 }
 230         }
 231
 232         if (!hsotg->phy) {
 233                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 234                 if (IS_ERR(hsotg->uphy)) {
 235                         ret = PTR_ERR(hsotg->uphy);
 236                         switch (ret) {
 237                         case -ENODEV:
 238                         case -ENXIO:
 239                                 hsotg->uphy = NULL;
 240                                 break;
 241                         case -EPROBE_DEFER:
 242                                 return ret;
 243                         default:
 244                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 245                                         ret);
 246                                 return ret;
 247                         }
 248                 }
 249         }
 250
 251         hsotg->plat = dev_get_platdata(hsotg->dev);
 252
 253         if (hsotg->phy) {
 254                 /*
 255                  * If using the generic PHY framework, check if the PHY bus
 256                  * width is 8-bit and set the phyif appropriately.
 257                  */
 258                 if (phy_get_bus_width(hsotg->phy) == 8)
 259                         hsotg->phyif = GUSBCFG_PHYIF8;
 260         }
 261
 262         /* Clock */
 263         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 264         if (IS_ERR(hsotg->clk)) {
 265                 hsotg->clk = NULL;
 266                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 267         }
 268
 269         /* Regulators */
 270         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 271                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 272
 273         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 274                                       hsotg->supplies);
 275         if (ret) {
 276                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 277                 return ret;
 278         }
 279         return 0;
 280 }
 281
 282 /**
 283  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 284  * DWC_otg driver
 285  *
 286  * @dev: Platform device
 287  *
 288  * This routine is called, for example, when the rmmod command is executed. The
 289  * device may or may not be electrically present. If it is present, the driver
 290  * stops device processing. Any resources used on behalf of this device are
 291  * freed.
 292  */
 293 static int dwc2_driver_remove(struct platform_device *dev)
 294 {
 295         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 296
 297         dwc2_debugfs_exit(hsotg);
 298         if (hsotg->hcd_enabled)
 299                 dwc2_hcd_remove(hsotg);
 300         if (hsotg->gadget_enabled)
 301                 dwc2_hsotg_remove(hsotg);
 302
 303         if (hsotg->ll_hw_enabled)
 304                 dwc2_lowlevel_hw_disable(hsotg);
 305
 306         return 0;
 307 }
 308
 309 static const struct of_device_id dwc2_of_match_table[] = {
 310         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 311         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 312         { .compatible = "snps,dwc2", .data = NULL },
 313         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 314         {},
 315 };
 316 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 317
 318 /**
 319  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 320  * driver
 321  *
 322  * @dev: Platform device
 323  *
 324  * This routine creates the driver components required to control the device
 325  * (core, HCD, and PCD) and initializes the device. The driver components are
 326  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 327  * in the device private data. This allows the driver to access the dwc2_hsotg
 328  * structure on subsequent calls to driver methods for this device.
 329  */
 330 static int dwc2_driver_probe(struct platform_device *dev)
 331 {
 332         const struct of_device_id *match;
 333         const struct dwc2_core_params *params;
 334         struct dwc2_core_params defparams;
 335         struct dwc2_hsotg *hsotg;
 336         struct resource *res;
 337         int retval;
 338         int irq;
 339
 340         match = of_match_device(dwc2_of_match_table, &dev->dev);
 341         if (match && match->data) {
 342                 params = match->data;
 343         } else {
 344                 /* Default all params to autodetect */
 345                 dwc2_set_all_params(&defparams, -1);
 346                 params = &defparams;
 347
 348                 /*
 349                  * Disable descriptor dma mode by default as the HW can support
 350                  * it, but does not support it for SPLIT transactions.
 351                  */
 352                 defparams.dma_desc_enable = 0;
 353         }
 354
 355         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 356         if (!hsotg)
 357                 return -ENOMEM;
 358
 359         hsotg->dev = &dev->dev;
 360
 361         /*
 362          * Use reasonable defaults so platforms don't have to provide these.
 363          */
 364         if (!dev->dev.dma_mask)
 365                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 366         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 367         if (retval)
 368                 return retval;
 369
 370         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 371         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 372         if (IS_ERR(hsotg->regs))
 373                 return PTR_ERR(hsotg->regs);
 374
 375         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 376                 (unsigned long)res->start, hsotg->regs);
 377
 378         hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
 379         if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
 380                         hsotg->dr_mode != USB_DR_MODE_HOST) {
 381                 hsotg->dr_mode = USB_DR_MODE_HOST;
 382                 dev_warn(hsotg->dev,
 383                         "Configuration mismatch. Forcing host mode\n");
 384         } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
 385                         hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 386                 hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
 387                 dev_warn(hsotg->dev,
 388                         "Configuration mismatch. Forcing peripheral mode\n");
 389         }
 390
 391         retval = dwc2_lowlevel_hw_init(hsotg);
 392         if (retval)
 393                 return retval;
 394
 395         spin_lock_init(&hsotg->lock);
 396
 397         hsotg->core_params = devm_kzalloc(&dev->dev,
 398                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 399         if (!hsotg->core_params)
 400                 return -ENOMEM;
 401
 402         dwc2_set_all_params(hsotg->core_params, -1);
 403
 404         irq = platform_get_irq(dev, 0);
 405         if (irq < 0) {
 406                 dev_err(&dev->dev, "missing IRQ resource\n");
 407                 return irq;
 408         }
 409
 410         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 411                 irq);
 412         retval = devm_request_irq(hsotg->dev, irq,
 413                                   dwc2_handle_common_intr, IRQF_SHARED,
 414                                   dev_name(hsotg->dev), hsotg);
 415         if (retval)
 416                 return retval;
 417
 418         retval = dwc2_lowlevel_hw_enable(hsotg);
 419         if (retval)
 420                 return retval;
 421
 422         /* Detect config values from hardware */
 423         retval = dwc2_get_hwparams(hsotg);
 424         if (retval)
 425                 goto error;
 426
 427         /* Validate parameter values */
 428         dwc2_set_parameters(hsotg, params);
 429
 430         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 431                 retval = dwc2_gadget_init(hsotg, irq);
 432                 if (retval)
 433                         goto error;
 434                 hsotg->gadget_enabled = 1;
 435         }
 436
 437         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 438                 retval = dwc2_hcd_init(hsotg, irq);
 439                 if (retval) {
 440                         if (hsotg->gadget_enabled)
 441                                 dwc2_hsotg_remove(hsotg);
 442                         goto error;
 443                 }
 444                 hsotg->hcd_enabled = 1;
 445         }
 446
 447         platform_set_drvdata(dev, hsotg);
 448
 449         dwc2_debugfs_init(hsotg);
 450
 451         /* Gadget code manages lowlevel hw on its own */
 452         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 453                 dwc2_lowlevel_hw_disable(hsotg);
 454
 455         return 0;
 456
 457 error:
 458         dwc2_lowlevel_hw_disable(hsotg);
 459         return retval;
 460 }
 461
 462 static int __maybe_unused dwc2_suspend(struct device *dev)
 463 {
 464         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 465         int ret = 0;
 466
 467         if (dwc2_is_device_mode(dwc2))
 468                 dwc2_hsotg_suspend(dwc2);
 469
 470         if (dwc2->ll_hw_enabled)
 471                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 472
 473         return ret;
 474 }
 475
 476 static int __maybe_unused dwc2_resume(struct device *dev)
 477 {
 478         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 479         int ret = 0;
 480
 481         if (dwc2->ll_hw_enabled) {
 482                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 483                 if (ret)
 484                         return ret;
 485         }
 486
 487         if (dwc2_is_device_mode(dwc2))
 488                 ret = dwc2_hsotg_resume(dwc2);
 489
 490         return ret;
 491 }
 492
 493 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 494         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 495 };
 496
 497 static struct platform_driver dwc2_platform_driver = {
 498         .driver = {
 499                 .name = dwc2_driver_name,
 500                 .of_match_table = dwc2_of_match_table,
 501                 .pm = &dwc2_dev_pm_ops,
 502         },
 503         .probe = dwc2_driver_probe,
 504         .remove = dwc2_driver_remove,
 505 };
 506
 507 module_platform_driver(dwc2_platform_driver);
 508
 509 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 510 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 511 MODULE_LICENSE("Dual BSD/GPL");