drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  51
  52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  53 {
  54         u32 reg;
  55
  56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  60 }
  61
  62 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  63 {
  64         struct dwc3             *dwc = dep->dwc;
  65         u32                     reg;
  66
  67         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  68                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  69                         DWC3_GDBGFIFOSPACE_TYPE(type));
  70
  71         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  72
  73         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  74 }
  75
  76 /**
  77  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  78  * @dwc: pointer to our context structure
  79  */
  80 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  81 {
  82         u32             reg;
  83         int             retries = 1000;
  84         int             ret;
  85
  86         usb_phy_init(dwc->usb2_phy);
  87         usb_phy_init(dwc->usb3_phy);
  88         ret = phy_init(dwc->usb2_generic_phy);
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = phy_init(dwc->usb3_generic_phy);
  93         if (ret < 0) {
  94                 phy_exit(dwc->usb2_generic_phy);
  95                 return ret;
  96         }
  97
  98         /*
  99          * We're resetting only the device side because, if we're in host mode,
 100          * XHCI driver will reset the host block. If dwc3 was configured for
 101          * host-only mode, then we can return early.
 102          */
 103         if (dwc->dr_mode == USB_DR_MODE_HOST)
 104                 return 0;
 105
 106         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 107         reg |= DWC3_DCTL_CSFTRST;
 108         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 109
 110         do {
 111                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112                 if (!(reg & DWC3_DCTL_CSFTRST))
 113                         return 0;
 114
 115                 udelay(1);
 116         } while (--retries);
 117
 118         return -ETIMEDOUT;
 119 }
 120
 121 /**
 122  * dwc3_soft_reset - Issue soft reset
 123  * @dwc: Pointer to our controller context structure
 124  */
 125 static int dwc3_soft_reset(struct dwc3 *dwc)
 126 {
 127         unsigned long timeout;
 128         u32 reg;
 129
 130         timeout = jiffies + msecs_to_jiffies(500);
 131         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 132         do {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 134                 if (!(reg & DWC3_DCTL_CSFTRST))
 135                         break;
 136
 137                 if (time_after(jiffies, timeout)) {
 138                         dev_err(dwc->dev, "Reset Timed Out\n");
 139                         return -ETIMEDOUT;
 140                 }
 141
 142                 cpu_relax();
 143         } while (true);
 144
 145         return 0;
 146 }
 147
 148 /*
 149  * dwc3_frame_length_adjustment - Adjusts frame length if required
 150  * @dwc3: Pointer to our controller context structure
 151  */
 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 153 {
 154         u32 reg;
 155         u32 dft;
 156
 157         if (dwc->revision < DWC3_REVISION_250A)
 158                 return;
 159
 160         if (dwc->fladj == 0)
 161                 return;
 162
 163         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 164         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 165         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
 166             "request value same as default, ignoring\n")) {
 167                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 168                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 169                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_free_one_event_buffer - Frees one event buffer
 175  * @dwc: Pointer to our controller context structure
 176  * @evt: Pointer to event buffer to be freed
 177  */
 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 179                 struct dwc3_event_buffer *evt)
 180 {
 181         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 182 }
 183
 184 /**
 185  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 186  * @dwc: Pointer to our controller context structure
 187  * @length: size of the event buffer
 188  *
 189  * Returns a pointer to the allocated event buffer structure on success
 190  * otherwise ERR_PTR(errno).
 191  */
 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 193                 unsigned length)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196
 197         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 198         if (!evt)
 199                 return ERR_PTR(-ENOMEM);
 200
 201         evt->dwc        = dwc;
 202         evt->length     = length;
 203         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 204                         &evt->dma, GFP_KERNEL);
 205         if (!evt->buf)
 206                 return ERR_PTR(-ENOMEM);
 207
 208         return evt;
 209 }
 210
 211 /**
 212  * dwc3_free_event_buffers - frees all allocated event buffers
 213  * @dwc: Pointer to our controller context structure
 214  */
 215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218
 219         evt = dwc->ev_buf;
 220         if (evt)
 221                 dwc3_free_one_event_buffer(dwc, evt);
 222 }
 223
 224 /**
 225  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 226  * @dwc: pointer to our controller context structure
 227  * @length: size of event buffer
 228  *
 229  * Returns 0 on success otherwise negative errno. In the error case, dwc
 230  * may contain some buffers allocated but not all which were requested.
 231  */
 232 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 233 {
 234         struct dwc3_event_buffer *evt;
 235
 236         evt = dwc3_alloc_one_event_buffer(dwc, length);
 237         if (IS_ERR(evt)) {
 238                 dev_err(dwc->dev, "can't allocate event buffer\n");
 239                 return PTR_ERR(evt);
 240         }
 241         dwc->ev_buf = evt;
 242
 243         return 0;
 244 }
 245
 246 /**
 247  * dwc3_event_buffers_setup - setup our allocated event buffers
 248  * @dwc: pointer to our controller context structure
 249  *
 250  * Returns 0 on success otherwise negative errno.
 251  */
 252 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 253 {
 254         struct dwc3_event_buffer        *evt;
 255
 256         evt = dwc->ev_buf;
 257         dwc3_trace(trace_dwc3_core,
 258                         "Event buf %p dma %08llx length %d\n",
 259                         evt->buf, (unsigned long long) evt->dma,
 260                         evt->length);
 261
 262         evt->lpos = 0;
 263
 264         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 265                         lower_32_bits(evt->dma));
 266         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 267                         upper_32_bits(evt->dma));
 268         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 269                         DWC3_GEVNTSIZ_SIZE(evt->length));
 270         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 271
 272         return 0;
 273 }
 274
 275 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 276 {
 277         struct dwc3_event_buffer        *evt;
 278
 279         evt = dwc->ev_buf;
 280
 281         evt->lpos = 0;
 282
 283         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 284         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 285         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 286                         | DWC3_GEVNTSIZ_SIZE(0));
 287         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 288 }
 289
 290 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 291 {
 292         if (!dwc->has_hibernation)
 293                 return 0;
 294
 295         if (!dwc->nr_scratch)
 296                 return 0;
 297
 298         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 299                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 300         if (!dwc->scratchbuf)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 307 {
 308         dma_addr_t scratch_addr;
 309         u32 param;
 310         int ret;
 311
 312         if (!dwc->has_hibernation)
 313                 return 0;
 314
 315         if (!dwc->nr_scratch)
 316                 return 0;
 317
 318          /* should never fall here */
 319         if (!WARN_ON(dwc->scratchbuf))
 320                 return 0;
 321
 322         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 323                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 324                         DMA_BIDIRECTIONAL);
 325         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 326                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 327                 ret = -EFAULT;
 328                 goto err0;
 329         }
 330
 331         dwc->scratch_addr = scratch_addr;
 332
 333         param = lower_32_bits(scratch_addr);
 334
 335         ret = dwc3_send_gadget_generic_command(dwc,
 336                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 337         if (ret < 0)
 338                 goto err1;
 339
 340         param = upper_32_bits(scratch_addr);
 341
 342         ret = dwc3_send_gadget_generic_command(dwc,
 343                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 344         if (ret < 0)
 345                 goto err1;
 346
 347         return 0;
 348
 349 err1:
 350         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 351                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 352
 353 err0:
 354         return ret;
 355 }
 356
 357 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 358 {
 359         if (!dwc->has_hibernation)
 360                 return;
 361
 362         if (!dwc->nr_scratch)
 363                 return;
 364
 365          /* should never fall here */
 366         if (!WARN_ON(dwc->scratchbuf))
 367                 return;
 368
 369         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 370                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 371         kfree(dwc->scratchbuf);
 372 }
 373
 374 static void dwc3_core_num_eps(struct dwc3 *dwc)
 375 {
 376         struct dwc3_hwparams    *parms = &dwc->hwparams;
 377
 378         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 379         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 380
 381         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 382                         dwc->num_in_eps, dwc->num_out_eps);
 383 }
 384
 385 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 386 {
 387         struct dwc3_hwparams    *parms = &dwc->hwparams;
 388
 389         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 390         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 391         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 392         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 393         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 394         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 395         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 396         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 397         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 398 }
 399
 400 /**
 401  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 402  * @dwc: Pointer to our controller context structure
 403  *
 404  * Returns 0 on success. The USB PHY interfaces are configured but not
 405  * initialized. The PHY interfaces and the PHYs get initialized together with
 406  * the core in dwc3_core_init.
 407  */
 408 static int dwc3_phy_setup(struct dwc3 *dwc)
 409 {
 410         u32 reg;
 411         int ret;
 412
 413         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 414
 415         /*
 416          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 417          * to '0' during coreConsultant configuration. So default value
 418          * will be '0' when the core is reset. Application needs to set it
 419          * to '1' after the core initialization is completed.
 420          */
 421         if (dwc->revision > DWC3_REVISION_194A)
 422                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 423
 424         if (dwc->u2ss_inp3_quirk)
 425                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 426
 427         if (dwc->dis_rxdet_inp3_quirk)
 428                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 429
 430         if (dwc->req_p1p2p3_quirk)
 431                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 432
 433         if (dwc->del_p1p2p3_quirk)
 434                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 435
 436         if (dwc->del_phy_power_chg_quirk)
 437                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 438
 439         if (dwc->lfps_filter_quirk)
 440                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 441
 442         if (dwc->rx_detect_poll_quirk)
 443                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 444
 445         if (dwc->tx_de_emphasis_quirk)
 446                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 447
 448         if (dwc->dis_u3_susphy_quirk)
 449                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 450
 451         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 452
 453         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 454
 455         /* Select the HS PHY interface */
 456         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 457         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 458                 if (dwc->hsphy_interface &&
 459                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 460                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 461                         break;
 462                 } else if (dwc->hsphy_interface &&
 463                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 464                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 465                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 466                 } else {
 467                         /* Relying on default value. */
 468                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 469                                 break;
 470                 }
 471                 /* FALLTHROUGH */
 472         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 473                 /* Making sure the interface and PHY are operational */
 474                 ret = dwc3_soft_reset(dwc);
 475                 if (ret)
 476                         return ret;
 477
 478                 udelay(1);
 479
 480                 ret = dwc3_ulpi_init(dwc);
 481                 if (ret)
 482                         return ret;
 483                 /* FALLTHROUGH */
 484         default:
 485                 break;
 486         }
 487
 488         /*
 489          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 490          * '0' during coreConsultant configuration. So default value will
 491          * be '0' when the core is reset. Application needs to set it to
 492          * '1' after the core initialization is completed.
 493          */
 494         if (dwc->revision > DWC3_REVISION_194A)
 495                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 496
 497         if (dwc->dis_u2_susphy_quirk)
 498                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 499
 500         if (dwc->dis_enblslpm_quirk)
 501                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 502
 503         if (dwc->dis_u2_freeclk_exists_quirk)
 504                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 505
 506         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 507
 508         return 0;
 509 }
 510
 511 static void dwc3_core_exit(struct dwc3 *dwc)
 512 {
 513         dwc3_event_buffers_cleanup(dwc);
 514
 515         usb_phy_shutdown(dwc->usb2_phy);
 516         usb_phy_shutdown(dwc->usb3_phy);
 517         phy_exit(dwc->usb2_generic_phy);
 518         phy_exit(dwc->usb3_generic_phy);
 519
 520         usb_phy_set_suspend(dwc->usb2_phy, 1);
 521         usb_phy_set_suspend(dwc->usb3_phy, 1);
 522         phy_power_off(dwc->usb2_generic_phy);
 523         phy_power_off(dwc->usb3_generic_phy);
 524 }
 525
 526 /**
 527  * dwc3_core_init - Low-level initialization of DWC3 Core
 528  * @dwc: Pointer to our controller context structure
 529  *
 530  * Returns 0 on success otherwise negative errno.
 531  */
 532 static int dwc3_core_init(struct dwc3 *dwc)
 533 {
 534         u32                     hwparams4 = dwc->hwparams.hwparams4;
 535         u32                     reg;
 536         int                     ret;
 537
 538         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 539         /* This should read as U3 followed by revision number */
 540         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 541                 /* Detected DWC_usb3 IP */
 542                 dwc->revision = reg;
 543         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 544                 /* Detected DWC_usb31 IP */
 545                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 546                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 547         } else {
 548                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 549                 ret = -ENODEV;
 550                 goto err0;
 551         }
 552
 553         /*
 554          * Write Linux Version Code to our GUID register so it's easy to figure
 555          * out which kernel version a bug was found.
 556          */
 557         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 558
 559         /* Handle USB2.0-only core configuration */
 560         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 561                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 562                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 563                         dwc->maximum_speed = USB_SPEED_HIGH;
 564         }
 565
 566         /* issue device SoftReset too */
 567         ret = dwc3_soft_reset(dwc);
 568         if (ret)
 569                 goto err0;
 570
 571         ret = dwc3_core_soft_reset(dwc);
 572         if (ret)
 573                 goto err0;
 574
 575         ret = dwc3_phy_setup(dwc);
 576         if (ret)
 577                 goto err0;
 578
 579         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 580         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 581
 582         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 583         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 584                 /**
 585                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 586                  * issue which would cause xHCI compliance tests to fail.
 587                  *
 588                  * Because of that we cannot enable clock gating on such
 589                  * configurations.
 590                  *
 591                  * Refers to:
 592                  *
 593                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 594                  * SOF/ITP Mode Used
 595                  */
 596                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 597                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 598                                 (dwc->revision >= DWC3_REVISION_210A &&
 599                                 dwc->revision <= DWC3_REVISION_250A))
 600                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 601                 else
 602                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 603                 break;
 604         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 605                 /* enable hibernation here */
 606                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 607
 608                 /*
 609                  * REVISIT Enabling this bit so that host-mode hibernation
 610                  * will work. Device-mode hibernation is not yet implemented.
 611                  */
 612                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 613                 break;
 614         default:
 615                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 616         }
 617
 618         /* check if current dwc3 is on simulation board */
 619         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 620                 dwc3_trace(trace_dwc3_core,
 621                                 "running on FPGA platform\n");
 622                 dwc->is_fpga = true;
 623         }
 624
 625         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 626                         "disable_scramble cannot be used on non-FPGA builds\n");
 627
 628         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 629                 reg |= DWC3_GCTL_DISSCRAMBLE;
 630         else
 631                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 632
 633         if (dwc->u2exit_lfps_quirk)
 634                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 635
 636         /*
 637          * WORKAROUND: DWC3 revisions <1.90a have a bug
 638          * where the device can fail to connect at SuperSpeed
 639          * and falls back to high-speed mode which causes
 640          * the device to enter a Connect/Disconnect loop
 641          */
 642         if (dwc->revision < DWC3_REVISION_190A)
 643                 reg |= DWC3_GCTL_U2RSTECN;
 644
 645         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 646
 647         dwc3_core_num_eps(dwc);
 648
 649         ret = dwc3_setup_scratch_buffers(dwc);
 650         if (ret)
 651                 goto err1;
 652
 653         /* Adjust Frame Length */
 654         dwc3_frame_length_adjustment(dwc);
 655
 656         usb_phy_set_suspend(dwc->usb2_phy, 0);
 657         usb_phy_set_suspend(dwc->usb3_phy, 0);
 658         ret = phy_power_on(dwc->usb2_generic_phy);
 659         if (ret < 0)
 660                 goto err2;
 661
 662         ret = phy_power_on(dwc->usb3_generic_phy);
 663         if (ret < 0)
 664                 goto err3;
 665
 666         ret = dwc3_event_buffers_setup(dwc);
 667         if (ret) {
 668                 dev_err(dwc->dev, "failed to setup event buffers\n");
 669                 goto err4;
 670         }
 671
 672         return 0;
 673
 674 err4:
 675         phy_power_off(dwc->usb2_generic_phy);
 676
 677 err3:
 678         phy_power_off(dwc->usb3_generic_phy);
 679
 680 err2:
 681         usb_phy_set_suspend(dwc->usb2_phy, 1);
 682         usb_phy_set_suspend(dwc->usb3_phy, 1);
 683         dwc3_core_exit(dwc);
 684
 685 err1:
 686         usb_phy_shutdown(dwc->usb2_phy);
 687         usb_phy_shutdown(dwc->usb3_phy);
 688         phy_exit(dwc->usb2_generic_phy);
 689         phy_exit(dwc->usb3_generic_phy);
 690
 691 err0:
 692         return ret;
 693 }
 694
 695 static int dwc3_core_get_phy(struct dwc3 *dwc)
 696 {
 697         struct device           *dev = dwc->dev;
 698         struct device_node      *node = dev->of_node;
 699         int ret;
 700
 701         if (node) {
 702                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 703                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 704         } else {
 705                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 706                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 707         }
 708
 709         if (IS_ERR(dwc->usb2_phy)) {
 710                 ret = PTR_ERR(dwc->usb2_phy);
 711                 if (ret == -ENXIO || ret == -ENODEV) {
 712                         dwc->usb2_phy = NULL;
 713                 } else if (ret == -EPROBE_DEFER) {
 714                         return ret;
 715                 } else {
 716                         dev_err(dev, "no usb2 phy configured\n");
 717                         return ret;
 718                 }
 719         }
 720
 721         if (IS_ERR(dwc->usb3_phy)) {
 722                 ret = PTR_ERR(dwc->usb3_phy);
 723                 if (ret == -ENXIO || ret == -ENODEV) {
 724                         dwc->usb3_phy = NULL;
 725                 } else if (ret == -EPROBE_DEFER) {
 726                         return ret;
 727                 } else {
 728                         dev_err(dev, "no usb3 phy configured\n");
 729                         return ret;
 730                 }
 731         }
 732
 733         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 734         if (IS_ERR(dwc->usb2_generic_phy)) {
 735                 ret = PTR_ERR(dwc->usb2_generic_phy);
 736                 if (ret == -ENOSYS || ret == -ENODEV) {
 737                         dwc->usb2_generic_phy = NULL;
 738                 } else if (ret == -EPROBE_DEFER) {
 739                         return ret;
 740                 } else {
 741                         dev_err(dev, "no usb2 phy configured\n");
 742                         return ret;
 743                 }
 744         }
 745
 746         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 747         if (IS_ERR(dwc->usb3_generic_phy)) {
 748                 ret = PTR_ERR(dwc->usb3_generic_phy);
 749                 if (ret == -ENOSYS || ret == -ENODEV) {
 750                         dwc->usb3_generic_phy = NULL;
 751                 } else if (ret == -EPROBE_DEFER) {
 752                         return ret;
 753                 } else {
 754                         dev_err(dev, "no usb3 phy configured\n");
 755                         return ret;
 756                 }
 757         }
 758
 759         return 0;
 760 }
 761
 762 static int dwc3_core_init_mode(struct dwc3 *dwc)
 763 {
 764         struct device *dev = dwc->dev;
 765         int ret;
 766
 767         switch (dwc->dr_mode) {
 768         case USB_DR_MODE_PERIPHERAL:
 769                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 770                 ret = dwc3_gadget_init(dwc);
 771                 if (ret) {
 772                         if (ret != -EPROBE_DEFER)
 773                                 dev_err(dev, "failed to initialize gadget\n");
 774                         return ret;
 775                 }
 776                 break;
 777         case USB_DR_MODE_HOST:
 778                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 779                 ret = dwc3_host_init(dwc);
 780                 if (ret) {
 781                         if (ret != -EPROBE_DEFER)
 782                                 dev_err(dev, "failed to initialize host\n");
 783                         return ret;
 784                 }
 785                 break;
 786         case USB_DR_MODE_OTG:
 787                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 788                 ret = dwc3_host_init(dwc);
 789                 if (ret) {
 790                         if (ret != -EPROBE_DEFER)
 791                                 dev_err(dev, "failed to initialize host\n");
 792                         return ret;
 793                 }
 794
 795                 ret = dwc3_gadget_init(dwc);
 796                 if (ret) {
 797                         if (ret != -EPROBE_DEFER)
 798                                 dev_err(dev, "failed to initialize gadget\n");
 799                         return ret;
 800                 }
 801                 break;
 802         default:
 803                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 804                 return -EINVAL;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 811 {
 812         switch (dwc->dr_mode) {
 813         case USB_DR_MODE_PERIPHERAL:
 814                 dwc3_gadget_exit(dwc);
 815                 break;
 816         case USB_DR_MODE_HOST:
 817                 dwc3_host_exit(dwc);
 818                 break;
 819         case USB_DR_MODE_OTG:
 820                 dwc3_host_exit(dwc);
 821                 dwc3_gadget_exit(dwc);
 822                 break;
 823         default:
 824                 /* do nothing */
 825                 break;
 826         }
 827 }
 828
 829 #define DWC3_ALIGN_MASK         (16 - 1)
 830
 831 static int dwc3_probe(struct platform_device *pdev)
 832 {
 833         struct device           *dev = &pdev->dev;
 834         struct resource         *res;
 835         struct dwc3             *dwc;
 836         u8                      lpm_nyet_threshold;
 837         u8                      tx_de_emphasis;
 838         u8                      hird_threshold;
 839
 840         int                     ret;
 841
 842         void __iomem            *regs;
 843         void                    *mem;
 844
 845         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 846         if (!mem)
 847                 return -ENOMEM;
 848
 849         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 850         dwc->mem = mem;
 851         dwc->dev = dev;
 852
 853         /* Try to set 64-bit DMA first */
 854         if (!pdev->dev.dma_mask)
 855                 /* Platform did not initialize dma_mask */
 856                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 857                                                    DMA_BIT_MASK(64));
 858         else
 859                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 860
 861         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 862         if (ret) {
 863                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 864                 if (ret)
 865                         return ret;
 866         }
 867
 868         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 869         if (!res) {
 870                 dev_err(dev, "missing memory resource\n");
 871                 return -ENODEV;
 872         }
 873
 874         dwc->xhci_resources[0].start = res->start;
 875         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 876                                         DWC3_XHCI_REGS_END;
 877         dwc->xhci_resources[0].flags = res->flags;
 878         dwc->xhci_resources[0].name = res->name;
 879
 880         res->start += DWC3_GLOBALS_REGS_START;
 881
 882         /*
 883          * Request memory region but exclude xHCI regs,
 884          * since it will be requested by the xhci-plat driver.
 885          */
 886         regs = devm_ioremap_resource(dev, res);
 887         if (IS_ERR(regs)) {
 888                 ret = PTR_ERR(regs);
 889                 goto err0;
 890         }
 891
 892         dwc->regs       = regs;
 893         dwc->regs_size  = resource_size(res);
 894
 895         /* default to highest possible threshold */
 896         lpm_nyet_threshold = 0xff;
 897
 898         /* default to -3.5dB de-emphasis */
 899         tx_de_emphasis = 1;
 900
 901         /*
 902          * default to assert utmi_sleep_n and use maximum allowed HIRD
 903          * threshold value of 0b1100
 904          */
 905         hird_threshold = 12;
 906
 907         dwc->maximum_speed = usb_get_maximum_speed(dev);
 908         dwc->dr_mode = usb_get_dr_mode(dev);
 909
 910         dwc->has_lpm_erratum = device_property_read_bool(dev,
 911                                 "snps,has-lpm-erratum");
 912         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 913                                 &lpm_nyet_threshold);
 914         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 915                                 "snps,is-utmi-l1-suspend");
 916         device_property_read_u8(dev, "snps,hird-threshold",
 917                                 &hird_threshold);
 918         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 919                                 "snps,usb3_lpm_capable");
 920
 921         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 922                                 "snps,disable_scramble_quirk");
 923         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 924                                 "snps,u2exit_lfps_quirk");
 925         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 926                                 "snps,u2ss_inp3_quirk");
 927         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 928                                 "snps,req_p1p2p3_quirk");
 929         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 930                                 "snps,del_p1p2p3_quirk");
 931         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 932                                 "snps,del_phy_power_chg_quirk");
 933         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 934                                 "snps,lfps_filter_quirk");
 935         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 936                                 "snps,rx_detect_poll_quirk");
 937         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 938                                 "snps,dis_u3_susphy_quirk");
 939         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 940                                 "snps,dis_u2_susphy_quirk");
 941         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 942                                 "snps,dis_enblslpm_quirk");
 943         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 944                                 "snps,dis_rxdet_inp3_quirk");
 945         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 946                                 "snps,dis-u2-freeclk-exists-quirk");
 947
 948         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 949                                 "snps,tx_de_emphasis_quirk");
 950         device_property_read_u8(dev, "snps,tx_de_emphasis",
 951                                 &tx_de_emphasis);
 952         device_property_read_string(dev, "snps,hsphy_interface",
 953                                     &dwc->hsphy_interface);
 954         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 955                                  &dwc->fladj);
 956
 957         /* default to superspeed if no maximum_speed passed */
 958         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 959                 dwc->maximum_speed = USB_SPEED_SUPER;
 960
 961         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 962         dwc->tx_de_emphasis = tx_de_emphasis;
 963
 964         dwc->hird_threshold = hird_threshold
 965                 | (dwc->is_utmi_l1_suspend << 4);
 966
 967         platform_set_drvdata(pdev, dwc);
 968         dwc3_cache_hwparams(dwc);
 969
 970         ret = dwc3_core_get_phy(dwc);
 971         if (ret)
 972                 goto err0;
 973
 974         spin_lock_init(&dwc->lock);
 975
 976         if (!dev->dma_mask) {
 977                 dev->dma_mask = dev->parent->dma_mask;
 978                 dev->dma_parms = dev->parent->dma_parms;
 979                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 980         }
 981
 982         pm_runtime_set_active(dev);
 983         pm_runtime_use_autosuspend(dev);
 984         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
 985         pm_runtime_enable(dev);
 986         ret = pm_runtime_get_sync(dev);
 987         if (ret < 0)
 988                 goto err1;
 989
 990         pm_runtime_forbid(dev);
 991
 992         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 993         if (ret) {
 994                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 995                 ret = -ENOMEM;
 996                 goto err2;
 997         }
 998
 999         if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
1000                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1001                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1002                 dwc->dr_mode = USB_DR_MODE_HOST;
1003         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
1004                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1005                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1006                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1007
1008         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1009                 dwc->dr_mode = USB_DR_MODE_OTG;
1010
1011         ret = dwc3_alloc_scratch_buffers(dwc);
1012         if (ret)
1013                 goto err3;
1014
1015         ret = dwc3_core_init(dwc);
1016         if (ret) {
1017                 dev_err(dev, "failed to initialize core\n");
1018                 goto err4;
1019         }
1020
1021         ret = dwc3_core_init_mode(dwc);
1022         if (ret)
1023                 goto err5;
1024
1025         dwc3_debugfs_init(dwc);
1026         pm_runtime_put(dev);
1027
1028         return 0;
1029
1030 err5:
1031         dwc3_event_buffers_cleanup(dwc);
1032
1033 err4:
1034         dwc3_free_scratch_buffers(dwc);
1035
1036 err3:
1037         dwc3_free_event_buffers(dwc);
1038         dwc3_ulpi_exit(dwc);
1039
1040 err2:
1041         pm_runtime_allow(&pdev->dev);
1042
1043 err1:
1044         pm_runtime_put_sync(&pdev->dev);
1045         pm_runtime_disable(&pdev->dev);
1046
1047 err0:
1048         /*
1049          * restore res->start back to its original value so that, in case the
1050          * probe is deferred, we don't end up getting error in request the
1051          * memory region the next time probe is called.
1052          */
1053         res->start -= DWC3_GLOBALS_REGS_START;
1054
1055         return ret;
1056 }
1057
1058 static int dwc3_remove(struct platform_device *pdev)
1059 {
1060         struct dwc3     *dwc = platform_get_drvdata(pdev);
1061         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1062
1063         pm_runtime_get_sync(&pdev->dev);
1064         /*
1065          * restore res->start back to its original value so that, in case the
1066          * probe is deferred, we don't end up getting error in request the
1067          * memory region the next time probe is called.
1068          */
1069         res->start -= DWC3_GLOBALS_REGS_START;
1070
1071         dwc3_debugfs_exit(dwc);
1072         dwc3_core_exit_mode(dwc);
1073
1074         dwc3_core_exit(dwc);
1075         dwc3_ulpi_exit(dwc);
1076
1077         pm_runtime_put_sync(&pdev->dev);
1078         pm_runtime_allow(&pdev->dev);
1079         pm_runtime_disable(&pdev->dev);
1080
1081         dwc3_free_event_buffers(dwc);
1082         dwc3_free_scratch_buffers(dwc);
1083
1084         return 0;
1085 }
1086
1087 #ifdef CONFIG_PM
1088 static int dwc3_suspend_common(struct dwc3 *dwc)
1089 {
1090         unsigned long   flags;
1091
1092         switch (dwc->dr_mode) {
1093         case USB_DR_MODE_PERIPHERAL:
1094         case USB_DR_MODE_OTG:
1095                 spin_lock_irqsave(&dwc->lock, flags);
1096                 dwc3_gadget_suspend(dwc);
1097                 spin_unlock_irqrestore(&dwc->lock, flags);
1098                 break;
1099         case USB_DR_MODE_HOST:
1100         default:
1101                 /* do nothing */
1102                 break;
1103         }
1104
1105         dwc3_core_exit(dwc);
1106
1107         return 0;
1108 }
1109
1110 static int dwc3_resume_common(struct dwc3 *dwc)
1111 {
1112         unsigned long   flags;
1113         int             ret;
1114
1115         ret = dwc3_core_init(dwc);
1116         if (ret)
1117                 return ret;
1118
1119         switch (dwc->dr_mode) {
1120         case USB_DR_MODE_PERIPHERAL:
1121         case USB_DR_MODE_OTG:
1122                 spin_lock_irqsave(&dwc->lock, flags);
1123                 dwc3_gadget_resume(dwc);
1124                 spin_unlock_irqrestore(&dwc->lock, flags);
1125                 /* FALLTHROUGH */
1126         case USB_DR_MODE_HOST:
1127         default:
1128                 /* do nothing */
1129                 break;
1130         }
1131
1132         return 0;
1133 }
1134
1135 static int dwc3_runtime_checks(struct dwc3 *dwc)
1136 {
1137         switch (dwc->dr_mode) {
1138         case USB_DR_MODE_PERIPHERAL:
1139         case USB_DR_MODE_OTG:
1140                 if (dwc->connected)
1141                         return -EBUSY;
1142                 break;
1143         case USB_DR_MODE_HOST:
1144         default:
1145                 /* do nothing */
1146                 break;
1147         }
1148
1149         return 0;
1150 }
1151
1152 static int dwc3_runtime_suspend(struct device *dev)
1153 {
1154         struct dwc3     *dwc = dev_get_drvdata(dev);
1155         int             ret;
1156
1157         if (dwc3_runtime_checks(dwc))
1158                 return -EBUSY;
1159
1160         ret = dwc3_suspend_common(dwc);
1161         if (ret)
1162                 return ret;
1163
1164         device_init_wakeup(dev, true);
1165
1166         return 0;
1167 }
1168
1169 static int dwc3_runtime_resume(struct device *dev)
1170 {
1171         struct dwc3     *dwc = dev_get_drvdata(dev);
1172         int             ret;
1173
1174         device_init_wakeup(dev, false);
1175
1176         ret = dwc3_resume_common(dwc);
1177         if (ret)
1178                 return ret;
1179
1180         switch (dwc->dr_mode) {
1181         case USB_DR_MODE_PERIPHERAL:
1182         case USB_DR_MODE_OTG:
1183                 dwc3_gadget_process_pending_events(dwc);
1184                 break;
1185         case USB_DR_MODE_HOST:
1186         default:
1187                 /* do nothing */
1188                 break;
1189         }
1190
1191         pm_runtime_mark_last_busy(dev);
1192
1193         return 0;
1194 }
1195
1196 static int dwc3_runtime_idle(struct device *dev)
1197 {
1198         struct dwc3     *dwc = dev_get_drvdata(dev);
1199
1200         switch (dwc->dr_mode) {
1201         case USB_DR_MODE_PERIPHERAL:
1202         case USB_DR_MODE_OTG:
1203                 if (dwc3_runtime_checks(dwc))
1204                         return -EBUSY;
1205                 break;
1206         case USB_DR_MODE_HOST:
1207         default:
1208                 /* do nothing */
1209                 break;
1210         }
1211
1212         pm_runtime_mark_last_busy(dev);
1213         pm_runtime_autosuspend(dev);
1214
1215         return 0;
1216 }
1217 #endif /* CONFIG_PM */
1218
1219 #ifdef CONFIG_PM_SLEEP
1220 static int dwc3_suspend(struct device *dev)
1221 {
1222         struct dwc3     *dwc = dev_get_drvdata(dev);
1223         int             ret;
1224
1225         ret = dwc3_suspend_common(dwc);
1226         if (ret)
1227                 return ret;
1228
1229         pinctrl_pm_select_sleep_state(dev);
1230
1231         return 0;
1232 }
1233
1234 static int dwc3_resume(struct device *dev)
1235 {
1236         struct dwc3     *dwc = dev_get_drvdata(dev);
1237         int             ret;
1238
1239         pinctrl_pm_select_default_state(dev);
1240
1241         ret = dwc3_resume_common(dwc);
1242         if (ret)
1243                 return ret;
1244
1245         pm_runtime_disable(dev);
1246         pm_runtime_set_active(dev);
1247         pm_runtime_enable(dev);
1248
1249         return 0;
1250 }
1251 #endif /* CONFIG_PM_SLEEP */
1252
1253 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1254         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1255         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1256                         dwc3_runtime_idle)
1257 };
1258
1259 #ifdef CONFIG_OF
1260 static const struct of_device_id of_dwc3_match[] = {
1261         {
1262                 .compatible = "snps,dwc3"
1263         },
1264         {
1265                 .compatible = "synopsys,dwc3"
1266         },
1267         { },
1268 };
1269 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1270 #endif
1271
1272 #ifdef CONFIG_ACPI
1273
1274 #define ACPI_ID_INTEL_BSW       "808622B7"
1275
1276 static const struct acpi_device_id dwc3_acpi_match[] = {
1277         { ACPI_ID_INTEL_BSW, 0 },
1278         { },
1279 };
1280 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1281 #endif
1282
1283 static struct platform_driver dwc3_driver = {
1284         .probe          = dwc3_probe,
1285         .remove         = dwc3_remove,
1286         .driver         = {
1287                 .name   = "dwc3",
1288                 .of_match_table = of_match_ptr(of_dwc3_match),
1289                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1290                 .pm     = &dwc3_dev_pm_ops,
1291         },
1292 };
1293
1294 module_platform_driver(dwc3_driver);
1295
1296 MODULE_ALIAS("platform:dwc3");
1297 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1298 MODULE_LICENSE("GPL v2");
1299 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");