drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  51
  52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  53 {
  54         u32 reg;
  55
  56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  60 }
  61
  62 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
  63 {
  64         struct dwc3             *dwc = dep->dwc;
  65         u32                     reg;
  66
  67         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
  68                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
  69                         DWC3_GDBGFIFOSPACE_TYPE(type));
  70
  71         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
  72
  73         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
  74 }
  75
  76 /**
  77  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  78  * @dwc: pointer to our context structure
  79  */
  80 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  81 {
  82         u32             reg;
  83         int             retries = 1000;
  84         int             ret;
  85
  86         usb_phy_init(dwc->usb2_phy);
  87         usb_phy_init(dwc->usb3_phy);
  88         ret = phy_init(dwc->usb2_generic_phy);
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = phy_init(dwc->usb3_generic_phy);
  93         if (ret < 0) {
  94                 phy_exit(dwc->usb2_generic_phy);
  95                 return ret;
  96         }
  97
  98         /*
  99          * We're resetting only the device side because, if we're in host mode,
 100          * XHCI driver will reset the host block. If dwc3 was configured for
 101          * host-only mode, then we can return early.
 102          */
 103         if (dwc->dr_mode == USB_DR_MODE_HOST)
 104                 return 0;
 105
 106         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 107         reg |= DWC3_DCTL_CSFTRST;
 108         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 109
 110         do {
 111                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112                 if (!(reg & DWC3_DCTL_CSFTRST))
 113                         return 0;
 114
 115                 udelay(1);
 116         } while (--retries);
 117
 118         return -ETIMEDOUT;
 119 }
 120
 121 /**
 122  * dwc3_soft_reset - Issue soft reset
 123  * @dwc: Pointer to our controller context structure
 124  */
 125 static int dwc3_soft_reset(struct dwc3 *dwc)
 126 {
 127         unsigned long timeout;
 128         u32 reg;
 129
 130         timeout = jiffies + msecs_to_jiffies(500);
 131         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 132         do {
 133                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 134                 if (!(reg & DWC3_DCTL_CSFTRST))
 135                         break;
 136
 137                 if (time_after(jiffies, timeout)) {
 138                         dev_err(dwc->dev, "Reset Timed Out\n");
 139                         return -ETIMEDOUT;
 140                 }
 141
 142                 cpu_relax();
 143         } while (true);
 144
 145         return 0;
 146 }
 147
 148 /*
 149  * dwc3_frame_length_adjustment - Adjusts frame length if required
 150  * @dwc3: Pointer to our controller context structure
 151  */
 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 153 {
 154         u32 reg;
 155         u32 dft;
 156
 157         if (dwc->revision < DWC3_REVISION_250A)
 158                 return;
 159
 160         if (dwc->fladj == 0)
 161                 return;
 162
 163         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 164         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 165         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
 166             "request value same as default, ignoring\n")) {
 167                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 168                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 169                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_free_one_event_buffer - Frees one event buffer
 175  * @dwc: Pointer to our controller context structure
 176  * @evt: Pointer to event buffer to be freed
 177  */
 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 179                 struct dwc3_event_buffer *evt)
 180 {
 181         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 182 }
 183
 184 /**
 185  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 186  * @dwc: Pointer to our controller context structure
 187  * @length: size of the event buffer
 188  *
 189  * Returns a pointer to the allocated event buffer structure on success
 190  * otherwise ERR_PTR(errno).
 191  */
 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 193                 unsigned length)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196
 197         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 198         if (!evt)
 199                 return ERR_PTR(-ENOMEM);
 200
 201         evt->dwc        = dwc;
 202         evt->length     = length;
 203         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 204                         &evt->dma, GFP_KERNEL);
 205         if (!evt->buf)
 206                 return ERR_PTR(-ENOMEM);
 207
 208         return evt;
 209 }
 210
 211 /**
 212  * dwc3_free_event_buffers - frees all allocated event buffers
 213  * @dwc: Pointer to our controller context structure
 214  */
 215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218
 219         evt = dwc->ev_buf;
 220         if (evt)
 221                 dwc3_free_one_event_buffer(dwc, evt);
 222 }
 223
 224 /**
 225  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 226  * @dwc: pointer to our controller context structure
 227  * @length: size of event buffer
 228  *
 229  * Returns 0 on success otherwise negative errno. In the error case, dwc
 230  * may contain some buffers allocated but not all which were requested.
 231  */
 232 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 233 {
 234         struct dwc3_event_buffer *evt;
 235
 236         evt = dwc3_alloc_one_event_buffer(dwc, length);
 237         if (IS_ERR(evt)) {
 238                 dev_err(dwc->dev, "can't allocate event buffer\n");
 239                 return PTR_ERR(evt);
 240         }
 241         dwc->ev_buf = evt;
 242
 243         return 0;
 244 }
 245
 246 /**
 247  * dwc3_event_buffers_setup - setup our allocated event buffers
 248  * @dwc: pointer to our controller context structure
 249  *
 250  * Returns 0 on success otherwise negative errno.
 251  */
 252 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 253 {
 254         struct dwc3_event_buffer        *evt;
 255
 256         evt = dwc->ev_buf;
 257         dwc3_trace(trace_dwc3_core,
 258                         "Event buf %p dma %08llx length %d\n",
 259                         evt->buf, (unsigned long long) evt->dma,
 260                         evt->length);
 261
 262         evt->lpos = 0;
 263
 264         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 265                         lower_32_bits(evt->dma));
 266         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 267                         upper_32_bits(evt->dma));
 268         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 269                         DWC3_GEVNTSIZ_SIZE(evt->length));
 270         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 271
 272         return 0;
 273 }
 274
 275 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 276 {
 277         struct dwc3_event_buffer        *evt;
 278
 279         evt = dwc->ev_buf;
 280
 281         evt->lpos = 0;
 282
 283         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 284         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 285         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 286                         | DWC3_GEVNTSIZ_SIZE(0));
 287         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 288 }
 289
 290 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 291 {
 292         if (!dwc->has_hibernation)
 293                 return 0;
 294
 295         if (!dwc->nr_scratch)
 296                 return 0;
 297
 298         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 299                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 300         if (!dwc->scratchbuf)
 301                 return -ENOMEM;
 302
 303         return 0;
 304 }
 305
 306 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 307 {
 308         dma_addr_t scratch_addr;
 309         u32 param;
 310         int ret;
 311
 312         if (!dwc->has_hibernation)
 313                 return 0;
 314
 315         if (!dwc->nr_scratch)
 316                 return 0;
 317
 318          /* should never fall here */
 319         if (!WARN_ON(dwc->scratchbuf))
 320                 return 0;
 321
 322         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 323                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 324                         DMA_BIDIRECTIONAL);
 325         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 326                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 327                 ret = -EFAULT;
 328                 goto err0;
 329         }
 330
 331         dwc->scratch_addr = scratch_addr;
 332
 333         param = lower_32_bits(scratch_addr);
 334
 335         ret = dwc3_send_gadget_generic_command(dwc,
 336                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 337         if (ret < 0)
 338                 goto err1;
 339
 340         param = upper_32_bits(scratch_addr);
 341
 342         ret = dwc3_send_gadget_generic_command(dwc,
 343                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 344         if (ret < 0)
 345                 goto err1;
 346
 347         return 0;
 348
 349 err1:
 350         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 351                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 352
 353 err0:
 354         return ret;
 355 }
 356
 357 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 358 {
 359         if (!dwc->has_hibernation)
 360                 return;
 361
 362         if (!dwc->nr_scratch)
 363                 return;
 364
 365          /* should never fall here */
 366         if (!WARN_ON(dwc->scratchbuf))
 367                 return;
 368
 369         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 370                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 371         kfree(dwc->scratchbuf);
 372 }
 373
 374 static void dwc3_core_num_eps(struct dwc3 *dwc)
 375 {
 376         struct dwc3_hwparams    *parms = &dwc->hwparams;
 377
 378         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 379         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 380
 381         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 382                         dwc->num_in_eps, dwc->num_out_eps);
 383 }
 384
 385 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 386 {
 387         struct dwc3_hwparams    *parms = &dwc->hwparams;
 388
 389         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 390         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 391         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 392         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 393         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 394         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 395         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 396         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 397         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 398 }
 399
 400 /**
 401  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 402  * @dwc: Pointer to our controller context structure
 403  *
 404  * Returns 0 on success. The USB PHY interfaces are configured but not
 405  * initialized. The PHY interfaces and the PHYs get initialized together with
 406  * the core in dwc3_core_init.
 407  */
 408 static int dwc3_phy_setup(struct dwc3 *dwc)
 409 {
 410         u32 reg;
 411         int ret;
 412
 413         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 414
 415         /*
 416          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 417          * to '0' during coreConsultant configuration. So default value
 418          * will be '0' when the core is reset. Application needs to set it
 419          * to '1' after the core initialization is completed.
 420          */
 421         if (dwc->revision > DWC3_REVISION_194A)
 422                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 423
 424         if (dwc->u2ss_inp3_quirk)
 425                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 426
 427         if (dwc->dis_rxdet_inp3_quirk)
 428                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 429
 430         if (dwc->req_p1p2p3_quirk)
 431                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 432
 433         if (dwc->del_p1p2p3_quirk)
 434                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 435
 436         if (dwc->del_phy_power_chg_quirk)
 437                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 438
 439         if (dwc->lfps_filter_quirk)
 440                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 441
 442         if (dwc->rx_detect_poll_quirk)
 443                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 444
 445         if (dwc->tx_de_emphasis_quirk)
 446                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 447
 448         if (dwc->dis_u3_susphy_quirk)
 449                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 450
 451         if (dwc->dis_del_phy_power_chg_quirk)
 452                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 453
 454         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 455
 456         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 457
 458         /* Select the HS PHY interface */
 459         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 460         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 461                 if (dwc->hsphy_interface &&
 462                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 463                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 464                         break;
 465                 } else if (dwc->hsphy_interface &&
 466                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 467                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 468                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 469                 } else {
 470                         /* Relying on default value. */
 471                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 472                                 break;
 473                 }
 474                 /* FALLTHROUGH */
 475         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 476                 /* Making sure the interface and PHY are operational */
 477                 ret = dwc3_soft_reset(dwc);
 478                 if (ret)
 479                         return ret;
 480
 481                 udelay(1);
 482
 483                 ret = dwc3_ulpi_init(dwc);
 484                 if (ret)
 485                         return ret;
 486                 /* FALLTHROUGH */
 487         default:
 488                 break;
 489         }
 490
 491         switch (dwc->hsphy_mode) {
 492         case USBPHY_INTERFACE_MODE_UTMI:
 493                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 494                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 495                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 496                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 497                 break;
 498         case USBPHY_INTERFACE_MODE_UTMIW:
 499                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 500                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 501                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 502                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 503                 break;
 504         default:
 505                 break;
 506         }
 507
 508         /*
 509          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 510          * '0' during coreConsultant configuration. So default value will
 511          * be '0' when the core is reset. Application needs to set it to
 512          * '1' after the core initialization is completed.
 513          */
 514         if (dwc->revision > DWC3_REVISION_194A)
 515                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 516
 517         if (dwc->dis_u2_susphy_quirk)
 518                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 519
 520         if (dwc->dis_enblslpm_quirk)
 521                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 522
 523         if (dwc->dis_u2_freeclk_exists_quirk)
 524                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 525
 526         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 527
 528         return 0;
 529 }
 530
 531 static void dwc3_core_exit(struct dwc3 *dwc)
 532 {
 533         dwc3_event_buffers_cleanup(dwc);
 534
 535         usb_phy_shutdown(dwc->usb2_phy);
 536         usb_phy_shutdown(dwc->usb3_phy);
 537         phy_exit(dwc->usb2_generic_phy);
 538         phy_exit(dwc->usb3_generic_phy);
 539
 540         usb_phy_set_suspend(dwc->usb2_phy, 1);
 541         usb_phy_set_suspend(dwc->usb3_phy, 1);
 542         phy_power_off(dwc->usb2_generic_phy);
 543         phy_power_off(dwc->usb3_generic_phy);
 544 }
 545
 546 /**
 547  * dwc3_core_init - Low-level initialization of DWC3 Core
 548  * @dwc: Pointer to our controller context structure
 549  *
 550  * Returns 0 on success otherwise negative errno.
 551  */
 552 static int dwc3_core_init(struct dwc3 *dwc)
 553 {
 554         u32                     hwparams4 = dwc->hwparams.hwparams4;
 555         u32                     reg;
 556         int                     ret;
 557
 558         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 559         /* This should read as U3 followed by revision number */
 560         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 561                 /* Detected DWC_usb3 IP */
 562                 dwc->revision = reg;
 563         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 564                 /* Detected DWC_usb31 IP */
 565                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 566                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 567         } else {
 568                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 569                 ret = -ENODEV;
 570                 goto err0;
 571         }
 572
 573         /*
 574          * Write Linux Version Code to our GUID register so it's easy to figure
 575          * out which kernel version a bug was found.
 576          */
 577         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 578
 579         /* Handle USB2.0-only core configuration */
 580         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 581                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 582                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 583                         dwc->maximum_speed = USB_SPEED_HIGH;
 584         }
 585
 586         /* issue device SoftReset too */
 587         ret = dwc3_soft_reset(dwc);
 588         if (ret)
 589                 goto err0;
 590
 591         ret = dwc3_core_soft_reset(dwc);
 592         if (ret)
 593                 goto err0;
 594
 595         ret = dwc3_phy_setup(dwc);
 596         if (ret)
 597                 goto err0;
 598
 599         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 600         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 601
 602         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 603         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 604                 /**
 605                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 606                  * issue which would cause xHCI compliance tests to fail.
 607                  *
 608                  * Because of that we cannot enable clock gating on such
 609                  * configurations.
 610                  *
 611                  * Refers to:
 612                  *
 613                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 614                  * SOF/ITP Mode Used
 615                  */
 616                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 617                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 618                                 (dwc->revision >= DWC3_REVISION_210A &&
 619                                 dwc->revision <= DWC3_REVISION_250A))
 620                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 621                 else
 622                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 623                 break;
 624         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 625                 /* enable hibernation here */
 626                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 627
 628                 /*
 629                  * REVISIT Enabling this bit so that host-mode hibernation
 630                  * will work. Device-mode hibernation is not yet implemented.
 631                  */
 632                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 633                 break;
 634         default:
 635                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 636         }
 637
 638         /* check if current dwc3 is on simulation board */
 639         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 640                 dwc3_trace(trace_dwc3_core,
 641                                 "running on FPGA platform\n");
 642                 dwc->is_fpga = true;
 643         }
 644
 645         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 646                         "disable_scramble cannot be used on non-FPGA builds\n");
 647
 648         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 649                 reg |= DWC3_GCTL_DISSCRAMBLE;
 650         else
 651                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 652
 653         if (dwc->u2exit_lfps_quirk)
 654                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 655
 656         /*
 657          * WORKAROUND: DWC3 revisions <1.90a have a bug
 658          * where the device can fail to connect at SuperSpeed
 659          * and falls back to high-speed mode which causes
 660          * the device to enter a Connect/Disconnect loop
 661          */
 662         if (dwc->revision < DWC3_REVISION_190A)
 663                 reg |= DWC3_GCTL_U2RSTECN;
 664
 665         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 666
 667         dwc3_core_num_eps(dwc);
 668
 669         ret = dwc3_setup_scratch_buffers(dwc);
 670         if (ret)
 671                 goto err1;
 672
 673         /* Adjust Frame Length */
 674         dwc3_frame_length_adjustment(dwc);
 675
 676         usb_phy_set_suspend(dwc->usb2_phy, 0);
 677         usb_phy_set_suspend(dwc->usb3_phy, 0);
 678         ret = phy_power_on(dwc->usb2_generic_phy);
 679         if (ret < 0)
 680                 goto err2;
 681
 682         ret = phy_power_on(dwc->usb3_generic_phy);
 683         if (ret < 0)
 684                 goto err3;
 685
 686         ret = dwc3_event_buffers_setup(dwc);
 687         if (ret) {
 688                 dev_err(dwc->dev, "failed to setup event buffers\n");
 689                 goto err4;
 690         }
 691
 692         switch (dwc->dr_mode) {
 693         case USB_DR_MODE_PERIPHERAL:
 694                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 695                 break;
 696         case USB_DR_MODE_HOST:
 697                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 698                 break;
 699         case USB_DR_MODE_OTG:
 700                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 701                 break;
 702         default:
 703                 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
 704                 break;
 705         }
 706
 707         return 0;
 708
 709 err4:
 710         phy_power_off(dwc->usb2_generic_phy);
 711
 712 err3:
 713         phy_power_off(dwc->usb3_generic_phy);
 714
 715 err2:
 716         usb_phy_set_suspend(dwc->usb2_phy, 1);
 717         usb_phy_set_suspend(dwc->usb3_phy, 1);
 718         dwc3_core_exit(dwc);
 719
 720 err1:
 721         usb_phy_shutdown(dwc->usb2_phy);
 722         usb_phy_shutdown(dwc->usb3_phy);
 723         phy_exit(dwc->usb2_generic_phy);
 724         phy_exit(dwc->usb3_generic_phy);
 725
 726 err0:
 727         return ret;
 728 }
 729
 730 static int dwc3_core_get_phy(struct dwc3 *dwc)
 731 {
 732         struct device           *dev = dwc->dev;
 733         struct device_node      *node = dev->of_node;
 734         int ret;
 735
 736         if (node) {
 737                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 738                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 739         } else {
 740                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 741                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 742         }
 743
 744         if (IS_ERR(dwc->usb2_phy)) {
 745                 ret = PTR_ERR(dwc->usb2_phy);
 746                 if (ret == -ENXIO || ret == -ENODEV) {
 747                         dwc->usb2_phy = NULL;
 748                 } else if (ret == -EPROBE_DEFER) {
 749                         return ret;
 750                 } else {
 751                         dev_err(dev, "no usb2 phy configured\n");
 752                         return ret;
 753                 }
 754         }
 755
 756         if (IS_ERR(dwc->usb3_phy)) {
 757                 ret = PTR_ERR(dwc->usb3_phy);
 758                 if (ret == -ENXIO || ret == -ENODEV) {
 759                         dwc->usb3_phy = NULL;
 760                 } else if (ret == -EPROBE_DEFER) {
 761                         return ret;
 762                 } else {
 763                         dev_err(dev, "no usb3 phy configured\n");
 764                         return ret;
 765                 }
 766         }
 767
 768         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 769         if (IS_ERR(dwc->usb2_generic_phy)) {
 770                 ret = PTR_ERR(dwc->usb2_generic_phy);
 771                 if (ret == -ENOSYS || ret == -ENODEV) {
 772                         dwc->usb2_generic_phy = NULL;
 773                 } else if (ret == -EPROBE_DEFER) {
 774                         return ret;
 775                 } else {
 776                         dev_err(dev, "no usb2 phy configured\n");
 777                         return ret;
 778                 }
 779         }
 780
 781         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 782         if (IS_ERR(dwc->usb3_generic_phy)) {
 783                 ret = PTR_ERR(dwc->usb3_generic_phy);
 784                 if (ret == -ENOSYS || ret == -ENODEV) {
 785                         dwc->usb3_generic_phy = NULL;
 786                 } else if (ret == -EPROBE_DEFER) {
 787                         return ret;
 788                 } else {
 789                         dev_err(dev, "no usb3 phy configured\n");
 790                         return ret;
 791                 }
 792         }
 793
 794         return 0;
 795 }
 796
 797 static int dwc3_core_init_mode(struct dwc3 *dwc)
 798 {
 799         struct device *dev = dwc->dev;
 800         int ret;
 801
 802         switch (dwc->dr_mode) {
 803         case USB_DR_MODE_PERIPHERAL:
 804                 ret = dwc3_gadget_init(dwc);
 805                 if (ret) {
 806                         if (ret != -EPROBE_DEFER)
 807                                 dev_err(dev, "failed to initialize gadget\n");
 808                         return ret;
 809                 }
 810                 break;
 811         case USB_DR_MODE_HOST:
 812                 ret = dwc3_host_init(dwc);
 813                 if (ret) {
 814                         if (ret != -EPROBE_DEFER)
 815                                 dev_err(dev, "failed to initialize host\n");
 816                         return ret;
 817                 }
 818                 break;
 819         case USB_DR_MODE_OTG:
 820                 ret = dwc3_host_init(dwc);
 821                 if (ret) {
 822                         if (ret != -EPROBE_DEFER)
 823                                 dev_err(dev, "failed to initialize host\n");
 824                         return ret;
 825                 }
 826
 827                 ret = dwc3_gadget_init(dwc);
 828                 if (ret) {
 829                         if (ret != -EPROBE_DEFER)
 830                                 dev_err(dev, "failed to initialize gadget\n");
 831                         return ret;
 832                 }
 833                 break;
 834         default:
 835                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 836                 return -EINVAL;
 837         }
 838
 839         return 0;
 840 }
 841
 842 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 843 {
 844         switch (dwc->dr_mode) {
 845         case USB_DR_MODE_PERIPHERAL:
 846                 dwc3_gadget_exit(dwc);
 847                 break;
 848         case USB_DR_MODE_HOST:
 849                 dwc3_host_exit(dwc);
 850                 break;
 851         case USB_DR_MODE_OTG:
 852                 dwc3_host_exit(dwc);
 853                 dwc3_gadget_exit(dwc);
 854                 break;
 855         default:
 856                 /* do nothing */
 857                 break;
 858         }
 859 }
 860
 861 #define DWC3_ALIGN_MASK         (16 - 1)
 862
 863 static int dwc3_probe(struct platform_device *pdev)
 864 {
 865         struct device           *dev = &pdev->dev;
 866         struct resource         *res;
 867         struct dwc3             *dwc;
 868         u8                      lpm_nyet_threshold;
 869         u8                      tx_de_emphasis;
 870         u8                      hird_threshold;
 871
 872         int                     ret;
 873
 874         void __iomem            *regs;
 875         void                    *mem;
 876
 877         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 878         if (!mem)
 879                 return -ENOMEM;
 880
 881         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 882         dwc->mem = mem;
 883         dwc->dev = dev;
 884
 885         /* Try to set 64-bit DMA first */
 886         if (!pdev->dev.dma_mask)
 887                 /* Platform did not initialize dma_mask */
 888                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 889                                                    DMA_BIT_MASK(64));
 890         else
 891                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 892
 893         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 894         if (ret) {
 895                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 896                 if (ret)
 897                         return ret;
 898         }
 899
 900         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 901         if (!res) {
 902                 dev_err(dev, "missing memory resource\n");
 903                 return -ENODEV;
 904         }
 905
 906         dwc->xhci_resources[0].start = res->start;
 907         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 908                                         DWC3_XHCI_REGS_END;
 909         dwc->xhci_resources[0].flags = res->flags;
 910         dwc->xhci_resources[0].name = res->name;
 911
 912         res->start += DWC3_GLOBALS_REGS_START;
 913
 914         /*
 915          * Request memory region but exclude xHCI regs,
 916          * since it will be requested by the xhci-plat driver.
 917          */
 918         regs = devm_ioremap_resource(dev, res);
 919         if (IS_ERR(regs)) {
 920                 ret = PTR_ERR(regs);
 921                 goto err0;
 922         }
 923
 924         dwc->regs       = regs;
 925         dwc->regs_size  = resource_size(res);
 926
 927         /* default to highest possible threshold */
 928         lpm_nyet_threshold = 0xff;
 929
 930         /* default to -3.5dB de-emphasis */
 931         tx_de_emphasis = 1;
 932
 933         /*
 934          * default to assert utmi_sleep_n and use maximum allowed HIRD
 935          * threshold value of 0b1100
 936          */
 937         hird_threshold = 12;
 938
 939         dwc->maximum_speed = usb_get_maximum_speed(dev);
 940         dwc->dr_mode = usb_get_dr_mode(dev);
 941         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
 942
 943         dwc->has_lpm_erratum = device_property_read_bool(dev,
 944                                 "snps,has-lpm-erratum");
 945         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 946                                 &lpm_nyet_threshold);
 947         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 948                                 "snps,is-utmi-l1-suspend");
 949         device_property_read_u8(dev, "snps,hird-threshold",
 950                                 &hird_threshold);
 951         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 952                                 "snps,usb3_lpm_capable");
 953
 954         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 955                                 "snps,disable_scramble_quirk");
 956         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 957                                 "snps,u2exit_lfps_quirk");
 958         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 959                                 "snps,u2ss_inp3_quirk");
 960         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 961                                 "snps,req_p1p2p3_quirk");
 962         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 963                                 "snps,del_p1p2p3_quirk");
 964         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 965                                 "snps,del_phy_power_chg_quirk");
 966         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 967                                 "snps,lfps_filter_quirk");
 968         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 969                                 "snps,rx_detect_poll_quirk");
 970         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 971                                 "snps,dis_u3_susphy_quirk");
 972         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 973                                 "snps,dis_u2_susphy_quirk");
 974         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 975                                 "snps,dis_enblslpm_quirk");
 976         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 977                                 "snps,dis_rxdet_inp3_quirk");
 978         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 979                                 "snps,dis-u2-freeclk-exists-quirk");
 980         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
 981                                 "snps,dis-del-phy-power-chg-quirk");
 982         dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
 983                                 "snps,xhci-slow-suspend-quirk");
 984
 985         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 986                                 "snps,tx_de_emphasis_quirk");
 987         device_property_read_u8(dev, "snps,tx_de_emphasis",
 988                                 &tx_de_emphasis);
 989         device_property_read_string(dev, "snps,hsphy_interface",
 990                                     &dwc->hsphy_interface);
 991         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 992                                  &dwc->fladj);
 993
 994         /* default to superspeed if no maximum_speed passed */
 995         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 996                 dwc->maximum_speed = USB_SPEED_SUPER;
 997
 998         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 999         dwc->tx_de_emphasis = tx_de_emphasis;
1000
1001         dwc->hird_threshold = hird_threshold
1002                 | (dwc->is_utmi_l1_suspend << 4);
1003
1004         platform_set_drvdata(pdev, dwc);
1005         dwc3_cache_hwparams(dwc);
1006
1007         ret = dwc3_core_get_phy(dwc);
1008         if (ret)
1009                 goto err0;
1010
1011         spin_lock_init(&dwc->lock);
1012
1013         if (!dev->dma_mask) {
1014                 dev->dma_mask = dev->parent->dma_mask;
1015                 dev->dma_parms = dev->parent->dma_parms;
1016                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1017         }
1018
1019         pm_runtime_set_active(dev);
1020         pm_runtime_use_autosuspend(dev);
1021         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1022         pm_runtime_enable(dev);
1023         ret = pm_runtime_get_sync(dev);
1024         if (ret < 0)
1025                 goto err1;
1026
1027         pm_runtime_forbid(dev);
1028
1029         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1030         if (ret) {
1031                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1032                 ret = -ENOMEM;
1033                 goto err2;
1034         }
1035
1036         if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
1037                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1038                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1039                 dwc->dr_mode = USB_DR_MODE_HOST;
1040         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
1041                         (dwc->dr_mode == USB_DR_MODE_OTG ||
1042                                         dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1043                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1044
1045         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1046                 dwc->dr_mode = USB_DR_MODE_OTG;
1047
1048         ret = dwc3_alloc_scratch_buffers(dwc);
1049         if (ret)
1050                 goto err3;
1051
1052         ret = dwc3_core_init(dwc);
1053         if (ret) {
1054                 dev_err(dev, "failed to initialize core\n");
1055                 goto err4;
1056         }
1057
1058         ret = dwc3_core_init_mode(dwc);
1059         if (ret)
1060                 goto err5;
1061
1062         dwc3_debugfs_init(dwc);
1063         pm_runtime_put(dev);
1064
1065         return 0;
1066
1067 err5:
1068         dwc3_event_buffers_cleanup(dwc);
1069
1070 err4:
1071         dwc3_free_scratch_buffers(dwc);
1072
1073 err3:
1074         dwc3_free_event_buffers(dwc);
1075         dwc3_ulpi_exit(dwc);
1076
1077 err2:
1078         pm_runtime_allow(&pdev->dev);
1079
1080 err1:
1081         pm_runtime_put_sync(&pdev->dev);
1082         pm_runtime_disable(&pdev->dev);
1083
1084 err0:
1085         /*
1086          * restore res->start back to its original value so that, in case the
1087          * probe is deferred, we don't end up getting error in request the
1088          * memory region the next time probe is called.
1089          */
1090         res->start -= DWC3_GLOBALS_REGS_START;
1091
1092         return ret;
1093 }
1094
1095 static int dwc3_remove(struct platform_device *pdev)
1096 {
1097         struct dwc3     *dwc = platform_get_drvdata(pdev);
1098         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099
1100         pm_runtime_get_sync(&pdev->dev);
1101         /*
1102          * restore res->start back to its original value so that, in case the
1103          * probe is deferred, we don't end up getting error in request the
1104          * memory region the next time probe is called.
1105          */
1106         res->start -= DWC3_GLOBALS_REGS_START;
1107
1108         dwc3_debugfs_exit(dwc);
1109         dwc3_core_exit_mode(dwc);
1110
1111         dwc3_core_exit(dwc);
1112         dwc3_ulpi_exit(dwc);
1113
1114         pm_runtime_put_sync(&pdev->dev);
1115         pm_runtime_allow(&pdev->dev);
1116         pm_runtime_disable(&pdev->dev);
1117
1118         dwc3_free_event_buffers(dwc);
1119         dwc3_free_scratch_buffers(dwc);
1120
1121         return 0;
1122 }
1123
1124 #ifdef CONFIG_PM
1125 static int dwc3_suspend_common(struct dwc3 *dwc)
1126 {
1127         unsigned long   flags;
1128
1129         switch (dwc->dr_mode) {
1130         case USB_DR_MODE_PERIPHERAL:
1131         case USB_DR_MODE_OTG:
1132                 spin_lock_irqsave(&dwc->lock, flags);
1133                 dwc3_gadget_suspend(dwc);
1134                 spin_unlock_irqrestore(&dwc->lock, flags);
1135                 break;
1136         case USB_DR_MODE_HOST:
1137         default:
1138                 /* do nothing */
1139                 break;
1140         }
1141
1142         dwc3_core_exit(dwc);
1143
1144         return 0;
1145 }
1146
1147 static int dwc3_resume_common(struct dwc3 *dwc)
1148 {
1149         unsigned long   flags;
1150         int             ret;
1151
1152         ret = dwc3_core_init(dwc);
1153         if (ret)
1154                 return ret;
1155
1156         switch (dwc->dr_mode) {
1157         case USB_DR_MODE_PERIPHERAL:
1158         case USB_DR_MODE_OTG:
1159                 spin_lock_irqsave(&dwc->lock, flags);
1160                 dwc3_gadget_resume(dwc);
1161                 spin_unlock_irqrestore(&dwc->lock, flags);
1162                 /* FALLTHROUGH */
1163         case USB_DR_MODE_HOST:
1164         default:
1165                 /* do nothing */
1166                 break;
1167         }
1168
1169         return 0;
1170 }
1171
1172 static int dwc3_runtime_checks(struct dwc3 *dwc)
1173 {
1174         switch (dwc->dr_mode) {
1175         case USB_DR_MODE_PERIPHERAL:
1176         case USB_DR_MODE_OTG:
1177                 if (dwc->connected)
1178                         return -EBUSY;
1179                 break;
1180         case USB_DR_MODE_HOST:
1181         default:
1182                 /* do nothing */
1183                 break;
1184         }
1185
1186         return 0;
1187 }
1188
1189 static int dwc3_runtime_suspend(struct device *dev)
1190 {
1191         struct dwc3     *dwc = dev_get_drvdata(dev);
1192         int             ret;
1193
1194         if (dwc3_runtime_checks(dwc))
1195                 return -EBUSY;
1196
1197         ret = dwc3_suspend_common(dwc);
1198         if (ret)
1199                 return ret;
1200
1201         device_init_wakeup(dev, true);
1202
1203         return 0;
1204 }
1205
1206 static int dwc3_runtime_resume(struct device *dev)
1207 {
1208         struct dwc3     *dwc = dev_get_drvdata(dev);
1209         int             ret;
1210
1211         device_init_wakeup(dev, false);
1212
1213         ret = dwc3_resume_common(dwc);
1214         if (ret)
1215                 return ret;
1216
1217         switch (dwc->dr_mode) {
1218         case USB_DR_MODE_PERIPHERAL:
1219         case USB_DR_MODE_OTG:
1220                 dwc3_gadget_process_pending_events(dwc);
1221                 break;
1222         case USB_DR_MODE_HOST:
1223         default:
1224                 /* do nothing */
1225                 break;
1226         }
1227
1228         pm_runtime_mark_last_busy(dev);
1229
1230         return 0;
1231 }
1232
1233 static int dwc3_runtime_idle(struct device *dev)
1234 {
1235         struct dwc3     *dwc = dev_get_drvdata(dev);
1236
1237         switch (dwc->dr_mode) {
1238         case USB_DR_MODE_PERIPHERAL:
1239         case USB_DR_MODE_OTG:
1240                 if (dwc3_runtime_checks(dwc))
1241                         return -EBUSY;
1242                 break;
1243         case USB_DR_MODE_HOST:
1244         default:
1245                 /* do nothing */
1246                 break;
1247         }
1248
1249         pm_runtime_mark_last_busy(dev);
1250         pm_runtime_autosuspend(dev);
1251
1252         return 0;
1253 }
1254 #endif /* CONFIG_PM */
1255
1256 #ifdef CONFIG_PM_SLEEP
1257 static int dwc3_suspend(struct device *dev)
1258 {
1259         struct dwc3     *dwc = dev_get_drvdata(dev);
1260         int             ret;
1261
1262         if (pm_runtime_suspended(dwc->dev))
1263                 return 0;
1264
1265         ret = dwc3_suspend_common(dwc);
1266         if (ret)
1267                 return ret;
1268
1269         pinctrl_pm_select_sleep_state(dev);
1270
1271         return 0;
1272 }
1273
1274 static int dwc3_resume(struct device *dev)
1275 {
1276         struct dwc3     *dwc = dev_get_drvdata(dev);
1277         int             ret;
1278
1279         if (pm_runtime_suspended(dwc->dev))
1280                 return 0;
1281
1282         pinctrl_pm_select_default_state(dev);
1283
1284         ret = dwc3_resume_common(dwc);
1285         if (ret)
1286                 return ret;
1287
1288         pm_runtime_disable(dev);
1289         pm_runtime_set_active(dev);
1290         pm_runtime_enable(dev);
1291
1292         return 0;
1293 }
1294 #endif /* CONFIG_PM_SLEEP */
1295
1296 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1297         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1298         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1299                         dwc3_runtime_idle)
1300 };
1301
1302 #ifdef CONFIG_OF
1303 static const struct of_device_id of_dwc3_match[] = {
1304         {
1305                 .compatible = "snps,dwc3"
1306         },
1307         {
1308                 .compatible = "synopsys,dwc3"
1309         },
1310         { },
1311 };
1312 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1313 #endif
1314
1315 #ifdef CONFIG_ACPI
1316
1317 #define ACPI_ID_INTEL_BSW       "808622B7"
1318
1319 static const struct acpi_device_id dwc3_acpi_match[] = {
1320         { ACPI_ID_INTEL_BSW, 0 },
1321         { },
1322 };
1323 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1324 #endif
1325
1326 static struct platform_driver dwc3_driver = {
1327         .probe          = dwc3_probe,
1328         .remove         = dwc3_remove,
1329         .driver         = {
1330                 .name   = "dwc3",
1331                 .of_match_table = of_match_ptr(of_dwc3_match),
1332                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1333                 .pm     = &dwc3_dev_pm_ops,
1334         },
1335 };
1336
1337 module_platform_driver(dwc3_driver);
1338
1339 MODULE_ALIAS("platform:dwc3");
1340 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1341 MODULE_LICENSE("GPL v2");
1342 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");