2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
56 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
58 reg |= DWC3_GCTL_PRTCAPDIR(mode);
59 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
62 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
64 struct dwc3 *dwc = dep->dwc;
67 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
68 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
69 DWC3_GDBGFIFOSPACE_TYPE(type));
71 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
73 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
77 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
78 * @dwc: pointer to our context structure
80 static int dwc3_core_soft_reset(struct dwc3 *dwc)
86 usb_phy_init(dwc->usb2_phy);
87 usb_phy_init(dwc->usb3_phy);
88 ret = phy_init(dwc->usb2_generic_phy);
92 ret = phy_init(dwc->usb3_generic_phy);
94 phy_exit(dwc->usb2_generic_phy);
99 * We're resetting only the device side because, if we're in host mode,
100 * XHCI driver will reset the host block. If dwc3 was configured for
101 * host-only mode, then we can return early.
103 if (dwc->dr_mode == USB_DR_MODE_HOST)
106 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
107 reg |= DWC3_DCTL_CSFTRST;
108 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 if (!(reg & DWC3_DCTL_CSFTRST))
122 * dwc3_soft_reset - Issue soft reset
123 * @dwc: Pointer to our controller context structure
125 static int dwc3_soft_reset(struct dwc3 *dwc)
127 unsigned long timeout;
130 timeout = jiffies + msecs_to_jiffies(500);
131 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
133 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
134 if (!(reg & DWC3_DCTL_CSFTRST))
137 if (time_after(jiffies, timeout)) {
138 dev_err(dwc->dev, "Reset Timed Out\n");
149 * dwc3_frame_length_adjustment - Adjusts frame length if required
150 * @dwc3: Pointer to our controller context structure
152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
157 if (dwc->revision < DWC3_REVISION_250A)
163 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
164 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
165 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
166 "request value same as default, ignoring\n")) {
167 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
168 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
169 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
174 * dwc3_free_one_event_buffer - Frees one event buffer
175 * @dwc: Pointer to our controller context structure
176 * @evt: Pointer to event buffer to be freed
178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
179 struct dwc3_event_buffer *evt)
181 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
185 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
186 * @dwc: Pointer to our controller context structure
187 * @length: size of the event buffer
189 * Returns a pointer to the allocated event buffer structure on success
190 * otherwise ERR_PTR(errno).
192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
195 struct dwc3_event_buffer *evt;
197 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
199 return ERR_PTR(-ENOMEM);
202 evt->length = length;
203 evt->buf = dma_alloc_coherent(dwc->dev, length,
204 &evt->dma, GFP_KERNEL);
206 return ERR_PTR(-ENOMEM);
212 * dwc3_free_event_buffers - frees all allocated event buffers
213 * @dwc: Pointer to our controller context structure
215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
217 struct dwc3_event_buffer *evt;
221 dwc3_free_one_event_buffer(dwc, evt);
225 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
226 * @dwc: pointer to our controller context structure
227 * @length: size of event buffer
229 * Returns 0 on success otherwise negative errno. In the error case, dwc
230 * may contain some buffers allocated but not all which were requested.
232 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
234 struct dwc3_event_buffer *evt;
236 evt = dwc3_alloc_one_event_buffer(dwc, length);
238 dev_err(dwc->dev, "can't allocate event buffer\n");
247 * dwc3_event_buffers_setup - setup our allocated event buffers
248 * @dwc: pointer to our controller context structure
250 * Returns 0 on success otherwise negative errno.
252 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
254 struct dwc3_event_buffer *evt;
257 dwc3_trace(trace_dwc3_core,
258 "Event buf %p dma %08llx length %d\n",
259 evt->buf, (unsigned long long) evt->dma,
264 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
265 lower_32_bits(evt->dma));
266 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
267 upper_32_bits(evt->dma));
268 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
269 DWC3_GEVNTSIZ_SIZE(evt->length));
270 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
275 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
277 struct dwc3_event_buffer *evt;
283 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
285 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
286 | DWC3_GEVNTSIZ_SIZE(0));
287 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
290 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
292 if (!dwc->has_hibernation)
295 if (!dwc->nr_scratch)
298 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
299 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
300 if (!dwc->scratchbuf)
306 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
308 dma_addr_t scratch_addr;
312 if (!dwc->has_hibernation)
315 if (!dwc->nr_scratch)
318 /* should never fall here */
319 if (!WARN_ON(dwc->scratchbuf))
322 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
323 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
325 if (dma_mapping_error(dwc->dev, scratch_addr)) {
326 dev_err(dwc->dev, "failed to map scratch buffer\n");
331 dwc->scratch_addr = scratch_addr;
333 param = lower_32_bits(scratch_addr);
335 ret = dwc3_send_gadget_generic_command(dwc,
336 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
340 param = upper_32_bits(scratch_addr);
342 ret = dwc3_send_gadget_generic_command(dwc,
343 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
350 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
351 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
357 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
359 if (!dwc->has_hibernation)
362 if (!dwc->nr_scratch)
365 /* should never fall here */
366 if (!WARN_ON(dwc->scratchbuf))
369 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
370 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
371 kfree(dwc->scratchbuf);
374 static void dwc3_core_num_eps(struct dwc3 *dwc)
376 struct dwc3_hwparams *parms = &dwc->hwparams;
378 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
379 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
381 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
382 dwc->num_in_eps, dwc->num_out_eps);
385 static void dwc3_cache_hwparams(struct dwc3 *dwc)
387 struct dwc3_hwparams *parms = &dwc->hwparams;
389 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
390 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
391 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
392 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
393 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
394 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
395 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
396 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
397 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
401 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
402 * @dwc: Pointer to our controller context structure
404 * Returns 0 on success. The USB PHY interfaces are configured but not
405 * initialized. The PHY interfaces and the PHYs get initialized together with
406 * the core in dwc3_core_init.
408 static int dwc3_phy_setup(struct dwc3 *dwc)
413 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
416 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
417 * to '0' during coreConsultant configuration. So default value
418 * will be '0' when the core is reset. Application needs to set it
419 * to '1' after the core initialization is completed.
421 if (dwc->revision > DWC3_REVISION_194A)
422 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
424 if (dwc->u2ss_inp3_quirk)
425 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
427 if (dwc->dis_rxdet_inp3_quirk)
428 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
430 if (dwc->req_p1p2p3_quirk)
431 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
433 if (dwc->del_p1p2p3_quirk)
434 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
436 if (dwc->del_phy_power_chg_quirk)
437 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
439 if (dwc->lfps_filter_quirk)
440 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
442 if (dwc->rx_detect_poll_quirk)
443 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
445 if (dwc->tx_de_emphasis_quirk)
446 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
448 if (dwc->dis_u3_susphy_quirk)
449 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
451 if (dwc->dis_del_phy_power_chg_quirk)
452 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
454 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
456 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
458 /* Select the HS PHY interface */
459 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
460 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
461 if (dwc->hsphy_interface &&
462 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
463 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
465 } else if (dwc->hsphy_interface &&
466 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
467 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
468 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
470 /* Relying on default value. */
471 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
475 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
476 /* Making sure the interface and PHY are operational */
477 ret = dwc3_soft_reset(dwc);
483 ret = dwc3_ulpi_init(dwc);
491 switch (dwc->hsphy_mode) {
492 case USBPHY_INTERFACE_MODE_UTMI:
493 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
494 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
495 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
496 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
498 case USBPHY_INTERFACE_MODE_UTMIW:
499 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
500 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
501 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
502 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
509 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
510 * '0' during coreConsultant configuration. So default value will
511 * be '0' when the core is reset. Application needs to set it to
512 * '1' after the core initialization is completed.
514 if (dwc->revision > DWC3_REVISION_194A)
515 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
517 if (dwc->dis_u2_susphy_quirk)
518 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
520 if (dwc->dis_enblslpm_quirk)
521 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
523 if (dwc->dis_u2_freeclk_exists_quirk)
524 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
526 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
531 static void dwc3_core_exit(struct dwc3 *dwc)
533 dwc3_event_buffers_cleanup(dwc);
535 usb_phy_shutdown(dwc->usb2_phy);
536 usb_phy_shutdown(dwc->usb3_phy);
537 phy_exit(dwc->usb2_generic_phy);
538 phy_exit(dwc->usb3_generic_phy);
540 usb_phy_set_suspend(dwc->usb2_phy, 1);
541 usb_phy_set_suspend(dwc->usb3_phy, 1);
542 phy_power_off(dwc->usb2_generic_phy);
543 phy_power_off(dwc->usb3_generic_phy);
547 * dwc3_core_init - Low-level initialization of DWC3 Core
548 * @dwc: Pointer to our controller context structure
550 * Returns 0 on success otherwise negative errno.
552 static int dwc3_core_init(struct dwc3 *dwc)
554 u32 hwparams4 = dwc->hwparams.hwparams4;
558 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
559 /* This should read as U3 followed by revision number */
560 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
561 /* Detected DWC_usb3 IP */
563 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
564 /* Detected DWC_usb31 IP */
565 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
566 dwc->revision |= DWC3_REVISION_IS_DWC31;
568 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
574 * Write Linux Version Code to our GUID register so it's easy to figure
575 * out which kernel version a bug was found.
577 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
579 /* Handle USB2.0-only core configuration */
580 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
581 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
582 if (dwc->maximum_speed == USB_SPEED_SUPER)
583 dwc->maximum_speed = USB_SPEED_HIGH;
586 /* issue device SoftReset too */
587 ret = dwc3_soft_reset(dwc);
591 ret = dwc3_core_soft_reset(dwc);
595 ret = dwc3_phy_setup(dwc);
599 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
600 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
602 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
603 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
605 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
606 * issue which would cause xHCI compliance tests to fail.
608 * Because of that we cannot enable clock gating on such
613 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
616 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
617 dwc->dr_mode == USB_DR_MODE_OTG) &&
618 (dwc->revision >= DWC3_REVISION_210A &&
619 dwc->revision <= DWC3_REVISION_250A))
620 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
622 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
624 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
625 /* enable hibernation here */
626 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
629 * REVISIT Enabling this bit so that host-mode hibernation
630 * will work. Device-mode hibernation is not yet implemented.
632 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
635 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
638 /* check if current dwc3 is on simulation board */
639 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
640 dwc3_trace(trace_dwc3_core,
641 "running on FPGA platform\n");
645 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
646 "disable_scramble cannot be used on non-FPGA builds\n");
648 if (dwc->disable_scramble_quirk && dwc->is_fpga)
649 reg |= DWC3_GCTL_DISSCRAMBLE;
651 reg &= ~DWC3_GCTL_DISSCRAMBLE;
653 if (dwc->u2exit_lfps_quirk)
654 reg |= DWC3_GCTL_U2EXIT_LFPS;
657 * WORKAROUND: DWC3 revisions <1.90a have a bug
658 * where the device can fail to connect at SuperSpeed
659 * and falls back to high-speed mode which causes
660 * the device to enter a Connect/Disconnect loop
662 if (dwc->revision < DWC3_REVISION_190A)
663 reg |= DWC3_GCTL_U2RSTECN;
665 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
667 dwc3_core_num_eps(dwc);
669 ret = dwc3_setup_scratch_buffers(dwc);
673 /* Adjust Frame Length */
674 dwc3_frame_length_adjustment(dwc);
676 usb_phy_set_suspend(dwc->usb2_phy, 0);
677 usb_phy_set_suspend(dwc->usb3_phy, 0);
678 ret = phy_power_on(dwc->usb2_generic_phy);
682 ret = phy_power_on(dwc->usb3_generic_phy);
686 ret = dwc3_event_buffers_setup(dwc);
688 dev_err(dwc->dev, "failed to setup event buffers\n");
692 switch (dwc->dr_mode) {
693 case USB_DR_MODE_PERIPHERAL:
694 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
696 case USB_DR_MODE_HOST:
697 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
699 case USB_DR_MODE_OTG:
700 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
703 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
710 phy_power_off(dwc->usb2_generic_phy);
713 phy_power_off(dwc->usb3_generic_phy);
716 usb_phy_set_suspend(dwc->usb2_phy, 1);
717 usb_phy_set_suspend(dwc->usb3_phy, 1);
721 usb_phy_shutdown(dwc->usb2_phy);
722 usb_phy_shutdown(dwc->usb3_phy);
723 phy_exit(dwc->usb2_generic_phy);
724 phy_exit(dwc->usb3_generic_phy);
730 static int dwc3_core_get_phy(struct dwc3 *dwc)
732 struct device *dev = dwc->dev;
733 struct device_node *node = dev->of_node;
737 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
738 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
740 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
741 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
744 if (IS_ERR(dwc->usb2_phy)) {
745 ret = PTR_ERR(dwc->usb2_phy);
746 if (ret == -ENXIO || ret == -ENODEV) {
747 dwc->usb2_phy = NULL;
748 } else if (ret == -EPROBE_DEFER) {
751 dev_err(dev, "no usb2 phy configured\n");
756 if (IS_ERR(dwc->usb3_phy)) {
757 ret = PTR_ERR(dwc->usb3_phy);
758 if (ret == -ENXIO || ret == -ENODEV) {
759 dwc->usb3_phy = NULL;
760 } else if (ret == -EPROBE_DEFER) {
763 dev_err(dev, "no usb3 phy configured\n");
768 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
769 if (IS_ERR(dwc->usb2_generic_phy)) {
770 ret = PTR_ERR(dwc->usb2_generic_phy);
771 if (ret == -ENOSYS || ret == -ENODEV) {
772 dwc->usb2_generic_phy = NULL;
773 } else if (ret == -EPROBE_DEFER) {
776 dev_err(dev, "no usb2 phy configured\n");
781 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
782 if (IS_ERR(dwc->usb3_generic_phy)) {
783 ret = PTR_ERR(dwc->usb3_generic_phy);
784 if (ret == -ENOSYS || ret == -ENODEV) {
785 dwc->usb3_generic_phy = NULL;
786 } else if (ret == -EPROBE_DEFER) {
789 dev_err(dev, "no usb3 phy configured\n");
797 static int dwc3_core_init_mode(struct dwc3 *dwc)
799 struct device *dev = dwc->dev;
802 switch (dwc->dr_mode) {
803 case USB_DR_MODE_PERIPHERAL:
804 ret = dwc3_gadget_init(dwc);
806 if (ret != -EPROBE_DEFER)
807 dev_err(dev, "failed to initialize gadget\n");
811 case USB_DR_MODE_HOST:
812 ret = dwc3_host_init(dwc);
814 if (ret != -EPROBE_DEFER)
815 dev_err(dev, "failed to initialize host\n");
819 case USB_DR_MODE_OTG:
820 ret = dwc3_host_init(dwc);
822 if (ret != -EPROBE_DEFER)
823 dev_err(dev, "failed to initialize host\n");
827 ret = dwc3_gadget_init(dwc);
829 if (ret != -EPROBE_DEFER)
830 dev_err(dev, "failed to initialize gadget\n");
835 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
842 static void dwc3_core_exit_mode(struct dwc3 *dwc)
844 switch (dwc->dr_mode) {
845 case USB_DR_MODE_PERIPHERAL:
846 dwc3_gadget_exit(dwc);
848 case USB_DR_MODE_HOST:
851 case USB_DR_MODE_OTG:
853 dwc3_gadget_exit(dwc);
861 #define DWC3_ALIGN_MASK (16 - 1)
863 static int dwc3_probe(struct platform_device *pdev)
865 struct device *dev = &pdev->dev;
866 struct resource *res;
868 u8 lpm_nyet_threshold;
877 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
881 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
885 /* Try to set 64-bit DMA first */
886 if (!pdev->dev.dma_mask)
887 /* Platform did not initialize dma_mask */
888 ret = dma_coerce_mask_and_coherent(&pdev->dev,
891 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
893 /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
895 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
900 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 dev_err(dev, "missing memory resource\n");
906 dwc->xhci_resources[0].start = res->start;
907 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
909 dwc->xhci_resources[0].flags = res->flags;
910 dwc->xhci_resources[0].name = res->name;
912 res->start += DWC3_GLOBALS_REGS_START;
915 * Request memory region but exclude xHCI regs,
916 * since it will be requested by the xhci-plat driver.
918 regs = devm_ioremap_resource(dev, res);
925 dwc->regs_size = resource_size(res);
927 /* default to highest possible threshold */
928 lpm_nyet_threshold = 0xff;
930 /* default to -3.5dB de-emphasis */
934 * default to assert utmi_sleep_n and use maximum allowed HIRD
935 * threshold value of 0b1100
939 dwc->maximum_speed = usb_get_maximum_speed(dev);
940 dwc->dr_mode = usb_get_dr_mode(dev);
941 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
943 dwc->has_lpm_erratum = device_property_read_bool(dev,
944 "snps,has-lpm-erratum");
945 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
946 &lpm_nyet_threshold);
947 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
948 "snps,is-utmi-l1-suspend");
949 device_property_read_u8(dev, "snps,hird-threshold",
951 dwc->usb3_lpm_capable = device_property_read_bool(dev,
952 "snps,usb3_lpm_capable");
954 dwc->disable_scramble_quirk = device_property_read_bool(dev,
955 "snps,disable_scramble_quirk");
956 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
957 "snps,u2exit_lfps_quirk");
958 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
959 "snps,u2ss_inp3_quirk");
960 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
961 "snps,req_p1p2p3_quirk");
962 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
963 "snps,del_p1p2p3_quirk");
964 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
965 "snps,del_phy_power_chg_quirk");
966 dwc->lfps_filter_quirk = device_property_read_bool(dev,
967 "snps,lfps_filter_quirk");
968 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
969 "snps,rx_detect_poll_quirk");
970 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
971 "snps,dis_u3_susphy_quirk");
972 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
973 "snps,dis_u2_susphy_quirk");
974 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
975 "snps,dis_enblslpm_quirk");
976 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
977 "snps,dis_rxdet_inp3_quirk");
978 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
979 "snps,dis-u2-freeclk-exists-quirk");
980 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
981 "snps,dis-del-phy-power-chg-quirk");
982 dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
983 "snps,xhci-slow-suspend-quirk");
985 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
986 "snps,tx_de_emphasis_quirk");
987 device_property_read_u8(dev, "snps,tx_de_emphasis",
989 device_property_read_string(dev, "snps,hsphy_interface",
990 &dwc->hsphy_interface);
991 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
994 /* default to superspeed if no maximum_speed passed */
995 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
996 dwc->maximum_speed = USB_SPEED_SUPER;
998 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
999 dwc->tx_de_emphasis = tx_de_emphasis;
1001 dwc->hird_threshold = hird_threshold
1002 | (dwc->is_utmi_l1_suspend << 4);
1004 platform_set_drvdata(pdev, dwc);
1005 dwc3_cache_hwparams(dwc);
1007 ret = dwc3_core_get_phy(dwc);
1011 spin_lock_init(&dwc->lock);
1013 if (!dev->dma_mask) {
1014 dev->dma_mask = dev->parent->dma_mask;
1015 dev->dma_parms = dev->parent->dma_parms;
1016 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1019 pm_runtime_set_active(dev);
1020 pm_runtime_use_autosuspend(dev);
1021 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1022 pm_runtime_enable(dev);
1023 ret = pm_runtime_get_sync(dev);
1027 pm_runtime_forbid(dev);
1029 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1031 dev_err(dwc->dev, "failed to allocate event buffers\n");
1036 if (IS_ENABLED(CONFIG_USB_DWC3_HOST) &&
1037 (dwc->dr_mode == USB_DR_MODE_OTG ||
1038 dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1039 dwc->dr_mode = USB_DR_MODE_HOST;
1040 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET) &&
1041 (dwc->dr_mode == USB_DR_MODE_OTG ||
1042 dwc->dr_mode == USB_DR_MODE_UNKNOWN))
1043 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1045 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1046 dwc->dr_mode = USB_DR_MODE_OTG;
1048 ret = dwc3_alloc_scratch_buffers(dwc);
1052 ret = dwc3_core_init(dwc);
1054 dev_err(dev, "failed to initialize core\n");
1058 ret = dwc3_core_init_mode(dwc);
1062 dwc3_debugfs_init(dwc);
1063 pm_runtime_put(dev);
1068 dwc3_event_buffers_cleanup(dwc);
1071 dwc3_free_scratch_buffers(dwc);
1074 dwc3_free_event_buffers(dwc);
1075 dwc3_ulpi_exit(dwc);
1078 pm_runtime_allow(&pdev->dev);
1081 pm_runtime_put_sync(&pdev->dev);
1082 pm_runtime_disable(&pdev->dev);
1086 * restore res->start back to its original value so that, in case the
1087 * probe is deferred, we don't end up getting error in request the
1088 * memory region the next time probe is called.
1090 res->start -= DWC3_GLOBALS_REGS_START;
1095 static int dwc3_remove(struct platform_device *pdev)
1097 struct dwc3 *dwc = platform_get_drvdata(pdev);
1098 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1100 pm_runtime_get_sync(&pdev->dev);
1102 * restore res->start back to its original value so that, in case the
1103 * probe is deferred, we don't end up getting error in request the
1104 * memory region the next time probe is called.
1106 res->start -= DWC3_GLOBALS_REGS_START;
1108 dwc3_debugfs_exit(dwc);
1109 dwc3_core_exit_mode(dwc);
1111 dwc3_core_exit(dwc);
1112 dwc3_ulpi_exit(dwc);
1114 pm_runtime_put_sync(&pdev->dev);
1115 pm_runtime_allow(&pdev->dev);
1116 pm_runtime_disable(&pdev->dev);
1118 dwc3_free_event_buffers(dwc);
1119 dwc3_free_scratch_buffers(dwc);
1125 static int dwc3_suspend_common(struct dwc3 *dwc)
1127 unsigned long flags;
1129 switch (dwc->dr_mode) {
1130 case USB_DR_MODE_PERIPHERAL:
1131 case USB_DR_MODE_OTG:
1132 spin_lock_irqsave(&dwc->lock, flags);
1133 dwc3_gadget_suspend(dwc);
1134 spin_unlock_irqrestore(&dwc->lock, flags);
1136 case USB_DR_MODE_HOST:
1142 dwc3_core_exit(dwc);
1147 static int dwc3_resume_common(struct dwc3 *dwc)
1149 unsigned long flags;
1152 ret = dwc3_core_init(dwc);
1156 switch (dwc->dr_mode) {
1157 case USB_DR_MODE_PERIPHERAL:
1158 case USB_DR_MODE_OTG:
1159 spin_lock_irqsave(&dwc->lock, flags);
1160 dwc3_gadget_resume(dwc);
1161 spin_unlock_irqrestore(&dwc->lock, flags);
1163 case USB_DR_MODE_HOST:
1172 static int dwc3_runtime_checks(struct dwc3 *dwc)
1174 switch (dwc->dr_mode) {
1175 case USB_DR_MODE_PERIPHERAL:
1176 case USB_DR_MODE_OTG:
1180 case USB_DR_MODE_HOST:
1189 static int dwc3_runtime_suspend(struct device *dev)
1191 struct dwc3 *dwc = dev_get_drvdata(dev);
1194 if (dwc3_runtime_checks(dwc))
1197 ret = dwc3_suspend_common(dwc);
1201 device_init_wakeup(dev, true);
1206 static int dwc3_runtime_resume(struct device *dev)
1208 struct dwc3 *dwc = dev_get_drvdata(dev);
1211 device_init_wakeup(dev, false);
1213 ret = dwc3_resume_common(dwc);
1217 switch (dwc->dr_mode) {
1218 case USB_DR_MODE_PERIPHERAL:
1219 case USB_DR_MODE_OTG:
1220 dwc3_gadget_process_pending_events(dwc);
1222 case USB_DR_MODE_HOST:
1228 pm_runtime_mark_last_busy(dev);
1233 static int dwc3_runtime_idle(struct device *dev)
1235 struct dwc3 *dwc = dev_get_drvdata(dev);
1237 switch (dwc->dr_mode) {
1238 case USB_DR_MODE_PERIPHERAL:
1239 case USB_DR_MODE_OTG:
1240 if (dwc3_runtime_checks(dwc))
1243 case USB_DR_MODE_HOST:
1249 pm_runtime_mark_last_busy(dev);
1250 pm_runtime_autosuspend(dev);
1254 #endif /* CONFIG_PM */
1256 #ifdef CONFIG_PM_SLEEP
1257 static int dwc3_suspend(struct device *dev)
1259 struct dwc3 *dwc = dev_get_drvdata(dev);
1262 if (pm_runtime_suspended(dwc->dev))
1265 ret = dwc3_suspend_common(dwc);
1269 pinctrl_pm_select_sleep_state(dev);
1274 static int dwc3_resume(struct device *dev)
1276 struct dwc3 *dwc = dev_get_drvdata(dev);
1279 if (pm_runtime_suspended(dwc->dev))
1282 pinctrl_pm_select_default_state(dev);
1284 ret = dwc3_resume_common(dwc);
1288 pm_runtime_disable(dev);
1289 pm_runtime_set_active(dev);
1290 pm_runtime_enable(dev);
1294 #endif /* CONFIG_PM_SLEEP */
1296 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1297 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1298 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1303 static const struct of_device_id of_dwc3_match[] = {
1305 .compatible = "snps,dwc3"
1308 .compatible = "synopsys,dwc3"
1312 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1317 #define ACPI_ID_INTEL_BSW "808622B7"
1319 static const struct acpi_device_id dwc3_acpi_match[] = {
1320 { ACPI_ID_INTEL_BSW, 0 },
1323 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1326 static struct platform_driver dwc3_driver = {
1327 .probe = dwc3_probe,
1328 .remove = dwc3_remove,
1331 .of_match_table = of_match_ptr(of_dwc3_match),
1332 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1333 .pm = &dwc3_dev_pm_ops,
1337 module_platform_driver(dwc3_driver);
1339 MODULE_ALIAS("platform:dwc3");
1340 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1341 MODULE_LICENSE("GPL v2");
1342 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");