drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37
  38 #include <linux/usb/ch9.h>
  39 #include <linux/usb/gadget.h>
  40 #include <linux/usb/of.h>
  41 #include <linux/usb/otg.h>
  42
  43 #include "platform_data.h"
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 /* -------------------------------------------------------------------------- */
  51
  52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  53 {
  54         u32 reg;
  55
  56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  60 }
  61
  62 /**
  63  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  64  * @dwc: pointer to our context structure
  65  */
  66 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  67 {
  68         u32             reg;
  69         int             ret;
  70
  71         /* Before Resetting PHY, put Core in Reset */
  72         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  73         reg |= DWC3_GCTL_CORESOFTRESET;
  74         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  75
  76         /* Assert USB3 PHY reset */
  77         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  78         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  79         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  80
  81         /* Assert USB2 PHY reset */
  82         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  83         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  84         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  85
  86         usb_phy_init(dwc->usb2_phy);
  87         usb_phy_init(dwc->usb3_phy);
  88         ret = phy_init(dwc->usb2_generic_phy);
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = phy_init(dwc->usb3_generic_phy);
  93         if (ret < 0) {
  94                 phy_exit(dwc->usb2_generic_phy);
  95                 return ret;
  96         }
  97         mdelay(100);
  98
  99         /* Clear USB3 PHY reset */
 100         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 101         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 102         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 103
 104         /* Clear USB2 PHY reset */
 105         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 106         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 107         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 108
 109         mdelay(100);
 110
 111         /* After PHYs are stable we can take Core out of reset state */
 112         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 113         reg &= ~DWC3_GCTL_CORESOFTRESET;
 114         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 115
 116         return 0;
 117 }
 118
 119 /**
 120  * dwc3_free_one_event_buffer - Frees one event buffer
 121  * @dwc: Pointer to our controller context structure
 122  * @evt: Pointer to event buffer to be freed
 123  */
 124 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 125                 struct dwc3_event_buffer *evt)
 126 {
 127         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 128 }
 129
 130 /**
 131  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 132  * @dwc: Pointer to our controller context structure
 133  * @length: size of the event buffer
 134  *
 135  * Returns a pointer to the allocated event buffer structure on success
 136  * otherwise ERR_PTR(errno).
 137  */
 138 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 139                 unsigned length)
 140 {
 141         struct dwc3_event_buffer        *evt;
 142
 143         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 144         if (!evt)
 145                 return ERR_PTR(-ENOMEM);
 146
 147         evt->dwc        = dwc;
 148         evt->length     = length;
 149         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 150                         &evt->dma, GFP_KERNEL);
 151         if (!evt->buf)
 152                 return ERR_PTR(-ENOMEM);
 153
 154         return evt;
 155 }
 156
 157 /**
 158  * dwc3_free_event_buffers - frees all allocated event buffers
 159  * @dwc: Pointer to our controller context structure
 160  */
 161 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 162 {
 163         struct dwc3_event_buffer        *evt;
 164         int i;
 165
 166         for (i = 0; i < dwc->num_event_buffers; i++) {
 167                 evt = dwc->ev_buffs[i];
 168                 if (evt)
 169                         dwc3_free_one_event_buffer(dwc, evt);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 175  * @dwc: pointer to our controller context structure
 176  * @length: size of event buffer
 177  *
 178  * Returns 0 on success otherwise negative errno. In the error case, dwc
 179  * may contain some buffers allocated but not all which were requested.
 180  */
 181 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 182 {
 183         int                     num;
 184         int                     i;
 185
 186         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 187         dwc->num_event_buffers = num;
 188
 189         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 190                         GFP_KERNEL);
 191         if (!dwc->ev_buffs)
 192                 return -ENOMEM;
 193
 194         for (i = 0; i < num; i++) {
 195                 struct dwc3_event_buffer        *evt;
 196
 197                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 198                 if (IS_ERR(evt)) {
 199                         dev_err(dwc->dev, "can't allocate event buffer\n");
 200                         return PTR_ERR(evt);
 201                 }
 202                 dwc->ev_buffs[i] = evt;
 203         }
 204
 205         return 0;
 206 }
 207
 208 /**
 209  * dwc3_event_buffers_setup - setup our allocated event buffers
 210  * @dwc: pointer to our controller context structure
 211  *
 212  * Returns 0 on success otherwise negative errno.
 213  */
 214 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 215 {
 216         struct dwc3_event_buffer        *evt;
 217         int                             n;
 218
 219         for (n = 0; n < dwc->num_event_buffers; n++) {
 220                 evt = dwc->ev_buffs[n];
 221                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 222                                 evt->buf, (unsigned long long) evt->dma,
 223                                 evt->length);
 224
 225                 evt->lpos = 0;
 226
 227                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 228                                 lower_32_bits(evt->dma));
 229                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 230                                 upper_32_bits(evt->dma));
 231                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 232                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 233                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 234         }
 235
 236         return 0;
 237 }
 238
 239 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 240 {
 241         struct dwc3_event_buffer        *evt;
 242         int                             n;
 243
 244         for (n = 0; n < dwc->num_event_buffers; n++) {
 245                 evt = dwc->ev_buffs[n];
 246
 247                 evt->lpos = 0;
 248
 249                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 250                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 251                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 252                                 | DWC3_GEVNTSIZ_SIZE(0));
 253                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 254         }
 255 }
 256
 257 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 258 {
 259         if (!dwc->has_hibernation)
 260                 return 0;
 261
 262         if (!dwc->nr_scratch)
 263                 return 0;
 264
 265         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 266                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 267         if (!dwc->scratchbuf)
 268                 return -ENOMEM;
 269
 270         return 0;
 271 }
 272
 273 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 274 {
 275         dma_addr_t scratch_addr;
 276         u32 param;
 277         int ret;
 278
 279         if (!dwc->has_hibernation)
 280                 return 0;
 281
 282         if (!dwc->nr_scratch)
 283                 return 0;
 284
 285          /* should never fall here */
 286         if (!WARN_ON(dwc->scratchbuf))
 287                 return 0;
 288
 289         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 290                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 291                         DMA_BIDIRECTIONAL);
 292         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 293                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 294                 ret = -EFAULT;
 295                 goto err0;
 296         }
 297
 298         dwc->scratch_addr = scratch_addr;
 299
 300         param = lower_32_bits(scratch_addr);
 301
 302         ret = dwc3_send_gadget_generic_command(dwc,
 303                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 304         if (ret < 0)
 305                 goto err1;
 306
 307         param = upper_32_bits(scratch_addr);
 308
 309         ret = dwc3_send_gadget_generic_command(dwc,
 310                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 311         if (ret < 0)
 312                 goto err1;
 313
 314         return 0;
 315
 316 err1:
 317         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 318                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 319
 320 err0:
 321         return ret;
 322 }
 323
 324 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 325 {
 326         if (!dwc->has_hibernation)
 327                 return;
 328
 329         if (!dwc->nr_scratch)
 330                 return;
 331
 332          /* should never fall here */
 333         if (!WARN_ON(dwc->scratchbuf))
 334                 return;
 335
 336         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 337                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 338         kfree(dwc->scratchbuf);
 339 }
 340
 341 static void dwc3_core_num_eps(struct dwc3 *dwc)
 342 {
 343         struct dwc3_hwparams    *parms = &dwc->hwparams;
 344
 345         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 346         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 347
 348         dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
 349                         dwc->num_in_eps, dwc->num_out_eps);
 350 }
 351
 352 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 353 {
 354         struct dwc3_hwparams    *parms = &dwc->hwparams;
 355
 356         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 357         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 358         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 359         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 360         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 361         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 362         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 363         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 364         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 365 }
 366
 367 /**
 368  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 369  * @dwc: Pointer to our controller context structure
 370  */
 371 static void dwc3_phy_setup(struct dwc3 *dwc)
 372 {
 373         u32 reg;
 374
 375         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 376
 377         if (dwc->u2ss_inp3_quirk)
 378                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 379
 380         if (dwc->req_p1p2p3_quirk)
 381                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 382
 383         if (dwc->del_p1p2p3_quirk)
 384                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 385
 386         if (dwc->del_phy_power_chg_quirk)
 387                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 388
 389         if (dwc->lfps_filter_quirk)
 390                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 391
 392         if (dwc->rx_detect_poll_quirk)
 393                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 394
 395         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 396
 397         mdelay(100);
 398 }
 399
 400 /**
 401  * dwc3_core_init - Low-level initialization of DWC3 Core
 402  * @dwc: Pointer to our controller context structure
 403  *
 404  * Returns 0 on success otherwise negative errno.
 405  */
 406 static int dwc3_core_init(struct dwc3 *dwc)
 407 {
 408         unsigned long           timeout;
 409         u32                     hwparams4 = dwc->hwparams.hwparams4;
 410         u32                     reg;
 411         int                     ret;
 412
 413         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 414         /* This should read as U3 followed by revision number */
 415         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 416                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 417                 ret = -ENODEV;
 418                 goto err0;
 419         }
 420         dwc->revision = reg;
 421
 422         /*
 423          * Write Linux Version Code to our GUID register so it's easy to figure
 424          * out which kernel version a bug was found.
 425          */
 426         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 427
 428         /* Handle USB2.0-only core configuration */
 429         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 430                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 431                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 432                         dwc->maximum_speed = USB_SPEED_HIGH;
 433         }
 434
 435         /* issue device SoftReset too */
 436         timeout = jiffies + msecs_to_jiffies(500);
 437         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 438         do {
 439                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 440                 if (!(reg & DWC3_DCTL_CSFTRST))
 441                         break;
 442
 443                 if (time_after(jiffies, timeout)) {
 444                         dev_err(dwc->dev, "Reset Timed Out\n");
 445                         ret = -ETIMEDOUT;
 446                         goto err0;
 447                 }
 448
 449                 cpu_relax();
 450         } while (true);
 451
 452         ret = dwc3_core_soft_reset(dwc);
 453         if (ret)
 454                 goto err0;
 455
 456         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 457         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 458
 459         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 460         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 461                 /**
 462                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 463                  * issue which would cause xHCI compliance tests to fail.
 464                  *
 465                  * Because of that we cannot enable clock gating on such
 466                  * configurations.
 467                  *
 468                  * Refers to:
 469                  *
 470                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 471                  * SOF/ITP Mode Used
 472                  */
 473                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 474                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 475                                 (dwc->revision >= DWC3_REVISION_210A &&
 476                                 dwc->revision <= DWC3_REVISION_250A))
 477                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 478                 else
 479                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 480                 break;
 481         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 482                 /* enable hibernation here */
 483                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 484
 485                 /*
 486                  * REVISIT Enabling this bit so that host-mode hibernation
 487                  * will work. Device-mode hibernation is not yet implemented.
 488                  */
 489                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 490                 break;
 491         default:
 492                 dev_dbg(dwc->dev, "No power optimization available\n");
 493         }
 494
 495         /* check if current dwc3 is on simulation board */
 496         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 497                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 498                 dwc->is_fpga = true;
 499         }
 500
 501         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 502                         "disable_scramble cannot be used on non-FPGA builds\n");
 503
 504         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 505                 reg |= DWC3_GCTL_DISSCRAMBLE;
 506         else
 507                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 508
 509         if (dwc->u2exit_lfps_quirk)
 510                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 511
 512         /*
 513          * WORKAROUND: DWC3 revisions <1.90a have a bug
 514          * where the device can fail to connect at SuperSpeed
 515          * and falls back to high-speed mode which causes
 516          * the device to enter a Connect/Disconnect loop
 517          */
 518         if (dwc->revision < DWC3_REVISION_190A)
 519                 reg |= DWC3_GCTL_U2RSTECN;
 520
 521         dwc3_core_num_eps(dwc);
 522
 523         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 524
 525         dwc3_phy_setup(dwc);
 526
 527         ret = dwc3_alloc_scratch_buffers(dwc);
 528         if (ret)
 529                 goto err1;
 530
 531         ret = dwc3_setup_scratch_buffers(dwc);
 532         if (ret)
 533                 goto err2;
 534
 535         return 0;
 536
 537 err2:
 538         dwc3_free_scratch_buffers(dwc);
 539
 540 err1:
 541         usb_phy_shutdown(dwc->usb2_phy);
 542         usb_phy_shutdown(dwc->usb3_phy);
 543         phy_exit(dwc->usb2_generic_phy);
 544         phy_exit(dwc->usb3_generic_phy);
 545
 546 err0:
 547         return ret;
 548 }
 549
 550 static void dwc3_core_exit(struct dwc3 *dwc)
 551 {
 552         dwc3_free_scratch_buffers(dwc);
 553         usb_phy_shutdown(dwc->usb2_phy);
 554         usb_phy_shutdown(dwc->usb3_phy);
 555         phy_exit(dwc->usb2_generic_phy);
 556         phy_exit(dwc->usb3_generic_phy);
 557 }
 558
 559 static int dwc3_core_get_phy(struct dwc3 *dwc)
 560 {
 561         struct device           *dev = dwc->dev;
 562         struct device_node      *node = dev->of_node;
 563         int ret;
 564
 565         if (node) {
 566                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 567                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 568         } else {
 569                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 570                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 571         }
 572
 573         if (IS_ERR(dwc->usb2_phy)) {
 574                 ret = PTR_ERR(dwc->usb2_phy);
 575                 if (ret == -ENXIO || ret == -ENODEV) {
 576                         dwc->usb2_phy = NULL;
 577                 } else if (ret == -EPROBE_DEFER) {
 578                         return ret;
 579                 } else {
 580                         dev_err(dev, "no usb2 phy configured\n");
 581                         return ret;
 582                 }
 583         }
 584
 585         if (IS_ERR(dwc->usb3_phy)) {
 586                 ret = PTR_ERR(dwc->usb3_phy);
 587                 if (ret == -ENXIO || ret == -ENODEV) {
 588                         dwc->usb3_phy = NULL;
 589                 } else if (ret == -EPROBE_DEFER) {
 590                         return ret;
 591                 } else {
 592                         dev_err(dev, "no usb3 phy configured\n");
 593                         return ret;
 594                 }
 595         }
 596
 597         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 598         if (IS_ERR(dwc->usb2_generic_phy)) {
 599                 ret = PTR_ERR(dwc->usb2_generic_phy);
 600                 if (ret == -ENOSYS || ret == -ENODEV) {
 601                         dwc->usb2_generic_phy = NULL;
 602                 } else if (ret == -EPROBE_DEFER) {
 603                         return ret;
 604                 } else {
 605                         dev_err(dev, "no usb2 phy configured\n");
 606                         return ret;
 607                 }
 608         }
 609
 610         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 611         if (IS_ERR(dwc->usb3_generic_phy)) {
 612                 ret = PTR_ERR(dwc->usb3_generic_phy);
 613                 if (ret == -ENOSYS || ret == -ENODEV) {
 614                         dwc->usb3_generic_phy = NULL;
 615                 } else if (ret == -EPROBE_DEFER) {
 616                         return ret;
 617                 } else {
 618                         dev_err(dev, "no usb3 phy configured\n");
 619                         return ret;
 620                 }
 621         }
 622
 623         return 0;
 624 }
 625
 626 static int dwc3_core_init_mode(struct dwc3 *dwc)
 627 {
 628         struct device *dev = dwc->dev;
 629         int ret;
 630
 631         switch (dwc->dr_mode) {
 632         case USB_DR_MODE_PERIPHERAL:
 633                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 634                 ret = dwc3_gadget_init(dwc);
 635                 if (ret) {
 636                         dev_err(dev, "failed to initialize gadget\n");
 637                         return ret;
 638                 }
 639                 break;
 640         case USB_DR_MODE_HOST:
 641                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 642                 ret = dwc3_host_init(dwc);
 643                 if (ret) {
 644                         dev_err(dev, "failed to initialize host\n");
 645                         return ret;
 646                 }
 647                 break;
 648         case USB_DR_MODE_OTG:
 649                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 650                 ret = dwc3_host_init(dwc);
 651                 if (ret) {
 652                         dev_err(dev, "failed to initialize host\n");
 653                         return ret;
 654                 }
 655
 656                 ret = dwc3_gadget_init(dwc);
 657                 if (ret) {
 658                         dev_err(dev, "failed to initialize gadget\n");
 659                         return ret;
 660                 }
 661                 break;
 662         default:
 663                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 664                 return -EINVAL;
 665         }
 666
 667         return 0;
 668 }
 669
 670 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 671 {
 672         switch (dwc->dr_mode) {
 673         case USB_DR_MODE_PERIPHERAL:
 674                 dwc3_gadget_exit(dwc);
 675                 break;
 676         case USB_DR_MODE_HOST:
 677                 dwc3_host_exit(dwc);
 678                 break;
 679         case USB_DR_MODE_OTG:
 680                 dwc3_host_exit(dwc);
 681                 dwc3_gadget_exit(dwc);
 682                 break;
 683         default:
 684                 /* do nothing */
 685                 break;
 686         }
 687 }
 688
 689 #define DWC3_ALIGN_MASK         (16 - 1)
 690
 691 static int dwc3_probe(struct platform_device *pdev)
 692 {
 693         struct device           *dev = &pdev->dev;
 694         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 695         struct device_node      *node = dev->of_node;
 696         struct resource         *res;
 697         struct dwc3             *dwc;
 698         u8                      lpm_nyet_threshold;
 699
 700         int                     ret;
 701
 702         void __iomem            *regs;
 703         void                    *mem;
 704
 705         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 706         if (!mem)
 707                 return -ENOMEM;
 708
 709         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 710         dwc->mem = mem;
 711         dwc->dev = dev;
 712
 713         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 714         if (!res) {
 715                 dev_err(dev, "missing IRQ\n");
 716                 return -ENODEV;
 717         }
 718         dwc->xhci_resources[1].start = res->start;
 719         dwc->xhci_resources[1].end = res->end;
 720         dwc->xhci_resources[1].flags = res->flags;
 721         dwc->xhci_resources[1].name = res->name;
 722
 723         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 724         if (!res) {
 725                 dev_err(dev, "missing memory resource\n");
 726                 return -ENODEV;
 727         }
 728
 729         dwc->xhci_resources[0].start = res->start;
 730         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 731                                         DWC3_XHCI_REGS_END;
 732         dwc->xhci_resources[0].flags = res->flags;
 733         dwc->xhci_resources[0].name = res->name;
 734
 735         res->start += DWC3_GLOBALS_REGS_START;
 736
 737         /*
 738          * Request memory region but exclude xHCI regs,
 739          * since it will be requested by the xhci-plat driver.
 740          */
 741         regs = devm_ioremap_resource(dev, res);
 742         if (IS_ERR(regs))
 743                 return PTR_ERR(regs);
 744
 745         dwc->regs       = regs;
 746         dwc->regs_size  = resource_size(res);
 747         /*
 748          * restore res->start back to its original value so that,
 749          * in case the probe is deferred, we don't end up getting error in
 750          * request the memory region the next time probe is called.
 751          */
 752         res->start -= DWC3_GLOBALS_REGS_START;
 753
 754         /* default to highest possible threshold */
 755         lpm_nyet_threshold = 0xff;
 756
 757         if (node) {
 758                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
 759                 dwc->has_lpm_erratum = of_property_read_bool(node,
 760                                 "snps,has-lpm-erratum");
 761                 of_property_read_u8(node, "snps,lpm-nyet-threshold",
 762                                 &lpm_nyet_threshold);
 763
 764                 dwc->needs_fifo_resize = of_property_read_bool(node,
 765                                 "tx-fifo-resize");
 766                 dwc->dr_mode = of_usb_get_dr_mode(node);
 767
 768                 dwc->disable_scramble_quirk = of_property_read_bool(node,
 769                                 "snps,disable_scramble_quirk");
 770                 dwc->u2exit_lfps_quirk = of_property_read_bool(node,
 771                                 "snps,u2exit_lfps_quirk");
 772                 dwc->u2ss_inp3_quirk = of_property_read_bool(node,
 773                                 "snps,u2ss_inp3_quirk");
 774                 dwc->req_p1p2p3_quirk = of_property_read_bool(node,
 775                                 "snps,req_p1p2p3_quirk");
 776                 dwc->del_p1p2p3_quirk = of_property_read_bool(node,
 777                                 "snps,del_p1p2p3_quirk");
 778                 dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
 779                                 "snps,del_phy_power_chg_quirk");
 780                 dwc->lfps_filter_quirk = of_property_read_bool(node,
 781                                 "snps,lfps_filter_quirk");
 782                 dwc->rx_detect_poll_quirk = of_property_read_bool(node,
 783                                 "snps,rx_detect_poll_quirk");
 784         } else if (pdata) {
 785                 dwc->maximum_speed = pdata->maximum_speed;
 786                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
 787                 if (pdata->lpm_nyet_threshold)
 788                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
 789
 790                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 791                 dwc->dr_mode = pdata->dr_mode;
 792
 793                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
 794                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
 795                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
 796                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
 797                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
 798                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
 799                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
 800                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
 801         }
 802
 803         /* default to superspeed if no maximum_speed passed */
 804         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 805                 dwc->maximum_speed = USB_SPEED_SUPER;
 806
 807         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 808
 809         ret = dwc3_core_get_phy(dwc);
 810         if (ret)
 811                 return ret;
 812
 813         spin_lock_init(&dwc->lock);
 814         platform_set_drvdata(pdev, dwc);
 815
 816         if (!dev->dma_mask) {
 817                 dev->dma_mask = dev->parent->dma_mask;
 818                 dev->dma_parms = dev->parent->dma_parms;
 819                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 820         }
 821
 822         pm_runtime_enable(dev);
 823         pm_runtime_get_sync(dev);
 824         pm_runtime_forbid(dev);
 825
 826         dwc3_cache_hwparams(dwc);
 827
 828         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 829         if (ret) {
 830                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 831                 ret = -ENOMEM;
 832                 goto err0;
 833         }
 834
 835         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 836                 dwc->dr_mode = USB_DR_MODE_HOST;
 837         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 838                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 839
 840         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 841                 dwc->dr_mode = USB_DR_MODE_OTG;
 842
 843         ret = dwc3_core_init(dwc);
 844         if (ret) {
 845                 dev_err(dev, "failed to initialize core\n");
 846                 goto err0;
 847         }
 848
 849         usb_phy_set_suspend(dwc->usb2_phy, 0);
 850         usb_phy_set_suspend(dwc->usb3_phy, 0);
 851         ret = phy_power_on(dwc->usb2_generic_phy);
 852         if (ret < 0)
 853                 goto err1;
 854
 855         ret = phy_power_on(dwc->usb3_generic_phy);
 856         if (ret < 0)
 857                 goto err_usb2phy_power;
 858
 859         ret = dwc3_event_buffers_setup(dwc);
 860         if (ret) {
 861                 dev_err(dwc->dev, "failed to setup event buffers\n");
 862                 goto err_usb3phy_power;
 863         }
 864
 865         ret = dwc3_core_init_mode(dwc);
 866         if (ret)
 867                 goto err2;
 868
 869         ret = dwc3_debugfs_init(dwc);
 870         if (ret) {
 871                 dev_err(dev, "failed to initialize debugfs\n");
 872                 goto err3;
 873         }
 874
 875         pm_runtime_allow(dev);
 876
 877         return 0;
 878
 879 err3:
 880         dwc3_core_exit_mode(dwc);
 881
 882 err2:
 883         dwc3_event_buffers_cleanup(dwc);
 884
 885 err_usb3phy_power:
 886         phy_power_off(dwc->usb3_generic_phy);
 887
 888 err_usb2phy_power:
 889         phy_power_off(dwc->usb2_generic_phy);
 890
 891 err1:
 892         usb_phy_set_suspend(dwc->usb2_phy, 1);
 893         usb_phy_set_suspend(dwc->usb3_phy, 1);
 894         dwc3_core_exit(dwc);
 895
 896 err0:
 897         dwc3_free_event_buffers(dwc);
 898
 899         return ret;
 900 }
 901
 902 static int dwc3_remove(struct platform_device *pdev)
 903 {
 904         struct dwc3     *dwc = platform_get_drvdata(pdev);
 905
 906         dwc3_debugfs_exit(dwc);
 907         dwc3_core_exit_mode(dwc);
 908         dwc3_event_buffers_cleanup(dwc);
 909         dwc3_free_event_buffers(dwc);
 910
 911         usb_phy_set_suspend(dwc->usb2_phy, 1);
 912         usb_phy_set_suspend(dwc->usb3_phy, 1);
 913         phy_power_off(dwc->usb2_generic_phy);
 914         phy_power_off(dwc->usb3_generic_phy);
 915
 916         dwc3_core_exit(dwc);
 917
 918         pm_runtime_put_sync(&pdev->dev);
 919         pm_runtime_disable(&pdev->dev);
 920
 921         return 0;
 922 }
 923
 924 #ifdef CONFIG_PM_SLEEP
 925 static int dwc3_suspend(struct device *dev)
 926 {
 927         struct dwc3     *dwc = dev_get_drvdata(dev);
 928         unsigned long   flags;
 929
 930         spin_lock_irqsave(&dwc->lock, flags);
 931
 932         switch (dwc->dr_mode) {
 933         case USB_DR_MODE_PERIPHERAL:
 934         case USB_DR_MODE_OTG:
 935                 dwc3_gadget_suspend(dwc);
 936                 /* FALLTHROUGH */
 937         case USB_DR_MODE_HOST:
 938         default:
 939                 dwc3_event_buffers_cleanup(dwc);
 940                 break;
 941         }
 942
 943         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
 944         spin_unlock_irqrestore(&dwc->lock, flags);
 945
 946         usb_phy_shutdown(dwc->usb3_phy);
 947         usb_phy_shutdown(dwc->usb2_phy);
 948         phy_exit(dwc->usb2_generic_phy);
 949         phy_exit(dwc->usb3_generic_phy);
 950
 951         return 0;
 952 }
 953
 954 static int dwc3_resume(struct device *dev)
 955 {
 956         struct dwc3     *dwc = dev_get_drvdata(dev);
 957         unsigned long   flags;
 958         int             ret;
 959
 960         usb_phy_init(dwc->usb3_phy);
 961         usb_phy_init(dwc->usb2_phy);
 962         ret = phy_init(dwc->usb2_generic_phy);
 963         if (ret < 0)
 964                 return ret;
 965
 966         ret = phy_init(dwc->usb3_generic_phy);
 967         if (ret < 0)
 968                 goto err_usb2phy_init;
 969
 970         spin_lock_irqsave(&dwc->lock, flags);
 971
 972         dwc3_event_buffers_setup(dwc);
 973         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
 974
 975         switch (dwc->dr_mode) {
 976         case USB_DR_MODE_PERIPHERAL:
 977         case USB_DR_MODE_OTG:
 978                 dwc3_gadget_resume(dwc);
 979                 /* FALLTHROUGH */
 980         case USB_DR_MODE_HOST:
 981         default:
 982                 /* do nothing */
 983                 break;
 984         }
 985
 986         spin_unlock_irqrestore(&dwc->lock, flags);
 987
 988         pm_runtime_disable(dev);
 989         pm_runtime_set_active(dev);
 990         pm_runtime_enable(dev);
 991
 992         return 0;
 993
 994 err_usb2phy_init:
 995         phy_exit(dwc->usb2_generic_phy);
 996
 997         return ret;
 998 }
 999
1000 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1001         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1002 };
1003
1004 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1005 #else
1006 #define DWC3_PM_OPS     NULL
1007 #endif
1008
1009 #ifdef CONFIG_OF
1010 static const struct of_device_id of_dwc3_match[] = {
1011         {
1012                 .compatible = "snps,dwc3"
1013         },
1014         {
1015                 .compatible = "synopsys,dwc3"
1016         },
1017         { },
1018 };
1019 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1020 #endif
1021
1022 #ifdef CONFIG_ACPI
1023
1024 #define ACPI_ID_INTEL_BSW       "808622B7"
1025
1026 static const struct acpi_device_id dwc3_acpi_match[] = {
1027         { ACPI_ID_INTEL_BSW, 0 },
1028         { },
1029 };
1030 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1031 #endif
1032
1033 static struct platform_driver dwc3_driver = {
1034         .probe          = dwc3_probe,
1035         .remove         = dwc3_remove,
1036         .driver         = {
1037                 .name   = "dwc3",
1038                 .of_match_table = of_match_ptr(of_dwc3_match),
1039                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1040                 .pm     = DWC3_PM_OPS,
1041         },
1042 };
1043
1044 module_platform_driver(dwc3_driver);
1045
1046 MODULE_ALIAS("platform:dwc3");
1047 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1048 MODULE_LICENSE("GPL v2");
1049 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");