2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
38 #include <linux/usb/ch9.h>
39 #include <linux/usb/gadget.h>
40 #include <linux/usb/of.h>
41 #include <linux/usb/otg.h>
43 #include "platform_data.h"
50 /* -------------------------------------------------------------------------- */
52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
56 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
57 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
58 reg |= DWC3_GCTL_PRTCAPDIR(mode);
59 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
63 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
64 * @dwc: pointer to our context structure
66 static int dwc3_core_soft_reset(struct dwc3 *dwc)
71 /* Before Resetting PHY, put Core in Reset */
72 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
73 reg |= DWC3_GCTL_CORESOFTRESET;
74 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
76 /* Assert USB3 PHY reset */
77 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
78 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
79 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
81 /* Assert USB2 PHY reset */
82 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
83 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
84 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
86 usb_phy_init(dwc->usb2_phy);
87 usb_phy_init(dwc->usb3_phy);
88 ret = phy_init(dwc->usb2_generic_phy);
92 ret = phy_init(dwc->usb3_generic_phy);
94 phy_exit(dwc->usb2_generic_phy);
99 /* Clear USB3 PHY reset */
100 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
101 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
102 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
104 /* Clear USB2 PHY reset */
105 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
106 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
107 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
111 /* After PHYs are stable we can take Core out of reset state */
112 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
113 reg &= ~DWC3_GCTL_CORESOFTRESET;
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
120 * dwc3_free_one_event_buffer - Frees one event buffer
121 * @dwc: Pointer to our controller context structure
122 * @evt: Pointer to event buffer to be freed
124 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
125 struct dwc3_event_buffer *evt)
127 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
131 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
132 * @dwc: Pointer to our controller context structure
133 * @length: size of the event buffer
135 * Returns a pointer to the allocated event buffer structure on success
136 * otherwise ERR_PTR(errno).
138 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
141 struct dwc3_event_buffer *evt;
143 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
145 return ERR_PTR(-ENOMEM);
148 evt->length = length;
149 evt->buf = dma_alloc_coherent(dwc->dev, length,
150 &evt->dma, GFP_KERNEL);
152 return ERR_PTR(-ENOMEM);
158 * dwc3_free_event_buffers - frees all allocated event buffers
159 * @dwc: Pointer to our controller context structure
161 static void dwc3_free_event_buffers(struct dwc3 *dwc)
163 struct dwc3_event_buffer *evt;
166 for (i = 0; i < dwc->num_event_buffers; i++) {
167 evt = dwc->ev_buffs[i];
169 dwc3_free_one_event_buffer(dwc, evt);
174 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
175 * @dwc: pointer to our controller context structure
176 * @length: size of event buffer
178 * Returns 0 on success otherwise negative errno. In the error case, dwc
179 * may contain some buffers allocated but not all which were requested.
181 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
186 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
187 dwc->num_event_buffers = num;
189 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
194 for (i = 0; i < num; i++) {
195 struct dwc3_event_buffer *evt;
197 evt = dwc3_alloc_one_event_buffer(dwc, length);
199 dev_err(dwc->dev, "can't allocate event buffer\n");
202 dwc->ev_buffs[i] = evt;
209 * dwc3_event_buffers_setup - setup our allocated event buffers
210 * @dwc: pointer to our controller context structure
212 * Returns 0 on success otherwise negative errno.
214 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
216 struct dwc3_event_buffer *evt;
219 for (n = 0; n < dwc->num_event_buffers; n++) {
220 evt = dwc->ev_buffs[n];
221 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
222 evt->buf, (unsigned long long) evt->dma,
227 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
228 lower_32_bits(evt->dma));
229 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
230 upper_32_bits(evt->dma));
231 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
232 DWC3_GEVNTSIZ_SIZE(evt->length));
233 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
239 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
241 struct dwc3_event_buffer *evt;
244 for (n = 0; n < dwc->num_event_buffers; n++) {
245 evt = dwc->ev_buffs[n];
249 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
250 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
251 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
252 | DWC3_GEVNTSIZ_SIZE(0));
253 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
257 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
259 if (!dwc->has_hibernation)
262 if (!dwc->nr_scratch)
265 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
266 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
267 if (!dwc->scratchbuf)
273 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
275 dma_addr_t scratch_addr;
279 if (!dwc->has_hibernation)
282 if (!dwc->nr_scratch)
285 /* should never fall here */
286 if (!WARN_ON(dwc->scratchbuf))
289 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
290 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
292 if (dma_mapping_error(dwc->dev, scratch_addr)) {
293 dev_err(dwc->dev, "failed to map scratch buffer\n");
298 dwc->scratch_addr = scratch_addr;
300 param = lower_32_bits(scratch_addr);
302 ret = dwc3_send_gadget_generic_command(dwc,
303 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
307 param = upper_32_bits(scratch_addr);
309 ret = dwc3_send_gadget_generic_command(dwc,
310 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
317 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
318 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
324 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
326 if (!dwc->has_hibernation)
329 if (!dwc->nr_scratch)
332 /* should never fall here */
333 if (!WARN_ON(dwc->scratchbuf))
336 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
337 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
338 kfree(dwc->scratchbuf);
341 static void dwc3_core_num_eps(struct dwc3 *dwc)
343 struct dwc3_hwparams *parms = &dwc->hwparams;
345 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
346 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
348 dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
349 dwc->num_in_eps, dwc->num_out_eps);
352 static void dwc3_cache_hwparams(struct dwc3 *dwc)
354 struct dwc3_hwparams *parms = &dwc->hwparams;
356 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
357 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
358 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
359 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
360 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
361 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
362 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
363 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
364 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
368 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
369 * @dwc: Pointer to our controller context structure
371 static void dwc3_phy_setup(struct dwc3 *dwc)
375 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
378 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
379 * to '0' during coreConsultant configuration. So default value
380 * will be '0' when the core is reset. Application needs to set it
381 * to '1' after the core initialization is completed.
383 if (dwc->revision > DWC3_REVISION_194A)
384 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
386 if (dwc->u2ss_inp3_quirk)
387 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
389 if (dwc->req_p1p2p3_quirk)
390 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
392 if (dwc->del_p1p2p3_quirk)
393 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
395 if (dwc->del_phy_power_chg_quirk)
396 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
398 if (dwc->lfps_filter_quirk)
399 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
401 if (dwc->rx_detect_poll_quirk)
402 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
404 if (dwc->tx_de_emphasis_quirk)
405 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
407 if (dwc->dis_u3_susphy_quirk)
408 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
410 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
417 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
418 * '0' during coreConsultant configuration. So default value will
419 * be '0' when the core is reset. Application needs to set it to
420 * '1' after the core initialization is completed.
422 if (dwc->revision > DWC3_REVISION_194A)
423 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
425 if (dwc->dis_u2_susphy_quirk)
426 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
428 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
434 * dwc3_core_init - Low-level initialization of DWC3 Core
435 * @dwc: Pointer to our controller context structure
437 * Returns 0 on success otherwise negative errno.
439 static int dwc3_core_init(struct dwc3 *dwc)
441 unsigned long timeout;
442 u32 hwparams4 = dwc->hwparams.hwparams4;
446 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
447 /* This should read as U3 followed by revision number */
448 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
449 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
456 * Write Linux Version Code to our GUID register so it's easy to figure
457 * out which kernel version a bug was found.
459 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
461 /* Handle USB2.0-only core configuration */
462 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
463 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
464 if (dwc->maximum_speed == USB_SPEED_SUPER)
465 dwc->maximum_speed = USB_SPEED_HIGH;
468 /* issue device SoftReset too */
469 timeout = jiffies + msecs_to_jiffies(500);
470 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
472 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
473 if (!(reg & DWC3_DCTL_CSFTRST))
476 if (time_after(jiffies, timeout)) {
477 dev_err(dwc->dev, "Reset Timed Out\n");
485 ret = dwc3_core_soft_reset(dwc);
489 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
490 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
492 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
493 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
495 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
496 * issue which would cause xHCI compliance tests to fail.
498 * Because of that we cannot enable clock gating on such
503 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
506 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
507 dwc->dr_mode == USB_DR_MODE_OTG) &&
508 (dwc->revision >= DWC3_REVISION_210A &&
509 dwc->revision <= DWC3_REVISION_250A))
510 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
512 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
514 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
515 /* enable hibernation here */
516 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
519 * REVISIT Enabling this bit so that host-mode hibernation
520 * will work. Device-mode hibernation is not yet implemented.
522 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
525 dev_dbg(dwc->dev, "No power optimization available\n");
528 /* check if current dwc3 is on simulation board */
529 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
530 dev_dbg(dwc->dev, "it is on FPGA board\n");
534 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
535 "disable_scramble cannot be used on non-FPGA builds\n");
537 if (dwc->disable_scramble_quirk && dwc->is_fpga)
538 reg |= DWC3_GCTL_DISSCRAMBLE;
540 reg &= ~DWC3_GCTL_DISSCRAMBLE;
542 if (dwc->u2exit_lfps_quirk)
543 reg |= DWC3_GCTL_U2EXIT_LFPS;
546 * WORKAROUND: DWC3 revisions <1.90a have a bug
547 * where the device can fail to connect at SuperSpeed
548 * and falls back to high-speed mode which causes
549 * the device to enter a Connect/Disconnect loop
551 if (dwc->revision < DWC3_REVISION_190A)
552 reg |= DWC3_GCTL_U2RSTECN;
554 dwc3_core_num_eps(dwc);
556 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
560 ret = dwc3_alloc_scratch_buffers(dwc);
564 ret = dwc3_setup_scratch_buffers(dwc);
571 dwc3_free_scratch_buffers(dwc);
574 usb_phy_shutdown(dwc->usb2_phy);
575 usb_phy_shutdown(dwc->usb3_phy);
576 phy_exit(dwc->usb2_generic_phy);
577 phy_exit(dwc->usb3_generic_phy);
583 static void dwc3_core_exit(struct dwc3 *dwc)
585 dwc3_free_scratch_buffers(dwc);
586 usb_phy_shutdown(dwc->usb2_phy);
587 usb_phy_shutdown(dwc->usb3_phy);
588 phy_exit(dwc->usb2_generic_phy);
589 phy_exit(dwc->usb3_generic_phy);
592 static int dwc3_core_get_phy(struct dwc3 *dwc)
594 struct device *dev = dwc->dev;
595 struct device_node *node = dev->of_node;
599 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
600 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
602 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
603 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
606 if (IS_ERR(dwc->usb2_phy)) {
607 ret = PTR_ERR(dwc->usb2_phy);
608 if (ret == -ENXIO || ret == -ENODEV) {
609 dwc->usb2_phy = NULL;
610 } else if (ret == -EPROBE_DEFER) {
613 dev_err(dev, "no usb2 phy configured\n");
618 if (IS_ERR(dwc->usb3_phy)) {
619 ret = PTR_ERR(dwc->usb3_phy);
620 if (ret == -ENXIO || ret == -ENODEV) {
621 dwc->usb3_phy = NULL;
622 } else if (ret == -EPROBE_DEFER) {
625 dev_err(dev, "no usb3 phy configured\n");
630 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
631 if (IS_ERR(dwc->usb2_generic_phy)) {
632 ret = PTR_ERR(dwc->usb2_generic_phy);
633 if (ret == -ENOSYS || ret == -ENODEV) {
634 dwc->usb2_generic_phy = NULL;
635 } else if (ret == -EPROBE_DEFER) {
638 dev_err(dev, "no usb2 phy configured\n");
643 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
644 if (IS_ERR(dwc->usb3_generic_phy)) {
645 ret = PTR_ERR(dwc->usb3_generic_phy);
646 if (ret == -ENOSYS || ret == -ENODEV) {
647 dwc->usb3_generic_phy = NULL;
648 } else if (ret == -EPROBE_DEFER) {
651 dev_err(dev, "no usb3 phy configured\n");
659 static int dwc3_core_init_mode(struct dwc3 *dwc)
661 struct device *dev = dwc->dev;
664 switch (dwc->dr_mode) {
665 case USB_DR_MODE_PERIPHERAL:
666 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
667 ret = dwc3_gadget_init(dwc);
669 dev_err(dev, "failed to initialize gadget\n");
673 case USB_DR_MODE_HOST:
674 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
675 ret = dwc3_host_init(dwc);
677 dev_err(dev, "failed to initialize host\n");
681 case USB_DR_MODE_OTG:
682 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
683 ret = dwc3_host_init(dwc);
685 dev_err(dev, "failed to initialize host\n");
689 ret = dwc3_gadget_init(dwc);
691 dev_err(dev, "failed to initialize gadget\n");
696 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
703 static void dwc3_core_exit_mode(struct dwc3 *dwc)
705 switch (dwc->dr_mode) {
706 case USB_DR_MODE_PERIPHERAL:
707 dwc3_gadget_exit(dwc);
709 case USB_DR_MODE_HOST:
712 case USB_DR_MODE_OTG:
714 dwc3_gadget_exit(dwc);
722 #define DWC3_ALIGN_MASK (16 - 1)
724 static int dwc3_probe(struct platform_device *pdev)
726 struct device *dev = &pdev->dev;
727 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
728 struct device_node *node = dev->of_node;
729 struct resource *res;
731 u8 lpm_nyet_threshold;
740 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
744 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
748 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
750 dev_err(dev, "missing IRQ\n");
753 dwc->xhci_resources[1].start = res->start;
754 dwc->xhci_resources[1].end = res->end;
755 dwc->xhci_resources[1].flags = res->flags;
756 dwc->xhci_resources[1].name = res->name;
758 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
760 dev_err(dev, "missing memory resource\n");
764 dwc->xhci_resources[0].start = res->start;
765 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
767 dwc->xhci_resources[0].flags = res->flags;
768 dwc->xhci_resources[0].name = res->name;
770 res->start += DWC3_GLOBALS_REGS_START;
773 * Request memory region but exclude xHCI regs,
774 * since it will be requested by the xhci-plat driver.
776 regs = devm_ioremap_resource(dev, res);
778 return PTR_ERR(regs);
781 dwc->regs_size = resource_size(res);
783 * restore res->start back to its original value so that,
784 * in case the probe is deferred, we don't end up getting error in
785 * request the memory region the next time probe is called.
787 res->start -= DWC3_GLOBALS_REGS_START;
789 /* default to highest possible threshold */
790 lpm_nyet_threshold = 0xff;
792 /* default to -3.5dB de-emphasis */
796 * default to assert utmi_sleep_n and use maximum allowed HIRD
797 * threshold value of 0b1100
802 dwc->maximum_speed = of_usb_get_maximum_speed(node);
803 dwc->has_lpm_erratum = of_property_read_bool(node,
804 "snps,has-lpm-erratum");
805 of_property_read_u8(node, "snps,lpm-nyet-threshold",
806 &lpm_nyet_threshold);
807 dwc->is_utmi_l1_suspend = of_property_read_bool(node,
808 "snps,is-utmi-l1-suspend");
809 of_property_read_u8(node, "snps,hird-threshold",
812 dwc->needs_fifo_resize = of_property_read_bool(node,
814 dwc->dr_mode = of_usb_get_dr_mode(node);
816 dwc->disable_scramble_quirk = of_property_read_bool(node,
817 "snps,disable_scramble_quirk");
818 dwc->u2exit_lfps_quirk = of_property_read_bool(node,
819 "snps,u2exit_lfps_quirk");
820 dwc->u2ss_inp3_quirk = of_property_read_bool(node,
821 "snps,u2ss_inp3_quirk");
822 dwc->req_p1p2p3_quirk = of_property_read_bool(node,
823 "snps,req_p1p2p3_quirk");
824 dwc->del_p1p2p3_quirk = of_property_read_bool(node,
825 "snps,del_p1p2p3_quirk");
826 dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
827 "snps,del_phy_power_chg_quirk");
828 dwc->lfps_filter_quirk = of_property_read_bool(node,
829 "snps,lfps_filter_quirk");
830 dwc->rx_detect_poll_quirk = of_property_read_bool(node,
831 "snps,rx_detect_poll_quirk");
832 dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
833 "snps,dis_u3_susphy_quirk");
834 dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
835 "snps,dis_u2_susphy_quirk");
837 dwc->tx_de_emphasis_quirk = of_property_read_bool(node,
838 "snps,tx_de_emphasis_quirk");
839 of_property_read_u8(node, "snps,tx_de_emphasis",
842 dwc->maximum_speed = pdata->maximum_speed;
843 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
844 if (pdata->lpm_nyet_threshold)
845 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
846 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
847 if (pdata->hird_threshold)
848 hird_threshold = pdata->hird_threshold;
850 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
851 dwc->dr_mode = pdata->dr_mode;
853 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
854 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
855 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
856 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
857 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
858 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
859 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
860 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
861 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
862 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
864 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
865 if (pdata->tx_de_emphasis)
866 tx_de_emphasis = pdata->tx_de_emphasis;
869 /* default to superspeed if no maximum_speed passed */
870 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
871 dwc->maximum_speed = USB_SPEED_SUPER;
873 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
874 dwc->tx_de_emphasis = tx_de_emphasis;
876 dwc->hird_threshold = hird_threshold
877 | (dwc->is_utmi_l1_suspend << 4);
879 ret = dwc3_core_get_phy(dwc);
883 spin_lock_init(&dwc->lock);
884 platform_set_drvdata(pdev, dwc);
886 if (!dev->dma_mask) {
887 dev->dma_mask = dev->parent->dma_mask;
888 dev->dma_parms = dev->parent->dma_parms;
889 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
892 pm_runtime_enable(dev);
893 pm_runtime_get_sync(dev);
894 pm_runtime_forbid(dev);
896 dwc3_cache_hwparams(dwc);
898 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
900 dev_err(dwc->dev, "failed to allocate event buffers\n");
905 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
906 dwc->dr_mode = USB_DR_MODE_HOST;
907 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
908 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
910 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
911 dwc->dr_mode = USB_DR_MODE_OTG;
913 ret = dwc3_core_init(dwc);
915 dev_err(dev, "failed to initialize core\n");
919 usb_phy_set_suspend(dwc->usb2_phy, 0);
920 usb_phy_set_suspend(dwc->usb3_phy, 0);
921 ret = phy_power_on(dwc->usb2_generic_phy);
925 ret = phy_power_on(dwc->usb3_generic_phy);
927 goto err_usb2phy_power;
929 ret = dwc3_event_buffers_setup(dwc);
931 dev_err(dwc->dev, "failed to setup event buffers\n");
932 goto err_usb3phy_power;
935 ret = dwc3_core_init_mode(dwc);
939 ret = dwc3_debugfs_init(dwc);
941 dev_err(dev, "failed to initialize debugfs\n");
945 pm_runtime_allow(dev);
950 dwc3_core_exit_mode(dwc);
953 dwc3_event_buffers_cleanup(dwc);
956 phy_power_off(dwc->usb3_generic_phy);
959 phy_power_off(dwc->usb2_generic_phy);
962 usb_phy_set_suspend(dwc->usb2_phy, 1);
963 usb_phy_set_suspend(dwc->usb3_phy, 1);
967 dwc3_free_event_buffers(dwc);
972 static int dwc3_remove(struct platform_device *pdev)
974 struct dwc3 *dwc = platform_get_drvdata(pdev);
976 dwc3_debugfs_exit(dwc);
977 dwc3_core_exit_mode(dwc);
978 dwc3_event_buffers_cleanup(dwc);
979 dwc3_free_event_buffers(dwc);
981 usb_phy_set_suspend(dwc->usb2_phy, 1);
982 usb_phy_set_suspend(dwc->usb3_phy, 1);
983 phy_power_off(dwc->usb2_generic_phy);
984 phy_power_off(dwc->usb3_generic_phy);
988 pm_runtime_put_sync(&pdev->dev);
989 pm_runtime_disable(&pdev->dev);
994 #ifdef CONFIG_PM_SLEEP
995 static int dwc3_suspend(struct device *dev)
997 struct dwc3 *dwc = dev_get_drvdata(dev);
1000 spin_lock_irqsave(&dwc->lock, flags);
1002 switch (dwc->dr_mode) {
1003 case USB_DR_MODE_PERIPHERAL:
1004 case USB_DR_MODE_OTG:
1005 dwc3_gadget_suspend(dwc);
1007 case USB_DR_MODE_HOST:
1009 dwc3_event_buffers_cleanup(dwc);
1013 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1014 spin_unlock_irqrestore(&dwc->lock, flags);
1016 usb_phy_shutdown(dwc->usb3_phy);
1017 usb_phy_shutdown(dwc->usb2_phy);
1018 phy_exit(dwc->usb2_generic_phy);
1019 phy_exit(dwc->usb3_generic_phy);
1024 static int dwc3_resume(struct device *dev)
1026 struct dwc3 *dwc = dev_get_drvdata(dev);
1027 unsigned long flags;
1030 usb_phy_init(dwc->usb3_phy);
1031 usb_phy_init(dwc->usb2_phy);
1032 ret = phy_init(dwc->usb2_generic_phy);
1036 ret = phy_init(dwc->usb3_generic_phy);
1038 goto err_usb2phy_init;
1040 spin_lock_irqsave(&dwc->lock, flags);
1042 dwc3_event_buffers_setup(dwc);
1043 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1045 switch (dwc->dr_mode) {
1046 case USB_DR_MODE_PERIPHERAL:
1047 case USB_DR_MODE_OTG:
1048 dwc3_gadget_resume(dwc);
1050 case USB_DR_MODE_HOST:
1056 spin_unlock_irqrestore(&dwc->lock, flags);
1058 pm_runtime_disable(dev);
1059 pm_runtime_set_active(dev);
1060 pm_runtime_enable(dev);
1065 phy_exit(dwc->usb2_generic_phy);
1070 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1071 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1074 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1076 #define DWC3_PM_OPS NULL
1080 static const struct of_device_id of_dwc3_match[] = {
1082 .compatible = "snps,dwc3"
1085 .compatible = "synopsys,dwc3"
1089 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1094 #define ACPI_ID_INTEL_BSW "808622B7"
1096 static const struct acpi_device_id dwc3_acpi_match[] = {
1097 { ACPI_ID_INTEL_BSW, 0 },
1100 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1103 static struct platform_driver dwc3_driver = {
1104 .probe = dwc3_probe,
1105 .remove = dwc3_remove,
1108 .of_match_table = of_match_ptr(of_dwc3_match),
1109 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1114 module_platform_driver(dwc3_driver);
1116 MODULE_ALIAS("platform:dwc3");
1117 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1118 MODULE_LICENSE("GPL v2");
1119 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");