2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
44 #include "platform_data.h"
51 /* -------------------------------------------------------------------------- */
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
64 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
65 * @dwc: pointer to our context structure
67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
73 usb_phy_init(dwc->usb2_phy);
74 usb_phy_init(dwc->usb3_phy);
75 ret = phy_init(dwc->usb2_generic_phy);
79 ret = phy_init(dwc->usb3_generic_phy);
81 phy_exit(dwc->usb2_generic_phy);
86 * We're resetting only the device side because, if we're in host mode,
87 * XHCI driver will reset the host block. If dwc3 was configured for
88 * host-only mode, then we can return early.
90 if (dwc->dr_mode == USB_DR_MODE_HOST)
93 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
94 reg |= DWC3_DCTL_CSFTRST;
95 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
98 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
99 if (!(reg & DWC3_DCTL_CSFTRST))
109 * dwc3_soft_reset - Issue soft reset
110 * @dwc: Pointer to our controller context structure
112 int dwc3_soft_reset(struct dwc3 *dwc)
114 unsigned long timeout;
117 timeout = jiffies + msecs_to_jiffies(500);
118 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 if (!(reg & DWC3_DCTL_CSFTRST))
124 if (time_after(jiffies, timeout)) {
125 dev_err(dwc->dev, "Reset Timed Out\n");
136 * dwc3_frame_length_adjustment - Adjusts frame length if required
137 * @dwc3: Pointer to our controller context structure
138 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
140 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
145 if (dwc->revision < DWC3_REVISION_250A)
151 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
152 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
153 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
154 "request value same as default, ignoring\n")) {
155 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
156 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
157 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
162 * dwc3_free_one_event_buffer - Frees one event buffer
163 * @dwc: Pointer to our controller context structure
164 * @evt: Pointer to event buffer to be freed
166 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
167 struct dwc3_event_buffer *evt)
169 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
173 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
174 * @dwc: Pointer to our controller context structure
175 * @length: size of the event buffer
177 * Returns a pointer to the allocated event buffer structure on success
178 * otherwise ERR_PTR(errno).
180 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
183 struct dwc3_event_buffer *evt;
185 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
187 return ERR_PTR(-ENOMEM);
190 evt->length = length;
191 evt->buf = dma_alloc_coherent(dwc->dev, length,
192 &evt->dma, GFP_KERNEL);
194 return ERR_PTR(-ENOMEM);
200 * dwc3_free_event_buffers - frees all allocated event buffers
201 * @dwc: Pointer to our controller context structure
203 static void dwc3_free_event_buffers(struct dwc3 *dwc)
205 struct dwc3_event_buffer *evt;
208 for (i = 0; i < dwc->num_event_buffers; i++) {
209 evt = dwc->ev_buffs[i];
211 dwc3_free_one_event_buffer(dwc, evt);
216 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
217 * @dwc: pointer to our controller context structure
218 * @length: size of event buffer
220 * Returns 0 on success otherwise negative errno. In the error case, dwc
221 * may contain some buffers allocated but not all which were requested.
223 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
228 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
229 dwc->num_event_buffers = num;
231 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
236 for (i = 0; i < num; i++) {
237 struct dwc3_event_buffer *evt;
239 evt = dwc3_alloc_one_event_buffer(dwc, length);
241 dev_err(dwc->dev, "can't allocate event buffer\n");
244 dwc->ev_buffs[i] = evt;
251 * dwc3_event_buffers_setup - setup our allocated event buffers
252 * @dwc: pointer to our controller context structure
254 * Returns 0 on success otherwise negative errno.
256 int dwc3_event_buffers_setup(struct dwc3 *dwc)
258 struct dwc3_event_buffer *evt;
261 for (n = 0; n < dwc->num_event_buffers; n++) {
262 evt = dwc->ev_buffs[n];
263 dwc3_trace(trace_dwc3_core,
264 "Event buf %p dma %08llx length %d\n",
265 evt->buf, (unsigned long long) evt->dma,
270 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
271 lower_32_bits(evt->dma));
272 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
273 upper_32_bits(evt->dma));
274 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
275 DWC3_GEVNTSIZ_SIZE(evt->length));
276 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
282 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
284 struct dwc3_event_buffer *evt;
287 for (n = 0; n < dwc->num_event_buffers; n++) {
288 evt = dwc->ev_buffs[n];
292 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
293 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
294 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
295 | DWC3_GEVNTSIZ_SIZE(0));
296 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
300 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
302 if (!dwc->has_hibernation)
305 if (!dwc->nr_scratch)
308 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
309 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
310 if (!dwc->scratchbuf)
316 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
318 dma_addr_t scratch_addr;
322 if (!dwc->has_hibernation)
325 if (!dwc->nr_scratch)
328 /* should never fall here */
329 if (!WARN_ON(dwc->scratchbuf))
332 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
333 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
335 if (dma_mapping_error(dwc->dev, scratch_addr)) {
336 dev_err(dwc->dev, "failed to map scratch buffer\n");
341 dwc->scratch_addr = scratch_addr;
343 param = lower_32_bits(scratch_addr);
345 ret = dwc3_send_gadget_generic_command(dwc,
346 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
350 param = upper_32_bits(scratch_addr);
352 ret = dwc3_send_gadget_generic_command(dwc,
353 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
360 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
361 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
367 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
369 if (!dwc->has_hibernation)
372 if (!dwc->nr_scratch)
375 /* should never fall here */
376 if (!WARN_ON(dwc->scratchbuf))
379 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
380 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
381 kfree(dwc->scratchbuf);
384 static void dwc3_core_num_eps(struct dwc3 *dwc)
386 struct dwc3_hwparams *parms = &dwc->hwparams;
388 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
389 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
391 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
392 dwc->num_in_eps, dwc->num_out_eps);
395 static void dwc3_cache_hwparams(struct dwc3 *dwc)
397 struct dwc3_hwparams *parms = &dwc->hwparams;
399 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
400 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
401 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
402 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
403 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
404 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
405 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
406 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
407 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
411 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
412 * @dwc: Pointer to our controller context structure
414 * Returns 0 on success. The USB PHY interfaces are configured but not
415 * initialized. The PHY interfaces and the PHYs get initialized together with
416 * the core in dwc3_core_init.
418 static int dwc3_phy_setup(struct dwc3 *dwc)
424 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
427 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
428 * to '0' during coreConsultant configuration. So default value
429 * will be '0' when the core is reset. Application needs to set it
430 * to '1' after the core initialization is completed.
432 if (dwc->revision > DWC3_REVISION_194A)
433 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
435 if (dwc->u2ss_inp3_quirk)
436 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
438 if (dwc->req_p1p2p3_quirk)
439 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
441 if (dwc->del_p1p2p3_quirk)
442 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
444 if (dwc->del_phy_power_chg_quirk)
445 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
447 if (dwc->lfps_filter_quirk)
448 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
450 if (dwc->rx_detect_poll_quirk)
451 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
453 if (dwc->tx_de_emphasis_quirk)
454 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
456 if (dwc->dis_u3_susphy_quirk)
457 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
459 if (dwc->dis_del_phy_power_chg_quirk)
460 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
462 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
464 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
466 /* Select the HS PHY interface */
467 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
468 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
469 if (dwc->hsphy_interface &&
470 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
471 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
473 } else if (dwc->hsphy_interface &&
474 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
475 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
476 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
478 /* Relying on default value. */
479 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
483 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
484 /* Making sure the interface and PHY are operational */
485 ret = dwc3_soft_reset(dwc);
491 ret = dwc3_ulpi_init(dwc);
500 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
501 * '0' during coreConsultant configuration. So default value will
502 * be '0' when the core is reset. Application needs to set it to
503 * '1' after the core initialization is completed.
505 if (dwc->revision > DWC3_REVISION_194A)
506 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
508 if (dwc->dis_u2_susphy_quirk)
509 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
511 if (dwc->dis_enblslpm_quirk)
512 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
514 if (dwc->dis_u2_freeclk_exists_quirk)
515 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
517 if (dwc->phyif_utmi_16_bits)
518 reg |= DWC3_GUSB2PHYCFG_PHYIF;
520 usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ?
521 USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
523 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
524 reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT);
526 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
532 * dwc3_core_init - Low-level initialization of DWC3 Core
533 * @dwc: Pointer to our controller context structure
535 * Returns 0 on success otherwise negative errno.
537 static int dwc3_core_init(struct dwc3 *dwc)
539 u32 hwparams4 = dwc->hwparams.hwparams4;
543 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
544 /* This should read as U3 followed by revision number */
545 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
546 /* Detected DWC_usb3 IP */
548 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
549 /* Detected DWC_usb31 IP */
550 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
551 dwc->revision |= DWC3_REVISION_IS_DWC31;
553 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
559 * Write Linux Version Code to our GUID register so it's easy to figure
560 * out which kernel version a bug was found.
562 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
564 /* Handle USB2.0-only core configuration */
565 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
566 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
567 if (dwc->maximum_speed == USB_SPEED_SUPER)
568 dwc->maximum_speed = USB_SPEED_HIGH;
571 /* issue device SoftReset too */
572 ret = dwc3_soft_reset(dwc);
576 ret = dwc3_core_soft_reset(dwc);
580 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
581 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
583 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
584 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
586 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
587 * issue which would cause xHCI compliance tests to fail.
589 * Because of that we cannot enable clock gating on such
594 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
597 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
598 dwc->dr_mode == USB_DR_MODE_OTG) &&
599 (dwc->revision >= DWC3_REVISION_210A &&
600 dwc->revision <= DWC3_REVISION_250A))
601 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
603 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
605 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
606 /* enable hibernation here */
607 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
610 * REVISIT Enabling this bit so that host-mode hibernation
611 * will work. Device-mode hibernation is not yet implemented.
613 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
616 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
619 /* check if current dwc3 is on simulation board */
620 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
621 dwc3_trace(trace_dwc3_core,
622 "running on FPGA platform\n");
626 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
627 "disable_scramble cannot be used on non-FPGA builds\n");
629 if (dwc->disable_scramble_quirk && dwc->is_fpga)
630 reg |= DWC3_GCTL_DISSCRAMBLE;
632 reg &= ~DWC3_GCTL_DISSCRAMBLE;
634 if (dwc->u2exit_lfps_quirk)
635 reg |= DWC3_GCTL_U2EXIT_LFPS;
638 * WORKAROUND: DWC3 revisions <1.90a have a bug
639 * where the device can fail to connect at SuperSpeed
640 * and falls back to high-speed mode which causes
641 * the device to enter a Connect/Disconnect loop
643 if (dwc->revision < DWC3_REVISION_190A)
644 reg |= DWC3_GCTL_U2RSTECN;
646 dwc3_core_num_eps(dwc);
648 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
650 ret = dwc3_alloc_scratch_buffers(dwc);
654 ret = dwc3_setup_scratch_buffers(dwc);
661 dwc3_free_scratch_buffers(dwc);
664 usb_phy_shutdown(dwc->usb2_phy);
665 usb_phy_shutdown(dwc->usb3_phy);
666 phy_exit(dwc->usb2_generic_phy);
667 phy_exit(dwc->usb3_generic_phy);
673 static void dwc3_core_exit(struct dwc3 *dwc)
675 dwc3_free_scratch_buffers(dwc);
676 usb_phy_shutdown(dwc->usb2_phy);
677 usb_phy_shutdown(dwc->usb3_phy);
678 phy_exit(dwc->usb2_generic_phy);
679 phy_exit(dwc->usb3_generic_phy);
682 static int dwc3_core_get_phy(struct dwc3 *dwc)
684 struct device *dev = dwc->dev;
685 struct device_node *node = dev->of_node;
689 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
690 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
692 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
693 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
696 if (IS_ERR(dwc->usb2_phy)) {
697 ret = PTR_ERR(dwc->usb2_phy);
698 if (ret == -ENXIO || ret == -ENODEV) {
699 dwc->usb2_phy = NULL;
700 } else if (ret == -EPROBE_DEFER) {
703 dev_err(dev, "no usb2 phy configured\n");
708 if (IS_ERR(dwc->usb3_phy)) {
709 ret = PTR_ERR(dwc->usb3_phy);
710 if (ret == -ENXIO || ret == -ENODEV) {
711 dwc->usb3_phy = NULL;
712 } else if (ret == -EPROBE_DEFER) {
715 dev_err(dev, "no usb3 phy configured\n");
720 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
721 if (IS_ERR(dwc->usb2_generic_phy)) {
722 ret = PTR_ERR(dwc->usb2_generic_phy);
723 if (ret == -ENOSYS || ret == -ENODEV) {
724 dwc->usb2_generic_phy = NULL;
725 } else if (ret == -EPROBE_DEFER) {
728 dev_err(dev, "no usb2 phy configured\n");
733 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
734 if (IS_ERR(dwc->usb3_generic_phy)) {
735 ret = PTR_ERR(dwc->usb3_generic_phy);
736 if (ret == -ENOSYS || ret == -ENODEV) {
737 dwc->usb3_generic_phy = NULL;
738 } else if (ret == -EPROBE_DEFER) {
741 dev_err(dev, "no usb3 phy configured\n");
749 static int dwc3_core_init_mode(struct dwc3 *dwc)
751 struct device *dev = dwc->dev;
754 switch (dwc->dr_mode) {
755 case USB_DR_MODE_PERIPHERAL:
756 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
757 ret = dwc3_gadget_init(dwc);
759 dev_err(dev, "failed to initialize gadget\n");
763 case USB_DR_MODE_HOST:
764 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
765 ret = dwc3_host_init(dwc);
767 dev_err(dev, "failed to initialize host\n");
771 case USB_DR_MODE_OTG:
772 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
773 ret = dwc3_host_init(dwc);
775 dev_err(dev, "failed to initialize host\n");
779 ret = dwc3_gadget_init(dwc);
781 dev_err(dev, "failed to initialize gadget\n");
786 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
793 static void dwc3_core_exit_mode(struct dwc3 *dwc)
795 switch (dwc->dr_mode) {
796 case USB_DR_MODE_PERIPHERAL:
797 dwc3_gadget_exit(dwc);
799 case USB_DR_MODE_HOST:
802 case USB_DR_MODE_OTG:
804 dwc3_gadget_exit(dwc);
812 /* Returns true if the controller is capable of DRD. */
813 bool dwc3_hw_is_drd(struct dwc3 *dwc)
815 u32 op_mode = DWC3_GHWPARAMS0_USB3_MODE(dwc->hwparams.hwparams0);
817 return (op_mode == DWC3_GHWPARAMS0_USB3_DRD);
820 bool dwc3_force_mode(struct dwc3 *dwc, u32 mode)
827 * Force mode has no effect if the hardware is not drd mode.
829 if (!dwc3_hw_is_drd(dwc))
832 * If dr_mode is either peripheral or host only, there is no
833 * need to ever force the mode to the opposite mode.
835 if (WARN_ON(mode == DWC3_GCTL_PRTCAP_DEVICE &&
836 dwc->dr_mode == USB_DR_MODE_HOST))
839 if (WARN_ON(mode == DWC3_GCTL_PRTCAP_HOST &&
840 dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
843 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
844 if (DWC3_GCTL_PRTCAP(reg) == mode)
847 hcd = dev_get_drvdata(&dwc->xhci->dev);
850 case DWC3_GCTL_PRTCAP_DEVICE:
851 if (hcd->state != HC_STATE_HALT) {
852 usb_remove_hcd(hcd->shared_hcd);
856 spin_lock_irqsave(&dwc->lock, flags);
857 dwc3_set_mode(dwc, mode);
858 dwc3_gadget_restart(dwc, true);
859 spin_unlock_irqrestore(&dwc->lock, flags);
862 case DWC3_GCTL_PRTCAP_HOST:
863 spin_lock_irqsave(&dwc->lock, flags);
864 dwc3_gadget_restart(dwc, false);
865 dwc3_set_mode(dwc, mode);
866 spin_unlock_irqrestore(&dwc->lock, flags);
868 if (hcd->state == HC_STATE_HALT) {
869 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
870 usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
882 #define DWC3_ALIGN_MASK (16 - 1)
884 static int dwc3_probe(struct platform_device *pdev)
886 struct device *dev = &pdev->dev;
887 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
888 struct resource *res;
890 u8 lpm_nyet_threshold;
900 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
904 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
908 /* Try to set 64-bit DMA first */
909 if (!pdev->dev.dma_mask)
910 /* Platform did not initialize dma_mask */
911 ret = dma_coerce_mask_and_coherent(&pdev->dev,
914 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
916 /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
918 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
923 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
925 dev_err(dev, "missing IRQ\n");
928 dwc->xhci_resources[1].start = res->start;
929 dwc->xhci_resources[1].end = res->end;
930 dwc->xhci_resources[1].flags = res->flags;
931 dwc->xhci_resources[1].name = res->name;
933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
935 dev_err(dev, "missing memory resource\n");
939 dwc->xhci_resources[0].start = res->start;
940 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
942 dwc->xhci_resources[0].flags = res->flags;
943 dwc->xhci_resources[0].name = res->name;
945 res->start += DWC3_GLOBALS_REGS_START;
948 * Request memory region but exclude xHCI regs,
949 * since it will be requested by the xhci-plat driver.
951 regs = devm_ioremap_resource(dev, res);
958 dwc->regs_size = resource_size(res);
960 /* default to highest possible threshold */
961 lpm_nyet_threshold = 0xff;
963 /* default to -3.5dB de-emphasis */
967 * default to assert utmi_sleep_n and use maximum allowed HIRD
968 * threshold value of 0b1100
972 dwc->maximum_speed = usb_get_maximum_speed(dev);
973 dwc->dr_mode = usb_get_dr_mode(dev);
975 dwc->has_lpm_erratum = device_property_read_bool(dev,
976 "snps,has-lpm-erratum");
977 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
978 &lpm_nyet_threshold);
979 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
980 "snps,is-utmi-l1-suspend");
981 device_property_read_u8(dev, "snps,hird-threshold",
983 dwc->usb3_lpm_capable = device_property_read_bool(dev,
984 "snps,usb3_lpm_capable");
986 dwc->disable_scramble_quirk = device_property_read_bool(dev,
987 "snps,disable_scramble_quirk");
988 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
989 "snps,u2exit_lfps_quirk");
990 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
991 "snps,u2ss_inp3_quirk");
992 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
993 "snps,req_p1p2p3_quirk");
994 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
995 "snps,del_p1p2p3_quirk");
996 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
997 "snps,del_phy_power_chg_quirk");
998 dwc->lfps_filter_quirk = device_property_read_bool(dev,
999 "snps,lfps_filter_quirk");
1000 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1001 "snps,rx_detect_poll_quirk");
1002 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1003 "snps,dis_u3_susphy_quirk");
1004 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1005 "snps,dis_u2_susphy_quirk");
1006 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1007 "snps,dis_enblslpm_quirk");
1008 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1009 "snps,dis_u2_freeclk_exists_quirk");
1010 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1011 "snps,dis_del_phy_power_chg_quirk");
1012 dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
1013 "snps,xhci_slow_suspend_quirk");
1014 dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
1015 "snps,phyif_utmi_16_bits");
1017 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1018 "snps,tx_de_emphasis_quirk");
1019 device_property_read_u8(dev, "snps,tx_de_emphasis",
1021 device_property_read_string(dev, "snps,hsphy_interface",
1022 &dwc->hsphy_interface);
1023 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1027 dwc->maximum_speed = pdata->maximum_speed;
1028 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
1029 if (pdata->lpm_nyet_threshold)
1030 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
1031 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
1032 if (pdata->hird_threshold)
1033 hird_threshold = pdata->hird_threshold;
1035 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
1036 dwc->dr_mode = pdata->dr_mode;
1038 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
1039 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
1040 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
1041 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
1042 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
1043 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
1044 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
1045 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
1046 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
1047 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
1048 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
1049 dwc->dis_u2_freeclk_exists_quirk =
1050 pdata->dis_u2_freeclk_exists_quirk;
1051 dwc->dis_del_phy_power_chg_quirk =
1052 pdata->dis_del_phy_power_chg_quirk;
1053 dwc->xhci_slow_suspend_quirk =
1054 pdata->xhci_slow_suspend_quirk;
1055 dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
1057 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1058 if (pdata->tx_de_emphasis)
1059 tx_de_emphasis = pdata->tx_de_emphasis;
1061 dwc->hsphy_interface = pdata->hsphy_interface;
1062 fladj = pdata->fladj_value;
1065 /* default to superspeed if no maximum_speed passed */
1066 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1067 dwc->maximum_speed = USB_SPEED_SUPER;
1069 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1070 dwc->tx_de_emphasis = tx_de_emphasis;
1072 dwc->hird_threshold = hird_threshold
1073 | (dwc->is_utmi_l1_suspend << 4);
1075 platform_set_drvdata(pdev, dwc);
1076 dwc3_cache_hwparams(dwc);
1078 ret = dwc3_phy_setup(dwc);
1082 ret = dwc3_core_get_phy(dwc);
1086 spin_lock_init(&dwc->lock);
1088 if (!dev->dma_mask) {
1089 dev->dma_mask = dev->parent->dma_mask;
1090 dev->dma_parms = dev->parent->dma_parms;
1091 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1094 pm_runtime_enable(dev);
1095 pm_runtime_get_sync(dev);
1096 pm_runtime_forbid(dev);
1098 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1100 dev_err(dwc->dev, "failed to allocate event buffers\n");
1105 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1106 dwc->dr_mode = USB_DR_MODE_HOST;
1107 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1108 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1110 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1111 dwc->dr_mode = USB_DR_MODE_OTG;
1113 ret = dwc3_core_init(dwc);
1115 dev_err(dev, "failed to initialize core\n");
1119 /* Adjust Frame Length */
1120 dwc3_frame_length_adjustment(dwc, fladj);
1122 usb_phy_set_suspend(dwc->usb2_phy, 0);
1123 usb_phy_set_suspend(dwc->usb3_phy, 0);
1124 ret = phy_power_on(dwc->usb2_generic_phy);
1128 ret = phy_power_on(dwc->usb3_generic_phy);
1132 ret = dwc3_event_buffers_setup(dwc);
1134 dev_err(dwc->dev, "failed to setup event buffers\n");
1138 ret = dwc3_core_init_mode(dwc);
1142 ret = dwc3_debugfs_init(dwc);
1144 dev_err(dev, "failed to initialize debugfs\n");
1148 pm_runtime_allow(dev);
1153 dwc3_core_exit_mode(dwc);
1156 dwc3_event_buffers_cleanup(dwc);
1159 phy_power_off(dwc->usb3_generic_phy);
1162 phy_power_off(dwc->usb2_generic_phy);
1165 usb_phy_set_suspend(dwc->usb2_phy, 1);
1166 usb_phy_set_suspend(dwc->usb3_phy, 1);
1167 dwc3_core_exit(dwc);
1170 dwc3_free_event_buffers(dwc);
1171 dwc3_ulpi_exit(dwc);
1175 * restore res->start back to its original value so that, in case the
1176 * probe is deferred, we don't end up getting error in request the
1177 * memory region the next time probe is called.
1179 res->start -= DWC3_GLOBALS_REGS_START;
1184 static int dwc3_remove(struct platform_device *pdev)
1186 struct dwc3 *dwc = platform_get_drvdata(pdev);
1187 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1190 * restore res->start back to its original value so that, in case the
1191 * probe is deferred, we don't end up getting error in request the
1192 * memory region the next time probe is called.
1194 res->start -= DWC3_GLOBALS_REGS_START;
1196 dwc3_debugfs_exit(dwc);
1197 dwc3_core_exit_mode(dwc);
1198 dwc3_event_buffers_cleanup(dwc);
1199 dwc3_free_event_buffers(dwc);
1201 usb_phy_set_suspend(dwc->usb2_phy, 1);
1202 usb_phy_set_suspend(dwc->usb3_phy, 1);
1203 phy_power_off(dwc->usb2_generic_phy);
1204 phy_power_off(dwc->usb3_generic_phy);
1206 dwc3_core_exit(dwc);
1207 dwc3_ulpi_exit(dwc);
1209 pm_runtime_put_sync(&pdev->dev);
1210 pm_runtime_disable(&pdev->dev);
1215 #ifdef CONFIG_PM_SLEEP
1216 static int dwc3_suspend(struct device *dev)
1218 struct dwc3 *dwc = dev_get_drvdata(dev);
1219 unsigned long flags;
1221 spin_lock_irqsave(&dwc->lock, flags);
1223 switch (dwc->dr_mode) {
1224 case USB_DR_MODE_PERIPHERAL:
1225 case USB_DR_MODE_OTG:
1226 dwc3_gadget_suspend(dwc);
1228 case USB_DR_MODE_HOST:
1230 dwc3_event_buffers_cleanup(dwc);
1234 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1235 spin_unlock_irqrestore(&dwc->lock, flags);
1237 usb_phy_shutdown(dwc->usb3_phy);
1238 usb_phy_shutdown(dwc->usb2_phy);
1239 phy_exit(dwc->usb2_generic_phy);
1240 phy_exit(dwc->usb3_generic_phy);
1242 pinctrl_pm_select_sleep_state(dev);
1247 static int dwc3_resume(struct device *dev)
1249 struct dwc3 *dwc = dev_get_drvdata(dev);
1250 unsigned long flags;
1253 pinctrl_pm_select_default_state(dev);
1255 usb_phy_init(dwc->usb3_phy);
1256 usb_phy_init(dwc->usb2_phy);
1257 ret = phy_init(dwc->usb2_generic_phy);
1261 ret = phy_init(dwc->usb3_generic_phy);
1263 goto err_usb2phy_init;
1265 spin_lock_irqsave(&dwc->lock, flags);
1267 dwc3_event_buffers_setup(dwc);
1268 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1270 switch (dwc->dr_mode) {
1271 case USB_DR_MODE_PERIPHERAL:
1272 case USB_DR_MODE_OTG:
1273 dwc3_gadget_resume(dwc);
1275 case USB_DR_MODE_HOST:
1281 spin_unlock_irqrestore(&dwc->lock, flags);
1283 pm_runtime_disable(dev);
1284 pm_runtime_set_active(dev);
1285 pm_runtime_enable(dev);
1290 phy_exit(dwc->usb2_generic_phy);
1295 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1296 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1299 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1301 #define DWC3_PM_OPS NULL
1305 static const struct of_device_id of_dwc3_match[] = {
1307 .compatible = "snps,dwc3"
1310 .compatible = "synopsys,dwc3"
1314 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1319 #define ACPI_ID_INTEL_BSW "808622B7"
1321 static const struct acpi_device_id dwc3_acpi_match[] = {
1322 { ACPI_ID_INTEL_BSW, 0 },
1325 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1328 static struct platform_driver dwc3_driver = {
1329 .probe = dwc3_probe,
1330 .remove = dwc3_remove,
1333 .of_match_table = of_match_ptr(of_dwc3_match),
1334 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1339 module_platform_driver(dwc3_driver);
1341 MODULE_ALIAS("platform:dwc3");
1342 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1343 MODULE_LICENSE("GPL v2");
1344 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");