2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
44 #include "platform_data.h"
51 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
63 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
65 struct dwc3 *dwc = dep->dwc;
68 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
69 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
70 DWC3_GDBGFIFOSPACE_TYPE(type));
72 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
74 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
78 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
79 * @dwc: pointer to our context structure
81 static int dwc3_core_soft_reset(struct dwc3 *dwc)
87 usb_phy_init(dwc->usb2_phy);
88 usb_phy_init(dwc->usb3_phy);
89 ret = phy_init(dwc->usb2_generic_phy);
93 ret = phy_init(dwc->usb3_generic_phy);
95 phy_exit(dwc->usb2_generic_phy);
100 * We're resetting only the device side because, if we're in host mode,
101 * XHCI driver will reset the host block. If dwc3 was configured for
102 * host-only mode, then we can return early.
104 if (dwc->dr_mode == USB_DR_MODE_HOST)
107 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
108 reg |= DWC3_DCTL_CSFTRST;
109 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
112 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
113 if (!(reg & DWC3_DCTL_CSFTRST))
123 * dwc3_soft_reset - Issue soft reset
124 * @dwc: Pointer to our controller context structure
126 static int dwc3_soft_reset(struct dwc3 *dwc)
128 unsigned long timeout;
131 timeout = jiffies + msecs_to_jiffies(500);
132 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
134 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
135 if (!(reg & DWC3_DCTL_CSFTRST))
138 if (time_after(jiffies, timeout)) {
139 dev_err(dwc->dev, "Reset Timed Out\n");
150 * dwc3_frame_length_adjustment - Adjusts frame length if required
151 * @dwc3: Pointer to our controller context structure
153 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
158 if (dwc->revision < DWC3_REVISION_250A)
164 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
165 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
166 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
167 "request value same as default, ignoring\n")) {
168 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
169 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
170 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
175 * dwc3_free_one_event_buffer - Frees one event buffer
176 * @dwc: Pointer to our controller context structure
177 * @evt: Pointer to event buffer to be freed
179 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
180 struct dwc3_event_buffer *evt)
182 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
186 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
187 * @dwc: Pointer to our controller context structure
188 * @length: size of the event buffer
190 * Returns a pointer to the allocated event buffer structure on success
191 * otherwise ERR_PTR(errno).
193 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
196 struct dwc3_event_buffer *evt;
198 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
200 return ERR_PTR(-ENOMEM);
203 evt->length = length;
204 evt->buf = dma_alloc_coherent(dwc->dev, length,
205 &evt->dma, GFP_KERNEL);
207 return ERR_PTR(-ENOMEM);
213 * dwc3_free_event_buffers - frees all allocated event buffers
214 * @dwc: Pointer to our controller context structure
216 static void dwc3_free_event_buffers(struct dwc3 *dwc)
218 struct dwc3_event_buffer *evt;
222 dwc3_free_one_event_buffer(dwc, evt);
226 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
227 * @dwc: pointer to our controller context structure
228 * @length: size of event buffer
230 * Returns 0 on success otherwise negative errno. In the error case, dwc
231 * may contain some buffers allocated but not all which were requested.
233 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
235 struct dwc3_event_buffer *evt;
237 evt = dwc3_alloc_one_event_buffer(dwc, length);
239 dev_err(dwc->dev, "can't allocate event buffer\n");
248 * dwc3_event_buffers_setup - setup our allocated event buffers
249 * @dwc: pointer to our controller context structure
251 * Returns 0 on success otherwise negative errno.
253 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
255 struct dwc3_event_buffer *evt;
258 dwc3_trace(trace_dwc3_core,
259 "Event buf %p dma %08llx length %d\n",
260 evt->buf, (unsigned long long) evt->dma,
265 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
266 lower_32_bits(evt->dma));
267 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
268 upper_32_bits(evt->dma));
269 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
270 DWC3_GEVNTSIZ_SIZE(evt->length));
271 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
276 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
278 struct dwc3_event_buffer *evt;
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
285 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
286 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
287 | DWC3_GEVNTSIZ_SIZE(0));
288 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
291 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
293 if (!dwc->has_hibernation)
296 if (!dwc->nr_scratch)
299 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
300 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
301 if (!dwc->scratchbuf)
307 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
309 dma_addr_t scratch_addr;
313 if (!dwc->has_hibernation)
316 if (!dwc->nr_scratch)
319 /* should never fall here */
320 if (!WARN_ON(dwc->scratchbuf))
323 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
324 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
326 if (dma_mapping_error(dwc->dev, scratch_addr)) {
327 dev_err(dwc->dev, "failed to map scratch buffer\n");
332 dwc->scratch_addr = scratch_addr;
334 param = lower_32_bits(scratch_addr);
336 ret = dwc3_send_gadget_generic_command(dwc,
337 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
341 param = upper_32_bits(scratch_addr);
343 ret = dwc3_send_gadget_generic_command(dwc,
344 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
351 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
352 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
358 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
360 if (!dwc->has_hibernation)
363 if (!dwc->nr_scratch)
366 /* should never fall here */
367 if (!WARN_ON(dwc->scratchbuf))
370 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
371 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
372 kfree(dwc->scratchbuf);
375 static void dwc3_core_num_eps(struct dwc3 *dwc)
377 struct dwc3_hwparams *parms = &dwc->hwparams;
379 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
380 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
382 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
383 dwc->num_in_eps, dwc->num_out_eps);
386 static void dwc3_cache_hwparams(struct dwc3 *dwc)
388 struct dwc3_hwparams *parms = &dwc->hwparams;
390 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
391 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
392 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
393 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
394 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
395 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
396 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
397 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
398 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
402 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
403 * @dwc: Pointer to our controller context structure
405 * Returns 0 on success. The USB PHY interfaces are configured but not
406 * initialized. The PHY interfaces and the PHYs get initialized together with
407 * the core in dwc3_core_init.
409 static int dwc3_phy_setup(struct dwc3 *dwc)
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
417 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
418 * to '0' during coreConsultant configuration. So default value
419 * will be '0' when the core is reset. Application needs to set it
420 * to '1' after the core initialization is completed.
422 if (dwc->revision > DWC3_REVISION_194A)
423 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
425 if (dwc->u2ss_inp3_quirk)
426 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
428 if (dwc->dis_rxdet_inp3_quirk)
429 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
431 if (dwc->req_p1p2p3_quirk)
432 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
434 if (dwc->del_p1p2p3_quirk)
435 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
437 if (dwc->del_phy_power_chg_quirk)
438 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
440 if (dwc->lfps_filter_quirk)
441 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
443 if (dwc->rx_detect_poll_quirk)
444 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
446 if (dwc->tx_de_emphasis_quirk)
447 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
449 if (dwc->dis_u3_susphy_quirk)
450 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
452 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
454 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
456 /* Select the HS PHY interface */
457 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
458 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
459 if (dwc->hsphy_interface &&
460 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
461 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
463 } else if (dwc->hsphy_interface &&
464 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
465 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
466 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
468 /* Relying on default value. */
469 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
473 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
474 /* Making sure the interface and PHY are operational */
475 ret = dwc3_soft_reset(dwc);
481 ret = dwc3_ulpi_init(dwc);
490 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
491 * '0' during coreConsultant configuration. So default value will
492 * be '0' when the core is reset. Application needs to set it to
493 * '1' after the core initialization is completed.
495 if (dwc->revision > DWC3_REVISION_194A)
496 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
498 if (dwc->dis_u2_susphy_quirk)
499 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
501 if (dwc->dis_enblslpm_quirk)
502 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
504 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
509 static void dwc3_core_exit(struct dwc3 *dwc)
511 dwc3_event_buffers_cleanup(dwc);
513 usb_phy_shutdown(dwc->usb2_phy);
514 usb_phy_shutdown(dwc->usb3_phy);
515 phy_exit(dwc->usb2_generic_phy);
516 phy_exit(dwc->usb3_generic_phy);
518 usb_phy_set_suspend(dwc->usb2_phy, 1);
519 usb_phy_set_suspend(dwc->usb3_phy, 1);
520 phy_power_off(dwc->usb2_generic_phy);
521 phy_power_off(dwc->usb3_generic_phy);
525 * dwc3_core_init - Low-level initialization of DWC3 Core
526 * @dwc: Pointer to our controller context structure
528 * Returns 0 on success otherwise negative errno.
530 static int dwc3_core_init(struct dwc3 *dwc)
532 u32 hwparams4 = dwc->hwparams.hwparams4;
536 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
537 /* This should read as U3 followed by revision number */
538 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
539 /* Detected DWC_usb3 IP */
541 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
542 /* Detected DWC_usb31 IP */
543 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
544 dwc->revision |= DWC3_REVISION_IS_DWC31;
546 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
552 * Write Linux Version Code to our GUID register so it's easy to figure
553 * out which kernel version a bug was found.
555 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
557 /* Handle USB2.0-only core configuration */
558 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
559 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
560 if (dwc->maximum_speed == USB_SPEED_SUPER)
561 dwc->maximum_speed = USB_SPEED_HIGH;
564 /* issue device SoftReset too */
565 ret = dwc3_soft_reset(dwc);
569 ret = dwc3_core_soft_reset(dwc);
573 ret = dwc3_phy_setup(dwc);
577 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
578 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
580 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
581 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
583 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
584 * issue which would cause xHCI compliance tests to fail.
586 * Because of that we cannot enable clock gating on such
591 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
594 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
595 dwc->dr_mode == USB_DR_MODE_OTG) &&
596 (dwc->revision >= DWC3_REVISION_210A &&
597 dwc->revision <= DWC3_REVISION_250A))
598 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
600 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
602 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
603 /* enable hibernation here */
604 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
607 * REVISIT Enabling this bit so that host-mode hibernation
608 * will work. Device-mode hibernation is not yet implemented.
610 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
613 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
616 /* check if current dwc3 is on simulation board */
617 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
618 dwc3_trace(trace_dwc3_core,
619 "running on FPGA platform\n");
623 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
624 "disable_scramble cannot be used on non-FPGA builds\n");
626 if (dwc->disable_scramble_quirk && dwc->is_fpga)
627 reg |= DWC3_GCTL_DISSCRAMBLE;
629 reg &= ~DWC3_GCTL_DISSCRAMBLE;
631 if (dwc->u2exit_lfps_quirk)
632 reg |= DWC3_GCTL_U2EXIT_LFPS;
635 * WORKAROUND: DWC3 revisions <1.90a have a bug
636 * where the device can fail to connect at SuperSpeed
637 * and falls back to high-speed mode which causes
638 * the device to enter a Connect/Disconnect loop
640 if (dwc->revision < DWC3_REVISION_190A)
641 reg |= DWC3_GCTL_U2RSTECN;
643 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
645 dwc3_core_num_eps(dwc);
647 ret = dwc3_setup_scratch_buffers(dwc);
651 /* Adjust Frame Length */
652 dwc3_frame_length_adjustment(dwc);
654 usb_phy_set_suspend(dwc->usb2_phy, 0);
655 usb_phy_set_suspend(dwc->usb3_phy, 0);
656 ret = phy_power_on(dwc->usb2_generic_phy);
660 ret = phy_power_on(dwc->usb3_generic_phy);
664 ret = dwc3_event_buffers_setup(dwc);
666 dev_err(dwc->dev, "failed to setup event buffers\n");
673 phy_power_off(dwc->usb2_generic_phy);
676 phy_power_off(dwc->usb3_generic_phy);
679 usb_phy_set_suspend(dwc->usb2_phy, 1);
680 usb_phy_set_suspend(dwc->usb3_phy, 1);
684 usb_phy_shutdown(dwc->usb2_phy);
685 usb_phy_shutdown(dwc->usb3_phy);
686 phy_exit(dwc->usb2_generic_phy);
687 phy_exit(dwc->usb3_generic_phy);
693 static int dwc3_core_get_phy(struct dwc3 *dwc)
695 struct device *dev = dwc->dev;
696 struct device_node *node = dev->of_node;
700 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
701 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
703 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
704 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
707 if (IS_ERR(dwc->usb2_phy)) {
708 ret = PTR_ERR(dwc->usb2_phy);
709 if (ret == -ENXIO || ret == -ENODEV) {
710 dwc->usb2_phy = NULL;
711 } else if (ret == -EPROBE_DEFER) {
714 dev_err(dev, "no usb2 phy configured\n");
719 if (IS_ERR(dwc->usb3_phy)) {
720 ret = PTR_ERR(dwc->usb3_phy);
721 if (ret == -ENXIO || ret == -ENODEV) {
722 dwc->usb3_phy = NULL;
723 } else if (ret == -EPROBE_DEFER) {
726 dev_err(dev, "no usb3 phy configured\n");
731 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
732 if (IS_ERR(dwc->usb2_generic_phy)) {
733 ret = PTR_ERR(dwc->usb2_generic_phy);
734 if (ret == -ENOSYS || ret == -ENODEV) {
735 dwc->usb2_generic_phy = NULL;
736 } else if (ret == -EPROBE_DEFER) {
739 dev_err(dev, "no usb2 phy configured\n");
744 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
745 if (IS_ERR(dwc->usb3_generic_phy)) {
746 ret = PTR_ERR(dwc->usb3_generic_phy);
747 if (ret == -ENOSYS || ret == -ENODEV) {
748 dwc->usb3_generic_phy = NULL;
749 } else if (ret == -EPROBE_DEFER) {
752 dev_err(dev, "no usb3 phy configured\n");
760 static int dwc3_core_init_mode(struct dwc3 *dwc)
762 struct device *dev = dwc->dev;
765 switch (dwc->dr_mode) {
766 case USB_DR_MODE_PERIPHERAL:
767 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
768 ret = dwc3_gadget_init(dwc);
770 dev_err(dev, "failed to initialize gadget\n");
774 case USB_DR_MODE_HOST:
775 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
776 ret = dwc3_host_init(dwc);
778 dev_err(dev, "failed to initialize host\n");
782 case USB_DR_MODE_OTG:
783 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
784 ret = dwc3_host_init(dwc);
786 dev_err(dev, "failed to initialize host\n");
790 ret = dwc3_gadget_init(dwc);
792 dev_err(dev, "failed to initialize gadget\n");
797 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
804 static void dwc3_core_exit_mode(struct dwc3 *dwc)
806 switch (dwc->dr_mode) {
807 case USB_DR_MODE_PERIPHERAL:
808 dwc3_gadget_exit(dwc);
810 case USB_DR_MODE_HOST:
813 case USB_DR_MODE_OTG:
815 dwc3_gadget_exit(dwc);
823 #define DWC3_ALIGN_MASK (16 - 1)
825 static int dwc3_probe(struct platform_device *pdev)
827 struct device *dev = &pdev->dev;
828 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
829 struct resource *res;
831 u8 lpm_nyet_threshold;
840 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
844 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
848 /* Try to set 64-bit DMA first */
849 if (!pdev->dev.dma_mask)
850 /* Platform did not initialize dma_mask */
851 ret = dma_coerce_mask_and_coherent(&pdev->dev,
854 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
856 /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
858 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
863 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
865 dev_err(dev, "missing IRQ\n");
868 dwc->xhci_resources[1].start = res->start;
869 dwc->xhci_resources[1].end = res->end;
870 dwc->xhci_resources[1].flags = res->flags;
871 dwc->xhci_resources[1].name = res->name;
873 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
875 dev_err(dev, "missing memory resource\n");
879 dwc->xhci_resources[0].start = res->start;
880 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
882 dwc->xhci_resources[0].flags = res->flags;
883 dwc->xhci_resources[0].name = res->name;
885 res->start += DWC3_GLOBALS_REGS_START;
888 * Request memory region but exclude xHCI regs,
889 * since it will be requested by the xhci-plat driver.
891 regs = devm_ioremap_resource(dev, res);
898 dwc->regs_size = resource_size(res);
900 /* default to highest possible threshold */
901 lpm_nyet_threshold = 0xff;
903 /* default to -3.5dB de-emphasis */
907 * default to assert utmi_sleep_n and use maximum allowed HIRD
908 * threshold value of 0b1100
912 dwc->maximum_speed = usb_get_maximum_speed(dev);
913 dwc->dr_mode = usb_get_dr_mode(dev);
915 dwc->has_lpm_erratum = device_property_read_bool(dev,
916 "snps,has-lpm-erratum");
917 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
918 &lpm_nyet_threshold);
919 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
920 "snps,is-utmi-l1-suspend");
921 device_property_read_u8(dev, "snps,hird-threshold",
923 dwc->usb3_lpm_capable = device_property_read_bool(dev,
924 "snps,usb3_lpm_capable");
926 dwc->disable_scramble_quirk = device_property_read_bool(dev,
927 "snps,disable_scramble_quirk");
928 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
929 "snps,u2exit_lfps_quirk");
930 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
931 "snps,u2ss_inp3_quirk");
932 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
933 "snps,req_p1p2p3_quirk");
934 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
935 "snps,del_p1p2p3_quirk");
936 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
937 "snps,del_phy_power_chg_quirk");
938 dwc->lfps_filter_quirk = device_property_read_bool(dev,
939 "snps,lfps_filter_quirk");
940 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
941 "snps,rx_detect_poll_quirk");
942 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
943 "snps,dis_u3_susphy_quirk");
944 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
945 "snps,dis_u2_susphy_quirk");
946 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
947 "snps,dis_enblslpm_quirk");
948 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
949 "snps,dis_rxdet_inp3_quirk");
951 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
952 "snps,tx_de_emphasis_quirk");
953 device_property_read_u8(dev, "snps,tx_de_emphasis",
955 device_property_read_string(dev, "snps,hsphy_interface",
956 &dwc->hsphy_interface);
957 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
961 dwc->maximum_speed = pdata->maximum_speed;
962 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
963 if (pdata->lpm_nyet_threshold)
964 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
965 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
966 if (pdata->hird_threshold)
967 hird_threshold = pdata->hird_threshold;
969 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
970 dwc->dr_mode = pdata->dr_mode;
972 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
973 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
974 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
975 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
976 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
977 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
978 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
979 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
980 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
981 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
982 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
983 dwc->dis_rxdet_inp3_quirk = pdata->dis_rxdet_inp3_quirk;
985 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
986 if (pdata->tx_de_emphasis)
987 tx_de_emphasis = pdata->tx_de_emphasis;
989 dwc->hsphy_interface = pdata->hsphy_interface;
990 dwc->fladj = pdata->fladj_value;
993 /* default to superspeed if no maximum_speed passed */
994 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
995 dwc->maximum_speed = USB_SPEED_SUPER;
997 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
998 dwc->tx_de_emphasis = tx_de_emphasis;
1000 dwc->hird_threshold = hird_threshold
1001 | (dwc->is_utmi_l1_suspend << 4);
1003 platform_set_drvdata(pdev, dwc);
1004 dwc3_cache_hwparams(dwc);
1006 ret = dwc3_core_get_phy(dwc);
1010 spin_lock_init(&dwc->lock);
1012 if (!dev->dma_mask) {
1013 dev->dma_mask = dev->parent->dma_mask;
1014 dev->dma_parms = dev->parent->dma_parms;
1015 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1018 pm_runtime_set_active(dev);
1019 pm_runtime_use_autosuspend(dev);
1020 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1021 pm_runtime_enable(dev);
1022 pm_runtime_get_sync(dev);
1023 pm_runtime_forbid(dev);
1025 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1027 dev_err(dwc->dev, "failed to allocate event buffers\n");
1032 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1033 dwc->dr_mode = USB_DR_MODE_HOST;
1034 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1035 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1037 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1038 dwc->dr_mode = USB_DR_MODE_OTG;
1040 ret = dwc3_alloc_scratch_buffers(dwc);
1044 ret = dwc3_core_init(dwc);
1046 dev_err(dev, "failed to initialize core\n");
1050 ret = dwc3_core_init_mode(dwc);
1054 dwc3_debugfs_init(dwc);
1055 pm_runtime_put(dev);
1060 dwc3_event_buffers_cleanup(dwc);
1063 dwc3_free_scratch_buffers(dwc);
1066 dwc3_free_event_buffers(dwc);
1067 dwc3_ulpi_exit(dwc);
1071 * restore res->start back to its original value so that, in case the
1072 * probe is deferred, we don't end up getting error in request the
1073 * memory region the next time probe is called.
1075 res->start -= DWC3_GLOBALS_REGS_START;
1080 static int dwc3_remove(struct platform_device *pdev)
1082 struct dwc3 *dwc = platform_get_drvdata(pdev);
1083 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085 pm_runtime_get_sync(&pdev->dev);
1087 * restore res->start back to its original value so that, in case the
1088 * probe is deferred, we don't end up getting error in request the
1089 * memory region the next time probe is called.
1091 res->start -= DWC3_GLOBALS_REGS_START;
1093 dwc3_debugfs_exit(dwc);
1094 dwc3_core_exit_mode(dwc);
1096 dwc3_core_exit(dwc);
1097 dwc3_ulpi_exit(dwc);
1099 pm_runtime_put_sync(&pdev->dev);
1100 pm_runtime_allow(&pdev->dev);
1101 pm_runtime_disable(&pdev->dev);
1103 dwc3_free_event_buffers(dwc);
1104 dwc3_free_scratch_buffers(dwc);
1110 static int dwc3_suspend_common(struct dwc3 *dwc)
1112 unsigned long flags;
1114 switch (dwc->dr_mode) {
1115 case USB_DR_MODE_PERIPHERAL:
1116 case USB_DR_MODE_OTG:
1117 spin_lock_irqsave(&dwc->lock, flags);
1118 dwc3_gadget_suspend(dwc);
1119 spin_unlock_irqrestore(&dwc->lock, flags);
1121 case USB_DR_MODE_HOST:
1127 dwc3_core_exit(dwc);
1132 static int dwc3_resume_common(struct dwc3 *dwc)
1134 unsigned long flags;
1137 ret = dwc3_core_init(dwc);
1141 switch (dwc->dr_mode) {
1142 case USB_DR_MODE_PERIPHERAL:
1143 case USB_DR_MODE_OTG:
1144 spin_lock_irqsave(&dwc->lock, flags);
1145 dwc3_gadget_resume(dwc);
1146 spin_unlock_irqrestore(&dwc->lock, flags);
1148 case USB_DR_MODE_HOST:
1157 static int dwc3_runtime_checks(struct dwc3 *dwc)
1159 switch (dwc->dr_mode) {
1160 case USB_DR_MODE_PERIPHERAL:
1161 case USB_DR_MODE_OTG:
1165 case USB_DR_MODE_HOST:
1174 static int dwc3_runtime_suspend(struct device *dev)
1176 struct dwc3 *dwc = dev_get_drvdata(dev);
1179 if (dwc3_runtime_checks(dwc))
1182 ret = dwc3_suspend_common(dwc);
1186 device_init_wakeup(dev, true);
1191 static int dwc3_runtime_resume(struct device *dev)
1193 struct dwc3 *dwc = dev_get_drvdata(dev);
1196 device_init_wakeup(dev, false);
1198 ret = dwc3_resume_common(dwc);
1202 switch (dwc->dr_mode) {
1203 case USB_DR_MODE_PERIPHERAL:
1204 case USB_DR_MODE_OTG:
1205 dwc3_gadget_process_pending_events(dwc);
1207 case USB_DR_MODE_HOST:
1213 pm_runtime_mark_last_busy(dev);
1218 static int dwc3_runtime_idle(struct device *dev)
1220 struct dwc3 *dwc = dev_get_drvdata(dev);
1222 switch (dwc->dr_mode) {
1223 case USB_DR_MODE_PERIPHERAL:
1224 case USB_DR_MODE_OTG:
1225 if (dwc3_runtime_checks(dwc))
1228 case USB_DR_MODE_HOST:
1234 pm_runtime_mark_last_busy(dev);
1235 pm_runtime_autosuspend(dev);
1239 #endif /* CONFIG_PM */
1241 #ifdef CONFIG_PM_SLEEP
1242 static int dwc3_suspend(struct device *dev)
1244 struct dwc3 *dwc = dev_get_drvdata(dev);
1247 ret = dwc3_suspend_common(dwc);
1251 pinctrl_pm_select_sleep_state(dev);
1256 static int dwc3_resume(struct device *dev)
1258 struct dwc3 *dwc = dev_get_drvdata(dev);
1261 pinctrl_pm_select_default_state(dev);
1263 ret = dwc3_resume_common(dwc);
1267 pm_runtime_disable(dev);
1268 pm_runtime_set_active(dev);
1269 pm_runtime_enable(dev);
1273 #endif /* CONFIG_PM_SLEEP */
1275 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1276 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1277 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1282 static const struct of_device_id of_dwc3_match[] = {
1284 .compatible = "snps,dwc3"
1287 .compatible = "synopsys,dwc3"
1291 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1296 #define ACPI_ID_INTEL_BSW "808622B7"
1298 static const struct acpi_device_id dwc3_acpi_match[] = {
1299 { ACPI_ID_INTEL_BSW, 0 },
1302 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1305 static struct platform_driver dwc3_driver = {
1306 .probe = dwc3_probe,
1307 .remove = dwc3_remove,
1310 .of_match_table = of_match_ptr(of_dwc3_match),
1311 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1312 .pm = &dwc3_dev_pm_ops,
1316 module_platform_driver(dwc3_driver);
1318 MODULE_ALIAS("platform:dwc3");
1319 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1320 MODULE_LICENSE("GPL v2");
1321 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");