2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
44 #include "platform_data.h"
51 /* -------------------------------------------------------------------------- */
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
64 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
65 * @dwc: pointer to our context structure
67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
72 /* Before Resetting PHY, put Core in Reset */
73 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
74 reg |= DWC3_GCTL_CORESOFTRESET;
75 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
77 /* Assert USB3 PHY reset */
78 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
79 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
80 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
82 /* Assert USB2 PHY reset */
83 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
84 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
85 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
87 usb_phy_init(dwc->usb2_phy);
88 usb_phy_init(dwc->usb3_phy);
89 ret = phy_init(dwc->usb2_generic_phy);
93 ret = phy_init(dwc->usb3_generic_phy);
95 phy_exit(dwc->usb2_generic_phy);
100 /* Clear USB3 PHY reset */
101 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
102 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
103 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
105 /* Clear USB2 PHY reset */
106 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
107 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
108 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
112 /* After PHYs are stable we can take Core out of reset state */
113 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
114 reg &= ~DWC3_GCTL_CORESOFTRESET;
115 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
121 * dwc3_soft_reset - Issue soft reset
122 * @dwc: Pointer to our controller context structure
124 static int dwc3_soft_reset(struct dwc3 *dwc)
126 unsigned long timeout;
129 timeout = jiffies + msecs_to_jiffies(500);
130 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
132 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
133 if (!(reg & DWC3_DCTL_CSFTRST))
136 if (time_after(jiffies, timeout)) {
137 dev_err(dwc->dev, "Reset Timed Out\n");
148 * dwc3_frame_length_adjustment - Adjusts frame length if required
149 * @dwc3: Pointer to our controller context structure
150 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
157 if (dwc->revision < DWC3_REVISION_250A)
163 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
164 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
165 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
166 "request value same as default, ignoring\n")) {
167 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
168 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
169 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
174 * dwc3_free_one_event_buffer - Frees one event buffer
175 * @dwc: Pointer to our controller context structure
176 * @evt: Pointer to event buffer to be freed
178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
179 struct dwc3_event_buffer *evt)
181 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
185 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
186 * @dwc: Pointer to our controller context structure
187 * @length: size of the event buffer
189 * Returns a pointer to the allocated event buffer structure on success
190 * otherwise ERR_PTR(errno).
192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
195 struct dwc3_event_buffer *evt;
197 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
199 return ERR_PTR(-ENOMEM);
202 evt->length = length;
203 evt->buf = dma_alloc_coherent(dwc->dev, length,
204 &evt->dma, GFP_KERNEL);
206 return ERR_PTR(-ENOMEM);
212 * dwc3_free_event_buffers - frees all allocated event buffers
213 * @dwc: Pointer to our controller context structure
215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
217 struct dwc3_event_buffer *evt;
220 for (i = 0; i < dwc->num_event_buffers; i++) {
221 evt = dwc->ev_buffs[i];
223 dwc3_free_one_event_buffer(dwc, evt);
228 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
229 * @dwc: pointer to our controller context structure
230 * @length: size of event buffer
232 * Returns 0 on success otherwise negative errno. In the error case, dwc
233 * may contain some buffers allocated but not all which were requested.
235 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
240 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
241 dwc->num_event_buffers = num;
243 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
248 for (i = 0; i < num; i++) {
249 struct dwc3_event_buffer *evt;
251 evt = dwc3_alloc_one_event_buffer(dwc, length);
253 dev_err(dwc->dev, "can't allocate event buffer\n");
256 dwc->ev_buffs[i] = evt;
263 * dwc3_event_buffers_setup - setup our allocated event buffers
264 * @dwc: pointer to our controller context structure
266 * Returns 0 on success otherwise negative errno.
268 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
270 struct dwc3_event_buffer *evt;
273 for (n = 0; n < dwc->num_event_buffers; n++) {
274 evt = dwc->ev_buffs[n];
275 dwc3_trace(trace_dwc3_core,
276 "Event buf %p dma %08llx length %d\n",
277 evt->buf, (unsigned long long) evt->dma,
282 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
283 lower_32_bits(evt->dma));
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
285 upper_32_bits(evt->dma));
286 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
287 DWC3_GEVNTSIZ_SIZE(evt->length));
288 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
294 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
296 struct dwc3_event_buffer *evt;
299 for (n = 0; n < dwc->num_event_buffers; n++) {
300 evt = dwc->ev_buffs[n];
304 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
305 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
306 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
307 | DWC3_GEVNTSIZ_SIZE(0));
308 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
312 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
314 if (!dwc->has_hibernation)
317 if (!dwc->nr_scratch)
320 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
321 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
322 if (!dwc->scratchbuf)
328 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
330 dma_addr_t scratch_addr;
334 if (!dwc->has_hibernation)
337 if (!dwc->nr_scratch)
340 /* should never fall here */
341 if (!WARN_ON(dwc->scratchbuf))
344 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
345 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
347 if (dma_mapping_error(dwc->dev, scratch_addr)) {
348 dev_err(dwc->dev, "failed to map scratch buffer\n");
353 dwc->scratch_addr = scratch_addr;
355 param = lower_32_bits(scratch_addr);
357 ret = dwc3_send_gadget_generic_command(dwc,
358 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
362 param = upper_32_bits(scratch_addr);
364 ret = dwc3_send_gadget_generic_command(dwc,
365 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
372 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
373 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
379 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
381 if (!dwc->has_hibernation)
384 if (!dwc->nr_scratch)
387 /* should never fall here */
388 if (!WARN_ON(dwc->scratchbuf))
391 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
392 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
393 kfree(dwc->scratchbuf);
396 static void dwc3_core_num_eps(struct dwc3 *dwc)
398 struct dwc3_hwparams *parms = &dwc->hwparams;
400 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
401 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
403 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
404 dwc->num_in_eps, dwc->num_out_eps);
407 static void dwc3_cache_hwparams(struct dwc3 *dwc)
409 struct dwc3_hwparams *parms = &dwc->hwparams;
411 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
412 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
413 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
414 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
415 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
416 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
417 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
418 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
419 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
423 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
424 * @dwc: Pointer to our controller context structure
426 * Returns 0 on success. The USB PHY interfaces are configured but not
427 * initialized. The PHY interfaces and the PHYs get initialized together with
428 * the core in dwc3_core_init.
430 static int dwc3_phy_setup(struct dwc3 *dwc)
436 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
439 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
440 * to '0' during coreConsultant configuration. So default value
441 * will be '0' when the core is reset. Application needs to set it
442 * to '1' after the core initialization is completed.
444 if (dwc->revision > DWC3_REVISION_194A)
445 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
447 if (dwc->u2ss_inp3_quirk)
448 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
450 if (dwc->req_p1p2p3_quirk)
451 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
453 if (dwc->del_p1p2p3_quirk)
454 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
456 if (dwc->del_phy_power_chg_quirk)
457 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
459 if (dwc->lfps_filter_quirk)
460 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
462 if (dwc->rx_detect_poll_quirk)
463 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
465 if (dwc->tx_de_emphasis_quirk)
466 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
468 if (dwc->dis_u3_susphy_quirk)
469 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
471 if (dwc->dis_del_phy_power_chg_quirk)
472 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
474 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
476 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
478 /* Select the HS PHY interface */
479 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
480 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
481 if (dwc->hsphy_interface &&
482 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
483 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
485 } else if (dwc->hsphy_interface &&
486 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
487 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
488 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
490 /* Relying on default value. */
491 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
495 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
496 /* Making sure the interface and PHY are operational */
497 ret = dwc3_soft_reset(dwc);
503 ret = dwc3_ulpi_init(dwc);
512 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
513 * '0' during coreConsultant configuration. So default value will
514 * be '0' when the core is reset. Application needs to set it to
515 * '1' after the core initialization is completed.
517 if (dwc->revision > DWC3_REVISION_194A)
518 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
520 if (dwc->dis_u2_susphy_quirk)
521 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
523 if (dwc->dis_enblslpm_quirk)
524 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
526 if (dwc->dis_u2_freeclk_exists_quirk)
527 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
529 if (dwc->phyif_utmi_16_bits)
530 reg |= DWC3_GUSB2PHYCFG_PHYIF;
532 usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ?
533 USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
535 reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
536 reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT);
538 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
544 * dwc3_core_init - Low-level initialization of DWC3 Core
545 * @dwc: Pointer to our controller context structure
547 * Returns 0 on success otherwise negative errno.
549 static int dwc3_core_init(struct dwc3 *dwc)
551 u32 hwparams4 = dwc->hwparams.hwparams4;
555 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
556 /* This should read as U3 followed by revision number */
557 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
558 /* Detected DWC_usb3 IP */
560 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
561 /* Detected DWC_usb31 IP */
562 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
563 dwc->revision |= DWC3_REVISION_IS_DWC31;
565 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
571 * Write Linux Version Code to our GUID register so it's easy to figure
572 * out which kernel version a bug was found.
574 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
576 /* Handle USB2.0-only core configuration */
577 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
578 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
579 if (dwc->maximum_speed == USB_SPEED_SUPER)
580 dwc->maximum_speed = USB_SPEED_HIGH;
583 /* issue device SoftReset too */
584 ret = dwc3_soft_reset(dwc);
588 ret = dwc3_core_soft_reset(dwc);
592 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
593 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
595 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
596 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
598 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
599 * issue which would cause xHCI compliance tests to fail.
601 * Because of that we cannot enable clock gating on such
606 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
609 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
610 dwc->dr_mode == USB_DR_MODE_OTG) &&
611 (dwc->revision >= DWC3_REVISION_210A &&
612 dwc->revision <= DWC3_REVISION_250A))
613 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
615 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
617 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
618 /* enable hibernation here */
619 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
622 * REVISIT Enabling this bit so that host-mode hibernation
623 * will work. Device-mode hibernation is not yet implemented.
625 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
628 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
631 /* check if current dwc3 is on simulation board */
632 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
633 dwc3_trace(trace_dwc3_core,
634 "running on FPGA platform\n");
638 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
639 "disable_scramble cannot be used on non-FPGA builds\n");
641 if (dwc->disable_scramble_quirk && dwc->is_fpga)
642 reg |= DWC3_GCTL_DISSCRAMBLE;
644 reg &= ~DWC3_GCTL_DISSCRAMBLE;
646 if (dwc->u2exit_lfps_quirk)
647 reg |= DWC3_GCTL_U2EXIT_LFPS;
650 * WORKAROUND: DWC3 revisions <1.90a have a bug
651 * where the device can fail to connect at SuperSpeed
652 * and falls back to high-speed mode which causes
653 * the device to enter a Connect/Disconnect loop
655 if (dwc->revision < DWC3_REVISION_190A)
656 reg |= DWC3_GCTL_U2RSTECN;
658 dwc3_core_num_eps(dwc);
660 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
662 ret = dwc3_alloc_scratch_buffers(dwc);
666 ret = dwc3_setup_scratch_buffers(dwc);
673 dwc3_free_scratch_buffers(dwc);
676 usb_phy_shutdown(dwc->usb2_phy);
677 usb_phy_shutdown(dwc->usb3_phy);
678 phy_exit(dwc->usb2_generic_phy);
679 phy_exit(dwc->usb3_generic_phy);
685 static void dwc3_core_exit(struct dwc3 *dwc)
687 dwc3_free_scratch_buffers(dwc);
688 usb_phy_shutdown(dwc->usb2_phy);
689 usb_phy_shutdown(dwc->usb3_phy);
690 phy_exit(dwc->usb2_generic_phy);
691 phy_exit(dwc->usb3_generic_phy);
694 static int dwc3_core_get_phy(struct dwc3 *dwc)
696 struct device *dev = dwc->dev;
697 struct device_node *node = dev->of_node;
701 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
702 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
704 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
705 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
708 if (IS_ERR(dwc->usb2_phy)) {
709 ret = PTR_ERR(dwc->usb2_phy);
710 if (ret == -ENXIO || ret == -ENODEV) {
711 dwc->usb2_phy = NULL;
712 } else if (ret == -EPROBE_DEFER) {
715 dev_err(dev, "no usb2 phy configured\n");
720 if (IS_ERR(dwc->usb3_phy)) {
721 ret = PTR_ERR(dwc->usb3_phy);
722 if (ret == -ENXIO || ret == -ENODEV) {
723 dwc->usb3_phy = NULL;
724 } else if (ret == -EPROBE_DEFER) {
727 dev_err(dev, "no usb3 phy configured\n");
732 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
733 if (IS_ERR(dwc->usb2_generic_phy)) {
734 ret = PTR_ERR(dwc->usb2_generic_phy);
735 if (ret == -ENOSYS || ret == -ENODEV) {
736 dwc->usb2_generic_phy = NULL;
737 } else if (ret == -EPROBE_DEFER) {
740 dev_err(dev, "no usb2 phy configured\n");
745 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
746 if (IS_ERR(dwc->usb3_generic_phy)) {
747 ret = PTR_ERR(dwc->usb3_generic_phy);
748 if (ret == -ENOSYS || ret == -ENODEV) {
749 dwc->usb3_generic_phy = NULL;
750 } else if (ret == -EPROBE_DEFER) {
753 dev_err(dev, "no usb3 phy configured\n");
761 static int dwc3_core_init_mode(struct dwc3 *dwc)
763 struct device *dev = dwc->dev;
766 switch (dwc->dr_mode) {
767 case USB_DR_MODE_PERIPHERAL:
768 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
769 ret = dwc3_gadget_init(dwc);
771 dev_err(dev, "failed to initialize gadget\n");
775 case USB_DR_MODE_HOST:
776 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
777 ret = dwc3_host_init(dwc);
779 dev_err(dev, "failed to initialize host\n");
783 case USB_DR_MODE_OTG:
784 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
785 ret = dwc3_host_init(dwc);
787 dev_err(dev, "failed to initialize host\n");
791 ret = dwc3_gadget_init(dwc);
793 dev_err(dev, "failed to initialize gadget\n");
798 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
805 static void dwc3_core_exit_mode(struct dwc3 *dwc)
807 switch (dwc->dr_mode) {
808 case USB_DR_MODE_PERIPHERAL:
809 dwc3_gadget_exit(dwc);
811 case USB_DR_MODE_HOST:
814 case USB_DR_MODE_OTG:
816 dwc3_gadget_exit(dwc);
824 #define DWC3_ALIGN_MASK (16 - 1)
826 static int dwc3_probe(struct platform_device *pdev)
828 struct device *dev = &pdev->dev;
829 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
830 struct resource *res;
832 u8 lpm_nyet_threshold;
842 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
846 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
850 /* Try to set 64-bit DMA first */
851 if (!pdev->dev.dma_mask)
852 /* Platform did not initialize dma_mask */
853 ret = dma_coerce_mask_and_coherent(&pdev->dev,
856 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
858 /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
860 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
865 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
867 dev_err(dev, "missing IRQ\n");
870 dwc->xhci_resources[1].start = res->start;
871 dwc->xhci_resources[1].end = res->end;
872 dwc->xhci_resources[1].flags = res->flags;
873 dwc->xhci_resources[1].name = res->name;
875 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
877 dev_err(dev, "missing memory resource\n");
881 dwc->xhci_resources[0].start = res->start;
882 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
884 dwc->xhci_resources[0].flags = res->flags;
885 dwc->xhci_resources[0].name = res->name;
887 res->start += DWC3_GLOBALS_REGS_START;
890 * Request memory region but exclude xHCI regs,
891 * since it will be requested by the xhci-plat driver.
893 regs = devm_ioremap_resource(dev, res);
900 dwc->regs_size = resource_size(res);
902 /* default to highest possible threshold */
903 lpm_nyet_threshold = 0xff;
905 /* default to -3.5dB de-emphasis */
909 * default to assert utmi_sleep_n and use maximum allowed HIRD
910 * threshold value of 0b1100
914 dwc->maximum_speed = usb_get_maximum_speed(dev);
915 dwc->dr_mode = usb_get_dr_mode(dev);
917 dwc->has_lpm_erratum = device_property_read_bool(dev,
918 "snps,has-lpm-erratum");
919 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
920 &lpm_nyet_threshold);
921 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
922 "snps,is-utmi-l1-suspend");
923 device_property_read_u8(dev, "snps,hird-threshold",
925 dwc->usb3_lpm_capable = device_property_read_bool(dev,
926 "snps,usb3_lpm_capable");
928 dwc->needs_fifo_resize = device_property_read_bool(dev,
931 dwc->disable_scramble_quirk = device_property_read_bool(dev,
932 "snps,disable_scramble_quirk");
933 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
934 "snps,u2exit_lfps_quirk");
935 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
936 "snps,u2ss_inp3_quirk");
937 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
938 "snps,req_p1p2p3_quirk");
939 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
940 "snps,del_p1p2p3_quirk");
941 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
942 "snps,del_phy_power_chg_quirk");
943 dwc->lfps_filter_quirk = device_property_read_bool(dev,
944 "snps,lfps_filter_quirk");
945 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
946 "snps,rx_detect_poll_quirk");
947 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
948 "snps,dis_u3_susphy_quirk");
949 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
950 "snps,dis_u2_susphy_quirk");
951 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
952 "snps,dis_enblslpm_quirk");
953 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
954 "snps,dis_u2_freeclk_exists_quirk");
955 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
956 "snps,dis_del_phy_power_chg_quirk");
957 dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
958 "snps,phyif_utmi_16_bits");
960 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
961 "snps,tx_de_emphasis_quirk");
962 device_property_read_u8(dev, "snps,tx_de_emphasis",
964 device_property_read_string(dev, "snps,hsphy_interface",
965 &dwc->hsphy_interface);
966 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
970 dwc->maximum_speed = pdata->maximum_speed;
971 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
972 if (pdata->lpm_nyet_threshold)
973 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
974 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
975 if (pdata->hird_threshold)
976 hird_threshold = pdata->hird_threshold;
978 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
979 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
980 dwc->dr_mode = pdata->dr_mode;
982 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
983 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
984 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
985 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
986 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
987 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
988 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
989 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
990 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
991 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
992 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
993 dwc->dis_u2_freeclk_exists_quirk =
994 pdata->dis_u2_freeclk_exists_quirk;
995 dwc->dis_del_phy_power_chg_quirk =
996 pdata->dis_del_phy_power_chg_quirk;
997 dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
999 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1000 if (pdata->tx_de_emphasis)
1001 tx_de_emphasis = pdata->tx_de_emphasis;
1003 dwc->hsphy_interface = pdata->hsphy_interface;
1004 fladj = pdata->fladj_value;
1007 /* default to superspeed if no maximum_speed passed */
1008 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1009 dwc->maximum_speed = USB_SPEED_SUPER;
1011 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1012 dwc->tx_de_emphasis = tx_de_emphasis;
1014 dwc->hird_threshold = hird_threshold
1015 | (dwc->is_utmi_l1_suspend << 4);
1017 platform_set_drvdata(pdev, dwc);
1018 dwc3_cache_hwparams(dwc);
1020 ret = dwc3_phy_setup(dwc);
1024 ret = dwc3_core_get_phy(dwc);
1028 spin_lock_init(&dwc->lock);
1030 if (!dev->dma_mask) {
1031 dev->dma_mask = dev->parent->dma_mask;
1032 dev->dma_parms = dev->parent->dma_parms;
1033 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1036 pm_runtime_enable(dev);
1037 pm_runtime_get_sync(dev);
1038 pm_runtime_forbid(dev);
1040 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1042 dev_err(dwc->dev, "failed to allocate event buffers\n");
1047 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1048 dwc->dr_mode = USB_DR_MODE_HOST;
1049 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1050 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1052 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1053 dwc->dr_mode = USB_DR_MODE_OTG;
1055 ret = dwc3_core_init(dwc);
1057 dev_err(dev, "failed to initialize core\n");
1061 /* Adjust Frame Length */
1062 dwc3_frame_length_adjustment(dwc, fladj);
1064 usb_phy_set_suspend(dwc->usb2_phy, 0);
1065 usb_phy_set_suspend(dwc->usb3_phy, 0);
1066 ret = phy_power_on(dwc->usb2_generic_phy);
1070 ret = phy_power_on(dwc->usb3_generic_phy);
1074 ret = dwc3_event_buffers_setup(dwc);
1076 dev_err(dwc->dev, "failed to setup event buffers\n");
1080 ret = dwc3_core_init_mode(dwc);
1084 ret = dwc3_debugfs_init(dwc);
1086 dev_err(dev, "failed to initialize debugfs\n");
1090 pm_runtime_allow(dev);
1095 dwc3_core_exit_mode(dwc);
1098 dwc3_event_buffers_cleanup(dwc);
1101 phy_power_off(dwc->usb3_generic_phy);
1104 phy_power_off(dwc->usb2_generic_phy);
1107 usb_phy_set_suspend(dwc->usb2_phy, 1);
1108 usb_phy_set_suspend(dwc->usb3_phy, 1);
1109 dwc3_core_exit(dwc);
1112 dwc3_free_event_buffers(dwc);
1113 dwc3_ulpi_exit(dwc);
1117 * restore res->start back to its original value so that, in case the
1118 * probe is deferred, we don't end up getting error in request the
1119 * memory region the next time probe is called.
1121 res->start -= DWC3_GLOBALS_REGS_START;
1126 static int dwc3_remove(struct platform_device *pdev)
1128 struct dwc3 *dwc = platform_get_drvdata(pdev);
1129 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132 * restore res->start back to its original value so that, in case the
1133 * probe is deferred, we don't end up getting error in request the
1134 * memory region the next time probe is called.
1136 res->start -= DWC3_GLOBALS_REGS_START;
1138 dwc3_debugfs_exit(dwc);
1139 dwc3_core_exit_mode(dwc);
1140 dwc3_event_buffers_cleanup(dwc);
1141 dwc3_free_event_buffers(dwc);
1143 usb_phy_set_suspend(dwc->usb2_phy, 1);
1144 usb_phy_set_suspend(dwc->usb3_phy, 1);
1145 phy_power_off(dwc->usb2_generic_phy);
1146 phy_power_off(dwc->usb3_generic_phy);
1148 dwc3_core_exit(dwc);
1149 dwc3_ulpi_exit(dwc);
1151 pm_runtime_put_sync(&pdev->dev);
1152 pm_runtime_disable(&pdev->dev);
1157 #ifdef CONFIG_PM_SLEEP
1158 static int dwc3_suspend(struct device *dev)
1160 struct dwc3 *dwc = dev_get_drvdata(dev);
1161 unsigned long flags;
1163 spin_lock_irqsave(&dwc->lock, flags);
1165 switch (dwc->dr_mode) {
1166 case USB_DR_MODE_PERIPHERAL:
1167 case USB_DR_MODE_OTG:
1168 dwc3_gadget_suspend(dwc);
1170 case USB_DR_MODE_HOST:
1172 dwc3_event_buffers_cleanup(dwc);
1176 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1177 spin_unlock_irqrestore(&dwc->lock, flags);
1179 usb_phy_shutdown(dwc->usb3_phy);
1180 usb_phy_shutdown(dwc->usb2_phy);
1181 phy_exit(dwc->usb2_generic_phy);
1182 phy_exit(dwc->usb3_generic_phy);
1184 pinctrl_pm_select_sleep_state(dev);
1189 static int dwc3_resume(struct device *dev)
1191 struct dwc3 *dwc = dev_get_drvdata(dev);
1192 unsigned long flags;
1195 pinctrl_pm_select_default_state(dev);
1197 usb_phy_init(dwc->usb3_phy);
1198 usb_phy_init(dwc->usb2_phy);
1199 ret = phy_init(dwc->usb2_generic_phy);
1203 ret = phy_init(dwc->usb3_generic_phy);
1205 goto err_usb2phy_init;
1207 spin_lock_irqsave(&dwc->lock, flags);
1209 dwc3_event_buffers_setup(dwc);
1210 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1212 switch (dwc->dr_mode) {
1213 case USB_DR_MODE_PERIPHERAL:
1214 case USB_DR_MODE_OTG:
1215 dwc3_gadget_resume(dwc);
1217 case USB_DR_MODE_HOST:
1223 spin_unlock_irqrestore(&dwc->lock, flags);
1225 pm_runtime_disable(dev);
1226 pm_runtime_set_active(dev);
1227 pm_runtime_enable(dev);
1232 phy_exit(dwc->usb2_generic_phy);
1237 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1238 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1241 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1243 #define DWC3_PM_OPS NULL
1247 static const struct of_device_id of_dwc3_match[] = {
1249 .compatible = "snps,dwc3"
1252 .compatible = "synopsys,dwc3"
1256 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1261 #define ACPI_ID_INTEL_BSW "808622B7"
1263 static const struct acpi_device_id dwc3_acpi_match[] = {
1264 { ACPI_ID_INTEL_BSW, 0 },
1267 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1270 static struct platform_driver dwc3_driver = {
1271 .probe = dwc3_probe,
1272 .remove = dwc3_remove,
1275 .of_match_table = of_match_ptr(of_dwc3_match),
1276 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1281 module_platform_driver(dwc3_driver);
1283 MODULE_ALIAS("platform:dwc3");
1284 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1285 MODULE_LICENSE("GPL v2");
1286 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");