2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
28 #include <linux/debugfs.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/otg.h>
33 #include <linux/ulpi/interface.h>
35 #include <linux/phy/phy.h>
37 #define DWC3_MSG_MAX 500
39 /* Global constants */
40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
41 #define DWC3_EP0_BOUNCE_SIZE 512
42 #define DWC3_ENDPOINTS_NUM 32
43 #define DWC3_XHCI_RESOURCES_NUM 2
45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
46 #define DWC3_EVENT_SIZE 4 /* bytes */
47 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
48 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
49 #define DWC3_EVENT_TYPE_MASK 0xfe
51 #define DWC3_EVENT_TYPE_DEV 0
52 #define DWC3_EVENT_TYPE_CARKIT 3
53 #define DWC3_EVENT_TYPE_I2C 4
55 #define DWC3_DEVICE_EVENT_DISCONNECT 0
56 #define DWC3_DEVICE_EVENT_RESET 1
57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59 #define DWC3_DEVICE_EVENT_WAKEUP 4
60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
61 #define DWC3_DEVICE_EVENT_EOPF 6
62 #define DWC3_DEVICE_EVENT_SOF 7
63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
65 #define DWC3_DEVICE_EVENT_OVERFLOW 11
67 #define DWC3_GEVNTCOUNT_MASK 0xfffc
68 #define DWC3_GSNPSID_MASK 0xffff0000
69 #define DWC3_GSNPSREV_MASK 0xffff
71 /* DWC3 registers memory space boundries */
72 #define DWC3_XHCI_REGS_START 0x0
73 #define DWC3_XHCI_REGS_END 0x7fff
74 #define DWC3_GLOBALS_REGS_START 0xc100
75 #define DWC3_GLOBALS_REGS_END 0xc6ff
76 #define DWC3_DEVICE_REGS_START 0xc700
77 #define DWC3_DEVICE_REGS_END 0xcbff
78 #define DWC3_OTG_REGS_START 0xcc00
79 #define DWC3_OTG_REGS_END 0xccff
81 /* Global Registers */
82 #define DWC3_GSBUSCFG0 0xc100
83 #define DWC3_GSBUSCFG1 0xc104
84 #define DWC3_GTXTHRCFG 0xc108
85 #define DWC3_GRXTHRCFG 0xc10c
86 #define DWC3_GCTL 0xc110
87 #define DWC3_GEVTEN 0xc114
88 #define DWC3_GSTS 0xc118
89 #define DWC3_GUCTL1 0xc11c
90 #define DWC3_GSNPSID 0xc120
91 #define DWC3_GGPIO 0xc124
92 #define DWC3_GUID 0xc128
93 #define DWC3_GUCTL 0xc12c
94 #define DWC3_GBUSERRADDR0 0xc130
95 #define DWC3_GBUSERRADDR1 0xc134
96 #define DWC3_GPRTBIMAP0 0xc138
97 #define DWC3_GPRTBIMAP1 0xc13c
98 #define DWC3_GHWPARAMS0 0xc140
99 #define DWC3_GHWPARAMS1 0xc144
100 #define DWC3_GHWPARAMS2 0xc148
101 #define DWC3_GHWPARAMS3 0xc14c
102 #define DWC3_GHWPARAMS4 0xc150
103 #define DWC3_GHWPARAMS5 0xc154
104 #define DWC3_GHWPARAMS6 0xc158
105 #define DWC3_GHWPARAMS7 0xc15c
106 #define DWC3_GDBGFIFOSPACE 0xc160
107 #define DWC3_GDBGLTSSM 0xc164
108 #define DWC3_GPRTBIMAP_HS0 0xc180
109 #define DWC3_GPRTBIMAP_HS1 0xc184
110 #define DWC3_GPRTBIMAP_FS0 0xc188
111 #define DWC3_GPRTBIMAP_FS1 0xc18c
113 #define DWC3_VER_NUMBER 0xc1a0
114 #define DWC3_VER_TYPE 0xc1a4
116 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
117 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
119 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
121 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
123 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
124 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
126 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
127 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
128 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
129 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
131 #define DWC3_GHWPARAMS8 0xc600
132 #define DWC3_GFLADJ 0xc630
134 /* Device Registers */
135 #define DWC3_DCFG 0xc700
136 #define DWC3_DCTL 0xc704
137 #define DWC3_DEVTEN 0xc708
138 #define DWC3_DSTS 0xc70c
139 #define DWC3_DGCMDPAR 0xc710
140 #define DWC3_DGCMD 0xc714
141 #define DWC3_DALEPENA 0xc720
142 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
143 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
144 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
145 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
148 #define DWC3_OCFG 0xcc00
149 #define DWC3_OCTL 0xcc04
150 #define DWC3_OEVT 0xcc08
151 #define DWC3_OEVTEN 0xcc0C
152 #define DWC3_OSTS 0xcc10
156 /* Global Configuration Register */
157 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
158 #define DWC3_GCTL_U2RSTECN (1 << 16)
159 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
160 #define DWC3_GCTL_CLK_BUS (0)
161 #define DWC3_GCTL_CLK_PIPE (1)
162 #define DWC3_GCTL_CLK_PIPEHALF (2)
163 #define DWC3_GCTL_CLK_MASK (3)
165 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
166 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
167 #define DWC3_GCTL_PRTCAP_HOST 1
168 #define DWC3_GCTL_PRTCAP_DEVICE 2
169 #define DWC3_GCTL_PRTCAP_OTG 3
171 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
172 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
173 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
174 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
175 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
176 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
177 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
178 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
180 /* Global USB2 PHY Configuration Register */
181 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
182 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
183 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
184 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
186 /* Global USB2 PHY Vendor Control Register */
187 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
188 #define DWC3_GUSB2PHYACC_BUSY (1 << 23)
189 #define DWC3_GUSB2PHYACC_WRITE (1 << 22)
190 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
191 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
192 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
194 /* Global USB3 PIPE Control Register */
195 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
196 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
197 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
198 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
199 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
200 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
201 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
202 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
203 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
204 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
205 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
206 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
208 /* Global TX Fifo Size Register */
209 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
210 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
212 /* Global Event Size Registers */
213 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
214 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
216 /* Global HWPARAMS1 Register */
217 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
218 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
219 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
220 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
221 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
222 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
224 /* Global HWPARAMS3 Register */
225 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
226 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
227 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
228 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
229 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
230 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
231 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
232 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
233 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
234 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
235 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
237 /* Global HWPARAMS4 Register */
238 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
239 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
241 /* Global HWPARAMS6 Register */
242 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
244 /* Global Frame Length Adjustment Register */
245 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
246 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
248 /* Device Configuration Register */
249 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
250 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
252 #define DWC3_DCFG_SPEED_MASK (7 << 0)
253 #define DWC3_DCFG_SUPERSPEED (4 << 0)
254 #define DWC3_DCFG_HIGHSPEED (0 << 0)
255 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
256 #define DWC3_DCFG_LOWSPEED (2 << 0)
257 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
259 #define DWC3_DCFG_LPM_CAP (1 << 22)
261 /* Device Control Register */
262 #define DWC3_DCTL_RUN_STOP (1 << 31)
263 #define DWC3_DCTL_CSFTRST (1 << 30)
264 #define DWC3_DCTL_LSFTRST (1 << 29)
266 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
267 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
269 #define DWC3_DCTL_APPL1RES (1 << 23)
271 /* These apply for core versions 1.87a and earlier */
272 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
273 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
274 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
275 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
276 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
277 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
278 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
280 /* These apply for core versions 1.94a and later */
281 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
282 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
284 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
285 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
286 #define DWC3_DCTL_CRS (1 << 17)
287 #define DWC3_DCTL_CSS (1 << 16)
289 #define DWC3_DCTL_INITU2ENA (1 << 12)
290 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
291 #define DWC3_DCTL_INITU1ENA (1 << 10)
292 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
293 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
295 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
296 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
298 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
299 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
300 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
301 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
302 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
303 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
304 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
306 /* Device Event Enable Register */
307 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
308 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
309 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
310 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
311 #define DWC3_DEVTEN_SOFEN (1 << 7)
312 #define DWC3_DEVTEN_EOPFEN (1 << 6)
313 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
314 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
315 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
316 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
317 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
318 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
320 /* Device Status Register */
321 #define DWC3_DSTS_DCNRD (1 << 29)
323 /* This applies for core versions 1.87a and earlier */
324 #define DWC3_DSTS_PWRUPREQ (1 << 24)
326 /* These apply for core versions 1.94a and later */
327 #define DWC3_DSTS_RSS (1 << 25)
328 #define DWC3_DSTS_SSS (1 << 24)
330 #define DWC3_DSTS_COREIDLE (1 << 23)
331 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
333 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
334 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
336 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
338 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
339 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
341 #define DWC3_DSTS_CONNECTSPD (7 << 0)
343 #define DWC3_DSTS_SUPERSPEED (4 << 0)
344 #define DWC3_DSTS_HIGHSPEED (0 << 0)
345 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
346 #define DWC3_DSTS_LOWSPEED (2 << 0)
347 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
349 /* Device Generic Command Register */
350 #define DWC3_DGCMD_SET_LMP 0x01
351 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
352 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
354 /* These apply for core versions 1.94a and later */
355 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
356 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
358 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
359 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
360 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
361 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
363 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
364 #define DWC3_DGCMD_CMDACT (1 << 10)
365 #define DWC3_DGCMD_CMDIOC (1 << 8)
367 /* Device Generic Command Parameter Register */
368 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
369 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
370 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
371 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
372 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
373 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
375 /* Device Endpoint Command Register */
376 #define DWC3_DEPCMD_PARAM_SHIFT 16
377 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
378 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
379 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
380 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
381 #define DWC3_DEPCMD_CMDACT (1 << 10)
382 #define DWC3_DEPCMD_CMDIOC (1 << 8)
384 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
385 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
386 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
387 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
388 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
389 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
390 /* This applies for core versions 1.90a and earlier */
391 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
392 /* This applies for core versions 1.94a and later */
393 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
394 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
395 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
397 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
398 #define DWC3_DALEPENA_EP(n) (1 << n)
400 #define DWC3_DEPCMD_TYPE_CONTROL 0
401 #define DWC3_DEPCMD_TYPE_ISOC 1
402 #define DWC3_DEPCMD_TYPE_BULK 2
403 #define DWC3_DEPCMD_TYPE_INTR 3
410 * struct dwc3_event_buffer - Software event buffer representation
412 * @length: size of this buffer
413 * @lpos: event offset
414 * @count: cache of last read event count register
415 * @flags: flags related to this event buffer
417 * @dwc: pointer to DWC controller
419 struct dwc3_event_buffer {
426 #define DWC3_EVENT_PENDING BIT(0)
433 #define DWC3_EP_FLAG_STALLED (1 << 0)
434 #define DWC3_EP_FLAG_WEDGED (1 << 1)
436 #define DWC3_EP_DIRECTION_TX true
437 #define DWC3_EP_DIRECTION_RX false
439 #define DWC3_TRB_NUM 32
440 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
443 * struct dwc3_ep - device side endpoint representation
444 * @endpoint: usb endpoint
445 * @request_list: list of requests for this endpoint
446 * @req_queued: list of requests on this ep which have TRBs setup
447 * @trb_pool: array of transaction buffers
448 * @trb_pool_dma: dma address of @trb_pool
449 * @free_slot: next slot which is going to be used
450 * @busy_slot: first slot which is owned by HW
451 * @desc: usb_endpoint_descriptor pointer
452 * @dwc: pointer to DWC controller
453 * @saved_state: ep state saved during hibernation
454 * @flags: endpoint flags (wedged, stalled, ...)
455 * @number: endpoint number (1 - 15)
456 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
457 * @resource_index: Resource transfer index
458 * @interval: the interval on which the ISOC transfer is started
459 * @name: a human readable name e.g. ep1out-bulk
460 * @direction: true for TX, false for RX
461 * @stream_capable: true when streams are enabled
464 struct usb_ep endpoint;
465 struct list_head request_list;
466 struct list_head req_queued;
468 struct dwc3_trb *trb_pool;
469 dma_addr_t trb_pool_dma;
472 const struct usb_ss_ep_comp_descriptor *comp_desc;
477 #define DWC3_EP_ENABLED (1 << 0)
478 #define DWC3_EP_STALL (1 << 1)
479 #define DWC3_EP_WEDGE (1 << 2)
480 #define DWC3_EP_BUSY (1 << 4)
481 #define DWC3_EP_PENDING_REQUEST (1 << 5)
482 #define DWC3_EP_MISSED_ISOC (1 << 6)
484 /* This last one is specific to EP0 */
485 #define DWC3_EP0_DIR_IN (1 << 31)
494 unsigned direction:1;
495 unsigned stream_capable:1;
499 DWC3_PHY_UNKNOWN = 0,
505 DWC3_EP0_UNKNOWN = 0,
508 DWC3_EP0_NRDY_STATUS,
511 enum dwc3_ep0_state {
518 enum dwc3_link_state {
520 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
521 DWC3_LINK_STATE_U1 = 0x01,
522 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
523 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
524 DWC3_LINK_STATE_SS_DIS = 0x04,
525 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
526 DWC3_LINK_STATE_SS_INACT = 0x06,
527 DWC3_LINK_STATE_POLL = 0x07,
528 DWC3_LINK_STATE_RECOV = 0x08,
529 DWC3_LINK_STATE_HRESET = 0x09,
530 DWC3_LINK_STATE_CMPLY = 0x0a,
531 DWC3_LINK_STATE_LPBK = 0x0b,
532 DWC3_LINK_STATE_RESET = 0x0e,
533 DWC3_LINK_STATE_RESUME = 0x0f,
534 DWC3_LINK_STATE_MASK = 0x0f,
537 /* TRB Length, PCM and Status */
538 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
539 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
540 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
541 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
543 #define DWC3_TRBSTS_OK 0
544 #define DWC3_TRBSTS_MISSED_ISOC 1
545 #define DWC3_TRBSTS_SETUP_PENDING 2
546 #define DWC3_TRB_STS_XFER_IN_PROG 4
549 #define DWC3_TRB_CTRL_HWO (1 << 0)
550 #define DWC3_TRB_CTRL_LST (1 << 1)
551 #define DWC3_TRB_CTRL_CHN (1 << 2)
552 #define DWC3_TRB_CTRL_CSP (1 << 3)
553 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
554 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
555 #define DWC3_TRB_CTRL_IOC (1 << 11)
556 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
558 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
559 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
560 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
561 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
562 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
563 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
564 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
565 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
568 * struct dwc3_trb - transfer request block (hw format)
582 * dwc3_hwparams - copy of HWPARAMS registers
583 * @hwparams0 - GHWPARAMS0
584 * @hwparams1 - GHWPARAMS1
585 * @hwparams2 - GHWPARAMS2
586 * @hwparams3 - GHWPARAMS3
587 * @hwparams4 - GHWPARAMS4
588 * @hwparams5 - GHWPARAMS5
589 * @hwparams6 - GHWPARAMS6
590 * @hwparams7 - GHWPARAMS7
591 * @hwparams8 - GHWPARAMS8
593 struct dwc3_hwparams {
606 #define DWC3_MODE(n) ((n) & 0x7)
608 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
611 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
614 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
615 #define DWC3_NUM_EPS_MASK (0x3f << 12)
616 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
617 (DWC3_NUM_EPS_MASK)) >> 12)
618 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
619 (DWC3_NUM_IN_EPS_MASK)) >> 18)
622 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
624 struct dwc3_request {
625 struct usb_request request;
626 struct list_head list;
631 struct dwc3_trb *trb;
634 unsigned direction:1;
640 * struct dwc3_scratchpad_array - hibernation scratchpad array
641 * (format defined by hw)
643 struct dwc3_scratchpad_array {
644 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
648 * struct dwc3 - representation of our controller
649 * @ctrl_req: usb control request which is used for ep0
650 * @ep0_trb: trb which is used for the ctrl_req
651 * @ep0_bounce: bounce buffer for ep0
652 * @zlp_buf: used when request->zero is set
653 * @setup_buf: used while precessing STD USB requests
654 * @ctrl_req_addr: dma address of ctrl_req
655 * @ep0_trb: dma address of ep0_trb
656 * @ep0_usb_req: dummy req used while handling STD USB requests
657 * @ep0_bounce_addr: dma address of ep0_bounce
658 * @scratch_addr: dma address of scratchbuf
659 * @lock: for synchronizing
660 * @dev: pointer to our struct device
661 * @xhci: pointer to our xHCI child
662 * @event_buffer_list: a list of event buffers
663 * @gadget: device side representation of the peripheral controller
664 * @gadget_driver: pointer to the gadget driver
665 * @regs: base address for our registers
666 * @regs_size: address space size
667 * @nr_scratch: number of scratch buffers
668 * @num_event_buffers: calculated number of event buffers
669 * @u1u2: only used on revisions <1.83a for workaround
670 * @maximum_speed: maximum speed requested (mainly for testing purposes)
671 * @revision: revision register contents
672 * @dr_mode: requested mode of operation
673 * @usb2_phy: pointer to USB2 PHY
674 * @usb3_phy: pointer to USB3 PHY
675 * @usb2_generic_phy: pointer to USB2 PHY
676 * @usb3_generic_phy: pointer to USB3 PHY
677 * @ulpi: pointer to ulpi interface
678 * @dcfg: saved contents of DCFG register
679 * @gctl: saved contents of GCTL register
680 * @isoch_delay: wValue from Set Isochronous Delay request;
681 * @u2sel: parameter from Set SEL request.
682 * @u2pel: parameter from Set SEL request.
683 * @u1sel: parameter from Set SEL request.
684 * @u1pel: parameter from Set SEL request.
685 * @num_out_eps: number of out endpoints
686 * @num_in_eps: number of in endpoints
687 * @ep0_next_event: hold the next expected event
688 * @ep0state: state of endpoint zero
689 * @link_state: link state
690 * @speed: device speed (super, high, full, low)
691 * @mem: points to start of memory which is used for this struct.
692 * @hwparams: copy of hwparams registers
693 * @root: debugfs root folder pointer
694 * @regset: debugfs pointer to regdump file
695 * @test_mode: true when we're entering a USB test mode
696 * @test_mode_nr: test feature selector
697 * @lpm_nyet_threshold: LPM NYET response threshold
698 * @hird_threshold: HIRD threshold
699 * @hsphy_interface: "utmi" or "ulpi"
700 * @delayed_status: true when gadget driver asks for delayed status
701 * @ep0_bounced: true when we used bounce buffer
702 * @ep0_expect_in: true when we expect a DATA IN transfer
703 * @has_hibernation: true when dwc3 was configured with Hibernation
704 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
705 * there's now way for software to detect this in runtime.
706 * @is_utmi_l1_suspend: the core asserts output signal
708 * 1 - utmi_l1_suspend_n
709 * @is_fpga: true when we are using the FPGA board
710 * @pullups_connected: true when Run/Stop bit is set
711 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
712 * @start_config_issued: true when StartConfig command has been issued
713 * @three_stage_setup: set if we perform a three phase setup
714 * @usb3_lpm_capable: set if hadrware supports Link Power Management
715 * @disable_scramble_quirk: set if we enable the disable scramble quirk
716 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
717 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
718 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
719 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
720 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
721 * @lfps_filter_quirk: set if we enable LFPS filter quirk
722 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
723 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
724 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
725 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
726 * disabling the suspend signal to the PHY.
727 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
728 * @tx_de_emphasis: Tx de-emphasis value
729 * 0 - -6dB de-emphasis
730 * 1 - -3.5dB de-emphasis
735 struct usb_ctrlrequest *ctrl_req;
736 struct dwc3_trb *ep0_trb;
741 dma_addr_t ctrl_req_addr;
742 dma_addr_t ep0_trb_addr;
743 dma_addr_t ep0_bounce_addr;
744 dma_addr_t scratch_addr;
745 struct dwc3_request ep0_usb_req;
752 struct platform_device *xhci;
753 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
755 struct dwc3_event_buffer **ev_buffs;
756 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
758 struct usb_gadget gadget;
759 struct usb_gadget_driver *gadget_driver;
761 struct usb_phy *usb2_phy;
762 struct usb_phy *usb3_phy;
764 struct phy *usb2_generic_phy;
765 struct phy *usb3_generic_phy;
772 enum usb_dr_mode dr_mode;
774 /* used for suspend/resume */
779 u32 num_event_buffers;
784 * All 3.1 IP version constants are greater than the 3.0 IP
785 * version constants. This works for most version checks in
786 * dwc3. However, in the future, this may not apply as
787 * features may be developed on newer versions of the 3.0 IP
788 * that are not in the 3.1 IP.
792 #define DWC3_REVISION_173A 0x5533173a
793 #define DWC3_REVISION_175A 0x5533175a
794 #define DWC3_REVISION_180A 0x5533180a
795 #define DWC3_REVISION_183A 0x5533183a
796 #define DWC3_REVISION_185A 0x5533185a
797 #define DWC3_REVISION_187A 0x5533187a
798 #define DWC3_REVISION_188A 0x5533188a
799 #define DWC3_REVISION_190A 0x5533190a
800 #define DWC3_REVISION_194A 0x5533194a
801 #define DWC3_REVISION_200A 0x5533200a
802 #define DWC3_REVISION_202A 0x5533202a
803 #define DWC3_REVISION_210A 0x5533210a
804 #define DWC3_REVISION_220A 0x5533220a
805 #define DWC3_REVISION_230A 0x5533230a
806 #define DWC3_REVISION_240A 0x5533240a
807 #define DWC3_REVISION_250A 0x5533250a
808 #define DWC3_REVISION_260A 0x5533260a
809 #define DWC3_REVISION_270A 0x5533270a
810 #define DWC3_REVISION_280A 0x5533280a
813 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
814 * just so dwc31 revisions are always larger than dwc3.
816 #define DWC3_REVISION_IS_DWC31 0x80000000
817 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31)
819 enum dwc3_ep0_next ep0_next_event;
820 enum dwc3_ep0_state ep0state;
821 enum dwc3_link_state link_state;
836 struct dwc3_hwparams hwparams;
838 struct debugfs_regset32 *regset;
842 u8 lpm_nyet_threshold;
845 const char *hsphy_interface;
847 unsigned delayed_status:1;
848 unsigned ep0_bounced:1;
849 unsigned ep0_expect_in:1;
850 unsigned has_hibernation:1;
851 unsigned has_lpm_erratum:1;
852 unsigned is_utmi_l1_suspend:1;
854 unsigned pullups_connected:1;
855 unsigned setup_packet_pending:1;
856 unsigned three_stage_setup:1;
857 unsigned usb3_lpm_capable:1;
859 unsigned disable_scramble_quirk:1;
860 unsigned u2exit_lfps_quirk:1;
861 unsigned u2ss_inp3_quirk:1;
862 unsigned req_p1p2p3_quirk:1;
863 unsigned del_p1p2p3_quirk:1;
864 unsigned del_phy_power_chg_quirk:1;
865 unsigned lfps_filter_quirk:1;
866 unsigned rx_detect_poll_quirk:1;
867 unsigned dis_u3_susphy_quirk:1;
868 unsigned dis_u2_susphy_quirk:1;
869 unsigned dis_enblslpm_quirk:1;
871 unsigned tx_de_emphasis_quirk:1;
872 unsigned tx_de_emphasis:2;
875 /* -------------------------------------------------------------------------- */
877 /* -------------------------------------------------------------------------- */
879 struct dwc3_event_type {
885 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
886 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
887 #define DWC3_DEPEVT_XFERNOTREADY 0x03
888 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
889 #define DWC3_DEPEVT_STREAMEVT 0x06
890 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
893 * struct dwc3_event_depvt - Device Endpoint Events
894 * @one_bit: indicates this is an endpoint event (not used)
895 * @endpoint_number: number of the endpoint
896 * @endpoint_event: The event we have:
898 * 0x01 - XferComplete
899 * 0x02 - XferInProgress
900 * 0x03 - XferNotReady
901 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
905 * @reserved11_10: Reserved, don't use.
906 * @status: Indicates the status of the event. Refer to databook for
908 * @parameters: Parameters of the current event. Refer to databook for
911 struct dwc3_event_depevt {
913 u32 endpoint_number:5;
914 u32 endpoint_event:4;
918 /* Within XferNotReady */
919 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
921 /* Within XferComplete */
922 #define DEPEVT_STATUS_BUSERR (1 << 0)
923 #define DEPEVT_STATUS_SHORT (1 << 1)
924 #define DEPEVT_STATUS_IOC (1 << 2)
925 #define DEPEVT_STATUS_LST (1 << 3)
927 /* Stream event only */
928 #define DEPEVT_STREAMEVT_FOUND 1
929 #define DEPEVT_STREAMEVT_NOTFOUND 2
931 /* Control-only Status */
932 #define DEPEVT_STATUS_CONTROL_DATA 1
933 #define DEPEVT_STATUS_CONTROL_STATUS 2
939 * struct dwc3_event_devt - Device Events
940 * @one_bit: indicates this is a non-endpoint event (not used)
941 * @device_event: indicates it's a device event. Should read as 0x00
942 * @type: indicates the type of device event.
955 * 12 - VndrDevTstRcved
956 * @reserved15_12: Reserved, not used
957 * @event_info: Information about this event
958 * @reserved31_25: Reserved, not used
960 struct dwc3_event_devt {
970 * struct dwc3_event_gevt - Other Core Events
971 * @one_bit: indicates this is a non-endpoint event (not used)
972 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
973 * @phy_port_number: self-explanatory
974 * @reserved31_12: Reserved, not used.
976 struct dwc3_event_gevt {
979 u32 phy_port_number:4;
980 u32 reserved31_12:20;
984 * union dwc3_event - representation of Event Buffer contents
985 * @raw: raw 32-bit event
986 * @type: the type of the event
987 * @depevt: Device Endpoint Event
988 * @devt: Device Event
989 * @gevt: Global Event
993 struct dwc3_event_type type;
994 struct dwc3_event_depevt depevt;
995 struct dwc3_event_devt devt;
996 struct dwc3_event_gevt gevt;
1000 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1002 * @param2: third parameter
1003 * @param1: second parameter
1004 * @param0: first parameter
1006 struct dwc3_gadget_ep_cmd_params {
1013 * DWC3 Features to be used as Driver Data
1016 #define DWC3_HAS_PERIPHERAL BIT(0)
1017 #define DWC3_HAS_XHCI BIT(1)
1018 #define DWC3_HAS_OTG BIT(3)
1021 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1023 /* check whether we are on the DWC_usb31 core */
1024 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1026 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1029 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1030 int dwc3_host_init(struct dwc3 *dwc);
1031 void dwc3_host_exit(struct dwc3 *dwc);
1033 static inline int dwc3_host_init(struct dwc3 *dwc)
1035 static inline void dwc3_host_exit(struct dwc3 *dwc)
1039 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1040 int dwc3_gadget_init(struct dwc3 *dwc);
1041 void dwc3_gadget_exit(struct dwc3 *dwc);
1042 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1043 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1044 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1045 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1046 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1047 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1049 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1051 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1053 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1055 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1057 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1058 enum dwc3_link_state state)
1061 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1062 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1064 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1069 /* power management interface */
1070 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1071 int dwc3_gadget_suspend(struct dwc3 *dwc);
1072 int dwc3_gadget_resume(struct dwc3 *dwc);
1074 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1079 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1083 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1085 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1086 int dwc3_ulpi_init(struct dwc3 *dwc);
1087 void dwc3_ulpi_exit(struct dwc3 *dwc);
1089 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1091 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1095 #endif /* __DRIVERS_USB_DWC3_CORE_H */