2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
28 #include <linux/debugfs.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/otg.h>
33 #include <linux/ulpi/interface.h>
35 #include <linux/phy/phy.h>
37 #define DWC3_MSG_MAX 500
39 /* Global constants */
40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
41 #define DWC3_EP0_BOUNCE_SIZE 512
42 #define DWC3_ENDPOINTS_NUM 32
43 #define DWC3_XHCI_RESOURCES_NUM 2
45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
46 #define DWC3_EVENT_SIZE 4 /* bytes */
47 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
48 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
49 #define DWC3_EVENT_TYPE_MASK 0xfe
51 #define DWC3_EVENT_TYPE_DEV 0
52 #define DWC3_EVENT_TYPE_CARKIT 3
53 #define DWC3_EVENT_TYPE_I2C 4
55 #define DWC3_DEVICE_EVENT_DISCONNECT 0
56 #define DWC3_DEVICE_EVENT_RESET 1
57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59 #define DWC3_DEVICE_EVENT_WAKEUP 4
60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
61 #define DWC3_DEVICE_EVENT_EOPF 6
62 #define DWC3_DEVICE_EVENT_SOF 7
63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
65 #define DWC3_DEVICE_EVENT_OVERFLOW 11
67 #define DWC3_GEVNTCOUNT_MASK 0xfffc
68 #define DWC3_GSNPSID_MASK 0xffff0000
69 #define DWC3_GSNPSREV_MASK 0xffff
71 /* DWC3 registers memory space boundries */
72 #define DWC3_XHCI_REGS_START 0x0
73 #define DWC3_XHCI_REGS_END 0x7fff
74 #define DWC3_GLOBALS_REGS_START 0xc100
75 #define DWC3_GLOBALS_REGS_END 0xc6ff
76 #define DWC3_DEVICE_REGS_START 0xc700
77 #define DWC3_DEVICE_REGS_END 0xcbff
78 #define DWC3_OTG_REGS_START 0xcc00
79 #define DWC3_OTG_REGS_END 0xccff
81 /* Global Registers */
82 #define DWC3_GSBUSCFG0 0xc100
83 #define DWC3_GSBUSCFG1 0xc104
84 #define DWC3_GTXTHRCFG 0xc108
85 #define DWC3_GRXTHRCFG 0xc10c
86 #define DWC3_GCTL 0xc110
87 #define DWC3_GEVTEN 0xc114
88 #define DWC3_GSTS 0xc118
89 #define DWC3_GUCTL1 0xc11c
90 #define DWC3_GSNPSID 0xc120
91 #define DWC3_GGPIO 0xc124
92 #define DWC3_GUID 0xc128
93 #define DWC3_GUCTL 0xc12c
94 #define DWC3_GBUSERRADDR0 0xc130
95 #define DWC3_GBUSERRADDR1 0xc134
96 #define DWC3_GPRTBIMAP0 0xc138
97 #define DWC3_GPRTBIMAP1 0xc13c
98 #define DWC3_GHWPARAMS0 0xc140
99 #define DWC3_GHWPARAMS1 0xc144
100 #define DWC3_GHWPARAMS2 0xc148
101 #define DWC3_GHWPARAMS3 0xc14c
102 #define DWC3_GHWPARAMS4 0xc150
103 #define DWC3_GHWPARAMS5 0xc154
104 #define DWC3_GHWPARAMS6 0xc158
105 #define DWC3_GHWPARAMS7 0xc15c
106 #define DWC3_GDBGFIFOSPACE 0xc160
107 #define DWC3_GDBGLTSSM 0xc164
108 #define DWC3_GPRTBIMAP_HS0 0xc180
109 #define DWC3_GPRTBIMAP_HS1 0xc184
110 #define DWC3_GPRTBIMAP_FS0 0xc188
111 #define DWC3_GPRTBIMAP_FS1 0xc18c
113 #define DWC3_VER_NUMBER 0xc1a0
114 #define DWC3_VER_TYPE 0xc1a4
116 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
117 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
119 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
121 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
123 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
124 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
126 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
127 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
128 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
129 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
131 #define DWC3_GHWPARAMS8 0xc600
132 #define DWC3_GFLADJ 0xc630
134 /* Device Registers */
135 #define DWC3_DCFG 0xc700
136 #define DWC3_DCTL 0xc704
137 #define DWC3_DEVTEN 0xc708
138 #define DWC3_DSTS 0xc70c
139 #define DWC3_DGCMDPAR 0xc710
140 #define DWC3_DGCMD 0xc714
141 #define DWC3_DALEPENA 0xc720
143 #define DWC3_DEP_BASE(n) (0xc800 + (n * 0x10))
144 #define DWC3_DEPCMDPAR2 0x00
145 #define DWC3_DEPCMDPAR1 0x04
146 #define DWC3_DEPCMDPAR0 0x08
147 #define DWC3_DEPCMD 0x0c
150 #define DWC3_OCFG 0xcc00
151 #define DWC3_OCTL 0xcc04
152 #define DWC3_OEVT 0xcc08
153 #define DWC3_OEVTEN 0xcc0C
154 #define DWC3_OSTS 0xcc10
158 /* Global Debug Queue/FIFO Space Available Register */
159 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
160 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
161 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
163 #define DWC3_TXFIFOQ 1
164 #define DWC3_RXFIFOQ 3
165 #define DWC3_TXREQQ 5
166 #define DWC3_RXREQQ 7
167 #define DWC3_RXINFOQ 9
168 #define DWC3_DESCFETCHQ 13
169 #define DWC3_EVENTQ 15
171 /* Global RX Threshold Configuration Register */
172 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
173 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
174 #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29)
176 /* Global Configuration Register */
177 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
178 #define DWC3_GCTL_U2RSTECN (1 << 16)
179 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
180 #define DWC3_GCTL_CLK_BUS (0)
181 #define DWC3_GCTL_CLK_PIPE (1)
182 #define DWC3_GCTL_CLK_PIPEHALF (2)
183 #define DWC3_GCTL_CLK_MASK (3)
185 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
186 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
187 #define DWC3_GCTL_PRTCAP_HOST 1
188 #define DWC3_GCTL_PRTCAP_DEVICE 2
189 #define DWC3_GCTL_PRTCAP_OTG 3
191 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
192 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
193 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
194 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
195 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
196 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
197 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
198 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
200 /* Global USB2 PHY Configuration Register */
201 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
202 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
203 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
204 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
206 /* Global USB2 PHY Vendor Control Register */
207 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
208 #define DWC3_GUSB2PHYACC_BUSY (1 << 23)
209 #define DWC3_GUSB2PHYACC_WRITE (1 << 22)
210 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
211 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
212 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
214 /* Global USB3 PIPE Control Register */
215 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
216 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
217 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28)
218 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
219 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
220 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
221 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
222 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
223 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
224 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
225 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
226 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
227 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
229 /* Global TX Fifo Size Register */
230 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
231 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
233 /* Global Event Size Registers */
234 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
235 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
237 /* Global HWPARAMS0 Register */
238 #define DWC3_GHWPARAMS0_USB3_MODE(n) ((n) & 0x3)
239 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
240 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
241 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
242 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
243 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
245 /* Global HWPARAMS1 Register */
246 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
247 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
248 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
249 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
250 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
251 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
253 /* Global HWPARAMS3 Register */
254 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
255 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
256 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
257 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
258 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
259 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
260 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
261 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
262 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
263 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
264 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
266 /* Global HWPARAMS4 Register */
267 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
268 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
270 /* Global HWPARAMS6 Register */
271 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
273 /* Global HWPARAMS7 Register */
274 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
275 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
277 /* Global Frame Length Adjustment Register */
278 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
279 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
281 /* Device Configuration Register */
282 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
283 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
285 #define DWC3_DCFG_SPEED_MASK (7 << 0)
286 #define DWC3_DCFG_SUPERSPEED (4 << 0)
287 #define DWC3_DCFG_HIGHSPEED (0 << 0)
288 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
289 #define DWC3_DCFG_LOWSPEED (2 << 0)
290 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
292 #define DWC3_DCFG_NUMP_SHIFT 17
293 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
294 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
295 #define DWC3_DCFG_LPM_CAP (1 << 22)
297 /* Device Control Register */
298 #define DWC3_DCTL_RUN_STOP (1 << 31)
299 #define DWC3_DCTL_CSFTRST (1 << 30)
300 #define DWC3_DCTL_LSFTRST (1 << 29)
302 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
303 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
305 #define DWC3_DCTL_APPL1RES (1 << 23)
307 /* These apply for core versions 1.87a and earlier */
308 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
309 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
310 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
311 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
312 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
313 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
314 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
316 /* These apply for core versions 1.94a and later */
317 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
318 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
320 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
321 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
322 #define DWC3_DCTL_CRS (1 << 17)
323 #define DWC3_DCTL_CSS (1 << 16)
325 #define DWC3_DCTL_INITU2ENA (1 << 12)
326 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
327 #define DWC3_DCTL_INITU1ENA (1 << 10)
328 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
329 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
331 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
332 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
334 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
335 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
336 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
337 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
338 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
339 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
340 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
342 /* Device Event Enable Register */
343 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
344 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
345 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
346 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
347 #define DWC3_DEVTEN_SOFEN (1 << 7)
348 #define DWC3_DEVTEN_EOPFEN (1 << 6)
349 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
350 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
351 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
352 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
353 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
354 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
356 /* Device Status Register */
357 #define DWC3_DSTS_DCNRD (1 << 29)
359 /* This applies for core versions 1.87a and earlier */
360 #define DWC3_DSTS_PWRUPREQ (1 << 24)
362 /* These apply for core versions 1.94a and later */
363 #define DWC3_DSTS_RSS (1 << 25)
364 #define DWC3_DSTS_SSS (1 << 24)
366 #define DWC3_DSTS_COREIDLE (1 << 23)
367 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
369 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
370 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
372 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
374 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
375 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
377 #define DWC3_DSTS_CONNECTSPD (7 << 0)
379 #define DWC3_DSTS_SUPERSPEED (4 << 0)
380 #define DWC3_DSTS_HIGHSPEED (0 << 0)
381 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
382 #define DWC3_DSTS_LOWSPEED (2 << 0)
383 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
385 /* Device Generic Command Register */
386 #define DWC3_DGCMD_SET_LMP 0x01
387 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
388 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
390 /* These apply for core versions 1.94a and later */
391 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
392 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
394 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
395 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
396 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
397 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
399 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
400 #define DWC3_DGCMD_CMDACT (1 << 10)
401 #define DWC3_DGCMD_CMDIOC (1 << 8)
403 /* Device Generic Command Parameter Register */
404 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
405 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
406 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
407 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
408 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
409 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
411 /* Device Endpoint Command Register */
412 #define DWC3_DEPCMD_PARAM_SHIFT 16
413 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
414 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
415 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
416 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
417 #define DWC3_DEPCMD_CLEARPENDIN (1 << 11)
418 #define DWC3_DEPCMD_CMDACT (1 << 10)
419 #define DWC3_DEPCMD_CMDIOC (1 << 8)
421 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
422 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
423 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
424 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
425 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
426 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
427 /* This applies for core versions 1.90a and earlier */
428 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
429 /* This applies for core versions 1.94a and later */
430 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
431 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
432 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
434 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
435 #define DWC3_DALEPENA_EP(n) (1 << n)
437 #define DWC3_DEPCMD_TYPE_CONTROL 0
438 #define DWC3_DEPCMD_TYPE_ISOC 1
439 #define DWC3_DEPCMD_TYPE_BULK 2
440 #define DWC3_DEPCMD_TYPE_INTR 3
447 * struct dwc3_event_buffer - Software event buffer representation
449 * @length: size of this buffer
450 * @lpos: event offset
451 * @count: cache of last read event count register
452 * @flags: flags related to this event buffer
454 * @dwc: pointer to DWC controller
456 struct dwc3_event_buffer {
463 #define DWC3_EVENT_PENDING BIT(0)
470 #define DWC3_EP_FLAG_STALLED (1 << 0)
471 #define DWC3_EP_FLAG_WEDGED (1 << 1)
473 #define DWC3_EP_DIRECTION_TX true
474 #define DWC3_EP_DIRECTION_RX false
476 #define DWC3_TRB_NUM 256
479 * struct dwc3_ep - device side endpoint representation
480 * @endpoint: usb endpoint
481 * @pending_list: list of pending requests for this endpoint
482 * @started_list: list of started requests on this endpoint
483 * @regs: pointer to first endpoint register
484 * @trb_pool: array of transaction buffers
485 * @trb_pool_dma: dma address of @trb_pool
486 * @trb_enqueue: enqueue 'pointer' into TRB array
487 * @trb_dequeue: dequeue 'pointer' into TRB array
488 * @desc: usb_endpoint_descriptor pointer
489 * @dwc: pointer to DWC controller
490 * @saved_state: ep state saved during hibernation
491 * @flags: endpoint flags (wedged, stalled, ...)
492 * @number: endpoint number (1 - 15)
493 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
494 * @resource_index: Resource transfer index
495 * @interval: the interval on which the ISOC transfer is started
496 * @name: a human readable name e.g. ep1out-bulk
497 * @direction: true for TX, false for RX
498 * @stream_capable: true when streams are enabled
501 struct usb_ep endpoint;
502 struct list_head pending_list;
503 struct list_head started_list;
507 struct dwc3_trb *trb_pool;
508 dma_addr_t trb_pool_dma;
509 const struct usb_ss_ep_comp_descriptor *comp_desc;
514 #define DWC3_EP_ENABLED (1 << 0)
515 #define DWC3_EP_STALL (1 << 1)
516 #define DWC3_EP_WEDGE (1 << 2)
517 #define DWC3_EP_BUSY (1 << 4)
518 #define DWC3_EP_PENDING_REQUEST (1 << 5)
519 #define DWC3_EP_MISSED_ISOC (1 << 6)
521 /* This last one is specific to EP0 */
522 #define DWC3_EP0_DIR_IN (1 << 31)
525 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
526 * use a u8 type here. If anybody decides to increase number of TRBs to
527 * anything larger than 256 - I can't see why people would want to do
528 * this though - then this type needs to be changed.
530 * By using u8 types we ensure that our % operator when incrementing
531 * enqueue and dequeue get optimized away by the compiler.
543 unsigned direction:1;
544 unsigned stream_capable:1;
548 DWC3_PHY_UNKNOWN = 0,
554 DWC3_EP0_UNKNOWN = 0,
557 DWC3_EP0_NRDY_STATUS,
560 enum dwc3_ep0_state {
567 enum dwc3_link_state {
569 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
570 DWC3_LINK_STATE_U1 = 0x01,
571 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
572 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
573 DWC3_LINK_STATE_SS_DIS = 0x04,
574 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
575 DWC3_LINK_STATE_SS_INACT = 0x06,
576 DWC3_LINK_STATE_POLL = 0x07,
577 DWC3_LINK_STATE_RECOV = 0x08,
578 DWC3_LINK_STATE_HRESET = 0x09,
579 DWC3_LINK_STATE_CMPLY = 0x0a,
580 DWC3_LINK_STATE_LPBK = 0x0b,
581 DWC3_LINK_STATE_RESET = 0x0e,
582 DWC3_LINK_STATE_RESUME = 0x0f,
583 DWC3_LINK_STATE_MASK = 0x0f,
586 /* TRB Length, PCM and Status */
587 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
588 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
589 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
590 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
592 #define DWC3_TRBSTS_OK 0
593 #define DWC3_TRBSTS_MISSED_ISOC 1
594 #define DWC3_TRBSTS_SETUP_PENDING 2
595 #define DWC3_TRB_STS_XFER_IN_PROG 4
598 #define DWC3_TRB_CTRL_HWO (1 << 0)
599 #define DWC3_TRB_CTRL_LST (1 << 1)
600 #define DWC3_TRB_CTRL_CHN (1 << 2)
601 #define DWC3_TRB_CTRL_CSP (1 << 3)
602 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
603 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
604 #define DWC3_TRB_CTRL_IOC (1 << 11)
605 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
607 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
608 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
609 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
610 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
611 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
612 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
613 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
614 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
615 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
618 * struct dwc3_trb - transfer request block (hw format)
632 * dwc3_hwparams - copy of HWPARAMS registers
633 * @hwparams0 - GHWPARAMS0
634 * @hwparams1 - GHWPARAMS1
635 * @hwparams2 - GHWPARAMS2
636 * @hwparams3 - GHWPARAMS3
637 * @hwparams4 - GHWPARAMS4
638 * @hwparams5 - GHWPARAMS5
639 * @hwparams6 - GHWPARAMS6
640 * @hwparams7 - GHWPARAMS7
641 * @hwparams8 - GHWPARAMS8
643 struct dwc3_hwparams {
656 #define DWC3_MODE(n) ((n) & 0x7)
658 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
661 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
664 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
665 #define DWC3_NUM_EPS_MASK (0x3f << 12)
666 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
667 (DWC3_NUM_EPS_MASK)) >> 12)
668 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
669 (DWC3_NUM_IN_EPS_MASK)) >> 18)
672 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
675 * struct dwc3_request - representation of a transfer request
676 * @request: struct usb_request to be transferred
677 * @list: a list_head used for request queueing
678 * @dep: struct dwc3_ep owning this request
679 * @first_trb_index: index to first trb used by this request
680 * @epnum: endpoint number to which this request refers
681 * @trb: pointer to struct dwc3_trb
682 * @trb_dma: DMA address of @trb
683 * @direction: IN or OUT direction flag
684 * @mapped: true when request has been dma-mapped
685 * @queued: true when request has been queued to HW
687 struct dwc3_request {
688 struct usb_request request;
689 struct list_head list;
694 struct dwc3_trb *trb;
697 unsigned direction:1;
703 * struct dwc3_scratchpad_array - hibernation scratchpad array
704 * (format defined by hw)
706 struct dwc3_scratchpad_array {
707 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
711 * struct dwc3 - representation of our controller
712 * @ctrl_req: usb control request which is used for ep0
713 * @ep0_trb: trb which is used for the ctrl_req
714 * @ep0_bounce: bounce buffer for ep0
715 * @zlp_buf: used when request->zero is set
716 * @setup_buf: used while precessing STD USB requests
717 * @ctrl_req_addr: dma address of ctrl_req
718 * @ep0_trb: dma address of ep0_trb
719 * @ep0_usb_req: dummy req used while handling STD USB requests
720 * @ep0_bounce_addr: dma address of ep0_bounce
721 * @scratch_addr: dma address of scratchbuf
722 * @lock: for synchronizing
723 * @dev: pointer to our struct device
724 * @xhci: pointer to our xHCI child
725 * @event_buffer_list: a list of event buffers
726 * @gadget: device side representation of the peripheral controller
727 * @gadget_driver: pointer to the gadget driver
728 * @regs: base address for our registers
729 * @regs_size: address space size
730 * @fladj: frame length adjustment
731 * @nr_scratch: number of scratch buffers
732 * @u1u2: only used on revisions <1.83a for workaround
733 * @maximum_speed: maximum speed requested (mainly for testing purposes)
734 * @revision: revision register contents
735 * @dr_mode: requested mode of operation
736 * @usb2_phy: pointer to USB2 PHY
737 * @usb3_phy: pointer to USB3 PHY
738 * @usb2_generic_phy: pointer to USB2 PHY
739 * @usb3_generic_phy: pointer to USB3 PHY
740 * @ulpi: pointer to ulpi interface
741 * @dcfg: saved contents of DCFG register
742 * @gctl: saved contents of GCTL register
743 * @isoch_delay: wValue from Set Isochronous Delay request;
744 * @u2sel: parameter from Set SEL request.
745 * @u2pel: parameter from Set SEL request.
746 * @u1sel: parameter from Set SEL request.
747 * @u1pel: parameter from Set SEL request.
748 * @num_out_eps: number of out endpoints
749 * @num_in_eps: number of in endpoints
750 * @ep0_next_event: hold the next expected event
751 * @ep0state: state of endpoint zero
752 * @link_state: link state
753 * @speed: device speed (super, high, full, low)
754 * @mem: points to start of memory which is used for this struct.
755 * @hwparams: copy of hwparams registers
756 * @root: debugfs root folder pointer
757 * @regset: debugfs pointer to regdump file
758 * @test_mode: true when we're entering a USB test mode
759 * @test_mode_nr: test feature selector
760 * @lpm_nyet_threshold: LPM NYET response threshold
761 * @hird_threshold: HIRD threshold
762 * @hsphy_interface: "utmi" or "ulpi"
763 * @delayed_status: true when gadget driver asks for delayed status
764 * @ep0_bounced: true when we used bounce buffer
765 * @ep0_expect_in: true when we expect a DATA IN transfer
766 * @has_hibernation: true when dwc3 was configured with Hibernation
767 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
768 * there's now way for software to detect this in runtime.
769 * @is_utmi_l1_suspend: the core asserts output signal
771 * 1 - utmi_l1_suspend_n
772 * @is_fpga: true when we are using the FPGA board
773 * @pullups_connected: true when Run/Stop bit is set
774 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
775 * @start_config_issued: true when StartConfig command has been issued
776 * @three_stage_setup: set if we perform a three phase setup
777 * @usb3_lpm_capable: set if hadrware supports Link Power Management
778 * @disable_scramble_quirk: set if we enable the disable scramble quirk
779 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
780 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
781 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
782 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
783 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
784 * @lfps_filter_quirk: set if we enable LFPS filter quirk
785 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
786 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
787 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
788 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
789 * disabling the suspend signal to the PHY.
790 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
791 * @tx_de_emphasis: Tx de-emphasis value
792 * 0 - -6dB de-emphasis
793 * 1 - -3.5dB de-emphasis
798 struct usb_ctrlrequest *ctrl_req;
799 struct dwc3_trb *ep0_trb;
804 dma_addr_t ctrl_req_addr;
805 dma_addr_t ep0_trb_addr;
806 dma_addr_t ep0_bounce_addr;
807 dma_addr_t scratch_addr;
808 struct dwc3_request ep0_usb_req;
815 struct platform_device *xhci;
816 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
818 struct dwc3_event_buffer *ev_buf;
819 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
821 struct usb_gadget gadget;
822 struct usb_gadget_driver *gadget_driver;
824 struct usb_phy *usb2_phy;
825 struct usb_phy *usb3_phy;
827 struct phy *usb2_generic_phy;
828 struct phy *usb3_generic_phy;
835 enum usb_dr_mode dr_mode;
837 /* used for suspend/resume */
846 * All 3.1 IP version constants are greater than the 3.0 IP
847 * version constants. This works for most version checks in
848 * dwc3. However, in the future, this may not apply as
849 * features may be developed on newer versions of the 3.0 IP
850 * that are not in the 3.1 IP.
854 #define DWC3_REVISION_173A 0x5533173a
855 #define DWC3_REVISION_175A 0x5533175a
856 #define DWC3_REVISION_180A 0x5533180a
857 #define DWC3_REVISION_183A 0x5533183a
858 #define DWC3_REVISION_185A 0x5533185a
859 #define DWC3_REVISION_187A 0x5533187a
860 #define DWC3_REVISION_188A 0x5533188a
861 #define DWC3_REVISION_190A 0x5533190a
862 #define DWC3_REVISION_194A 0x5533194a
863 #define DWC3_REVISION_200A 0x5533200a
864 #define DWC3_REVISION_202A 0x5533202a
865 #define DWC3_REVISION_210A 0x5533210a
866 #define DWC3_REVISION_220A 0x5533220a
867 #define DWC3_REVISION_230A 0x5533230a
868 #define DWC3_REVISION_240A 0x5533240a
869 #define DWC3_REVISION_250A 0x5533250a
870 #define DWC3_REVISION_260A 0x5533260a
871 #define DWC3_REVISION_270A 0x5533270a
872 #define DWC3_REVISION_280A 0x5533280a
875 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
876 * just so dwc31 revisions are always larger than dwc3.
878 #define DWC3_REVISION_IS_DWC31 0x80000000
879 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31)
881 enum dwc3_ep0_next ep0_next_event;
882 enum dwc3_ep0_state ep0state;
883 enum dwc3_link_state link_state;
898 struct dwc3_hwparams hwparams;
900 struct debugfs_regset32 *regset;
904 u8 lpm_nyet_threshold;
907 const char *hsphy_interface;
909 unsigned delayed_status:1;
910 unsigned ep0_bounced:1;
911 unsigned ep0_expect_in:1;
912 unsigned has_hibernation:1;
913 unsigned has_lpm_erratum:1;
914 unsigned is_utmi_l1_suspend:1;
916 unsigned pullups_connected:1;
917 unsigned setup_packet_pending:1;
918 unsigned three_stage_setup:1;
919 unsigned usb3_lpm_capable:1;
921 unsigned disable_scramble_quirk:1;
922 unsigned u2exit_lfps_quirk:1;
923 unsigned u2ss_inp3_quirk:1;
924 unsigned req_p1p2p3_quirk:1;
925 unsigned del_p1p2p3_quirk:1;
926 unsigned del_phy_power_chg_quirk:1;
927 unsigned lfps_filter_quirk:1;
928 unsigned rx_detect_poll_quirk:1;
929 unsigned dis_u3_susphy_quirk:1;
930 unsigned dis_u2_susphy_quirk:1;
931 unsigned dis_enblslpm_quirk:1;
932 unsigned dis_rxdet_inp3_quirk:1;
934 unsigned tx_de_emphasis_quirk:1;
935 unsigned tx_de_emphasis:2;
938 /* -------------------------------------------------------------------------- */
940 /* -------------------------------------------------------------------------- */
942 struct dwc3_event_type {
948 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
949 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
950 #define DWC3_DEPEVT_XFERNOTREADY 0x03
951 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
952 #define DWC3_DEPEVT_STREAMEVT 0x06
953 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
956 * struct dwc3_event_depvt - Device Endpoint Events
957 * @one_bit: indicates this is an endpoint event (not used)
958 * @endpoint_number: number of the endpoint
959 * @endpoint_event: The event we have:
961 * 0x01 - XferComplete
962 * 0x02 - XferInProgress
963 * 0x03 - XferNotReady
964 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
968 * @reserved11_10: Reserved, don't use.
969 * @status: Indicates the status of the event. Refer to databook for
971 * @parameters: Parameters of the current event. Refer to databook for
974 struct dwc3_event_depevt {
976 u32 endpoint_number:5;
977 u32 endpoint_event:4;
981 /* Within XferNotReady */
982 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
984 /* Within XferComplete */
985 #define DEPEVT_STATUS_BUSERR (1 << 0)
986 #define DEPEVT_STATUS_SHORT (1 << 1)
987 #define DEPEVT_STATUS_IOC (1 << 2)
988 #define DEPEVT_STATUS_LST (1 << 3)
990 /* Stream event only */
991 #define DEPEVT_STREAMEVT_FOUND 1
992 #define DEPEVT_STREAMEVT_NOTFOUND 2
994 /* Control-only Status */
995 #define DEPEVT_STATUS_CONTROL_DATA 1
996 #define DEPEVT_STATUS_CONTROL_STATUS 2
998 /* In response to Start Transfer */
999 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1000 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1006 * struct dwc3_event_devt - Device Events
1007 * @one_bit: indicates this is a non-endpoint event (not used)
1008 * @device_event: indicates it's a device event. Should read as 0x00
1009 * @type: indicates the type of device event.
1022 * 12 - VndrDevTstRcved
1023 * @reserved15_12: Reserved, not used
1024 * @event_info: Information about this event
1025 * @reserved31_25: Reserved, not used
1027 struct dwc3_event_devt {
1031 u32 reserved15_12:4;
1033 u32 reserved31_25:7;
1037 * struct dwc3_event_gevt - Other Core Events
1038 * @one_bit: indicates this is a non-endpoint event (not used)
1039 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1040 * @phy_port_number: self-explanatory
1041 * @reserved31_12: Reserved, not used.
1043 struct dwc3_event_gevt {
1046 u32 phy_port_number:4;
1047 u32 reserved31_12:20;
1051 * union dwc3_event - representation of Event Buffer contents
1052 * @raw: raw 32-bit event
1053 * @type: the type of the event
1054 * @depevt: Device Endpoint Event
1055 * @devt: Device Event
1056 * @gevt: Global Event
1060 struct dwc3_event_type type;
1061 struct dwc3_event_depevt depevt;
1062 struct dwc3_event_devt devt;
1063 struct dwc3_event_gevt gevt;
1067 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1069 * @param2: third parameter
1070 * @param1: second parameter
1071 * @param0: first parameter
1073 struct dwc3_gadget_ep_cmd_params {
1080 * DWC3 Features to be used as Driver Data
1083 #define DWC3_HAS_PERIPHERAL BIT(0)
1084 #define DWC3_HAS_XHCI BIT(1)
1085 #define DWC3_HAS_OTG BIT(3)
1088 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1089 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1091 /* check whether we are on the DWC_usb31 core */
1092 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1094 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1097 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1098 int dwc3_host_init(struct dwc3 *dwc);
1099 void dwc3_host_exit(struct dwc3 *dwc);
1101 static inline int dwc3_host_init(struct dwc3 *dwc)
1103 static inline void dwc3_host_exit(struct dwc3 *dwc)
1107 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1108 int dwc3_gadget_init(struct dwc3 *dwc);
1109 void dwc3_gadget_exit(struct dwc3 *dwc);
1110 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1111 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1112 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1113 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1114 struct dwc3_gadget_ep_cmd_params *params);
1115 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1117 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1119 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1121 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1123 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1125 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1126 enum dwc3_link_state state)
1129 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1130 struct dwc3_gadget_ep_cmd_params *params)
1132 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1137 /* power management interface */
1138 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1139 int dwc3_gadget_suspend(struct dwc3 *dwc);
1140 int dwc3_gadget_resume(struct dwc3 *dwc);
1142 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1147 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1151 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1153 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1154 int dwc3_ulpi_init(struct dwc3 *dwc);
1155 void dwc3_ulpi_exit(struct dwc3 *dwc);
1157 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1159 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1163 #endif /* __DRIVERS_USB_DWC3_CORE_H */