2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
28 #include <linux/debugfs.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/otg.h>
33 #include <linux/ulpi/interface.h>
35 #include <linux/phy/phy.h>
37 #define DWC3_MSG_MAX 500
39 /* Global constants */
40 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
41 #define DWC3_EP0_BOUNCE_SIZE 512
42 #define DWC3_ENDPOINTS_NUM 32
43 #define DWC3_XHCI_RESOURCES_NUM 2
45 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
46 #define DWC3_EVENT_SIZE 4 /* bytes */
47 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
48 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
49 #define DWC3_EVENT_TYPE_MASK 0xfe
51 #define DWC3_EVENT_TYPE_DEV 0
52 #define DWC3_EVENT_TYPE_CARKIT 3
53 #define DWC3_EVENT_TYPE_I2C 4
55 #define DWC3_DEVICE_EVENT_DISCONNECT 0
56 #define DWC3_DEVICE_EVENT_RESET 1
57 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59 #define DWC3_DEVICE_EVENT_WAKEUP 4
60 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
61 #define DWC3_DEVICE_EVENT_EOPF 6
62 #define DWC3_DEVICE_EVENT_SOF 7
63 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
65 #define DWC3_DEVICE_EVENT_OVERFLOW 11
67 #define DWC3_GEVNTCOUNT_MASK 0xfffc
68 #define DWC3_GSNPSID_MASK 0xffff0000
69 #define DWC3_GSNPSREV_MASK 0xffff
71 /* DWC3 registers memory space boundries */
72 #define DWC3_XHCI_REGS_START 0x0
73 #define DWC3_XHCI_REGS_END 0x7fff
74 #define DWC3_GLOBALS_REGS_START 0xc100
75 #define DWC3_GLOBALS_REGS_END 0xc6ff
76 #define DWC3_DEVICE_REGS_START 0xc700
77 #define DWC3_DEVICE_REGS_END 0xcbff
78 #define DWC3_OTG_REGS_START 0xcc00
79 #define DWC3_OTG_REGS_END 0xccff
81 /* Global Registers */
82 #define DWC3_GSBUSCFG0 0xc100
83 #define DWC3_GSBUSCFG1 0xc104
84 #define DWC3_GTXTHRCFG 0xc108
85 #define DWC3_GRXTHRCFG 0xc10c
86 #define DWC3_GCTL 0xc110
87 #define DWC3_GEVTEN 0xc114
88 #define DWC3_GSTS 0xc118
89 #define DWC3_GUCTL1 0xc11c
90 #define DWC3_GSNPSID 0xc120
91 #define DWC3_GGPIO 0xc124
92 #define DWC3_GUID 0xc128
93 #define DWC3_GUCTL 0xc12c
94 #define DWC3_GBUSERRADDR0 0xc130
95 #define DWC3_GBUSERRADDR1 0xc134
96 #define DWC3_GPRTBIMAP0 0xc138
97 #define DWC3_GPRTBIMAP1 0xc13c
98 #define DWC3_GHWPARAMS0 0xc140
99 #define DWC3_GHWPARAMS1 0xc144
100 #define DWC3_GHWPARAMS2 0xc148
101 #define DWC3_GHWPARAMS3 0xc14c
102 #define DWC3_GHWPARAMS4 0xc150
103 #define DWC3_GHWPARAMS5 0xc154
104 #define DWC3_GHWPARAMS6 0xc158
105 #define DWC3_GHWPARAMS7 0xc15c
106 #define DWC3_GDBGFIFOSPACE 0xc160
107 #define DWC3_GDBGLTSSM 0xc164
108 #define DWC3_GPRTBIMAP_HS0 0xc180
109 #define DWC3_GPRTBIMAP_HS1 0xc184
110 #define DWC3_GPRTBIMAP_FS0 0xc188
111 #define DWC3_GPRTBIMAP_FS1 0xc18c
113 #define DWC3_VER_NUMBER 0xc1a0
114 #define DWC3_VER_TYPE 0xc1a4
116 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
117 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
119 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
121 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
123 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
124 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
126 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
127 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
128 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
129 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
131 #define DWC3_GHWPARAMS8 0xc600
132 #define DWC3_GFLADJ 0xc630
134 /* Device Registers */
135 #define DWC3_DCFG 0xc700
136 #define DWC3_DCTL 0xc704
137 #define DWC3_DEVTEN 0xc708
138 #define DWC3_DSTS 0xc70c
139 #define DWC3_DGCMDPAR 0xc710
140 #define DWC3_DGCMD 0xc714
141 #define DWC3_DALEPENA 0xc720
142 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
143 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
144 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
145 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
148 #define DWC3_OCFG 0xcc00
149 #define DWC3_OCTL 0xcc04
150 #define DWC3_OEVT 0xcc08
151 #define DWC3_OEVTEN 0xcc0C
152 #define DWC3_OSTS 0xcc10
156 /* Global Debug Queue/FIFO Space Available Register */
157 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
158 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
159 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
161 #define DWC3_TXFIFOQ 1
162 #define DWC3_RXFIFOQ 3
163 #define DWC3_TXREQQ 5
164 #define DWC3_RXREQQ 7
165 #define DWC3_RXINFOQ 9
166 #define DWC3_DESCFETCHQ 13
167 #define DWC3_EVENTQ 15
169 /* Global RX Threshold Configuration Register */
170 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
171 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
172 #define DWC3_GRXTHRCFG_PKTCNTSEL (1 << 29)
174 /* Global Configuration Register */
175 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
176 #define DWC3_GCTL_U2RSTECN (1 << 16)
177 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
178 #define DWC3_GCTL_CLK_BUS (0)
179 #define DWC3_GCTL_CLK_PIPE (1)
180 #define DWC3_GCTL_CLK_PIPEHALF (2)
181 #define DWC3_GCTL_CLK_MASK (3)
183 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
184 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
185 #define DWC3_GCTL_PRTCAP_HOST 1
186 #define DWC3_GCTL_PRTCAP_DEVICE 2
187 #define DWC3_GCTL_PRTCAP_OTG 3
189 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
190 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
191 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
192 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
193 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
194 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
195 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
196 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
198 /* Global USB2 PHY Configuration Register */
199 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
200 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
201 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
202 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
204 /* Global USB2 PHY Vendor Control Register */
205 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
206 #define DWC3_GUSB2PHYACC_BUSY (1 << 23)
207 #define DWC3_GUSB2PHYACC_WRITE (1 << 22)
208 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
209 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
210 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
212 /* Global USB3 PIPE Control Register */
213 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
214 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
215 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 (1 << 28)
216 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
217 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
218 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
219 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
220 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
221 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
222 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
223 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
224 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
225 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
227 /* Global TX Fifo Size Register */
228 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
229 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
231 /* Global Event Size Registers */
232 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
233 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
235 /* Global HWPARAMS1 Register */
236 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
237 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
238 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
239 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
240 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
241 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
243 /* Global HWPARAMS3 Register */
244 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
245 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
246 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
247 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
248 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
249 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
250 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
251 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
252 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
253 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
254 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
256 /* Global HWPARAMS4 Register */
257 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
258 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
260 /* Global HWPARAMS6 Register */
261 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
263 /* Global Frame Length Adjustment Register */
264 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
265 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
267 /* Device Configuration Register */
268 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
269 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
271 #define DWC3_DCFG_SPEED_MASK (7 << 0)
272 #define DWC3_DCFG_SUPERSPEED (4 << 0)
273 #define DWC3_DCFG_HIGHSPEED (0 << 0)
274 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
275 #define DWC3_DCFG_LOWSPEED (2 << 0)
276 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
278 #define DWC3_DCFG_NUMP_SHIFT 17
279 #define DWC3_DCFG_NUMP(n) (((n) & 0x1f) >> DWC3_DCFG_NUMP_SHIFT)
280 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
281 #define DWC3_DCFG_LPM_CAP (1 << 22)
283 /* Device Control Register */
284 #define DWC3_DCTL_RUN_STOP (1 << 31)
285 #define DWC3_DCTL_CSFTRST (1 << 30)
286 #define DWC3_DCTL_LSFTRST (1 << 29)
288 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
289 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
291 #define DWC3_DCTL_APPL1RES (1 << 23)
293 /* These apply for core versions 1.87a and earlier */
294 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
295 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
296 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
297 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
298 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
299 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
300 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
302 /* These apply for core versions 1.94a and later */
303 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
304 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
306 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
307 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
308 #define DWC3_DCTL_CRS (1 << 17)
309 #define DWC3_DCTL_CSS (1 << 16)
311 #define DWC3_DCTL_INITU2ENA (1 << 12)
312 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
313 #define DWC3_DCTL_INITU1ENA (1 << 10)
314 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
315 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
317 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
318 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
320 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
321 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
322 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
323 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
324 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
325 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
326 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
328 /* Device Event Enable Register */
329 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
330 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
331 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
332 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
333 #define DWC3_DEVTEN_SOFEN (1 << 7)
334 #define DWC3_DEVTEN_EOPFEN (1 << 6)
335 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
336 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
337 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
338 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
339 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
340 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
342 /* Device Status Register */
343 #define DWC3_DSTS_DCNRD (1 << 29)
345 /* This applies for core versions 1.87a and earlier */
346 #define DWC3_DSTS_PWRUPREQ (1 << 24)
348 /* These apply for core versions 1.94a and later */
349 #define DWC3_DSTS_RSS (1 << 25)
350 #define DWC3_DSTS_SSS (1 << 24)
352 #define DWC3_DSTS_COREIDLE (1 << 23)
353 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
355 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
356 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
358 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
360 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
361 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
363 #define DWC3_DSTS_CONNECTSPD (7 << 0)
365 #define DWC3_DSTS_SUPERSPEED (4 << 0)
366 #define DWC3_DSTS_HIGHSPEED (0 << 0)
367 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
368 #define DWC3_DSTS_LOWSPEED (2 << 0)
369 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
371 /* Device Generic Command Register */
372 #define DWC3_DGCMD_SET_LMP 0x01
373 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
374 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
376 /* These apply for core versions 1.94a and later */
377 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
378 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
380 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
381 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
382 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
383 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
385 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
386 #define DWC3_DGCMD_CMDACT (1 << 10)
387 #define DWC3_DGCMD_CMDIOC (1 << 8)
389 /* Device Generic Command Parameter Register */
390 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
391 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
392 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
393 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
394 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
395 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
397 /* Device Endpoint Command Register */
398 #define DWC3_DEPCMD_PARAM_SHIFT 16
399 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
400 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
401 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
402 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
403 #define DWC3_DEPCMD_CMDACT (1 << 10)
404 #define DWC3_DEPCMD_CMDIOC (1 << 8)
406 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
407 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
408 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
409 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
410 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
411 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
412 /* This applies for core versions 1.90a and earlier */
413 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
414 /* This applies for core versions 1.94a and later */
415 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
416 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
417 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
419 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
420 #define DWC3_DALEPENA_EP(n) (1 << n)
422 #define DWC3_DEPCMD_TYPE_CONTROL 0
423 #define DWC3_DEPCMD_TYPE_ISOC 1
424 #define DWC3_DEPCMD_TYPE_BULK 2
425 #define DWC3_DEPCMD_TYPE_INTR 3
432 * struct dwc3_event_buffer - Software event buffer representation
434 * @length: size of this buffer
435 * @lpos: event offset
436 * @count: cache of last read event count register
437 * @flags: flags related to this event buffer
439 * @dwc: pointer to DWC controller
441 struct dwc3_event_buffer {
448 #define DWC3_EVENT_PENDING BIT(0)
455 #define DWC3_EP_FLAG_STALLED (1 << 0)
456 #define DWC3_EP_FLAG_WEDGED (1 << 1)
458 #define DWC3_EP_DIRECTION_TX true
459 #define DWC3_EP_DIRECTION_RX false
461 #define DWC3_TRB_NUM 256
464 * struct dwc3_ep - device side endpoint representation
465 * @endpoint: usb endpoint
466 * @pending_list: list of pending requests for this endpoint
467 * @started_list: list of started requests on this endpoint
468 * @trb_pool: array of transaction buffers
469 * @trb_pool_dma: dma address of @trb_pool
470 * @trb_enqueue: enqueue 'pointer' into TRB array
471 * @trb_dequeue: dequeue 'pointer' into TRB array
472 * @desc: usb_endpoint_descriptor pointer
473 * @dwc: pointer to DWC controller
474 * @saved_state: ep state saved during hibernation
475 * @flags: endpoint flags (wedged, stalled, ...)
476 * @number: endpoint number (1 - 15)
477 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
478 * @resource_index: Resource transfer index
479 * @interval: the interval on which the ISOC transfer is started
480 * @name: a human readable name e.g. ep1out-bulk
481 * @direction: true for TX, false for RX
482 * @stream_capable: true when streams are enabled
485 struct usb_ep endpoint;
486 struct list_head pending_list;
487 struct list_head started_list;
489 struct dwc3_trb *trb_pool;
490 dma_addr_t trb_pool_dma;
491 const struct usb_ss_ep_comp_descriptor *comp_desc;
496 #define DWC3_EP_ENABLED (1 << 0)
497 #define DWC3_EP_STALL (1 << 1)
498 #define DWC3_EP_WEDGE (1 << 2)
499 #define DWC3_EP_BUSY (1 << 4)
500 #define DWC3_EP_PENDING_REQUEST (1 << 5)
501 #define DWC3_EP_MISSED_ISOC (1 << 6)
503 /* This last one is specific to EP0 */
504 #define DWC3_EP0_DIR_IN (1 << 31)
507 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
508 * use a u8 type here. If anybody decides to increase number of TRBs to
509 * anything larger than 256 - I can't see why people would want to do
510 * this though - then this type needs to be changed.
512 * By using u8 types we ensure that our % operator when incrementing
513 * enqueue and dequeue get optimized away by the compiler.
525 unsigned direction:1;
526 unsigned stream_capable:1;
530 DWC3_PHY_UNKNOWN = 0,
536 DWC3_EP0_UNKNOWN = 0,
539 DWC3_EP0_NRDY_STATUS,
542 enum dwc3_ep0_state {
549 enum dwc3_link_state {
551 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
552 DWC3_LINK_STATE_U1 = 0x01,
553 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
554 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
555 DWC3_LINK_STATE_SS_DIS = 0x04,
556 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
557 DWC3_LINK_STATE_SS_INACT = 0x06,
558 DWC3_LINK_STATE_POLL = 0x07,
559 DWC3_LINK_STATE_RECOV = 0x08,
560 DWC3_LINK_STATE_HRESET = 0x09,
561 DWC3_LINK_STATE_CMPLY = 0x0a,
562 DWC3_LINK_STATE_LPBK = 0x0b,
563 DWC3_LINK_STATE_RESET = 0x0e,
564 DWC3_LINK_STATE_RESUME = 0x0f,
565 DWC3_LINK_STATE_MASK = 0x0f,
568 /* TRB Length, PCM and Status */
569 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
570 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
571 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
572 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
574 #define DWC3_TRBSTS_OK 0
575 #define DWC3_TRBSTS_MISSED_ISOC 1
576 #define DWC3_TRBSTS_SETUP_PENDING 2
577 #define DWC3_TRB_STS_XFER_IN_PROG 4
580 #define DWC3_TRB_CTRL_HWO (1 << 0)
581 #define DWC3_TRB_CTRL_LST (1 << 1)
582 #define DWC3_TRB_CTRL_CHN (1 << 2)
583 #define DWC3_TRB_CTRL_CSP (1 << 3)
584 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
585 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
586 #define DWC3_TRB_CTRL_IOC (1 << 11)
587 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
589 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
590 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
591 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
592 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
593 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
594 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
595 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
596 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
597 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
600 * struct dwc3_trb - transfer request block (hw format)
614 * dwc3_hwparams - copy of HWPARAMS registers
615 * @hwparams0 - GHWPARAMS0
616 * @hwparams1 - GHWPARAMS1
617 * @hwparams2 - GHWPARAMS2
618 * @hwparams3 - GHWPARAMS3
619 * @hwparams4 - GHWPARAMS4
620 * @hwparams5 - GHWPARAMS5
621 * @hwparams6 - GHWPARAMS6
622 * @hwparams7 - GHWPARAMS7
623 * @hwparams8 - GHWPARAMS8
625 struct dwc3_hwparams {
638 #define DWC3_MODE(n) ((n) & 0x7)
640 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
643 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
646 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
647 #define DWC3_NUM_EPS_MASK (0x3f << 12)
648 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
649 (DWC3_NUM_EPS_MASK)) >> 12)
650 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
651 (DWC3_NUM_IN_EPS_MASK)) >> 18)
654 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
657 * struct dwc3_request - representation of a transfer request
658 * @request: struct usb_request to be transferred
659 * @list: a list_head used for request queueing
660 * @dep: struct dwc3_ep owning this request
661 * @first_trb_index: index to first trb used by this request
662 * @epnum: endpoint number to which this request refers
663 * @trb: pointer to struct dwc3_trb
664 * @trb_dma: DMA address of @trb
665 * @direction: IN or OUT direction flag
666 * @mapped: true when request has been dma-mapped
667 * @queued: true when request has been queued to HW
669 struct dwc3_request {
670 struct usb_request request;
671 struct list_head list;
676 struct dwc3_trb *trb;
679 unsigned direction:1;
685 * struct dwc3_scratchpad_array - hibernation scratchpad array
686 * (format defined by hw)
688 struct dwc3_scratchpad_array {
689 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
693 * struct dwc3 - representation of our controller
694 * @ctrl_req: usb control request which is used for ep0
695 * @ep0_trb: trb which is used for the ctrl_req
696 * @ep0_bounce: bounce buffer for ep0
697 * @zlp_buf: used when request->zero is set
698 * @setup_buf: used while precessing STD USB requests
699 * @ctrl_req_addr: dma address of ctrl_req
700 * @ep0_trb: dma address of ep0_trb
701 * @ep0_usb_req: dummy req used while handling STD USB requests
702 * @ep0_bounce_addr: dma address of ep0_bounce
703 * @scratch_addr: dma address of scratchbuf
704 * @lock: for synchronizing
705 * @dev: pointer to our struct device
706 * @xhci: pointer to our xHCI child
707 * @event_buffer_list: a list of event buffers
708 * @gadget: device side representation of the peripheral controller
709 * @gadget_driver: pointer to the gadget driver
710 * @regs: base address for our registers
711 * @regs_size: address space size
712 * @nr_scratch: number of scratch buffers
713 * @u1u2: only used on revisions <1.83a for workaround
714 * @maximum_speed: maximum speed requested (mainly for testing purposes)
715 * @revision: revision register contents
716 * @dr_mode: requested mode of operation
717 * @usb2_phy: pointer to USB2 PHY
718 * @usb3_phy: pointer to USB3 PHY
719 * @usb2_generic_phy: pointer to USB2 PHY
720 * @usb3_generic_phy: pointer to USB3 PHY
721 * @ulpi: pointer to ulpi interface
722 * @dcfg: saved contents of DCFG register
723 * @gctl: saved contents of GCTL register
724 * @isoch_delay: wValue from Set Isochronous Delay request;
725 * @u2sel: parameter from Set SEL request.
726 * @u2pel: parameter from Set SEL request.
727 * @u1sel: parameter from Set SEL request.
728 * @u1pel: parameter from Set SEL request.
729 * @num_out_eps: number of out endpoints
730 * @num_in_eps: number of in endpoints
731 * @ep0_next_event: hold the next expected event
732 * @ep0state: state of endpoint zero
733 * @link_state: link state
734 * @speed: device speed (super, high, full, low)
735 * @mem: points to start of memory which is used for this struct.
736 * @hwparams: copy of hwparams registers
737 * @root: debugfs root folder pointer
738 * @regset: debugfs pointer to regdump file
739 * @test_mode: true when we're entering a USB test mode
740 * @test_mode_nr: test feature selector
741 * @lpm_nyet_threshold: LPM NYET response threshold
742 * @hird_threshold: HIRD threshold
743 * @hsphy_interface: "utmi" or "ulpi"
744 * @delayed_status: true when gadget driver asks for delayed status
745 * @ep0_bounced: true when we used bounce buffer
746 * @ep0_expect_in: true when we expect a DATA IN transfer
747 * @has_hibernation: true when dwc3 was configured with Hibernation
748 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
749 * there's now way for software to detect this in runtime.
750 * @is_utmi_l1_suspend: the core asserts output signal
752 * 1 - utmi_l1_suspend_n
753 * @is_fpga: true when we are using the FPGA board
754 * @pullups_connected: true when Run/Stop bit is set
755 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
756 * @start_config_issued: true when StartConfig command has been issued
757 * @three_stage_setup: set if we perform a three phase setup
758 * @usb3_lpm_capable: set if hadrware supports Link Power Management
759 * @disable_scramble_quirk: set if we enable the disable scramble quirk
760 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
761 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
762 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
763 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
764 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
765 * @lfps_filter_quirk: set if we enable LFPS filter quirk
766 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
767 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
768 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
769 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
770 * disabling the suspend signal to the PHY.
771 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
772 * @tx_de_emphasis: Tx de-emphasis value
773 * 0 - -6dB de-emphasis
774 * 1 - -3.5dB de-emphasis
779 struct usb_ctrlrequest *ctrl_req;
780 struct dwc3_trb *ep0_trb;
785 dma_addr_t ctrl_req_addr;
786 dma_addr_t ep0_trb_addr;
787 dma_addr_t ep0_bounce_addr;
788 dma_addr_t scratch_addr;
789 struct dwc3_request ep0_usb_req;
796 struct platform_device *xhci;
797 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
799 struct dwc3_event_buffer *ev_buf;
800 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
802 struct usb_gadget gadget;
803 struct usb_gadget_driver *gadget_driver;
805 struct usb_phy *usb2_phy;
806 struct usb_phy *usb3_phy;
808 struct phy *usb2_generic_phy;
809 struct phy *usb3_generic_phy;
816 enum usb_dr_mode dr_mode;
818 /* used for suspend/resume */
827 * All 3.1 IP version constants are greater than the 3.0 IP
828 * version constants. This works for most version checks in
829 * dwc3. However, in the future, this may not apply as
830 * features may be developed on newer versions of the 3.0 IP
831 * that are not in the 3.1 IP.
835 #define DWC3_REVISION_173A 0x5533173a
836 #define DWC3_REVISION_175A 0x5533175a
837 #define DWC3_REVISION_180A 0x5533180a
838 #define DWC3_REVISION_183A 0x5533183a
839 #define DWC3_REVISION_185A 0x5533185a
840 #define DWC3_REVISION_187A 0x5533187a
841 #define DWC3_REVISION_188A 0x5533188a
842 #define DWC3_REVISION_190A 0x5533190a
843 #define DWC3_REVISION_194A 0x5533194a
844 #define DWC3_REVISION_200A 0x5533200a
845 #define DWC3_REVISION_202A 0x5533202a
846 #define DWC3_REVISION_210A 0x5533210a
847 #define DWC3_REVISION_220A 0x5533220a
848 #define DWC3_REVISION_230A 0x5533230a
849 #define DWC3_REVISION_240A 0x5533240a
850 #define DWC3_REVISION_250A 0x5533250a
851 #define DWC3_REVISION_260A 0x5533260a
852 #define DWC3_REVISION_270A 0x5533270a
853 #define DWC3_REVISION_280A 0x5533280a
856 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
857 * just so dwc31 revisions are always larger than dwc3.
859 #define DWC3_REVISION_IS_DWC31 0x80000000
860 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31)
862 enum dwc3_ep0_next ep0_next_event;
863 enum dwc3_ep0_state ep0state;
864 enum dwc3_link_state link_state;
879 struct dwc3_hwparams hwparams;
881 struct debugfs_regset32 *regset;
885 u8 lpm_nyet_threshold;
888 const char *hsphy_interface;
890 unsigned delayed_status:1;
891 unsigned ep0_bounced:1;
892 unsigned ep0_expect_in:1;
893 unsigned has_hibernation:1;
894 unsigned has_lpm_erratum:1;
895 unsigned is_utmi_l1_suspend:1;
897 unsigned pullups_connected:1;
898 unsigned setup_packet_pending:1;
899 unsigned three_stage_setup:1;
900 unsigned usb3_lpm_capable:1;
902 unsigned disable_scramble_quirk:1;
903 unsigned u2exit_lfps_quirk:1;
904 unsigned u2ss_inp3_quirk:1;
905 unsigned req_p1p2p3_quirk:1;
906 unsigned del_p1p2p3_quirk:1;
907 unsigned del_phy_power_chg_quirk:1;
908 unsigned lfps_filter_quirk:1;
909 unsigned rx_detect_poll_quirk:1;
910 unsigned dis_u3_susphy_quirk:1;
911 unsigned dis_u2_susphy_quirk:1;
912 unsigned dis_enblslpm_quirk:1;
913 unsigned dis_rxdet_inp3_quirk:1;
915 unsigned tx_de_emphasis_quirk:1;
916 unsigned tx_de_emphasis:2;
919 /* -------------------------------------------------------------------------- */
921 /* -------------------------------------------------------------------------- */
923 struct dwc3_event_type {
929 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
930 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
931 #define DWC3_DEPEVT_XFERNOTREADY 0x03
932 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
933 #define DWC3_DEPEVT_STREAMEVT 0x06
934 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
937 * struct dwc3_event_depvt - Device Endpoint Events
938 * @one_bit: indicates this is an endpoint event (not used)
939 * @endpoint_number: number of the endpoint
940 * @endpoint_event: The event we have:
942 * 0x01 - XferComplete
943 * 0x02 - XferInProgress
944 * 0x03 - XferNotReady
945 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
949 * @reserved11_10: Reserved, don't use.
950 * @status: Indicates the status of the event. Refer to databook for
952 * @parameters: Parameters of the current event. Refer to databook for
955 struct dwc3_event_depevt {
957 u32 endpoint_number:5;
958 u32 endpoint_event:4;
962 /* Within XferNotReady */
963 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
965 /* Within XferComplete */
966 #define DEPEVT_STATUS_BUSERR (1 << 0)
967 #define DEPEVT_STATUS_SHORT (1 << 1)
968 #define DEPEVT_STATUS_IOC (1 << 2)
969 #define DEPEVT_STATUS_LST (1 << 3)
971 /* Stream event only */
972 #define DEPEVT_STREAMEVT_FOUND 1
973 #define DEPEVT_STREAMEVT_NOTFOUND 2
975 /* Control-only Status */
976 #define DEPEVT_STATUS_CONTROL_DATA 1
977 #define DEPEVT_STATUS_CONTROL_STATUS 2
979 /* In response to Start Transfer */
980 #define DEPEVT_TRANSFER_NO_RESOURCE 1
981 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
987 * struct dwc3_event_devt - Device Events
988 * @one_bit: indicates this is a non-endpoint event (not used)
989 * @device_event: indicates it's a device event. Should read as 0x00
990 * @type: indicates the type of device event.
1003 * 12 - VndrDevTstRcved
1004 * @reserved15_12: Reserved, not used
1005 * @event_info: Information about this event
1006 * @reserved31_25: Reserved, not used
1008 struct dwc3_event_devt {
1012 u32 reserved15_12:4;
1014 u32 reserved31_25:7;
1018 * struct dwc3_event_gevt - Other Core Events
1019 * @one_bit: indicates this is a non-endpoint event (not used)
1020 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1021 * @phy_port_number: self-explanatory
1022 * @reserved31_12: Reserved, not used.
1024 struct dwc3_event_gevt {
1027 u32 phy_port_number:4;
1028 u32 reserved31_12:20;
1032 * union dwc3_event - representation of Event Buffer contents
1033 * @raw: raw 32-bit event
1034 * @type: the type of the event
1035 * @depevt: Device Endpoint Event
1036 * @devt: Device Event
1037 * @gevt: Global Event
1041 struct dwc3_event_type type;
1042 struct dwc3_event_depevt depevt;
1043 struct dwc3_event_devt devt;
1044 struct dwc3_event_gevt gevt;
1048 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1050 * @param2: third parameter
1051 * @param1: second parameter
1052 * @param0: first parameter
1054 struct dwc3_gadget_ep_cmd_params {
1061 * DWC3 Features to be used as Driver Data
1064 #define DWC3_HAS_PERIPHERAL BIT(0)
1065 #define DWC3_HAS_XHCI BIT(1)
1066 #define DWC3_HAS_OTG BIT(3)
1069 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1070 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1072 /* check whether we are on the DWC_usb31 core */
1073 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1075 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1078 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1079 int dwc3_host_init(struct dwc3 *dwc);
1080 void dwc3_host_exit(struct dwc3 *dwc);
1082 static inline int dwc3_host_init(struct dwc3 *dwc)
1084 static inline void dwc3_host_exit(struct dwc3 *dwc)
1088 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1089 int dwc3_gadget_init(struct dwc3 *dwc);
1090 void dwc3_gadget_exit(struct dwc3 *dwc);
1091 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1092 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1093 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1094 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1095 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1096 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1098 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1100 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1102 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1104 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1106 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1107 enum dwc3_link_state state)
1110 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1111 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1113 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1118 /* power management interface */
1119 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1120 int dwc3_gadget_suspend(struct dwc3 *dwc);
1121 int dwc3_gadget_resume(struct dwc3 *dwc);
1123 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1128 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1132 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1134 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1135 int dwc3_ulpi_init(struct dwc3 *dwc);
1136 void dwc3_ulpi_exit(struct dwc3 *dwc);
1138 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1140 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1144 #endif /* __DRIVERS_USB_DWC3_CORE_H */