2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef __DRIVERS_USB_DWC3_CORE_H
20 #define __DRIVERS_USB_DWC3_CORE_H
22 #include <linux/device.h>
23 #include <linux/spinlock.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/dma-mapping.h>
28 #include <linux/debugfs.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/otg.h>
33 #include <linux/usb.h>
34 #include <linux/usb/hcd.h>
35 #include <linux/platform_device.h>
36 #include <linux/version.h>
37 #include <linux/ulpi/interface.h>
39 #include <linux/phy/phy.h>
41 #define DWC3_MSG_MAX 500
43 /* Global constants */
44 #define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
45 #define DWC3_EP0_BOUNCE_SIZE 512
46 #define DWC3_ENDPOINTS_NUM 32
47 #define DWC3_XHCI_RESOURCES_NUM 2
49 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
50 #define DWC3_EVENT_SIZE 4 /* bytes */
51 #define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
52 #define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
53 #define DWC3_EVENT_TYPE_MASK 0xfe
55 #define DWC3_EVENT_TYPE_DEV 0
56 #define DWC3_EVENT_TYPE_CARKIT 3
57 #define DWC3_EVENT_TYPE_I2C 4
59 #define DWC3_DEVICE_EVENT_DISCONNECT 0
60 #define DWC3_DEVICE_EVENT_RESET 1
61 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
62 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
63 #define DWC3_DEVICE_EVENT_WAKEUP 4
64 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
65 #define DWC3_DEVICE_EVENT_EOPF 6
66 #define DWC3_DEVICE_EVENT_SOF 7
67 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
68 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
69 #define DWC3_DEVICE_EVENT_OVERFLOW 11
71 #define DWC3_GEVNTCOUNT_MASK 0xfffc
72 #define DWC3_GSNPSID_MASK 0xffff0000
73 #define DWC3_GSNPSREV_MASK 0xffff
75 /* DWC3 registers memory space boundries */
76 #define DWC3_XHCI_REGS_START 0x0
77 #define DWC3_XHCI_REGS_END 0x7fff
78 #define DWC3_GLOBALS_REGS_START 0xc100
79 #define DWC3_GLOBALS_REGS_END 0xc6ff
80 #define DWC3_DEVICE_REGS_START 0xc700
81 #define DWC3_DEVICE_REGS_END 0xcbff
82 #define DWC3_OTG_REGS_START 0xcc00
83 #define DWC3_OTG_REGS_END 0xccff
85 /* Global Registers */
86 #define DWC3_GSBUSCFG0 0xc100
87 #define DWC3_GSBUSCFG1 0xc104
88 #define DWC3_GTXTHRCFG 0xc108
89 #define DWC3_GRXTHRCFG 0xc10c
90 #define DWC3_GCTL 0xc110
91 #define DWC3_GEVTEN 0xc114
92 #define DWC3_GSTS 0xc118
93 #define DWC3_GUCTL1 0xc11c
94 #define DWC3_GSNPSID 0xc120
95 #define DWC3_GGPIO 0xc124
96 #define DWC3_GUID 0xc128
97 #define DWC3_GUCTL 0xc12c
98 #define DWC3_GBUSERRADDR0 0xc130
99 #define DWC3_GBUSERRADDR1 0xc134
100 #define DWC3_GPRTBIMAP0 0xc138
101 #define DWC3_GPRTBIMAP1 0xc13c
102 #define DWC3_GHWPARAMS0 0xc140
103 #define DWC3_GHWPARAMS1 0xc144
104 #define DWC3_GHWPARAMS2 0xc148
105 #define DWC3_GHWPARAMS3 0xc14c
106 #define DWC3_GHWPARAMS4 0xc150
107 #define DWC3_GHWPARAMS5 0xc154
108 #define DWC3_GHWPARAMS6 0xc158
109 #define DWC3_GHWPARAMS7 0xc15c
110 #define DWC3_GDBGFIFOSPACE 0xc160
111 #define DWC3_GDBGLTSSM 0xc164
112 #define DWC3_GPRTBIMAP_HS0 0xc180
113 #define DWC3_GPRTBIMAP_HS1 0xc184
114 #define DWC3_GPRTBIMAP_FS0 0xc188
115 #define DWC3_GPRTBIMAP_FS1 0xc18c
117 #define DWC3_VER_NUMBER 0xc1a0
118 #define DWC3_VER_TYPE 0xc1a4
120 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
121 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
123 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
125 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
127 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
128 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
130 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
131 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
132 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
133 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
135 #define DWC3_GHWPARAMS8 0xc600
136 #define DWC3_GFLADJ 0xc630
138 /* Device Registers */
139 #define DWC3_DCFG 0xc700
140 #define DWC3_DCTL 0xc704
141 #define DWC3_DEVTEN 0xc708
142 #define DWC3_DSTS 0xc70c
143 #define DWC3_DGCMDPAR 0xc710
144 #define DWC3_DGCMD 0xc714
145 #define DWC3_DALEPENA 0xc720
146 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
147 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
148 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
149 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
152 #define DWC3_OCFG 0xcc00
153 #define DWC3_OCTL 0xcc04
154 #define DWC3_OEVT 0xcc08
155 #define DWC3_OEVTEN 0xcc0C
156 #define DWC3_OSTS 0xcc10
160 /* Global Configuration Register */
161 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
162 #define DWC3_GCTL_U2RSTECN (1 << 16)
163 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
164 #define DWC3_GCTL_CLK_BUS (0)
165 #define DWC3_GCTL_CLK_PIPE (1)
166 #define DWC3_GCTL_CLK_PIPEHALF (2)
167 #define DWC3_GCTL_CLK_MASK (3)
169 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
170 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
171 #define DWC3_GCTL_PRTCAP_HOST 1
172 #define DWC3_GCTL_PRTCAP_DEVICE 2
173 #define DWC3_GCTL_PRTCAP_OTG 3
175 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
176 #define DWC3_GCTL_SOFITPSYNC (1 << 10)
177 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
178 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
179 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
180 #define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
181 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
182 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
184 /* Global USB2 PHY Configuration Register */
185 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
186 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
187 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
188 #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
189 #define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
190 #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
191 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
192 #define DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT 10
193 #define USBTRDTIM_UTMI_8_BIT 9
194 #define USBTRDTIM_UTMI_16_BIT 5
196 /* Global USB2 PHY Vendor Control Register */
197 #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
198 #define DWC3_GUSB2PHYACC_BUSY (1 << 23)
199 #define DWC3_GUSB2PHYACC_WRITE (1 << 22)
200 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
201 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
202 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
204 /* Global USB3 PIPE Control Register */
205 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
206 #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
207 #define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
208 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
209 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
210 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
211 #define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
212 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
213 #define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
214 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
215 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
216 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
218 /* Global TX Fifo Size Register */
219 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
220 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
222 /* Global Event Size Registers */
223 #define DWC3_GEVNTSIZ_INTMASK (1 << 31)
224 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
226 /* Global HWPARAMS0 Register */
227 #define DWC3_GHWPARAMS0_USB3_MODE(n) ((n) & 7)
228 #define DWC3_GHWPARAMS0_USB3_DRD 2
230 /* Global HWPARAMS1 Register */
231 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
232 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
233 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
234 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
235 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
236 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
238 /* Global HWPARAMS3 Register */
239 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
240 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
241 #define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1
242 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
243 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
244 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
245 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
246 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
247 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
248 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
249 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
251 /* Global HWPARAMS4 Register */
252 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
253 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
255 /* Global HWPARAMS6 Register */
256 #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
258 /* Global Frame Length Adjustment Register */
259 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
260 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
262 /* Device Configuration Register */
263 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
264 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
266 #define DWC3_DCFG_SPEED_MASK (7 << 0)
267 #define DWC3_DCFG_SUPERSPEED (4 << 0)
268 #define DWC3_DCFG_HIGHSPEED (0 << 0)
269 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
270 #define DWC3_DCFG_LOWSPEED (2 << 0)
271 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
273 #define DWC3_DCFG_LPM_CAP (1 << 22)
275 /* Device Control Register */
276 #define DWC3_DCTL_RUN_STOP (1 << 31)
277 #define DWC3_DCTL_CSFTRST (1 << 30)
278 #define DWC3_DCTL_LSFTRST (1 << 29)
280 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
281 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
283 #define DWC3_DCTL_APPL1RES (1 << 23)
285 /* These apply for core versions 1.87a and earlier */
286 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
287 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
288 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
289 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
290 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
291 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
292 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
294 /* These apply for core versions 1.94a and later */
295 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
296 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
298 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
299 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
300 #define DWC3_DCTL_CRS (1 << 17)
301 #define DWC3_DCTL_CSS (1 << 16)
303 #define DWC3_DCTL_INITU2ENA (1 << 12)
304 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
305 #define DWC3_DCTL_INITU1ENA (1 << 10)
306 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
307 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
309 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
310 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
312 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
313 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
314 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
315 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
316 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
317 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
318 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
320 /* Device Event Enable Register */
321 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
322 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
323 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
324 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
325 #define DWC3_DEVTEN_SOFEN (1 << 7)
326 #define DWC3_DEVTEN_EOPFEN (1 << 6)
327 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
328 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
329 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
330 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
331 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
332 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
334 /* Device Status Register */
335 #define DWC3_DSTS_DCNRD (1 << 29)
337 /* This applies for core versions 1.87a and earlier */
338 #define DWC3_DSTS_PWRUPREQ (1 << 24)
340 /* These apply for core versions 1.94a and later */
341 #define DWC3_DSTS_RSS (1 << 25)
342 #define DWC3_DSTS_SSS (1 << 24)
344 #define DWC3_DSTS_COREIDLE (1 << 23)
345 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
347 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
348 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
350 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
352 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
353 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
355 #define DWC3_DSTS_CONNECTSPD (7 << 0)
357 #define DWC3_DSTS_SUPERSPEED (4 << 0)
358 #define DWC3_DSTS_HIGHSPEED (0 << 0)
359 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
360 #define DWC3_DSTS_LOWSPEED (2 << 0)
361 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
363 /* Device Generic Command Register */
364 #define DWC3_DGCMD_SET_LMP 0x01
365 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
366 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
368 /* These apply for core versions 1.94a and later */
369 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
370 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
372 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
373 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
374 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
375 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
377 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
378 #define DWC3_DGCMD_CMDACT (1 << 10)
379 #define DWC3_DGCMD_CMDIOC (1 << 8)
381 /* Device Generic Command Parameter Register */
382 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
383 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
384 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
385 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
386 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
387 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
389 /* Device Endpoint Command Register */
390 #define DWC3_DEPCMD_PARAM_SHIFT 16
391 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
392 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
393 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
394 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
395 #define DWC3_DEPCMD_CMDACT (1 << 10)
396 #define DWC3_DEPCMD_CMDIOC (1 << 8)
398 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
399 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
400 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
401 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
402 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
403 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
404 /* This applies for core versions 1.90a and earlier */
405 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
406 /* This applies for core versions 1.94a and later */
407 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
408 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
409 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
411 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
412 #define DWC3_DALEPENA_EP(n) (1 << n)
414 #define DWC3_DEPCMD_TYPE_CONTROL 0
415 #define DWC3_DEPCMD_TYPE_ISOC 1
416 #define DWC3_DEPCMD_TYPE_BULK 2
417 #define DWC3_DEPCMD_TYPE_INTR 3
424 * struct dwc3_event_buffer - Software event buffer representation
426 * @length: size of this buffer
427 * @lpos: event offset
428 * @count: cache of last read event count register
429 * @flags: flags related to this event buffer
431 * @dwc: pointer to DWC controller
433 struct dwc3_event_buffer {
440 #define DWC3_EVENT_PENDING BIT(0)
447 #define DWC3_EP_FLAG_STALLED (1 << 0)
448 #define DWC3_EP_FLAG_WEDGED (1 << 1)
450 #define DWC3_EP_DIRECTION_TX true
451 #define DWC3_EP_DIRECTION_RX false
453 #define DWC3_TRB_NUM 32
454 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
457 * struct dwc3_ep - device side endpoint representation
458 * @endpoint: usb endpoint
459 * @request_list: list of requests for this endpoint
460 * @req_queued: list of requests on this ep which have TRBs setup
461 * @trb_pool: array of transaction buffers
462 * @trb_pool_dma: dma address of @trb_pool
463 * @free_slot: next slot which is going to be used
464 * @busy_slot: first slot which is owned by HW
465 * @desc: usb_endpoint_descriptor pointer
466 * @dwc: pointer to DWC controller
467 * @saved_state: ep state saved during hibernation
468 * @flags: endpoint flags (wedged, stalled, ...)
469 * @number: endpoint number (1 - 15)
470 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
471 * @resource_index: Resource transfer index
472 * @interval: the interval on which the ISOC transfer is started
473 * @name: a human readable name e.g. ep1out-bulk
474 * @direction: true for TX, false for RX
475 * @stream_capable: true when streams are enabled
478 struct usb_ep endpoint;
479 struct list_head request_list;
480 struct list_head req_queued;
482 struct dwc3_trb *trb_pool;
483 dma_addr_t trb_pool_dma;
486 const struct usb_ss_ep_comp_descriptor *comp_desc;
491 #define DWC3_EP_ENABLED (1 << 0)
492 #define DWC3_EP_STALL (1 << 1)
493 #define DWC3_EP_WEDGE (1 << 2)
494 #define DWC3_EP_BUSY (1 << 4)
495 #define DWC3_EP_PENDING_REQUEST (1 << 5)
496 #define DWC3_EP_MISSED_ISOC (1 << 6)
498 /* This last one is specific to EP0 */
499 #define DWC3_EP0_DIR_IN (1 << 31)
508 unsigned direction:1;
509 unsigned stream_capable:1;
513 DWC3_PHY_UNKNOWN = 0,
519 DWC3_EP0_UNKNOWN = 0,
522 DWC3_EP0_NRDY_STATUS,
525 enum dwc3_ep0_state {
532 enum dwc3_link_state {
534 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
535 DWC3_LINK_STATE_U1 = 0x01,
536 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
537 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
538 DWC3_LINK_STATE_SS_DIS = 0x04,
539 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
540 DWC3_LINK_STATE_SS_INACT = 0x06,
541 DWC3_LINK_STATE_POLL = 0x07,
542 DWC3_LINK_STATE_RECOV = 0x08,
543 DWC3_LINK_STATE_HRESET = 0x09,
544 DWC3_LINK_STATE_CMPLY = 0x0a,
545 DWC3_LINK_STATE_LPBK = 0x0b,
546 DWC3_LINK_STATE_RESET = 0x0e,
547 DWC3_LINK_STATE_RESUME = 0x0f,
548 DWC3_LINK_STATE_MASK = 0x0f,
551 /* TRB Length, PCM and Status */
552 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
553 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
554 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
555 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
557 #define DWC3_TRBSTS_OK 0
558 #define DWC3_TRBSTS_MISSED_ISOC 1
559 #define DWC3_TRBSTS_SETUP_PENDING 2
560 #define DWC3_TRB_STS_XFER_IN_PROG 4
563 #define DWC3_TRB_CTRL_HWO (1 << 0)
564 #define DWC3_TRB_CTRL_LST (1 << 1)
565 #define DWC3_TRB_CTRL_CHN (1 << 2)
566 #define DWC3_TRB_CTRL_CSP (1 << 3)
567 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
568 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
569 #define DWC3_TRB_CTRL_IOC (1 << 11)
570 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
572 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
573 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
574 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
575 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
576 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
577 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
578 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
579 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
582 * struct dwc3_trb - transfer request block (hw format)
596 * dwc3_hwparams - copy of HWPARAMS registers
597 * @hwparams0 - GHWPARAMS0
598 * @hwparams1 - GHWPARAMS1
599 * @hwparams2 - GHWPARAMS2
600 * @hwparams3 - GHWPARAMS3
601 * @hwparams4 - GHWPARAMS4
602 * @hwparams5 - GHWPARAMS5
603 * @hwparams6 - GHWPARAMS6
604 * @hwparams7 - GHWPARAMS7
605 * @hwparams8 - GHWPARAMS8
607 struct dwc3_hwparams {
620 #define DWC3_MODE(n) ((n) & 0x7)
622 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
625 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
628 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
629 #define DWC3_NUM_EPS_MASK (0x3f << 12)
630 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
631 (DWC3_NUM_EPS_MASK)) >> 12)
632 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
633 (DWC3_NUM_IN_EPS_MASK)) >> 18)
636 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
638 struct dwc3_request {
639 struct usb_request request;
640 struct list_head list;
645 struct dwc3_trb *trb;
648 unsigned direction:1;
654 * struct dwc3_scratchpad_array - hibernation scratchpad array
655 * (format defined by hw)
657 struct dwc3_scratchpad_array {
658 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
662 * struct dwc3 - representation of our controller
663 * @ctrl_req: usb control request which is used for ep0
664 * @ep0_trb: trb which is used for the ctrl_req
665 * @ep0_bounce: bounce buffer for ep0
666 * @zlp_buf: used when request->zero is set
667 * @setup_buf: used while precessing STD USB requests
668 * @ctrl_req_addr: dma address of ctrl_req
669 * @ep0_trb: dma address of ep0_trb
670 * @ep0_usb_req: dummy req used while handling STD USB requests
671 * @ep0_bounce_addr: dma address of ep0_bounce
672 * @scratch_addr: dma address of scratchbuf
673 * @lock: for synchronizing
674 * @dev: pointer to our struct device
675 * @xhci: pointer to our xHCI child
676 * @event_buffer_list: a list of event buffers
677 * @gadget: device side representation of the peripheral controller
678 * @gadget_driver: pointer to the gadget driver
679 * @regs: base address for our registers
680 * @regs_size: address space size
681 * @nr_scratch: number of scratch buffers
682 * @num_event_buffers: calculated number of event buffers
683 * @u1u2: only used on revisions <1.83a for workaround
684 * @maximum_speed: maximum speed requested (mainly for testing purposes)
685 * @revision: revision register contents
686 * @dr_mode: requested mode of operation
687 * @usb2_phy: pointer to USB2 PHY
688 * @usb3_phy: pointer to USB3 PHY
689 * @usb2_generic_phy: pointer to USB2 PHY
690 * @usb3_generic_phy: pointer to USB3 PHY
691 * @ulpi: pointer to ulpi interface
692 * @dcfg: saved contents of DCFG register
693 * @gctl: saved contents of GCTL register
694 * @isoch_delay: wValue from Set Isochronous Delay request;
695 * @u2sel: parameter from Set SEL request.
696 * @u2pel: parameter from Set SEL request.
697 * @u1sel: parameter from Set SEL request.
698 * @u1pel: parameter from Set SEL request.
699 * @num_out_eps: number of out endpoints
700 * @num_in_eps: number of in endpoints
701 * @ep0_next_event: hold the next expected event
702 * @ep0state: state of endpoint zero
703 * @link_state: link state
704 * @speed: device speed (super, high, full, low)
705 * @mem: points to start of memory which is used for this struct.
706 * @hwparams: copy of hwparams registers
707 * @root: debugfs root folder pointer
708 * @regset: debugfs pointer to regdump file
709 * @test_mode: true when we're entering a USB test mode
710 * @test_mode_nr: test feature selector
711 * @lpm_nyet_threshold: LPM NYET response threshold
712 * @hird_threshold: HIRD threshold
713 * @hsphy_interface: "utmi" or "ulpi"
714 * @delayed_status: true when gadget driver asks for delayed status
715 * @ep0_bounced: true when we used bounce buffer
716 * @ep0_expect_in: true when we expect a DATA IN transfer
717 * @has_hibernation: true when dwc3 was configured with Hibernation
718 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
719 * there's now way for software to detect this in runtime.
720 * @is_utmi_l1_suspend: the core asserts output signal
722 * 1 - utmi_l1_suspend_n
723 * @is_fpga: true when we are using the FPGA board
724 * @needs_fifo_resize: not all users might want fifo resizing, flag it
725 * @enabled: true when gadget driver is ready
726 * @pullups_connected: true when Run/Stop bit is set
727 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
728 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
729 * @start_config_issued: true when StartConfig command has been issued
730 * @three_stage_setup: set if we perform a three phase setup
731 * @usb3_lpm_capable: set if hadrware supports Link Power Management
732 * @phyif_utmi_16_bits: set if configure the core to support UTMI+ PHY
733 * with an 16-bit interface
734 * @disable_scramble_quirk: set if we enable the disable scramble quirk
735 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
736 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
737 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
738 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
739 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
740 * @lfps_filter_quirk: set if we enable LFPS filter quirk
741 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
742 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
743 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
744 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
745 * disabling the suspend signal to the PHY.
746 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
747 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
748 * provide a free-running PHY clock.
749 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
751 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
752 * @tx_de_emphasis: Tx de-emphasis value
753 * 0 - -6dB de-emphasis
754 * 1 - -3.5dB de-emphasis
759 struct usb_ctrlrequest *ctrl_req;
760 struct dwc3_trb *ep0_trb;
765 dma_addr_t ctrl_req_addr;
766 dma_addr_t ep0_trb_addr;
767 dma_addr_t ep0_bounce_addr;
768 dma_addr_t scratch_addr;
769 struct dwc3_request ep0_usb_req;
776 struct platform_device *xhci;
777 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
779 struct dwc3_event_buffer **ev_buffs;
780 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
782 struct usb_gadget gadget;
783 struct usb_gadget_driver *gadget_driver;
785 struct usb_phy *usb2_phy;
786 struct usb_phy *usb3_phy;
788 struct phy *usb2_generic_phy;
789 struct phy *usb3_generic_phy;
796 enum usb_dr_mode dr_mode;
798 /* used for suspend/resume */
803 u32 num_event_buffers;
808 * All 3.1 IP version constants are greater than the 3.0 IP
809 * version constants. This works for most version checks in
810 * dwc3. However, in the future, this may not apply as
811 * features may be developed on newer versions of the 3.0 IP
812 * that are not in the 3.1 IP.
816 #define DWC3_REVISION_173A 0x5533173a
817 #define DWC3_REVISION_175A 0x5533175a
818 #define DWC3_REVISION_180A 0x5533180a
819 #define DWC3_REVISION_183A 0x5533183a
820 #define DWC3_REVISION_185A 0x5533185a
821 #define DWC3_REVISION_187A 0x5533187a
822 #define DWC3_REVISION_188A 0x5533188a
823 #define DWC3_REVISION_190A 0x5533190a
824 #define DWC3_REVISION_194A 0x5533194a
825 #define DWC3_REVISION_200A 0x5533200a
826 #define DWC3_REVISION_202A 0x5533202a
827 #define DWC3_REVISION_210A 0x5533210a
828 #define DWC3_REVISION_220A 0x5533220a
829 #define DWC3_REVISION_230A 0x5533230a
830 #define DWC3_REVISION_240A 0x5533240a
831 #define DWC3_REVISION_250A 0x5533250a
832 #define DWC3_REVISION_260A 0x5533260a
833 #define DWC3_REVISION_270A 0x5533270a
834 #define DWC3_REVISION_280A 0x5533280a
837 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
838 * just so dwc31 revisions are always larger than dwc3.
840 #define DWC3_REVISION_IS_DWC31 0x80000000
841 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31)
843 enum dwc3_ep0_next ep0_next_event;
844 enum dwc3_ep0_state ep0state;
845 enum dwc3_link_state link_state;
860 struct dwc3_hwparams hwparams;
862 struct debugfs_regset32 *regset;
866 u8 lpm_nyet_threshold;
869 const char *hsphy_interface;
871 unsigned delayed_status:1;
872 unsigned ep0_bounced:1;
873 unsigned ep0_expect_in:1;
874 unsigned has_hibernation:1;
875 unsigned has_lpm_erratum:1;
876 unsigned is_utmi_l1_suspend:1;
878 unsigned needs_fifo_resize:1;
880 unsigned pullups_connected:1;
881 unsigned resize_fifos:1;
882 unsigned setup_packet_pending:1;
883 unsigned three_stage_setup:1;
884 unsigned usb3_lpm_capable:1;
885 unsigned phyif_utmi_16_bits:1;
887 unsigned disable_scramble_quirk:1;
888 unsigned u2exit_lfps_quirk:1;
889 unsigned u2ss_inp3_quirk:1;
890 unsigned req_p1p2p3_quirk:1;
891 unsigned del_p1p2p3_quirk:1;
892 unsigned del_phy_power_chg_quirk:1;
893 unsigned lfps_filter_quirk:1;
894 unsigned rx_detect_poll_quirk:1;
895 unsigned dis_u3_susphy_quirk:1;
896 unsigned dis_u2_susphy_quirk:1;
897 unsigned dis_enblslpm_quirk:1;
898 unsigned dis_u2_freeclk_exists_quirk:1;
899 unsigned dis_del_phy_power_chg_quirk:1;
901 unsigned tx_de_emphasis_quirk:1;
902 unsigned tx_de_emphasis:2;
905 /* -------------------------------------------------------------------------- */
907 /* -------------------------------------------------------------------------- */
909 struct dwc3_event_type {
915 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
916 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
917 #define DWC3_DEPEVT_XFERNOTREADY 0x03
918 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
919 #define DWC3_DEPEVT_STREAMEVT 0x06
920 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
923 * struct dwc3_event_depvt - Device Endpoint Events
924 * @one_bit: indicates this is an endpoint event (not used)
925 * @endpoint_number: number of the endpoint
926 * @endpoint_event: The event we have:
928 * 0x01 - XferComplete
929 * 0x02 - XferInProgress
930 * 0x03 - XferNotReady
931 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
935 * @reserved11_10: Reserved, don't use.
936 * @status: Indicates the status of the event. Refer to databook for
938 * @parameters: Parameters of the current event. Refer to databook for
941 struct dwc3_event_depevt {
943 u32 endpoint_number:5;
944 u32 endpoint_event:4;
948 /* Within XferNotReady */
949 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
951 /* Within XferComplete */
952 #define DEPEVT_STATUS_BUSERR (1 << 0)
953 #define DEPEVT_STATUS_SHORT (1 << 1)
954 #define DEPEVT_STATUS_IOC (1 << 2)
955 #define DEPEVT_STATUS_LST (1 << 3)
957 /* Stream event only */
958 #define DEPEVT_STREAMEVT_FOUND 1
959 #define DEPEVT_STREAMEVT_NOTFOUND 2
961 /* Control-only Status */
962 #define DEPEVT_STATUS_CONTROL_DATA 1
963 #define DEPEVT_STATUS_CONTROL_STATUS 2
969 * struct dwc3_event_devt - Device Events
970 * @one_bit: indicates this is a non-endpoint event (not used)
971 * @device_event: indicates it's a device event. Should read as 0x00
972 * @type: indicates the type of device event.
985 * 12 - VndrDevTstRcved
986 * @reserved15_12: Reserved, not used
987 * @event_info: Information about this event
988 * @reserved31_25: Reserved, not used
990 struct dwc3_event_devt {
1000 * struct dwc3_event_gevt - Other Core Events
1001 * @one_bit: indicates this is a non-endpoint event (not used)
1002 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1003 * @phy_port_number: self-explanatory
1004 * @reserved31_12: Reserved, not used.
1006 struct dwc3_event_gevt {
1009 u32 phy_port_number:4;
1010 u32 reserved31_12:20;
1014 * union dwc3_event - representation of Event Buffer contents
1015 * @raw: raw 32-bit event
1016 * @type: the type of the event
1017 * @depevt: Device Endpoint Event
1018 * @devt: Device Event
1019 * @gevt: Global Event
1023 struct dwc3_event_type type;
1024 struct dwc3_event_depevt depevt;
1025 struct dwc3_event_devt devt;
1026 struct dwc3_event_gevt gevt;
1030 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1032 * @param2: third parameter
1033 * @param1: second parameter
1034 * @param0: first parameter
1036 struct dwc3_gadget_ep_cmd_params {
1043 * DWC3 Features to be used as Driver Data
1046 #define DWC3_HAS_PERIPHERAL BIT(0)
1047 #define DWC3_HAS_XHCI BIT(1)
1048 #define DWC3_HAS_OTG BIT(3)
1051 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1052 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
1053 int dwc3_soft_reset(struct dwc3 *dwc);
1054 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1055 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1056 bool dwc3_force_mode(struct dwc3 *dwc, u32 mode);
1058 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1059 int dwc3_host_init(struct dwc3 *dwc);
1060 void dwc3_host_exit(struct dwc3 *dwc);
1062 static inline int dwc3_host_init(struct dwc3 *dwc)
1064 static inline void dwc3_host_exit(struct dwc3 *dwc)
1068 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1069 int dwc3_gadget_init(struct dwc3 *dwc);
1070 void dwc3_gadget_exit(struct dwc3 *dwc);
1071 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1072 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1073 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1074 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1075 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1076 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1077 int dwc3_gadget_restart(struct dwc3 *dwc, bool start);
1079 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1081 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1083 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1085 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1087 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1088 enum dwc3_link_state state)
1091 static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1092 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1094 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1097 static inline int dwc3_gadget_restart(struct dwc3 *dwc, bool start)
1101 /* power management interface */
1102 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1103 int dwc3_gadget_suspend(struct dwc3 *dwc);
1104 int dwc3_gadget_resume(struct dwc3 *dwc);
1106 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1111 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1115 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1117 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1118 int dwc3_ulpi_init(struct dwc3 *dwc);
1119 void dwc3_ulpi_exit(struct dwc3 *dwc);
1121 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1123 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1127 #endif /* __DRIVERS_USB_DWC3_CORE_H */