2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/platform_data/dwc3-omap.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ioport.h>
30 #include <linux/of_platform.h>
31 #include <linux/extcon.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/usb/otg.h>
37 * All these registers belong to OMAP's Wrapper around the
38 * DesignWare USB3 Core.
41 #define USBOTGSS_REVISION 0x0000
42 #define USBOTGSS_SYSCONFIG 0x0010
43 #define USBOTGSS_IRQ_EOI 0x0020
44 #define USBOTGSS_EOI_OFFSET 0x0008
45 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
46 #define USBOTGSS_IRQSTATUS_0 0x0028
47 #define USBOTGSS_IRQENABLE_SET_0 0x002c
48 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
49 #define USBOTGSS_IRQ0_OFFSET 0x0004
50 #define USBOTGSS_IRQSTATUS_RAW_1 0x0030
51 #define USBOTGSS_IRQSTATUS_1 0x0034
52 #define USBOTGSS_IRQENABLE_SET_1 0x0038
53 #define USBOTGSS_IRQENABLE_CLR_1 0x003c
54 #define USBOTGSS_IRQSTATUS_RAW_2 0x0040
55 #define USBOTGSS_IRQSTATUS_2 0x0044
56 #define USBOTGSS_IRQENABLE_SET_2 0x0048
57 #define USBOTGSS_IRQENABLE_CLR_2 0x004c
58 #define USBOTGSS_IRQSTATUS_RAW_3 0x0050
59 #define USBOTGSS_IRQSTATUS_3 0x0054
60 #define USBOTGSS_IRQENABLE_SET_3 0x0058
61 #define USBOTGSS_IRQENABLE_CLR_3 0x005c
62 #define USBOTGSS_IRQSTATUS_EOI_MISC 0x0030
63 #define USBOTGSS_IRQSTATUS_RAW_MISC 0x0034
64 #define USBOTGSS_IRQSTATUS_MISC 0x0038
65 #define USBOTGSS_IRQENABLE_SET_MISC 0x003c
66 #define USBOTGSS_IRQENABLE_CLR_MISC 0x0040
67 #define USBOTGSS_IRQMISC_OFFSET 0x03fc
68 #define USBOTGSS_UTMI_OTG_CTRL 0x0080
69 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
70 #define USBOTGSS_UTMI_OTG_OFFSET 0x0480
71 #define USBOTGSS_TXFIFO_DEPTH 0x0508
72 #define USBOTGSS_RXFIFO_DEPTH 0x050c
73 #define USBOTGSS_MMRAM_OFFSET 0x0100
74 #define USBOTGSS_FLADJ 0x0104
75 #define USBOTGSS_DEBUG_CFG 0x0108
76 #define USBOTGSS_DEBUG_DATA 0x010c
77 #define USBOTGSS_DEV_EBC_EN 0x0110
78 #define USBOTGSS_DEBUG_OFFSET 0x0600
80 /* SYSCONFIG REGISTER */
81 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
83 /* IRQ_EOI REGISTER */
84 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
87 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
90 #define USBOTGSS_IRQMISC_DMADISABLECLR (1 << 17)
91 #define USBOTGSS_IRQMISC_OEVT (1 << 16)
92 #define USBOTGSS_IRQMISC_DRVVBUS_RISE (1 << 13)
93 #define USBOTGSS_IRQMISC_CHRGVBUS_RISE (1 << 12)
94 #define USBOTGSS_IRQMISC_DISCHRGVBUS_RISE (1 << 11)
95 #define USBOTGSS_IRQMISC_IDPULLUP_RISE (1 << 8)
96 #define USBOTGSS_IRQMISC_DRVVBUS_FALL (1 << 5)
97 #define USBOTGSS_IRQMISC_CHRGVBUS_FALL (1 << 4)
98 #define USBOTGSS_IRQMISC_DISCHRGVBUS_FALL (1 << 3)
99 #define USBOTGSS_IRQMISC_IDPULLUP_FALL (1 << 0)
101 /* UTMI_OTG_CTRL REGISTER */
102 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
103 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
104 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
105 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
107 /* UTMI_OTG_STATUS REGISTER */
108 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
109 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
110 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
111 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
112 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
113 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
114 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
131 struct extcon_specific_cable_nb extcon_vbus_dev;
132 struct extcon_specific_cable_nb extcon_id_dev;
133 struct notifier_block vbus_nb;
134 struct notifier_block id_nb;
136 struct regulator *vbus_reg;
139 enum omap_dwc3_vbus_id_status {
143 OMAP_DWC3_VBUS_VALID,
146 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
148 return readl(base + offset);
151 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
153 writel(value, base + offset);
156 static u32 dwc3_omap_read_utmi_status(struct dwc3_omap *omap)
158 return dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS +
159 omap->utmi_otg_offset);
162 static void dwc3_omap_write_utmi_status(struct dwc3_omap *omap, u32 value)
164 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS +
165 omap->utmi_otg_offset, value);
169 static u32 dwc3_omap_read_irq0_status(struct dwc3_omap *omap)
171 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0 -
175 static void dwc3_omap_write_irq0_status(struct dwc3_omap *omap, u32 value)
177 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0 -
178 omap->irq0_offset, value);
182 static u32 dwc3_omap_read_irqmisc_status(struct dwc3_omap *omap)
184 return dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_MISC +
185 omap->irqmisc_offset);
188 static void dwc3_omap_write_irqmisc_status(struct dwc3_omap *omap, u32 value)
190 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_MISC +
191 omap->irqmisc_offset, value);
195 static void dwc3_omap_write_irqmisc_set(struct dwc3_omap *omap, u32 value)
197 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_MISC +
198 omap->irqmisc_offset, value);
202 static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value)
204 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0 -
205 omap->irq0_offset, value);
208 static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,
209 enum omap_dwc3_vbus_id_status status)
215 case OMAP_DWC3_ID_GROUND:
216 dev_dbg(omap->dev, "ID GND\n");
218 if (omap->vbus_reg) {
219 ret = regulator_enable(omap->vbus_reg);
221 dev_dbg(omap->dev, "regulator enable failed\n");
226 val = dwc3_omap_read_utmi_status(omap);
227 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
228 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
229 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
230 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
231 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
232 dwc3_omap_write_utmi_status(omap, val);
235 case OMAP_DWC3_VBUS_VALID:
236 dev_dbg(omap->dev, "VBUS Connect\n");
238 val = dwc3_omap_read_utmi_status(omap);
239 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
240 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
241 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
242 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
243 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
244 dwc3_omap_write_utmi_status(omap, val);
247 case OMAP_DWC3_ID_FLOAT:
249 regulator_disable(omap->vbus_reg);
251 case OMAP_DWC3_VBUS_OFF:
252 dev_dbg(omap->dev, "VBUS Disconnect\n");
254 val = dwc3_omap_read_utmi_status(omap);
255 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
256 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
257 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
258 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
259 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
260 dwc3_omap_write_utmi_status(omap, val);
264 dev_dbg(omap->dev, "invalid state\n");
268 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
270 struct dwc3_omap *omap = _omap;
273 reg = dwc3_omap_read_irqmisc_status(omap);
275 if (reg & USBOTGSS_IRQMISC_DMADISABLECLR) {
276 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
277 omap->dma_status = false;
280 if (reg & USBOTGSS_IRQMISC_OEVT)
281 dev_dbg(omap->dev, "OTG Event\n");
283 if (reg & USBOTGSS_IRQMISC_DRVVBUS_RISE)
284 dev_dbg(omap->dev, "DRVVBUS Rise\n");
286 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_RISE)
287 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
289 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_RISE)
290 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
292 if (reg & USBOTGSS_IRQMISC_IDPULLUP_RISE)
293 dev_dbg(omap->dev, "IDPULLUP Rise\n");
295 if (reg & USBOTGSS_IRQMISC_DRVVBUS_FALL)
296 dev_dbg(omap->dev, "DRVVBUS Fall\n");
298 if (reg & USBOTGSS_IRQMISC_CHRGVBUS_FALL)
299 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
301 if (reg & USBOTGSS_IRQMISC_DISCHRGVBUS_FALL)
302 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
304 if (reg & USBOTGSS_IRQMISC_IDPULLUP_FALL)
305 dev_dbg(omap->dev, "IDPULLUP Fall\n");
307 dwc3_omap_write_irqmisc_status(omap, reg);
309 reg = dwc3_omap_read_irq0_status(omap);
311 dwc3_omap_write_irq0_status(omap, reg);
316 static int dwc3_omap_remove_core(struct device *dev, void *c)
318 struct platform_device *pdev = to_platform_device(dev);
320 of_device_unregister(pdev);
325 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
329 /* enable all IRQs */
330 reg = USBOTGSS_IRQO_COREIRQ_ST;
331 dwc3_omap_write_irq0_set(omap, reg);
333 reg = (USBOTGSS_IRQMISC_OEVT |
334 USBOTGSS_IRQMISC_DRVVBUS_RISE |
335 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
336 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
337 USBOTGSS_IRQMISC_IDPULLUP_RISE |
338 USBOTGSS_IRQMISC_DRVVBUS_FALL |
339 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
340 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
341 USBOTGSS_IRQMISC_IDPULLUP_FALL);
343 dwc3_omap_write_irqmisc_set(omap, reg);
346 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
348 /* disable all IRQs */
349 dwc3_omap_write_irqmisc_set(omap, 0x00);
350 dwc3_omap_write_irq0_set(omap, 0x00);
353 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
355 static int dwc3_omap_id_notifier(struct notifier_block *nb,
356 unsigned long event, void *ptr)
358 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, id_nb);
361 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
363 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_FLOAT);
368 static int dwc3_omap_vbus_notifier(struct notifier_block *nb,
369 unsigned long event, void *ptr)
371 struct dwc3_omap *omap = container_of(nb, struct dwc3_omap, vbus_nb);
374 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
376 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_OFF);
381 static void dwc3_omap_map_offset(struct dwc3_omap *omap)
383 struct device_node *node = omap->dev->of_node;
386 * Differentiate between OMAP5 and AM437x.
388 * For OMAP5(ES2.0) and AM437x wrapper revision is same, even
389 * though there are changes in wrapper register offsets.
391 * Using dt compatible to differentiate AM437x.
393 if (of_device_is_compatible(node, "ti,am437x-dwc3")) {
394 omap->irq_eoi_offset = USBOTGSS_EOI_OFFSET;
395 omap->irq0_offset = USBOTGSS_IRQ0_OFFSET;
396 omap->irqmisc_offset = USBOTGSS_IRQMISC_OFFSET;
397 omap->utmi_otg_offset = USBOTGSS_UTMI_OTG_OFFSET;
398 omap->debug_offset = USBOTGSS_DEBUG_OFFSET;
402 static void dwc3_omap_set_utmi_mode(struct dwc3_omap *omap)
405 struct device_node *node = omap->dev->of_node;
408 reg = dwc3_omap_read_utmi_status(omap);
410 of_property_read_u32(node, "utmi-mode", &utmi_mode);
413 case DWC3_OMAP_UTMI_MODE_SW:
414 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
416 case DWC3_OMAP_UTMI_MODE_HW:
417 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
420 dev_dbg(omap->dev, "UNKNOWN utmi mode %d\n", utmi_mode);
423 dwc3_omap_write_utmi_status(omap, reg);
426 static int dwc3_omap_extcon_register(struct dwc3_omap *omap)
429 struct device_node *node = omap->dev->of_node;
430 struct extcon_dev *edev;
432 if (of_property_read_bool(node, "extcon")) {
433 edev = extcon_get_edev_by_phandle(omap->dev, 0);
435 dev_vdbg(omap->dev, "couldn't get extcon device\n");
436 return -EPROBE_DEFER;
439 omap->vbus_nb.notifier_call = dwc3_omap_vbus_notifier;
440 ret = extcon_register_interest(&omap->extcon_vbus_dev,
444 dev_vdbg(omap->dev, "failed to register notifier for USB\n");
446 omap->id_nb.notifier_call = dwc3_omap_id_notifier;
447 ret = extcon_register_interest(&omap->extcon_id_dev,
448 edev->name, "USB-HOST",
451 dev_vdbg(omap->dev, "failed to register notifier for USB-HOST\n");
453 if (extcon_get_cable_state(edev, "USB") == true)
454 dwc3_omap_set_mailbox(omap, OMAP_DWC3_VBUS_VALID);
455 if (extcon_get_cable_state(edev, "USB-HOST") == true)
456 dwc3_omap_set_mailbox(omap, OMAP_DWC3_ID_GROUND);
462 static int dwc3_omap_probe(struct platform_device *pdev)
464 struct device_node *node = pdev->dev.of_node;
466 struct dwc3_omap *omap;
467 struct resource *res;
468 struct device *dev = &pdev->dev;
469 struct regulator *vbus_reg = NULL;
479 dev_err(dev, "device node not found\n");
483 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
485 dev_err(dev, "not enough memory\n");
489 platform_set_drvdata(pdev, omap);
491 irq = platform_get_irq(pdev, 0);
493 dev_err(dev, "missing IRQ resource\n");
497 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
498 base = devm_ioremap_resource(dev, res);
500 return PTR_ERR(base);
502 if (of_property_read_bool(node, "vbus-supply")) {
503 vbus_reg = devm_regulator_get(dev, "vbus");
504 if (IS_ERR(vbus_reg)) {
505 dev_err(dev, "vbus init failed\n");
506 return PTR_ERR(vbus_reg);
513 omap->vbus_reg = vbus_reg;
514 dev->dma_mask = &dwc3_omap_dma_mask;
516 pm_runtime_enable(dev);
517 ret = pm_runtime_get_sync(dev);
519 dev_err(dev, "get_sync failed with err %d\n", ret);
523 dwc3_omap_map_offset(omap);
524 dwc3_omap_set_utmi_mode(omap);
526 /* check the DMA Status */
527 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
528 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
530 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
533 dev_err(dev, "failed to request IRQ #%d --> %d\n",
538 dwc3_omap_enable_irqs(omap);
540 ret = dwc3_omap_extcon_register(omap);
544 ret = of_platform_populate(node, NULL, NULL, dev);
546 dev_err(&pdev->dev, "failed to create dwc3 core\n");
553 if (omap->extcon_vbus_dev.edev)
554 extcon_unregister_interest(&omap->extcon_vbus_dev);
555 if (omap->extcon_id_dev.edev)
556 extcon_unregister_interest(&omap->extcon_id_dev);
559 dwc3_omap_disable_irqs(omap);
562 pm_runtime_put_sync(dev);
565 pm_runtime_disable(dev);
570 static int dwc3_omap_remove(struct platform_device *pdev)
572 struct dwc3_omap *omap = platform_get_drvdata(pdev);
574 if (omap->extcon_vbus_dev.edev)
575 extcon_unregister_interest(&omap->extcon_vbus_dev);
576 if (omap->extcon_id_dev.edev)
577 extcon_unregister_interest(&omap->extcon_id_dev);
578 dwc3_omap_disable_irqs(omap);
579 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
580 pm_runtime_put_sync(&pdev->dev);
581 pm_runtime_disable(&pdev->dev);
586 static const struct of_device_id of_dwc3_match[] = {
588 .compatible = "ti,dwc3"
591 .compatible = "ti,am437x-dwc3"
595 MODULE_DEVICE_TABLE(of, of_dwc3_match);
597 #ifdef CONFIG_PM_SLEEP
598 static int dwc3_omap_prepare(struct device *dev)
600 struct dwc3_omap *omap = dev_get_drvdata(dev);
602 dwc3_omap_write_irqmisc_set(omap, 0x00);
607 static void dwc3_omap_complete(struct device *dev)
609 struct dwc3_omap *omap = dev_get_drvdata(dev);
612 reg = (USBOTGSS_IRQMISC_OEVT |
613 USBOTGSS_IRQMISC_DRVVBUS_RISE |
614 USBOTGSS_IRQMISC_CHRGVBUS_RISE |
615 USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |
616 USBOTGSS_IRQMISC_IDPULLUP_RISE |
617 USBOTGSS_IRQMISC_DRVVBUS_FALL |
618 USBOTGSS_IRQMISC_CHRGVBUS_FALL |
619 USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |
620 USBOTGSS_IRQMISC_IDPULLUP_FALL);
622 dwc3_omap_write_irqmisc_set(omap, reg);
625 static int dwc3_omap_suspend(struct device *dev)
627 struct dwc3_omap *omap = dev_get_drvdata(dev);
629 omap->utmi_otg_status = dwc3_omap_read_utmi_status(omap);
634 static int dwc3_omap_resume(struct device *dev)
636 struct dwc3_omap *omap = dev_get_drvdata(dev);
638 dwc3_omap_write_utmi_status(omap, omap->utmi_otg_status);
640 pm_runtime_disable(dev);
641 pm_runtime_set_active(dev);
642 pm_runtime_enable(dev);
647 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
648 .prepare = dwc3_omap_prepare,
649 .complete = dwc3_omap_complete,
651 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
654 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
656 #define DEV_PM_OPS NULL
657 #endif /* CONFIG_PM_SLEEP */
659 static struct platform_driver dwc3_omap_driver = {
660 .probe = dwc3_omap_probe,
661 .remove = dwc3_omap_remove,
664 .of_match_table = of_dwc3_match,
669 module_platform_driver(dwc3_omap_driver);
671 MODULE_ALIAS("platform:omap-dwc3");
672 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
673 MODULE_LICENSE("GPL v2");
674 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");