2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
37 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
38 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
39 struct dwc3_ep *dep, struct dwc3_request *req);
41 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
50 case EP0_STATUS_PHASE:
51 return "Status Phase";
57 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
60 struct dwc3_gadget_ep_cmd_params params;
66 dep = dwc->eps[epnum];
67 if (dep->flags & DWC3_EP_BUSY) {
68 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);
74 trb->bpl = lower_32_bits(buf_dma);
75 trb->bph = upper_32_bits(buf_dma);
79 trb->ctrl |= (DWC3_TRB_CTRL_HWO
82 | DWC3_TRB_CTRL_ISP_IMI);
84 memset(¶ms, 0, sizeof(params));
85 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
86 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
88 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
89 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
91 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
95 dep->flags |= DWC3_EP_BUSY;
96 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
99 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
104 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
105 struct dwc3_request *req)
107 struct dwc3 *dwc = dep->dwc;
109 req->request.actual = 0;
110 req->request.status = -EINPROGRESS;
111 req->epnum = dep->number;
113 list_add_tail(&req->list, &dep->request_list);
116 * Gadget driver might not be quick enough to queue a request
117 * before we get a Transfer Not Ready event on this endpoint.
119 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
120 * flag is set, it's telling us that as soon as Gadget queues the
121 * required request, we should kick the transfer here because the
122 * IRQ we were waiting for is long gone.
124 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
127 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
129 if (dwc->ep0state != EP0_DATA_PHASE) {
130 dev_WARN(dwc->dev, "Unexpected pending request\n");
134 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
136 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
143 * In case gadget driver asked us to delay the STATUS phase,
146 if (dwc->delayed_status) {
149 direction = !dwc->ep0_expect_in;
150 dwc->delayed_status = false;
151 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
153 if (dwc->ep0state == EP0_STATUS_PHASE)
154 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
156 dev_dbg(dwc->dev, "too early for delayed status\n");
162 * Unfortunately we have uncovered a limitation wrt the Data Phase.
164 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
165 * come before issueing Start Transfer command, but if we do, we will
166 * miss situations where the host starts another SETUP phase instead of
167 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
168 * Layer Compliance Suite.
170 * The problem surfaces due to the fact that in case of back-to-back
171 * SETUP packets there will be no XferNotReady(DATA) generated and we
172 * will be stuck waiting for XferNotReady(DATA) forever.
174 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
175 * it tells us to start Data Phase right away. It also mentions that if
176 * we receive a SETUP phase instead of the DATA phase, core will issue
177 * XferComplete for the DATA phase, before actually initiating it in
178 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
179 * can only be used to print some debugging logs, as the core expects
180 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
181 * just so it completes right away, without transferring anything and,
182 * only then, we can go back to the SETUP phase.
184 * Because of this scenario, SNPS decided to change the programming
185 * model of control transfers and support on-demand transfers only for
186 * the STATUS phase. To fix the issue we have now, we will always wait
187 * for gadget driver to queue the DATA phase's struct usb_request, then
188 * start it right away.
190 * If we're actually in a 2-stage transfer, we will wait for
191 * XferNotReady(STATUS).
193 if (dwc->three_stage_setup) {
196 direction = dwc->ep0_expect_in;
197 dwc->ep0state = EP0_DATA_PHASE;
199 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
201 dep->flags &= ~DWC3_EP0_DIR_IN;
207 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
210 struct dwc3_request *req = to_dwc3_request(request);
211 struct dwc3_ep *dep = to_dwc3_ep(ep);
212 struct dwc3 *dwc = dep->dwc;
218 spin_lock_irqsave(&dwc->lock, flags);
219 if (!dep->endpoint.desc) {
220 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
226 /* we share one TRB for ep0/1 */
227 if (!list_empty(&dep->request_list)) {
232 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
233 request, dep->name, request->length,
234 dwc3_ep0_state_string(dwc->ep0state));
236 ret = __dwc3_gadget_ep0_queue(dep, req);
239 spin_unlock_irqrestore(&dwc->lock, flags);
244 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
248 /* reinitialize physical ep1 */
250 dep->flags = DWC3_EP_ENABLED;
252 /* stall is always issued on EP0 */
254 __dwc3_gadget_ep_set_halt(dep, 1);
255 dep->flags = DWC3_EP_ENABLED;
256 dwc->delayed_status = false;
258 if (!list_empty(&dep->request_list)) {
259 struct dwc3_request *req;
261 req = next_request(&dep->request_list);
262 dwc3_gadget_giveback(dep, req, -ECONNRESET);
265 dwc->ep0state = EP0_SETUP_PHASE;
266 dwc3_ep0_out_start(dwc);
269 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
271 struct dwc3_ep *dep = to_dwc3_ep(ep);
272 struct dwc3 *dwc = dep->dwc;
274 dwc3_ep0_stall_and_restart(dwc);
279 void dwc3_ep0_out_start(struct dwc3 *dwc)
283 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
284 DWC3_TRBCTL_CONTROL_SETUP);
288 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
291 u32 windex = le16_to_cpu(wIndex_le);
294 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
295 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
298 dep = dwc->eps[epnum];
299 if (dep->flags & DWC3_EP_ENABLED)
305 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
311 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
312 struct usb_ctrlrequest *ctrl)
318 __le16 *response_pkt;
320 recip = ctrl->bRequestType & USB_RECIP_MASK;
322 case USB_RECIP_DEVICE:
324 * LTM will be set once we know how to set this in HW.
326 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
328 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
329 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
330 if (reg & DWC3_DCTL_INITU1ENA)
331 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
332 if (reg & DWC3_DCTL_INITU2ENA)
333 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
338 case USB_RECIP_INTERFACE:
340 * Function Remote Wake Capable D0
341 * Function Remote Wakeup D1
345 case USB_RECIP_ENDPOINT:
346 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
350 if (dep->flags & DWC3_EP_STALL)
351 usb_status = 1 << USB_ENDPOINT_HALT;
357 response_pkt = (__le16 *) dwc->setup_buf;
358 *response_pkt = cpu_to_le16(usb_status);
361 dwc->ep0_usb_req.dep = dep;
362 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
363 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
364 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
366 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
369 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
370 struct usb_ctrlrequest *ctrl, int set)
378 enum usb_device_state state;
380 wValue = le16_to_cpu(ctrl->wValue);
381 wIndex = le16_to_cpu(ctrl->wIndex);
382 recip = ctrl->bRequestType & USB_RECIP_MASK;
383 state = dwc->gadget.state;
386 case USB_RECIP_DEVICE:
389 case USB_DEVICE_REMOTE_WAKEUP:
392 * 9.4.1 says only only for SS, in AddressState only for
393 * default control pipe
395 case USB_DEVICE_U1_ENABLE:
396 if (state != USB_STATE_CONFIGURED)
398 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
401 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
403 reg |= DWC3_DCTL_INITU1ENA;
405 reg &= ~DWC3_DCTL_INITU1ENA;
406 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
409 case USB_DEVICE_U2_ENABLE:
410 if (state != USB_STATE_CONFIGURED)
412 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
417 reg |= DWC3_DCTL_INITU2ENA;
419 reg &= ~DWC3_DCTL_INITU2ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
423 case USB_DEVICE_LTM_ENABLE:
427 case USB_DEVICE_TEST_MODE:
428 if ((wIndex & 0xff) != 0)
433 dwc->test_mode_nr = wIndex >> 8;
434 dwc->test_mode = true;
441 case USB_RECIP_INTERFACE:
443 case USB_INTRF_FUNC_SUSPEND:
444 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
445 /* XXX enable Low power suspend */
447 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
448 /* XXX enable remote wakeup */
456 case USB_RECIP_ENDPOINT:
458 case USB_ENDPOINT_HALT:
459 dep = dwc3_wIndex_to_dep(dwc, wIndex);
462 ret = __dwc3_gadget_ep_set_halt(dep, set);
478 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
480 enum usb_device_state state = dwc->gadget.state;
484 addr = le16_to_cpu(ctrl->wValue);
486 dev_dbg(dwc->dev, "invalid device address %d\n", addr);
490 if (state == USB_STATE_CONFIGURED) {
491 dev_dbg(dwc->dev, "trying to set address when configured\n");
495 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
496 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
497 reg |= DWC3_DCFG_DEVADDR(addr);
498 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
501 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
503 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
508 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
512 spin_unlock(&dwc->lock);
513 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
514 spin_lock(&dwc->lock);
518 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
520 enum usb_device_state state = dwc->gadget.state;
525 dwc->start_config_issued = false;
526 cfg = le16_to_cpu(ctrl->wValue);
529 case USB_STATE_DEFAULT:
533 case USB_STATE_ADDRESS:
534 ret = dwc3_ep0_delegate_req(dwc, ctrl);
535 /* if the cfg matches and the cfg is non zero */
536 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
539 * only change state if set_config has already
540 * been processed. If gadget driver returns
541 * USB_GADGET_DELAYED_STATUS, we will wait
542 * to change the state on the next usb_ep_queue()
545 usb_gadget_set_state(&dwc->gadget,
546 USB_STATE_CONFIGURED);
549 * Enable transition to U1/U2 state when
550 * nothing is pending from application.
552 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
553 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
554 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
556 dwc->resize_fifos = true;
557 dev_dbg(dwc->dev, "resize fifos flag SET\n");
561 case USB_STATE_CONFIGURED:
562 ret = dwc3_ep0_delegate_req(dwc, ctrl);
564 usb_gadget_set_state(&dwc->gadget,
573 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
575 struct dwc3_ep *dep = to_dwc3_ep(ep);
576 struct dwc3 *dwc = dep->dwc;
590 memcpy(&timing, req->buf, sizeof(timing));
592 dwc->u1sel = timing.u1sel;
593 dwc->u1pel = timing.u1pel;
594 dwc->u2sel = le16_to_cpu(timing.u2sel);
595 dwc->u2pel = le16_to_cpu(timing.u2pel);
597 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
598 if (reg & DWC3_DCTL_INITU2ENA)
600 if (reg & DWC3_DCTL_INITU1ENA)
604 * According to Synopsys Databook, if parameter is
605 * greater than 125, a value of zero should be
606 * programmed in the register.
611 /* now that we have the time, issue DGCMD Set Sel */
612 ret = dwc3_send_gadget_generic_command(dwc,
613 DWC3_DGCMD_SET_PERIODIC_PAR, param);
617 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
620 enum usb_device_state state = dwc->gadget.state;
624 if (state == USB_STATE_DEFAULT)
627 wValue = le16_to_cpu(ctrl->wValue);
628 wLength = le16_to_cpu(ctrl->wLength);
631 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
637 * To handle Set SEL we need to receive 6 bytes from Host. So let's
638 * queue a usb_request for 6 bytes.
640 * Remember, though, this controller can't handle non-wMaxPacketSize
641 * aligned transfers on the OUT direction, so we queue a request for
642 * wMaxPacketSize instead.
645 dwc->ep0_usb_req.dep = dep;
646 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
647 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
648 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
650 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
653 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
659 wValue = le16_to_cpu(ctrl->wValue);
660 wLength = le16_to_cpu(ctrl->wLength);
661 wIndex = le16_to_cpu(ctrl->wIndex);
663 if (wIndex || wLength)
667 * REVISIT It's unclear from Databook what to do with this
668 * value. For now, just cache it.
670 dwc->isoch_delay = wValue;
675 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
679 switch (ctrl->bRequest) {
680 case USB_REQ_GET_STATUS:
681 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");
682 ret = dwc3_ep0_handle_status(dwc, ctrl);
684 case USB_REQ_CLEAR_FEATURE:
685 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");
686 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
688 case USB_REQ_SET_FEATURE:
689 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");
690 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
692 case USB_REQ_SET_ADDRESS:
693 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");
694 ret = dwc3_ep0_set_address(dwc, ctrl);
696 case USB_REQ_SET_CONFIGURATION:
697 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");
698 ret = dwc3_ep0_set_config(dwc, ctrl);
700 case USB_REQ_SET_SEL:
701 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");
702 ret = dwc3_ep0_set_sel(dwc, ctrl);
704 case USB_REQ_SET_ISOCH_DELAY:
705 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");
706 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
709 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");
710 ret = dwc3_ep0_delegate_req(dwc, ctrl);
717 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
718 const struct dwc3_event_depevt *event)
720 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
724 if (!dwc->gadget_driver)
727 len = le16_to_cpu(ctrl->wLength);
729 dwc->three_stage_setup = false;
730 dwc->ep0_expect_in = false;
731 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
733 dwc->three_stage_setup = true;
734 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
735 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
738 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
739 ret = dwc3_ep0_std_request(dwc, ctrl);
741 ret = dwc3_ep0_delegate_req(dwc, ctrl);
743 if (ret == USB_GADGET_DELAYED_STATUS)
744 dwc->delayed_status = true;
748 dwc3_ep0_stall_and_restart(dwc);
751 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
752 const struct dwc3_event_depevt *event)
754 struct dwc3_request *r = NULL;
755 struct usb_request *ur;
756 struct dwc3_trb *trb;
763 epnum = event->endpoint_number;
766 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
768 r = next_request(&ep0->request_list);
773 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
774 if (status == DWC3_TRBSTS_SETUP_PENDING) {
775 dev_dbg(dwc->dev, "Setup Pending received\n");
778 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
783 length = trb->size & DWC3_TRB_SIZE_MASK;
785 if (dwc->ep0_bounced) {
786 unsigned transfer_size = ur->length;
787 unsigned maxp = ep0->endpoint.maxpacket;
789 transfer_size += (maxp - (transfer_size % maxp));
790 transferred = min_t(u32, ur->length,
791 transfer_size - length);
792 memcpy(ur->buf, dwc->ep0_bounce, transferred);
794 transferred = ur->length - length;
797 ur->actual += transferred;
799 if ((epnum & 1) && ur->actual < ur->length) {
800 /* for some reason we did not get everything out */
802 dwc3_ep0_stall_and_restart(dwc);
805 * handle the case where we have to send a zero packet. This
806 * seems to be case when req.length > maxpacket. Could it be?
809 dwc3_gadget_giveback(ep0, r, 0);
813 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
814 const struct dwc3_event_depevt *event)
816 struct dwc3_request *r;
818 struct dwc3_trb *trb;
824 if (!list_empty(&dep->request_list)) {
825 r = next_request(&dep->request_list);
827 dwc3_gadget_giveback(dep, r, 0);
830 if (dwc->test_mode) {
833 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
835 dev_dbg(dwc->dev, "Invalid Test #%d\n",
837 dwc3_ep0_stall_and_restart(dwc);
842 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
843 if (status == DWC3_TRBSTS_SETUP_PENDING)
844 dev_dbg(dwc->dev, "Setup Pending received\n");
846 dwc->ep0state = EP0_SETUP_PHASE;
847 dwc3_ep0_out_start(dwc);
850 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
851 const struct dwc3_event_depevt *event)
853 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
855 dep->flags &= ~DWC3_EP_BUSY;
856 dep->resource_index = 0;
857 dwc->setup_packet_pending = false;
859 switch (dwc->ep0state) {
860 case EP0_SETUP_PHASE:
861 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");
862 dwc3_ep0_inspect_setup(dwc, event);
866 dev_vdbg(dwc->dev, "Data Phase\n");
867 dwc3_ep0_complete_data(dwc, event);
870 case EP0_STATUS_PHASE:
871 dev_vdbg(dwc->dev, "Status Phase\n");
872 dwc3_ep0_complete_status(dwc, event);
875 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
879 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
880 struct dwc3_ep *dep, struct dwc3_request *req)
884 req->direction = !!dep->number;
886 if (req->request.length == 0) {
887 ret = dwc3_ep0_start_trans(dwc, dep->number,
888 dwc->ctrl_req_addr, 0,
889 DWC3_TRBCTL_CONTROL_DATA);
890 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
891 && (dep->number == 0)) {
895 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
898 dev_dbg(dwc->dev, "failed to map request\n");
902 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
904 maxpacket = dep->endpoint.maxpacket;
905 transfer_size = roundup(req->request.length, maxpacket);
907 dwc->ep0_bounced = true;
910 * REVISIT in case request length is bigger than
911 * DWC3_EP0_BOUNCE_SIZE we will need two chained
912 * TRBs to handle the transfer.
914 ret = dwc3_ep0_start_trans(dwc, dep->number,
915 dwc->ep0_bounce_addr, transfer_size,
916 DWC3_TRBCTL_CONTROL_DATA);
918 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
921 dev_dbg(dwc->dev, "failed to map request\n");
925 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
926 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
932 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
934 struct dwc3 *dwc = dep->dwc;
937 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
938 : DWC3_TRBCTL_CONTROL_STATUS2;
940 return dwc3_ep0_start_trans(dwc, dep->number,
941 dwc->ctrl_req_addr, 0, type);
944 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
946 if (dwc->resize_fifos) {
947 dev_dbg(dwc->dev, "starting to resize fifos\n");
948 dwc3_gadget_resize_tx_fifos(dwc);
949 dwc->resize_fifos = 0;
952 WARN_ON(dwc3_ep0_start_control_status(dep));
955 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
956 const struct dwc3_event_depevt *event)
958 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
960 __dwc3_ep0_do_control_status(dwc, dep);
963 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
965 struct dwc3_gadget_ep_cmd_params params;
969 if (!dep->resource_index)
972 cmd = DWC3_DEPCMD_ENDTRANSFER;
973 cmd |= DWC3_DEPCMD_CMDIOC;
974 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
975 memset(¶ms, 0, sizeof(params));
976 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
978 dep->resource_index = 0;
981 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
982 const struct dwc3_event_depevt *event)
984 dwc->setup_packet_pending = true;
986 switch (event->status) {
987 case DEPEVT_STATUS_CONTROL_DATA:
988 dev_vdbg(dwc->dev, "Control Data\n");
991 * We already have a DATA transfer in the controller's cache,
992 * if we receive a XferNotReady(DATA) we will ignore it, unless
993 * it's for the wrong direction.
995 * In that case, we must issue END_TRANSFER command to the Data
996 * Phase we already have started and issue SetStall on the
999 if (dwc->ep0_expect_in != event->endpoint_number) {
1000 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1002 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");
1003 dwc3_ep0_end_control_data(dwc, dep);
1004 dwc3_ep0_stall_and_restart(dwc);
1010 case DEPEVT_STATUS_CONTROL_STATUS:
1011 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1014 dev_vdbg(dwc->dev, "Control Status\n");
1016 dwc->ep0state = EP0_STATUS_PHASE;
1018 if (dwc->delayed_status) {
1019 WARN_ON_ONCE(event->endpoint_number != 1);
1020 dev_vdbg(dwc->dev, "Mass Storage delayed status\n");
1024 dwc3_ep0_do_control_status(dwc, event);
1028 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1029 const struct dwc3_event_depevt *event)
1031 u8 epnum = event->endpoint_number;
1033 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
1034 dwc3_ep_event_string(event->endpoint_event),
1035 epnum >> 1, (epnum & 1) ? "in" : "out",
1036 dwc3_ep0_state_string(dwc->ep0state));
1038 switch (event->endpoint_event) {
1039 case DWC3_DEPEVT_XFERCOMPLETE:
1040 dwc3_ep0_xfer_complete(dwc, event);
1043 case DWC3_DEPEVT_XFERNOTREADY:
1044 dwc3_ep0_xfernotready(dwc, event);
1047 case DWC3_DEPEVT_XFERINPROGRESS:
1048 case DWC3_DEPEVT_RXTXFIFOEVT:
1049 case DWC3_DEPEVT_STREAMEVT:
1050 case DWC3_DEPEVT_EPCMDCMPLT: