2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
59 u32 len, u32 type, bool chain)
61 struct dwc3_gadget_ep_cmd_params params;
67 dep = dwc->eps[epnum];
68 if (dep->flags & DWC3_EP_BUSY) {
69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
73 trb = &dwc->ep0_trb[dep->trb_enqueue];
78 trb->bpl = lower_32_bits(buf_dma);
79 trb->bph = upper_32_bits(buf_dma);
83 trb->ctrl |= (DWC3_TRB_CTRL_HWO
84 | DWC3_TRB_CTRL_ISP_IMI);
87 trb->ctrl |= DWC3_TRB_CTRL_CHN;
89 trb->ctrl |= (DWC3_TRB_CTRL_IOC
95 memset(¶ms, 0, sizeof(params));
96 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
97 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
99 trace_dwc3_prepare_trb(dep, trb);
101 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
103 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
108 dep->flags |= DWC3_EP_BUSY;
109 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
110 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
115 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
116 struct dwc3_request *req)
118 struct dwc3 *dwc = dep->dwc;
120 req->request.actual = 0;
121 req->request.status = -EINPROGRESS;
122 req->epnum = dep->number;
124 list_add_tail(&req->list, &dep->pending_list);
127 * Gadget driver might not be quick enough to queue a request
128 * before we get a Transfer Not Ready event on this endpoint.
130 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
131 * flag is set, it's telling us that as soon as Gadget queues the
132 * required request, we should kick the transfer here because the
133 * IRQ we were waiting for is long gone.
135 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
138 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
140 if (dwc->ep0state != EP0_DATA_PHASE) {
141 dev_WARN(dwc->dev, "Unexpected pending request\n");
145 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
147 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
154 * In case gadget driver asked us to delay the STATUS phase,
157 if (dwc->delayed_status) {
160 direction = !dwc->ep0_expect_in;
161 dwc->delayed_status = false;
162 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
164 if (dwc->ep0state == EP0_STATUS_PHASE)
165 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
167 dwc3_trace(trace_dwc3_ep0,
168 "too early for delayed status");
174 * Unfortunately we have uncovered a limitation wrt the Data Phase.
176 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
177 * come before issueing Start Transfer command, but if we do, we will
178 * miss situations where the host starts another SETUP phase instead of
179 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
180 * Layer Compliance Suite.
182 * The problem surfaces due to the fact that in case of back-to-back
183 * SETUP packets there will be no XferNotReady(DATA) generated and we
184 * will be stuck waiting for XferNotReady(DATA) forever.
186 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
187 * it tells us to start Data Phase right away. It also mentions that if
188 * we receive a SETUP phase instead of the DATA phase, core will issue
189 * XferComplete for the DATA phase, before actually initiating it in
190 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
191 * can only be used to print some debugging logs, as the core expects
192 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
193 * just so it completes right away, without transferring anything and,
194 * only then, we can go back to the SETUP phase.
196 * Because of this scenario, SNPS decided to change the programming
197 * model of control transfers and support on-demand transfers only for
198 * the STATUS phase. To fix the issue we have now, we will always wait
199 * for gadget driver to queue the DATA phase's struct usb_request, then
200 * start it right away.
202 * If we're actually in a 2-stage transfer, we will wait for
203 * XferNotReady(STATUS).
205 if (dwc->three_stage_setup) {
208 direction = dwc->ep0_expect_in;
209 dwc->ep0state = EP0_DATA_PHASE;
211 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
213 dep->flags &= ~DWC3_EP0_DIR_IN;
219 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
222 struct dwc3_request *req = to_dwc3_request(request);
223 struct dwc3_ep *dep = to_dwc3_ep(ep);
224 struct dwc3 *dwc = dep->dwc;
230 spin_lock_irqsave(&dwc->lock, flags);
231 if (!dep->endpoint.desc) {
232 dwc3_trace(trace_dwc3_ep0,
233 "trying to queue request %p to disabled %s",
239 /* we share one TRB for ep0/1 */
240 if (!list_empty(&dep->pending_list)) {
245 dwc3_trace(trace_dwc3_ep0,
246 "queueing request %p to %s length %d state '%s'",
247 request, dep->name, request->length,
248 dwc3_ep0_state_string(dwc->ep0state));
250 ret = __dwc3_gadget_ep0_queue(dep, req);
253 spin_unlock_irqrestore(&dwc->lock, flags);
258 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
262 /* reinitialize physical ep1 */
264 dep->flags = DWC3_EP_ENABLED;
266 /* stall is always issued on EP0 */
268 __dwc3_gadget_ep_set_halt(dep, 1, false);
269 dep->flags = DWC3_EP_ENABLED;
270 dwc->delayed_status = false;
272 if (!list_empty(&dep->pending_list)) {
273 struct dwc3_request *req;
275 req = next_request(&dep->pending_list);
276 dwc3_gadget_giveback(dep, req, -ECONNRESET);
279 dwc->ep0state = EP0_SETUP_PHASE;
280 dwc3_ep0_out_start(dwc);
283 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
285 struct dwc3_ep *dep = to_dwc3_ep(ep);
286 struct dwc3 *dwc = dep->dwc;
288 dwc3_ep0_stall_and_restart(dwc);
293 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
295 struct dwc3_ep *dep = to_dwc3_ep(ep);
296 struct dwc3 *dwc = dep->dwc;
300 spin_lock_irqsave(&dwc->lock, flags);
301 ret = __dwc3_gadget_ep0_set_halt(ep, value);
302 spin_unlock_irqrestore(&dwc->lock, flags);
307 void dwc3_ep0_out_start(struct dwc3 *dwc)
311 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
312 DWC3_TRBCTL_CONTROL_SETUP, false);
316 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
319 u32 windex = le16_to_cpu(wIndex_le);
322 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
323 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
326 dep = dwc->eps[epnum];
327 if (dep->flags & DWC3_EP_ENABLED)
333 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
339 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
340 struct usb_ctrlrequest *ctrl)
346 __le16 *response_pkt;
348 recip = ctrl->bRequestType & USB_RECIP_MASK;
350 case USB_RECIP_DEVICE:
352 * LTM will be set once we know how to set this in HW.
354 usb_status |= dwc->gadget.is_selfpowered;
356 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
357 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
358 if (reg & DWC3_DCTL_INITU1ENA)
359 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
360 if (reg & DWC3_DCTL_INITU2ENA)
361 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
366 case USB_RECIP_INTERFACE:
368 * Function Remote Wake Capable D0
369 * Function Remote Wakeup D1
373 case USB_RECIP_ENDPOINT:
374 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
378 if (dep->flags & DWC3_EP_STALL)
379 usb_status = 1 << USB_ENDPOINT_HALT;
385 response_pkt = (__le16 *) dwc->setup_buf;
386 *response_pkt = cpu_to_le16(usb_status);
389 dwc->ep0_usb_req.dep = dep;
390 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
391 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
392 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
394 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
397 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
398 struct usb_ctrlrequest *ctrl, int set)
406 enum usb_device_state state;
408 wValue = le16_to_cpu(ctrl->wValue);
409 wIndex = le16_to_cpu(ctrl->wIndex);
410 recip = ctrl->bRequestType & USB_RECIP_MASK;
411 state = dwc->gadget.state;
414 case USB_RECIP_DEVICE:
417 case USB_DEVICE_REMOTE_WAKEUP:
420 * 9.4.1 says only only for SS, in AddressState only for
421 * default control pipe
423 case USB_DEVICE_U1_ENABLE:
424 if (state != USB_STATE_CONFIGURED)
426 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
429 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
431 reg |= DWC3_DCTL_INITU1ENA;
433 reg &= ~DWC3_DCTL_INITU1ENA;
434 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
437 case USB_DEVICE_U2_ENABLE:
438 if (state != USB_STATE_CONFIGURED)
440 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
443 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
445 reg |= DWC3_DCTL_INITU2ENA;
447 reg &= ~DWC3_DCTL_INITU2ENA;
448 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
451 case USB_DEVICE_LTM_ENABLE:
454 case USB_DEVICE_TEST_MODE:
455 if ((wIndex & 0xff) != 0)
460 switch (wIndex >> 8) {
466 dwc->test_mode_nr = wIndex >> 8;
467 dwc->test_mode = true;
478 case USB_RECIP_INTERFACE:
480 case USB_INTRF_FUNC_SUSPEND:
481 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
482 /* XXX enable Low power suspend */
484 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
485 /* XXX enable remote wakeup */
493 case USB_RECIP_ENDPOINT:
495 case USB_ENDPOINT_HALT:
496 dep = dwc3_wIndex_to_dep(dwc, wIndex);
499 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
501 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
517 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
519 enum usb_device_state state = dwc->gadget.state;
523 addr = le16_to_cpu(ctrl->wValue);
525 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
529 if (state == USB_STATE_CONFIGURED) {
530 dwc3_trace(trace_dwc3_ep0,
531 "trying to set address when configured");
535 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
536 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
537 reg |= DWC3_DCFG_DEVADDR(addr);
538 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
541 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
543 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
548 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
552 spin_unlock(&dwc->lock);
553 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
554 spin_lock(&dwc->lock);
558 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
560 enum usb_device_state state = dwc->gadget.state;
565 cfg = le16_to_cpu(ctrl->wValue);
568 case USB_STATE_DEFAULT:
571 case USB_STATE_ADDRESS:
572 ret = dwc3_ep0_delegate_req(dwc, ctrl);
573 /* if the cfg matches and the cfg is non zero */
574 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
577 * only change state if set_config has already
578 * been processed. If gadget driver returns
579 * USB_GADGET_DELAYED_STATUS, we will wait
580 * to change the state on the next usb_ep_queue()
583 usb_gadget_set_state(&dwc->gadget,
584 USB_STATE_CONFIGURED);
587 * Enable transition to U1/U2 state when
588 * nothing is pending from application.
590 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
591 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
592 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
596 case USB_STATE_CONFIGURED:
597 ret = dwc3_ep0_delegate_req(dwc, ctrl);
599 usb_gadget_set_state(&dwc->gadget,
608 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
610 struct dwc3_ep *dep = to_dwc3_ep(ep);
611 struct dwc3 *dwc = dep->dwc;
625 memcpy(&timing, req->buf, sizeof(timing));
627 dwc->u1sel = timing.u1sel;
628 dwc->u1pel = timing.u1pel;
629 dwc->u2sel = le16_to_cpu(timing.u2sel);
630 dwc->u2pel = le16_to_cpu(timing.u2pel);
632 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
633 if (reg & DWC3_DCTL_INITU2ENA)
635 if (reg & DWC3_DCTL_INITU1ENA)
639 * According to Synopsys Databook, if parameter is
640 * greater than 125, a value of zero should be
641 * programmed in the register.
646 /* now that we have the time, issue DGCMD Set Sel */
647 ret = dwc3_send_gadget_generic_command(dwc,
648 DWC3_DGCMD_SET_PERIODIC_PAR, param);
652 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
655 enum usb_device_state state = dwc->gadget.state;
659 if (state == USB_STATE_DEFAULT)
662 wValue = le16_to_cpu(ctrl->wValue);
663 wLength = le16_to_cpu(ctrl->wLength);
666 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
672 * To handle Set SEL we need to receive 6 bytes from Host. So let's
673 * queue a usb_request for 6 bytes.
675 * Remember, though, this controller can't handle non-wMaxPacketSize
676 * aligned transfers on the OUT direction, so we queue a request for
677 * wMaxPacketSize instead.
680 dwc->ep0_usb_req.dep = dep;
681 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
682 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
683 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
685 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
688 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
694 wValue = le16_to_cpu(ctrl->wValue);
695 wLength = le16_to_cpu(ctrl->wLength);
696 wIndex = le16_to_cpu(ctrl->wIndex);
698 if (wIndex || wLength)
702 * REVISIT It's unclear from Databook what to do with this
703 * value. For now, just cache it.
705 dwc->isoch_delay = wValue;
710 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
714 switch (ctrl->bRequest) {
715 case USB_REQ_GET_STATUS:
716 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
717 ret = dwc3_ep0_handle_status(dwc, ctrl);
719 case USB_REQ_CLEAR_FEATURE:
720 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
721 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
723 case USB_REQ_SET_FEATURE:
724 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
725 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
727 case USB_REQ_SET_ADDRESS:
728 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
729 ret = dwc3_ep0_set_address(dwc, ctrl);
731 case USB_REQ_SET_CONFIGURATION:
732 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
733 ret = dwc3_ep0_set_config(dwc, ctrl);
735 case USB_REQ_SET_SEL:
736 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
737 ret = dwc3_ep0_set_sel(dwc, ctrl);
739 case USB_REQ_SET_ISOCH_DELAY:
740 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
741 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
744 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
745 ret = dwc3_ep0_delegate_req(dwc, ctrl);
752 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
753 const struct dwc3_event_depevt *event)
755 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
759 if (!dwc->gadget_driver)
762 trace_dwc3_ctrl_req(ctrl);
764 len = le16_to_cpu(ctrl->wLength);
766 dwc->three_stage_setup = false;
767 dwc->ep0_expect_in = false;
768 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
770 dwc->three_stage_setup = true;
771 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
772 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
775 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
776 ret = dwc3_ep0_std_request(dwc, ctrl);
778 ret = dwc3_ep0_delegate_req(dwc, ctrl);
780 if (ret == USB_GADGET_DELAYED_STATUS)
781 dwc->delayed_status = true;
785 dwc3_ep0_stall_and_restart(dwc);
788 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
789 const struct dwc3_event_depevt *event)
791 struct dwc3_request *r = NULL;
792 struct usb_request *ur;
793 struct dwc3_trb *trb;
795 unsigned transfer_size = 0;
797 unsigned remaining_ur_length;
804 epnum = event->endpoint_number;
807 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
811 trace_dwc3_complete_trb(ep0, trb);
813 r = next_request(&ep0->pending_list);
817 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
818 if (status == DWC3_TRBSTS_SETUP_PENDING) {
819 dwc->setup_packet_pending = true;
821 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
824 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
831 remaining_ur_length = ur->length;
833 length = trb->size & DWC3_TRB_SIZE_MASK;
835 maxp = ep0->endpoint.maxpacket;
837 if (dwc->ep0_bounced) {
839 * Handle the first TRB before handling the bounce buffer if
840 * the request length is greater than the bounce buffer size
842 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
843 transfer_size = ALIGN(ur->length - maxp, maxp);
844 transferred = transfer_size - length;
845 buf = (u8 *)buf + transferred;
846 ur->actual += transferred;
847 remaining_ur_length -= transferred;
850 length = trb->size & DWC3_TRB_SIZE_MASK;
852 ep0->trb_enqueue = 0;
855 transfer_size = roundup((ur->length - transfer_size),
858 transferred = min_t(u32, remaining_ur_length,
859 transfer_size - length);
860 memcpy(buf, dwc->ep0_bounce, transferred);
862 transferred = ur->length - length;
865 ur->actual += transferred;
867 if ((epnum & 1) && ur->actual < ur->length) {
868 /* for some reason we did not get everything out */
870 dwc3_ep0_stall_and_restart(dwc);
872 dwc3_gadget_giveback(ep0, r, 0);
874 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
875 ur->length && ur->zero) {
878 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
880 ret = dwc3_ep0_start_trans(dwc, epnum,
881 dwc->ctrl_req_addr, 0,
882 DWC3_TRBCTL_CONTROL_DATA, false);
888 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
889 const struct dwc3_event_depevt *event)
891 struct dwc3_request *r;
893 struct dwc3_trb *trb;
899 trace_dwc3_complete_trb(dep, trb);
901 if (!list_empty(&dep->pending_list)) {
902 r = next_request(&dep->pending_list);
904 dwc3_gadget_giveback(dep, r, 0);
907 if (dwc->test_mode) {
910 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
912 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
914 dwc3_ep0_stall_and_restart(dwc);
919 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
920 if (status == DWC3_TRBSTS_SETUP_PENDING) {
921 dwc->setup_packet_pending = true;
922 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
925 dwc->ep0state = EP0_SETUP_PHASE;
926 dwc3_ep0_out_start(dwc);
929 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
930 const struct dwc3_event_depevt *event)
932 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
934 dep->flags &= ~DWC3_EP_BUSY;
935 dep->resource_index = 0;
936 dwc->setup_packet_pending = false;
938 switch (dwc->ep0state) {
939 case EP0_SETUP_PHASE:
940 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
941 dwc3_ep0_inspect_setup(dwc, event);
945 dwc3_trace(trace_dwc3_ep0, "Data Phase");
946 dwc3_ep0_complete_data(dwc, event);
949 case EP0_STATUS_PHASE:
950 dwc3_trace(trace_dwc3_ep0, "Status Phase");
951 dwc3_ep0_complete_status(dwc, event);
954 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
958 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
959 struct dwc3_ep *dep, struct dwc3_request *req)
963 req->direction = !!dep->number;
965 if (req->request.length == 0) {
966 ret = dwc3_ep0_start_trans(dwc, dep->number,
967 dwc->ctrl_req_addr, 0,
968 DWC3_TRBCTL_CONTROL_DATA, false);
969 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
970 && (dep->number == 0)) {
971 u32 transfer_size = 0;
974 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
977 dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
981 maxpacket = dep->endpoint.maxpacket;
983 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
984 transfer_size = ALIGN(req->request.length - maxpacket,
986 ret = dwc3_ep0_start_trans(dwc, dep->number,
989 DWC3_TRBCTL_CONTROL_DATA,
993 transfer_size = roundup((req->request.length - transfer_size),
996 dwc->ep0_bounced = true;
998 ret = dwc3_ep0_start_trans(dwc, dep->number,
999 dwc->ep0_bounce_addr, transfer_size,
1000 DWC3_TRBCTL_CONTROL_DATA, false);
1002 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1005 dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1009 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1010 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1017 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1019 struct dwc3 *dwc = dep->dwc;
1022 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1023 : DWC3_TRBCTL_CONTROL_STATUS2;
1025 return dwc3_ep0_start_trans(dwc, dep->number,
1026 dwc->ctrl_req_addr, 0, type, false);
1029 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1031 WARN_ON(dwc3_ep0_start_control_status(dep));
1034 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1035 const struct dwc3_event_depevt *event)
1037 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1039 __dwc3_ep0_do_control_status(dwc, dep);
1042 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1044 struct dwc3_gadget_ep_cmd_params params;
1048 if (!dep->resource_index)
1051 cmd = DWC3_DEPCMD_ENDTRANSFER;
1052 cmd |= DWC3_DEPCMD_CMDIOC;
1053 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1054 memset(¶ms, 0, sizeof(params));
1055 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1057 dep->resource_index = 0;
1060 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1061 const struct dwc3_event_depevt *event)
1063 switch (event->status) {
1064 case DEPEVT_STATUS_CONTROL_DATA:
1065 dwc3_trace(trace_dwc3_ep0, "Control Data");
1068 * We already have a DATA transfer in the controller's cache,
1069 * if we receive a XferNotReady(DATA) we will ignore it, unless
1070 * it's for the wrong direction.
1072 * In that case, we must issue END_TRANSFER command to the Data
1073 * Phase we already have started and issue SetStall on the
1076 if (dwc->ep0_expect_in != event->endpoint_number) {
1077 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1079 dwc3_trace(trace_dwc3_ep0,
1080 "Wrong direction for Data phase");
1081 dwc3_ep0_end_control_data(dwc, dep);
1082 dwc3_ep0_stall_and_restart(dwc);
1088 case DEPEVT_STATUS_CONTROL_STATUS:
1089 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1092 dwc3_trace(trace_dwc3_ep0, "Control Status");
1094 dwc->ep0state = EP0_STATUS_PHASE;
1096 if (dwc->delayed_status) {
1097 WARN_ON_ONCE(event->endpoint_number != 1);
1098 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1102 dwc3_ep0_do_control_status(dwc, event);
1106 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1107 const struct dwc3_event_depevt *event)
1109 u8 epnum = event->endpoint_number;
1111 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1112 dwc3_ep_event_string(event->endpoint_event),
1113 epnum >> 1, (epnum & 1) ? "in" : "out",
1114 dwc3_ep0_state_string(dwc->ep0state));
1116 switch (event->endpoint_event) {
1117 case DWC3_DEPEVT_XFERCOMPLETE:
1118 dwc3_ep0_xfer_complete(dwc, event);
1121 case DWC3_DEPEVT_XFERNOTREADY:
1122 dwc3_ep0_xfernotready(dwc, event);
1125 case DWC3_DEPEVT_XFERINPROGRESS:
1126 case DWC3_DEPEVT_RXTXFIFOEVT:
1127 case DWC3_DEPEVT_STREAMEVT:
1128 case DWC3_DEPEVT_EPCMDCMPLT: