2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
61 struct dwc3_gadget_ep_cmd_params params;
67 dep = dwc->eps[epnum];
68 if (dep->flags & DWC3_EP_BUSY) {
69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
75 trb->bpl = lower_32_bits(buf_dma);
76 trb->bph = upper_32_bits(buf_dma);
80 trb->ctrl |= (DWC3_TRB_CTRL_HWO
83 | DWC3_TRB_CTRL_ISP_IMI);
85 memset(¶ms, 0, sizeof(params));
86 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
87 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
89 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
90 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
92 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
97 dep->flags |= DWC3_EP_BUSY;
98 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
101 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
106 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
107 struct dwc3_request *req)
109 struct dwc3 *dwc = dep->dwc;
111 req->request.actual = 0;
112 req->request.status = -EINPROGRESS;
113 req->epnum = dep->number;
115 list_add_tail(&req->list, &dep->request_list);
118 * Gadget driver might not be quick enough to queue a request
119 * before we get a Transfer Not Ready event on this endpoint.
121 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
122 * flag is set, it's telling us that as soon as Gadget queues the
123 * required request, we should kick the transfer here because the
124 * IRQ we were waiting for is long gone.
126 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
129 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
131 if (dwc->ep0state != EP0_DATA_PHASE) {
132 dev_WARN(dwc->dev, "Unexpected pending request\n");
136 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
138 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
145 * In case gadget driver asked us to delay the STATUS phase,
148 if (dwc->delayed_status) {
151 direction = !dwc->ep0_expect_in;
152 dwc->delayed_status = false;
153 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
155 if (dwc->ep0state == EP0_STATUS_PHASE)
156 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
158 dwc3_trace(trace_dwc3_ep0,
159 "too early for delayed status");
165 * Unfortunately we have uncovered a limitation wrt the Data Phase.
167 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
168 * come before issueing Start Transfer command, but if we do, we will
169 * miss situations where the host starts another SETUP phase instead of
170 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
171 * Layer Compliance Suite.
173 * The problem surfaces due to the fact that in case of back-to-back
174 * SETUP packets there will be no XferNotReady(DATA) generated and we
175 * will be stuck waiting for XferNotReady(DATA) forever.
177 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
178 * it tells us to start Data Phase right away. It also mentions that if
179 * we receive a SETUP phase instead of the DATA phase, core will issue
180 * XferComplete for the DATA phase, before actually initiating it in
181 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
182 * can only be used to print some debugging logs, as the core expects
183 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
184 * just so it completes right away, without transferring anything and,
185 * only then, we can go back to the SETUP phase.
187 * Because of this scenario, SNPS decided to change the programming
188 * model of control transfers and support on-demand transfers only for
189 * the STATUS phase. To fix the issue we have now, we will always wait
190 * for gadget driver to queue the DATA phase's struct usb_request, then
191 * start it right away.
193 * If we're actually in a 2-stage transfer, we will wait for
194 * XferNotReady(STATUS).
196 if (dwc->three_stage_setup) {
199 direction = dwc->ep0_expect_in;
200 dwc->ep0state = EP0_DATA_PHASE;
202 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
204 dep->flags &= ~DWC3_EP0_DIR_IN;
210 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
213 struct dwc3_request *req = to_dwc3_request(request);
214 struct dwc3_ep *dep = to_dwc3_ep(ep);
215 struct dwc3 *dwc = dep->dwc;
221 spin_lock_irqsave(&dwc->lock, flags);
222 if (!dep->endpoint.desc) {
223 dwc3_trace(trace_dwc3_ep0,
224 "trying to queue request %p to disabled %s",
230 /* we share one TRB for ep0/1 */
231 if (!list_empty(&dep->request_list)) {
236 dwc3_trace(trace_dwc3_ep0,
237 "queueing request %p to %s length %d state '%s'",
238 request, dep->name, request->length,
239 dwc3_ep0_state_string(dwc->ep0state));
241 ret = __dwc3_gadget_ep0_queue(dep, req);
244 spin_unlock_irqrestore(&dwc->lock, flags);
249 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
253 /* reinitialize physical ep1 */
255 dep->flags = DWC3_EP_ENABLED;
257 /* stall is always issued on EP0 */
259 __dwc3_gadget_ep_set_halt(dep, 1, false);
260 dep->flags = DWC3_EP_ENABLED;
261 dwc->delayed_status = false;
263 if (!list_empty(&dep->request_list)) {
264 struct dwc3_request *req;
266 req = next_request(&dep->request_list);
267 dwc3_gadget_giveback(dep, req, -ECONNRESET);
270 dwc->ep0state = EP0_SETUP_PHASE;
271 dwc3_ep0_out_start(dwc);
274 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
276 struct dwc3_ep *dep = to_dwc3_ep(ep);
277 struct dwc3 *dwc = dep->dwc;
279 dwc3_ep0_stall_and_restart(dwc);
284 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
286 struct dwc3_ep *dep = to_dwc3_ep(ep);
287 struct dwc3 *dwc = dep->dwc;
291 spin_lock_irqsave(&dwc->lock, flags);
292 ret = __dwc3_gadget_ep0_set_halt(ep, value);
293 spin_unlock_irqrestore(&dwc->lock, flags);
298 void dwc3_ep0_out_start(struct dwc3 *dwc)
302 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
303 DWC3_TRBCTL_CONTROL_SETUP);
307 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
310 u32 windex = le16_to_cpu(wIndex_le);
313 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
314 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
317 dep = dwc->eps[epnum];
318 if (dep->flags & DWC3_EP_ENABLED)
324 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
330 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
331 struct usb_ctrlrequest *ctrl)
337 __le16 *response_pkt;
339 recip = ctrl->bRequestType & USB_RECIP_MASK;
341 case USB_RECIP_DEVICE:
343 * LTM will be set once we know how to set this in HW.
345 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
347 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
348 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
349 if (reg & DWC3_DCTL_INITU1ENA)
350 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
351 if (reg & DWC3_DCTL_INITU2ENA)
352 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
357 case USB_RECIP_INTERFACE:
359 * Function Remote Wake Capable D0
360 * Function Remote Wakeup D1
364 case USB_RECIP_ENDPOINT:
365 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
369 if (dep->flags & DWC3_EP_STALL)
370 usb_status = 1 << USB_ENDPOINT_HALT;
376 response_pkt = (__le16 *) dwc->setup_buf;
377 *response_pkt = cpu_to_le16(usb_status);
380 dwc->ep0_usb_req.dep = dep;
381 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
382 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
383 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
385 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
388 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
389 struct usb_ctrlrequest *ctrl, int set)
397 enum usb_device_state state;
399 wValue = le16_to_cpu(ctrl->wValue);
400 wIndex = le16_to_cpu(ctrl->wIndex);
401 recip = ctrl->bRequestType & USB_RECIP_MASK;
402 state = dwc->gadget.state;
405 case USB_RECIP_DEVICE:
408 case USB_DEVICE_REMOTE_WAKEUP:
411 * 9.4.1 says only only for SS, in AddressState only for
412 * default control pipe
414 case USB_DEVICE_U1_ENABLE:
415 if (state != USB_STATE_CONFIGURED)
417 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
420 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
422 reg |= DWC3_DCTL_INITU1ENA;
424 reg &= ~DWC3_DCTL_INITU1ENA;
425 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
428 case USB_DEVICE_U2_ENABLE:
429 if (state != USB_STATE_CONFIGURED)
431 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
434 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
436 reg |= DWC3_DCTL_INITU2ENA;
438 reg &= ~DWC3_DCTL_INITU2ENA;
439 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
442 case USB_DEVICE_LTM_ENABLE:
446 case USB_DEVICE_TEST_MODE:
447 if ((wIndex & 0xff) != 0)
452 dwc->test_mode_nr = wIndex >> 8;
453 dwc->test_mode = true;
460 case USB_RECIP_INTERFACE:
462 case USB_INTRF_FUNC_SUSPEND:
463 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
464 /* XXX enable Low power suspend */
466 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
467 /* XXX enable remote wakeup */
475 case USB_RECIP_ENDPOINT:
477 case USB_ENDPOINT_HALT:
478 dep = dwc3_wIndex_to_dep(dwc, wIndex);
481 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
483 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
499 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
501 enum usb_device_state state = dwc->gadget.state;
505 addr = le16_to_cpu(ctrl->wValue);
507 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
511 if (state == USB_STATE_CONFIGURED) {
512 dwc3_trace(trace_dwc3_ep0,
513 "trying to set address when configured");
517 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
518 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
519 reg |= DWC3_DCFG_DEVADDR(addr);
520 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
523 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
525 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
530 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
534 spin_unlock(&dwc->lock);
535 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
536 spin_lock(&dwc->lock);
540 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
542 enum usb_device_state state = dwc->gadget.state;
547 dwc->start_config_issued = false;
548 cfg = le16_to_cpu(ctrl->wValue);
551 case USB_STATE_DEFAULT:
555 case USB_STATE_ADDRESS:
556 ret = dwc3_ep0_delegate_req(dwc, ctrl);
557 /* if the cfg matches and the cfg is non zero */
558 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
561 * only change state if set_config has already
562 * been processed. If gadget driver returns
563 * USB_GADGET_DELAYED_STATUS, we will wait
564 * to change the state on the next usb_ep_queue()
567 usb_gadget_set_state(&dwc->gadget,
568 USB_STATE_CONFIGURED);
571 * Enable transition to U1/U2 state when
572 * nothing is pending from application.
574 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
575 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
576 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
578 dwc->resize_fifos = true;
579 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
583 case USB_STATE_CONFIGURED:
584 ret = dwc3_ep0_delegate_req(dwc, ctrl);
586 usb_gadget_set_state(&dwc->gadget,
595 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
597 struct dwc3_ep *dep = to_dwc3_ep(ep);
598 struct dwc3 *dwc = dep->dwc;
612 memcpy(&timing, req->buf, sizeof(timing));
614 dwc->u1sel = timing.u1sel;
615 dwc->u1pel = timing.u1pel;
616 dwc->u2sel = le16_to_cpu(timing.u2sel);
617 dwc->u2pel = le16_to_cpu(timing.u2pel);
619 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
620 if (reg & DWC3_DCTL_INITU2ENA)
622 if (reg & DWC3_DCTL_INITU1ENA)
626 * According to Synopsys Databook, if parameter is
627 * greater than 125, a value of zero should be
628 * programmed in the register.
633 /* now that we have the time, issue DGCMD Set Sel */
634 ret = dwc3_send_gadget_generic_command(dwc,
635 DWC3_DGCMD_SET_PERIODIC_PAR, param);
639 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
642 enum usb_device_state state = dwc->gadget.state;
646 if (state == USB_STATE_DEFAULT)
649 wValue = le16_to_cpu(ctrl->wValue);
650 wLength = le16_to_cpu(ctrl->wLength);
653 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
659 * To handle Set SEL we need to receive 6 bytes from Host. So let's
660 * queue a usb_request for 6 bytes.
662 * Remember, though, this controller can't handle non-wMaxPacketSize
663 * aligned transfers on the OUT direction, so we queue a request for
664 * wMaxPacketSize instead.
667 dwc->ep0_usb_req.dep = dep;
668 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
669 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
670 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
672 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
675 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
681 wValue = le16_to_cpu(ctrl->wValue);
682 wLength = le16_to_cpu(ctrl->wLength);
683 wIndex = le16_to_cpu(ctrl->wIndex);
685 if (wIndex || wLength)
689 * REVISIT It's unclear from Databook what to do with this
690 * value. For now, just cache it.
692 dwc->isoch_delay = wValue;
697 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
701 switch (ctrl->bRequest) {
702 case USB_REQ_GET_STATUS:
703 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS\n");
704 ret = dwc3_ep0_handle_status(dwc, ctrl);
706 case USB_REQ_CLEAR_FEATURE:
707 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE\n");
708 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
710 case USB_REQ_SET_FEATURE:
711 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE\n");
712 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
714 case USB_REQ_SET_ADDRESS:
715 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS\n");
716 ret = dwc3_ep0_set_address(dwc, ctrl);
718 case USB_REQ_SET_CONFIGURATION:
719 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION\n");
720 ret = dwc3_ep0_set_config(dwc, ctrl);
722 case USB_REQ_SET_SEL:
723 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL\n");
724 ret = dwc3_ep0_set_sel(dwc, ctrl);
726 case USB_REQ_SET_ISOCH_DELAY:
727 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY\n");
728 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
731 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver\n");
732 ret = dwc3_ep0_delegate_req(dwc, ctrl);
739 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
740 const struct dwc3_event_depevt *event)
742 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
746 if (!dwc->gadget_driver)
749 trace_dwc3_ctrl_req(ctrl);
751 len = le16_to_cpu(ctrl->wLength);
753 dwc->three_stage_setup = false;
754 dwc->ep0_expect_in = false;
755 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
757 dwc->three_stage_setup = true;
758 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
759 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
762 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
763 ret = dwc3_ep0_std_request(dwc, ctrl);
765 ret = dwc3_ep0_delegate_req(dwc, ctrl);
767 if (ret == USB_GADGET_DELAYED_STATUS)
768 dwc->delayed_status = true;
772 dwc3_ep0_stall_and_restart(dwc);
775 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
776 const struct dwc3_event_depevt *event)
778 struct dwc3_request *r = NULL;
779 struct usb_request *ur;
780 struct dwc3_trb *trb;
787 epnum = event->endpoint_number;
790 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
794 r = next_request(&ep0->request_list);
798 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
799 if (status == DWC3_TRBSTS_SETUP_PENDING) {
800 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
803 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
810 length = trb->size & DWC3_TRB_SIZE_MASK;
812 if (dwc->ep0_bounced) {
813 unsigned transfer_size = ur->length;
814 unsigned maxp = ep0->endpoint.maxpacket;
816 transfer_size += (maxp - (transfer_size % maxp));
817 transferred = min_t(u32, ur->length,
818 transfer_size - length);
819 memcpy(ur->buf, dwc->ep0_bounce, transferred);
821 transferred = ur->length - length;
824 ur->actual += transferred;
826 if ((epnum & 1) && ur->actual < ur->length) {
827 /* for some reason we did not get everything out */
829 dwc3_ep0_stall_and_restart(dwc);
831 dwc3_gadget_giveback(ep0, r, 0);
833 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
834 ur->length && ur->zero) {
837 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
839 ret = dwc3_ep0_start_trans(dwc, epnum,
840 dwc->ctrl_req_addr, 0,
841 DWC3_TRBCTL_CONTROL_DATA);
847 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
848 const struct dwc3_event_depevt *event)
850 struct dwc3_request *r;
852 struct dwc3_trb *trb;
858 if (!list_empty(&dep->request_list)) {
859 r = next_request(&dep->request_list);
861 dwc3_gadget_giveback(dep, r, 0);
864 if (dwc->test_mode) {
867 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
869 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
871 dwc3_ep0_stall_and_restart(dwc);
876 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
877 if (status == DWC3_TRBSTS_SETUP_PENDING)
878 dwc3_trace(trace_dwc3_ep0, "Setup Pending received\n");
880 dwc->ep0state = EP0_SETUP_PHASE;
881 dwc3_ep0_out_start(dwc);
884 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
885 const struct dwc3_event_depevt *event)
887 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
889 dep->flags &= ~DWC3_EP_BUSY;
890 dep->resource_index = 0;
891 dwc->setup_packet_pending = false;
893 switch (dwc->ep0state) {
894 case EP0_SETUP_PHASE:
895 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
896 dwc3_ep0_inspect_setup(dwc, event);
900 dwc3_trace(trace_dwc3_ep0, "Data Phase");
901 dwc3_ep0_complete_data(dwc, event);
904 case EP0_STATUS_PHASE:
905 dwc3_trace(trace_dwc3_ep0, "Status Phase");
906 dwc3_ep0_complete_status(dwc, event);
909 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
913 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
914 struct dwc3_ep *dep, struct dwc3_request *req)
918 req->direction = !!dep->number;
920 if (req->request.length == 0) {
921 ret = dwc3_ep0_start_trans(dwc, dep->number,
922 dwc->ctrl_req_addr, 0,
923 DWC3_TRBCTL_CONTROL_DATA);
924 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
925 && (dep->number == 0)) {
929 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
932 dev_dbg(dwc->dev, "failed to map request\n");
936 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
938 maxpacket = dep->endpoint.maxpacket;
939 transfer_size = roundup(req->request.length, maxpacket);
941 dwc->ep0_bounced = true;
944 * REVISIT in case request length is bigger than
945 * DWC3_EP0_BOUNCE_SIZE we will need two chained
946 * TRBs to handle the transfer.
948 ret = dwc3_ep0_start_trans(dwc, dep->number,
949 dwc->ep0_bounce_addr, transfer_size,
950 DWC3_TRBCTL_CONTROL_DATA);
952 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
955 dev_dbg(dwc->dev, "failed to map request\n");
959 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
960 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
966 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
968 struct dwc3 *dwc = dep->dwc;
971 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
972 : DWC3_TRBCTL_CONTROL_STATUS2;
974 return dwc3_ep0_start_trans(dwc, dep->number,
975 dwc->ctrl_req_addr, 0, type);
978 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
980 if (dwc->resize_fifos) {
981 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
982 dwc3_gadget_resize_tx_fifos(dwc);
983 dwc->resize_fifos = 0;
986 WARN_ON(dwc3_ep0_start_control_status(dep));
989 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
990 const struct dwc3_event_depevt *event)
992 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
994 __dwc3_ep0_do_control_status(dwc, dep);
997 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
999 struct dwc3_gadget_ep_cmd_params params;
1003 if (!dep->resource_index)
1006 cmd = DWC3_DEPCMD_ENDTRANSFER;
1007 cmd |= DWC3_DEPCMD_CMDIOC;
1008 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1009 memset(¶ms, 0, sizeof(params));
1010 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1012 dep->resource_index = 0;
1015 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1016 const struct dwc3_event_depevt *event)
1018 dwc->setup_packet_pending = true;
1020 switch (event->status) {
1021 case DEPEVT_STATUS_CONTROL_DATA:
1022 dwc3_trace(trace_dwc3_ep0, "Control Data");
1025 * We already have a DATA transfer in the controller's cache,
1026 * if we receive a XferNotReady(DATA) we will ignore it, unless
1027 * it's for the wrong direction.
1029 * In that case, we must issue END_TRANSFER command to the Data
1030 * Phase we already have started and issue SetStall on the
1033 if (dwc->ep0_expect_in != event->endpoint_number) {
1034 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1036 dwc3_trace(trace_dwc3_ep0,
1037 "Wrong direction for Data phase");
1038 dwc3_ep0_end_control_data(dwc, dep);
1039 dwc3_ep0_stall_and_restart(dwc);
1045 case DEPEVT_STATUS_CONTROL_STATUS:
1046 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1049 dwc3_trace(trace_dwc3_ep0, "Control Status");
1051 dwc->ep0state = EP0_STATUS_PHASE;
1053 if (dwc->delayed_status) {
1054 WARN_ON_ONCE(event->endpoint_number != 1);
1055 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1059 dwc3_ep0_do_control_status(dwc, event);
1063 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1064 const struct dwc3_event_depevt *event)
1066 u8 epnum = event->endpoint_number;
1068 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1069 dwc3_ep_event_string(event->endpoint_event),
1070 epnum >> 1, (epnum & 1) ? "in" : "out",
1071 dwc3_ep0_state_string(dwc->ep0state));
1073 switch (event->endpoint_event) {
1074 case DWC3_DEPEVT_XFERCOMPLETE:
1075 dwc3_ep0_xfer_complete(dwc, event);
1078 case DWC3_DEPEVT_XFERNOTREADY:
1079 dwc3_ep0_xfernotready(dwc, event);
1082 case DWC3_DEPEVT_XFERINPROGRESS:
1083 case DWC3_DEPEVT_RXTXFIFOEVT:
1084 case DWC3_DEPEVT_STREAMEVT:
1085 case DWC3_DEPEVT_EPCMDCMPLT: