2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
59 u32 len, u32 type, bool chain)
61 struct dwc3_gadget_ep_cmd_params params;
67 dep = dwc->eps[epnum];
68 if (dep->flags & DWC3_EP_BUSY) {
69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
73 trb = &dwc->ep0_trb[dep->free_slot];
78 trb->bpl = lower_32_bits(buf_dma);
79 trb->bph = upper_32_bits(buf_dma);
83 trb->ctrl |= (DWC3_TRB_CTRL_HWO
84 | DWC3_TRB_CTRL_ISP_IMI);
87 trb->ctrl |= DWC3_TRB_CTRL_CHN;
89 trb->ctrl |= (DWC3_TRB_CTRL_IOC
95 memset(¶ms, 0, sizeof(params));
96 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
97 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
99 trace_dwc3_prepare_trb(dep, trb);
101 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
102 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
104 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
109 dep->flags |= DWC3_EP_BUSY;
110 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
113 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
119 struct dwc3_request *req)
121 struct dwc3 *dwc = dep->dwc;
123 req->request.actual = 0;
124 req->request.status = -EINPROGRESS;
125 req->epnum = dep->number;
127 list_add_tail(&req->list, &dep->pending_list);
130 * Gadget driver might not be quick enough to queue a request
131 * before we get a Transfer Not Ready event on this endpoint.
133 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
134 * flag is set, it's telling us that as soon as Gadget queues the
135 * required request, we should kick the transfer here because the
136 * IRQ we were waiting for is long gone.
138 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
141 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
143 if (dwc->ep0state != EP0_DATA_PHASE) {
144 dev_WARN(dwc->dev, "Unexpected pending request\n");
148 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
150 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
157 * In case gadget driver asked us to delay the STATUS phase,
160 if (dwc->delayed_status) {
163 direction = !dwc->ep0_expect_in;
164 dwc->delayed_status = false;
165 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
167 if (dwc->ep0state == EP0_STATUS_PHASE)
168 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
170 dwc3_trace(trace_dwc3_ep0,
171 "too early for delayed status");
177 * Unfortunately we have uncovered a limitation wrt the Data Phase.
179 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
180 * come before issueing Start Transfer command, but if we do, we will
181 * miss situations where the host starts another SETUP phase instead of
182 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
183 * Layer Compliance Suite.
185 * The problem surfaces due to the fact that in case of back-to-back
186 * SETUP packets there will be no XferNotReady(DATA) generated and we
187 * will be stuck waiting for XferNotReady(DATA) forever.
189 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
190 * it tells us to start Data Phase right away. It also mentions that if
191 * we receive a SETUP phase instead of the DATA phase, core will issue
192 * XferComplete for the DATA phase, before actually initiating it in
193 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
194 * can only be used to print some debugging logs, as the core expects
195 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
196 * just so it completes right away, without transferring anything and,
197 * only then, we can go back to the SETUP phase.
199 * Because of this scenario, SNPS decided to change the programming
200 * model of control transfers and support on-demand transfers only for
201 * the STATUS phase. To fix the issue we have now, we will always wait
202 * for gadget driver to queue the DATA phase's struct usb_request, then
203 * start it right away.
205 * If we're actually in a 2-stage transfer, we will wait for
206 * XferNotReady(STATUS).
208 if (dwc->three_stage_setup) {
211 direction = dwc->ep0_expect_in;
212 dwc->ep0state = EP0_DATA_PHASE;
214 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
216 dep->flags &= ~DWC3_EP0_DIR_IN;
222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
225 struct dwc3_request *req = to_dwc3_request(request);
226 struct dwc3_ep *dep = to_dwc3_ep(ep);
227 struct dwc3 *dwc = dep->dwc;
233 spin_lock_irqsave(&dwc->lock, flags);
234 if (!dep->endpoint.desc) {
235 dwc3_trace(trace_dwc3_ep0,
236 "trying to queue request %p to disabled %s",
242 /* we share one TRB for ep0/1 */
243 if (!list_empty(&dep->pending_list)) {
248 dwc3_trace(trace_dwc3_ep0,
249 "queueing request %p to %s length %d state '%s'",
250 request, dep->name, request->length,
251 dwc3_ep0_state_string(dwc->ep0state));
253 ret = __dwc3_gadget_ep0_queue(dep, req);
256 spin_unlock_irqrestore(&dwc->lock, flags);
261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
265 /* reinitialize physical ep1 */
267 dep->flags = DWC3_EP_ENABLED;
269 /* stall is always issued on EP0 */
271 __dwc3_gadget_ep_set_halt(dep, 1, false);
272 dep->flags = DWC3_EP_ENABLED;
273 dwc->delayed_status = false;
275 if (!list_empty(&dep->pending_list)) {
276 struct dwc3_request *req;
278 req = next_request(&dep->pending_list);
279 dwc3_gadget_giveback(dep, req, -ECONNRESET);
282 dwc->ep0state = EP0_SETUP_PHASE;
283 dwc3_ep0_out_start(dwc);
286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
288 struct dwc3_ep *dep = to_dwc3_ep(ep);
289 struct dwc3 *dwc = dep->dwc;
291 dwc3_ep0_stall_and_restart(dwc);
296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
298 struct dwc3_ep *dep = to_dwc3_ep(ep);
299 struct dwc3 *dwc = dep->dwc;
303 spin_lock_irqsave(&dwc->lock, flags);
304 ret = __dwc3_gadget_ep0_set_halt(ep, value);
305 spin_unlock_irqrestore(&dwc->lock, flags);
310 void dwc3_ep0_out_start(struct dwc3 *dwc)
314 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
315 DWC3_TRBCTL_CONTROL_SETUP, false);
319 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
322 u32 windex = le16_to_cpu(wIndex_le);
325 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
326 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
329 dep = dwc->eps[epnum];
330 if (dep->flags & DWC3_EP_ENABLED)
336 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
342 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
343 struct usb_ctrlrequest *ctrl)
349 __le16 *response_pkt;
351 recip = ctrl->bRequestType & USB_RECIP_MASK;
353 case USB_RECIP_DEVICE:
355 * LTM will be set once we know how to set this in HW.
357 usb_status |= dwc->gadget.is_selfpowered;
359 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
360 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
361 if (reg & DWC3_DCTL_INITU1ENA)
362 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
363 if (reg & DWC3_DCTL_INITU2ENA)
364 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
369 case USB_RECIP_INTERFACE:
371 * Function Remote Wake Capable D0
372 * Function Remote Wakeup D1
376 case USB_RECIP_ENDPOINT:
377 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
381 if (dep->flags & DWC3_EP_STALL)
382 usb_status = 1 << USB_ENDPOINT_HALT;
388 response_pkt = (__le16 *) dwc->setup_buf;
389 *response_pkt = cpu_to_le16(usb_status);
392 dwc->ep0_usb_req.dep = dep;
393 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
394 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
395 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
397 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
400 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
401 struct usb_ctrlrequest *ctrl, int set)
409 enum usb_device_state state;
411 wValue = le16_to_cpu(ctrl->wValue);
412 wIndex = le16_to_cpu(ctrl->wIndex);
413 recip = ctrl->bRequestType & USB_RECIP_MASK;
414 state = dwc->gadget.state;
417 case USB_RECIP_DEVICE:
420 case USB_DEVICE_REMOTE_WAKEUP:
423 * 9.4.1 says only only for SS, in AddressState only for
424 * default control pipe
426 case USB_DEVICE_U1_ENABLE:
427 if (state != USB_STATE_CONFIGURED)
429 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
432 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
434 reg |= DWC3_DCTL_INITU1ENA;
436 reg &= ~DWC3_DCTL_INITU1ENA;
437 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
440 case USB_DEVICE_U2_ENABLE:
441 if (state != USB_STATE_CONFIGURED)
443 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
446 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
448 reg |= DWC3_DCTL_INITU2ENA;
450 reg &= ~DWC3_DCTL_INITU2ENA;
451 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
454 case USB_DEVICE_LTM_ENABLE:
457 case USB_DEVICE_TEST_MODE:
458 if ((wIndex & 0xff) != 0)
463 dwc->test_mode_nr = wIndex >> 8;
464 dwc->test_mode = true;
471 case USB_RECIP_INTERFACE:
473 case USB_INTRF_FUNC_SUSPEND:
474 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
475 /* XXX enable Low power suspend */
477 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
478 /* XXX enable remote wakeup */
486 case USB_RECIP_ENDPOINT:
488 case USB_ENDPOINT_HALT:
489 dep = dwc3_wIndex_to_dep(dwc, wIndex);
492 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
494 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
510 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
512 enum usb_device_state state = dwc->gadget.state;
516 addr = le16_to_cpu(ctrl->wValue);
518 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
522 if (state == USB_STATE_CONFIGURED) {
523 dwc3_trace(trace_dwc3_ep0,
524 "trying to set address when configured");
528 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
529 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
530 reg |= DWC3_DCFG_DEVADDR(addr);
531 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
534 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
536 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
541 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
545 spin_unlock(&dwc->lock);
546 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
547 spin_lock(&dwc->lock);
551 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
553 enum usb_device_state state = dwc->gadget.state;
558 cfg = le16_to_cpu(ctrl->wValue);
561 case USB_STATE_DEFAULT:
564 case USB_STATE_ADDRESS:
565 ret = dwc3_ep0_delegate_req(dwc, ctrl);
566 /* if the cfg matches and the cfg is non zero */
567 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
570 * only change state if set_config has already
571 * been processed. If gadget driver returns
572 * USB_GADGET_DELAYED_STATUS, we will wait
573 * to change the state on the next usb_ep_queue()
576 usb_gadget_set_state(&dwc->gadget,
577 USB_STATE_CONFIGURED);
580 * Enable transition to U1/U2 state when
581 * nothing is pending from application.
583 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
584 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
585 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
589 case USB_STATE_CONFIGURED:
590 ret = dwc3_ep0_delegate_req(dwc, ctrl);
592 usb_gadget_set_state(&dwc->gadget,
601 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
603 struct dwc3_ep *dep = to_dwc3_ep(ep);
604 struct dwc3 *dwc = dep->dwc;
618 memcpy(&timing, req->buf, sizeof(timing));
620 dwc->u1sel = timing.u1sel;
621 dwc->u1pel = timing.u1pel;
622 dwc->u2sel = le16_to_cpu(timing.u2sel);
623 dwc->u2pel = le16_to_cpu(timing.u2pel);
625 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
626 if (reg & DWC3_DCTL_INITU2ENA)
628 if (reg & DWC3_DCTL_INITU1ENA)
632 * According to Synopsys Databook, if parameter is
633 * greater than 125, a value of zero should be
634 * programmed in the register.
639 /* now that we have the time, issue DGCMD Set Sel */
640 ret = dwc3_send_gadget_generic_command(dwc,
641 DWC3_DGCMD_SET_PERIODIC_PAR, param);
645 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
648 enum usb_device_state state = dwc->gadget.state;
652 if (state == USB_STATE_DEFAULT)
655 wValue = le16_to_cpu(ctrl->wValue);
656 wLength = le16_to_cpu(ctrl->wLength);
659 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
665 * To handle Set SEL we need to receive 6 bytes from Host. So let's
666 * queue a usb_request for 6 bytes.
668 * Remember, though, this controller can't handle non-wMaxPacketSize
669 * aligned transfers on the OUT direction, so we queue a request for
670 * wMaxPacketSize instead.
673 dwc->ep0_usb_req.dep = dep;
674 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
675 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
676 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
678 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
681 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
687 wValue = le16_to_cpu(ctrl->wValue);
688 wLength = le16_to_cpu(ctrl->wLength);
689 wIndex = le16_to_cpu(ctrl->wIndex);
691 if (wIndex || wLength)
695 * REVISIT It's unclear from Databook what to do with this
696 * value. For now, just cache it.
698 dwc->isoch_delay = wValue;
703 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
707 switch (ctrl->bRequest) {
708 case USB_REQ_GET_STATUS:
709 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
710 ret = dwc3_ep0_handle_status(dwc, ctrl);
712 case USB_REQ_CLEAR_FEATURE:
713 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
714 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
716 case USB_REQ_SET_FEATURE:
717 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
718 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
720 case USB_REQ_SET_ADDRESS:
721 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
722 ret = dwc3_ep0_set_address(dwc, ctrl);
724 case USB_REQ_SET_CONFIGURATION:
725 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
726 ret = dwc3_ep0_set_config(dwc, ctrl);
728 case USB_REQ_SET_SEL:
729 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
730 ret = dwc3_ep0_set_sel(dwc, ctrl);
732 case USB_REQ_SET_ISOCH_DELAY:
733 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
734 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
737 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
738 ret = dwc3_ep0_delegate_req(dwc, ctrl);
745 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
746 const struct dwc3_event_depevt *event)
748 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
752 if (!dwc->gadget_driver)
755 trace_dwc3_ctrl_req(ctrl);
757 len = le16_to_cpu(ctrl->wLength);
759 dwc->three_stage_setup = false;
760 dwc->ep0_expect_in = false;
761 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
763 dwc->three_stage_setup = true;
764 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
765 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
768 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
769 ret = dwc3_ep0_std_request(dwc, ctrl);
771 ret = dwc3_ep0_delegate_req(dwc, ctrl);
773 if (ret == USB_GADGET_DELAYED_STATUS)
774 dwc->delayed_status = true;
778 dwc3_ep0_stall_and_restart(dwc);
781 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
782 const struct dwc3_event_depevt *event)
784 struct dwc3_request *r = NULL;
785 struct usb_request *ur;
786 struct dwc3_trb *trb;
788 unsigned transfer_size = 0;
790 unsigned remaining_ur_length;
797 epnum = event->endpoint_number;
800 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
804 trace_dwc3_complete_trb(ep0, trb);
806 r = next_request(&ep0->pending_list);
810 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
811 if (status == DWC3_TRBSTS_SETUP_PENDING) {
812 dwc->setup_packet_pending = true;
814 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
817 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
824 remaining_ur_length = ur->length;
826 length = trb->size & DWC3_TRB_SIZE_MASK;
828 maxp = ep0->endpoint.maxpacket;
830 if (dwc->ep0_bounced) {
832 * Handle the first TRB before handling the bounce buffer if
833 * the request length is greater than the bounce buffer size
835 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
836 transfer_size = ALIGN(ur->length - maxp, maxp);
837 transferred = transfer_size - length;
838 buf = (u8 *)buf + transferred;
839 ur->actual += transferred;
840 remaining_ur_length -= transferred;
843 length = trb->size & DWC3_TRB_SIZE_MASK;
848 transfer_size = roundup((ur->length - transfer_size),
851 transferred = min_t(u32, remaining_ur_length,
852 transfer_size - length);
853 memcpy(buf, dwc->ep0_bounce, transferred);
855 transferred = ur->length - length;
858 ur->actual += transferred;
860 if ((epnum & 1) && ur->actual < ur->length) {
861 /* for some reason we did not get everything out */
863 dwc3_ep0_stall_and_restart(dwc);
865 dwc3_gadget_giveback(ep0, r, 0);
867 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
868 ur->length && ur->zero) {
871 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
873 ret = dwc3_ep0_start_trans(dwc, epnum,
874 dwc->ctrl_req_addr, 0,
875 DWC3_TRBCTL_CONTROL_DATA, false);
881 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
882 const struct dwc3_event_depevt *event)
884 struct dwc3_request *r;
886 struct dwc3_trb *trb;
892 trace_dwc3_complete_trb(dep, trb);
894 if (!list_empty(&dep->pending_list)) {
895 r = next_request(&dep->pending_list);
897 dwc3_gadget_giveback(dep, r, 0);
900 if (dwc->test_mode) {
903 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
905 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
907 dwc3_ep0_stall_and_restart(dwc);
912 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
913 if (status == DWC3_TRBSTS_SETUP_PENDING) {
914 dwc->setup_packet_pending = true;
915 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
918 dwc->ep0state = EP0_SETUP_PHASE;
919 dwc3_ep0_out_start(dwc);
922 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
923 const struct dwc3_event_depevt *event)
925 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
927 dep->flags &= ~DWC3_EP_BUSY;
928 dep->resource_index = 0;
929 dwc->setup_packet_pending = false;
931 switch (dwc->ep0state) {
932 case EP0_SETUP_PHASE:
933 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
934 dwc3_ep0_inspect_setup(dwc, event);
938 dwc3_trace(trace_dwc3_ep0, "Data Phase");
939 dwc3_ep0_complete_data(dwc, event);
942 case EP0_STATUS_PHASE:
943 dwc3_trace(trace_dwc3_ep0, "Status Phase");
944 dwc3_ep0_complete_status(dwc, event);
947 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
951 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
952 struct dwc3_ep *dep, struct dwc3_request *req)
956 req->direction = !!dep->number;
958 if (req->request.length == 0) {
959 ret = dwc3_ep0_start_trans(dwc, dep->number,
960 dwc->ctrl_req_addr, 0,
961 DWC3_TRBCTL_CONTROL_DATA, false);
962 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
963 && (dep->number == 0)) {
964 u32 transfer_size = 0;
967 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
970 dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
974 maxpacket = dep->endpoint.maxpacket;
976 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
977 transfer_size = ALIGN(req->request.length - maxpacket,
979 ret = dwc3_ep0_start_trans(dwc, dep->number,
982 DWC3_TRBCTL_CONTROL_DATA,
986 transfer_size = roundup((req->request.length - transfer_size),
989 dwc->ep0_bounced = true;
991 ret = dwc3_ep0_start_trans(dwc, dep->number,
992 dwc->ep0_bounce_addr, transfer_size,
993 DWC3_TRBCTL_CONTROL_DATA, false);
995 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
998 dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1002 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1003 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1010 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1012 struct dwc3 *dwc = dep->dwc;
1015 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1016 : DWC3_TRBCTL_CONTROL_STATUS2;
1018 return dwc3_ep0_start_trans(dwc, dep->number,
1019 dwc->ctrl_req_addr, 0, type, false);
1022 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1024 WARN_ON(dwc3_ep0_start_control_status(dep));
1027 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1028 const struct dwc3_event_depevt *event)
1030 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1032 __dwc3_ep0_do_control_status(dwc, dep);
1035 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1037 struct dwc3_gadget_ep_cmd_params params;
1041 if (!dep->resource_index)
1044 cmd = DWC3_DEPCMD_ENDTRANSFER;
1045 cmd |= DWC3_DEPCMD_CMDIOC;
1046 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1047 memset(¶ms, 0, sizeof(params));
1048 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1050 dep->resource_index = 0;
1053 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1054 const struct dwc3_event_depevt *event)
1056 switch (event->status) {
1057 case DEPEVT_STATUS_CONTROL_DATA:
1058 dwc3_trace(trace_dwc3_ep0, "Control Data");
1061 * We already have a DATA transfer in the controller's cache,
1062 * if we receive a XferNotReady(DATA) we will ignore it, unless
1063 * it's for the wrong direction.
1065 * In that case, we must issue END_TRANSFER command to the Data
1066 * Phase we already have started and issue SetStall on the
1069 if (dwc->ep0_expect_in != event->endpoint_number) {
1070 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1072 dwc3_trace(trace_dwc3_ep0,
1073 "Wrong direction for Data phase");
1074 dwc3_ep0_end_control_data(dwc, dep);
1075 dwc3_ep0_stall_and_restart(dwc);
1081 case DEPEVT_STATUS_CONTROL_STATUS:
1082 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1085 dwc3_trace(trace_dwc3_ep0, "Control Status");
1087 dwc->ep0state = EP0_STATUS_PHASE;
1089 if (dwc->delayed_status) {
1090 WARN_ON_ONCE(event->endpoint_number != 1);
1091 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1095 dwc3_ep0_do_control_status(dwc, event);
1099 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1100 const struct dwc3_event_depevt *event)
1102 u8 epnum = event->endpoint_number;
1104 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1105 dwc3_ep_event_string(event->endpoint_event),
1106 epnum >> 1, (epnum & 1) ? "in" : "out",
1107 dwc3_ep0_state_string(dwc->ep0state));
1109 switch (event->endpoint_event) {
1110 case DWC3_DEPEVT_XFERCOMPLETE:
1111 dwc3_ep0_xfer_complete(dwc, event);
1114 case DWC3_DEPEVT_XFERNOTREADY:
1115 dwc3_ep0_xfernotready(dwc, event);
1118 case DWC3_DEPEVT_XFERINPROGRESS:
1119 case DWC3_DEPEVT_RXTXFIFOEVT:
1120 case DWC3_DEPEVT_STREAMEVT:
1121 case DWC3_DEPEVT_EPCMDCMPLT: