2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc->revision >= DWC3_REVISION_194A) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc->revision >= DWC3_REVISION_194A)
134 /* wait for a change in DSTS */
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
139 if (DWC3_DSTS_USBLNKST(reg) == state)
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
173 int last_fifo_depth = 0;
179 if (!dwc->needs_fifo_resize)
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
200 if (!(dep->number & 1))
203 if (!(dep->flags & DWC3_EP_ENABLED))
206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
226 fifo_size |= (last_fifo_depth << 16);
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
234 last_fifo_depth += (fifo_size & 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
243 struct dwc3 *dwc = dep->dwc;
246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
260 list_del(&req->list);
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
266 usb_gadget_unmap_request(&dwc->gadget, &req->request,
269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
270 req, dep->name, req->request.actual,
271 req->request.length, status);
273 spin_unlock(&dwc->lock);
274 req->request.complete(&dep->endpoint, &req->request);
275 spin_lock(&dwc->lock);
278 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
281 case DWC3_DEPCMD_DEPSTARTCFG:
282 return "Start New Configuration";
283 case DWC3_DEPCMD_ENDTRANSFER:
284 return "End Transfer";
285 case DWC3_DEPCMD_UPDATETRANSFER:
286 return "Update Transfer";
287 case DWC3_DEPCMD_STARTTRANSFER:
288 return "Start Transfer";
289 case DWC3_DEPCMD_CLEARSTALL:
290 return "Clear Stall";
291 case DWC3_DEPCMD_SETSTALL:
293 case DWC3_DEPCMD_GETEPSTATE:
294 return "Get Endpoint State";
295 case DWC3_DEPCMD_SETTRANSFRESOURCE:
296 return "Set Endpoint Transfer Resource";
297 case DWC3_DEPCMD_SETEPCONFIG:
298 return "Set Endpoint Configuration";
300 return "UNKNOWN command";
304 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
314 if (!(reg & DWC3_DGCMD_CMDACT)) {
315 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
316 DWC3_DGCMD_STATUS(reg));
321 * We can't sleep here, because it's also called from
331 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
334 struct dwc3_ep *dep = dwc->eps[ep];
338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
340 dwc3_gadget_ep_cmd_string(cmd), params->param0,
341 params->param1, params->param2);
343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
350 if (!(reg & DWC3_DEPCMD_CMDACT)) {
351 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
352 DWC3_DEPCMD_STATUS(reg));
357 * We can't sleep here, because it is also called from
368 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
369 struct dwc3_trb *trb)
371 u32 offset = (char *) trb - (char *) dep->trb_pool;
373 return dep->trb_pool_dma + offset;
376 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
378 struct dwc3 *dwc = dep->dwc;
383 if (dep->number == 0 || dep->number == 1)
386 dep->trb_pool = dma_alloc_coherent(dwc->dev,
387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
388 &dep->trb_pool_dma, GFP_KERNEL);
389 if (!dep->trb_pool) {
390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
398 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
400 struct dwc3 *dwc = dep->dwc;
402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
403 dep->trb_pool, dep->trb_pool_dma);
405 dep->trb_pool = NULL;
406 dep->trb_pool_dma = 0;
409 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
411 struct dwc3_gadget_ep_cmd_params params;
414 memset(¶ms, 0x00, sizeof(params));
416 if (dep->number != 1) {
417 cmd = DWC3_DEPCMD_DEPSTARTCFG;
418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
419 if (dep->number > 1) {
420 if (dwc->start_config_issued)
422 dwc->start_config_issued = true;
423 cmd |= DWC3_DEPCMD_PARAM(2);
426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
432 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
433 const struct usb_endpoint_descriptor *desc,
434 const struct usb_ss_ep_comp_descriptor *comp_desc)
436 struct dwc3_gadget_ep_cmd_params params;
438 memset(¶ms, 0x00, sizeof(params));
440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
445 | DWC3_DEPCFG_XFER_NOT_READY_EN;
447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
449 | DWC3_DEPCFG_STREAM_EVENT_EN;
450 dep->stream_capable = true;
453 if (usb_endpoint_xfer_isoc(desc))
454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
457 * We are doing 1:1 mapping for endpoints, meaning
458 * Physical Endpoints 2 maps to Logical Endpoint 2 and
459 * so on. We consider the direction bit as part of the physical
460 * endpoint number. So USB endpoint 0x81 is 0x03.
462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
465 * We must use the lower 16 TX FIFOs even though
469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
471 if (desc->bInterval) {
472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
473 dep->interval = 1 << (desc->bInterval - 1);
476 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
477 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
480 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
482 struct dwc3_gadget_ep_cmd_params params;
484 memset(¶ms, 0x00, sizeof(params));
486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
494 * @dep: endpoint to be initialized
495 * @desc: USB Endpoint Descriptor
497 * Caller should take care of locking
499 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
500 const struct usb_endpoint_descriptor *desc,
501 const struct usb_ss_ep_comp_descriptor *comp_desc)
503 struct dwc3 *dwc = dep->dwc;
507 if (!(dep->flags & DWC3_EP_ENABLED)) {
508 ret = dwc3_gadget_start_config(dwc, dep);
513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
517 if (!(dep->flags & DWC3_EP_ENABLED)) {
518 struct dwc3_trb *trb_st_hw;
519 struct dwc3_trb *trb_link;
521 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
525 dep->endpoint.desc = desc;
526 dep->comp_desc = comp_desc;
527 dep->type = usb_endpoint_type(desc);
528 dep->flags |= DWC3_EP_ENABLED;
530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
531 reg |= DWC3_DALEPENA_EP(dep->number);
532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
534 if (!usb_endpoint_xfer_isoc(desc))
537 memset(&trb_link, 0, sizeof(trb_link));
539 /* Link TRB for ISOC. The HWO bit is never reset */
540 trb_st_hw = &dep->trb_pool[0];
542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
553 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
554 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
556 struct dwc3_request *req;
558 if (!list_empty(&dep->req_queued))
559 dwc3_stop_active_transfer(dwc, dep->number);
561 while (!list_empty(&dep->request_list)) {
562 req = next_request(&dep->request_list);
564 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
569 * __dwc3_gadget_ep_disable - Disables a HW endpoint
570 * @dep: the endpoint to disable
572 * This function also removes requests which are currently processed ny the
573 * hardware and those which are not yet scheduled.
574 * Caller should take care of locking.
576 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
578 struct dwc3 *dwc = dep->dwc;
581 dwc3_remove_requests(dwc, dep);
583 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
584 reg &= ~DWC3_DALEPENA_EP(dep->number);
585 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
587 dep->stream_capable = false;
588 dep->endpoint.desc = NULL;
589 dep->comp_desc = NULL;
596 /* -------------------------------------------------------------------------- */
598 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
599 const struct usb_endpoint_descriptor *desc)
604 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
609 /* -------------------------------------------------------------------------- */
611 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
612 const struct usb_endpoint_descriptor *desc)
619 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
620 pr_debug("dwc3: invalid parameters\n");
624 if (!desc->wMaxPacketSize) {
625 pr_debug("dwc3: missing wMaxPacketSize\n");
629 dep = to_dwc3_ep(ep);
632 switch (usb_endpoint_type(desc)) {
633 case USB_ENDPOINT_XFER_CONTROL:
634 strlcat(dep->name, "-control", sizeof(dep->name));
636 case USB_ENDPOINT_XFER_ISOC:
637 strlcat(dep->name, "-isoc", sizeof(dep->name));
639 case USB_ENDPOINT_XFER_BULK:
640 strlcat(dep->name, "-bulk", sizeof(dep->name));
642 case USB_ENDPOINT_XFER_INT:
643 strlcat(dep->name, "-int", sizeof(dep->name));
646 dev_err(dwc->dev, "invalid endpoint transfer type\n");
649 if (dep->flags & DWC3_EP_ENABLED) {
650 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
655 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
657 spin_lock_irqsave(&dwc->lock, flags);
658 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
659 spin_unlock_irqrestore(&dwc->lock, flags);
664 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
672 pr_debug("dwc3: invalid parameters\n");
676 dep = to_dwc3_ep(ep);
679 if (!(dep->flags & DWC3_EP_ENABLED)) {
680 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
685 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
687 (dep->number & 1) ? "in" : "out");
689 spin_lock_irqsave(&dwc->lock, flags);
690 ret = __dwc3_gadget_ep_disable(dep);
691 spin_unlock_irqrestore(&dwc->lock, flags);
696 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
699 struct dwc3_request *req;
700 struct dwc3_ep *dep = to_dwc3_ep(ep);
701 struct dwc3 *dwc = dep->dwc;
703 req = kzalloc(sizeof(*req), gfp_flags);
705 dev_err(dwc->dev, "not enough memory\n");
709 req->epnum = dep->number;
712 return &req->request;
715 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
716 struct usb_request *request)
718 struct dwc3_request *req = to_dwc3_request(request);
724 * dwc3_prepare_one_trb - setup one TRB from one request
725 * @dep: endpoint for which this request is prepared
726 * @req: dwc3_request pointer
728 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
729 struct dwc3_request *req, dma_addr_t dma,
730 unsigned length, unsigned last, unsigned chain)
732 struct dwc3 *dwc = dep->dwc;
733 struct dwc3_trb *trb;
735 unsigned int cur_slot;
737 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
738 dep->name, req, (unsigned long long) dma,
739 length, last ? " last" : "",
740 chain ? " chain" : "");
742 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
743 cur_slot = dep->free_slot;
746 /* Skip the LINK-TRB on ISOC */
747 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
748 usb_endpoint_xfer_isoc(dep->endpoint.desc))
752 dwc3_gadget_move_request_queued(req);
754 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
757 trb->size = DWC3_TRB_SIZE_LENGTH(length);
758 trb->bpl = lower_32_bits(dma);
759 trb->bph = upper_32_bits(dma);
761 switch (usb_endpoint_type(dep->endpoint.desc)) {
762 case USB_ENDPOINT_XFER_CONTROL:
763 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
766 case USB_ENDPOINT_XFER_ISOC:
767 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
769 if (!req->request.no_interrupt)
770 trb->ctrl |= DWC3_TRB_CTRL_IOC;
773 case USB_ENDPOINT_XFER_BULK:
774 case USB_ENDPOINT_XFER_INT:
775 trb->ctrl = DWC3_TRBCTL_NORMAL;
779 * This is only possible with faulty memory because we
780 * checked it already :)
785 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
786 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
787 trb->ctrl |= DWC3_TRB_CTRL_CSP;
790 trb->ctrl |= DWC3_TRB_CTRL_CHN;
793 trb->ctrl |= DWC3_TRB_CTRL_LST;
796 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
797 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
799 trb->ctrl |= DWC3_TRB_CTRL_HWO;
803 * dwc3_prepare_trbs - setup TRBs from requests
804 * @dep: endpoint for which requests are being prepared
805 * @starting: true if the endpoint is idle and no requests are queued.
807 * The function goes through the requests list and sets up TRBs for the
808 * transfers. The function returns once there are no more TRBs available or
809 * it runs out of requests.
811 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
813 struct dwc3_request *req, *n;
816 unsigned int last_one = 0;
818 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
820 /* the first request must not be queued */
821 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
823 /* Can't wrap around on a non-isoc EP since there's no link TRB */
824 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
825 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
831 * If busy & slot are equal than it is either full or empty. If we are
832 * starting to process requests then we are empty. Otherwise we are
833 * full and don't do anything
838 trbs_left = DWC3_TRB_NUM;
840 * In case we start from scratch, we queue the ISOC requests
841 * starting from slot 1. This is done because we use ring
842 * buffer and have no LST bit to stop us. Instead, we place
843 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
844 * after the first request so we start at slot 1 and have
845 * 7 requests proceed before we hit the first IOC.
846 * Other transfer types don't use the ring buffer and are
847 * processed from the first TRB until the last one. Since we
848 * don't wrap around we have to start at the beginning.
850 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
859 /* The last TRB is a link TRB, not used for xfer */
860 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
863 list_for_each_entry_safe(req, n, &dep->request_list, list) {
867 if (req->request.num_mapped_sgs > 0) {
868 struct usb_request *request = &req->request;
869 struct scatterlist *sg = request->sg;
870 struct scatterlist *s;
873 for_each_sg(sg, s, request->num_mapped_sgs, i) {
874 unsigned chain = true;
876 length = sg_dma_len(s);
877 dma = sg_dma_address(s);
879 if (i == (request->num_mapped_sgs - 1) ||
892 dwc3_prepare_one_trb(dep, req, dma, length,
899 dma = req->request.dma;
900 length = req->request.length;
906 /* Is this the last request? */
907 if (list_is_last(&req->list, &dep->request_list))
910 dwc3_prepare_one_trb(dep, req, dma, length,
919 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
922 struct dwc3_gadget_ep_cmd_params params;
923 struct dwc3_request *req;
924 struct dwc3 *dwc = dep->dwc;
928 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
929 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
932 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
935 * If we are getting here after a short-out-packet we don't enqueue any
936 * new requests as we try to set the IOC bit only on the last request.
939 if (list_empty(&dep->req_queued))
940 dwc3_prepare_trbs(dep, start_new);
942 /* req points to the first request which will be sent */
943 req = next_request(&dep->req_queued);
945 dwc3_prepare_trbs(dep, start_new);
948 * req points to the first request where HWO changed from 0 to 1
950 req = next_request(&dep->req_queued);
953 dep->flags |= DWC3_EP_PENDING_REQUEST;
957 memset(¶ms, 0, sizeof(params));
958 params.param0 = upper_32_bits(req->trb_dma);
959 params.param1 = lower_32_bits(req->trb_dma);
962 cmd = DWC3_DEPCMD_STARTTRANSFER;
964 cmd = DWC3_DEPCMD_UPDATETRANSFER;
966 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
967 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
969 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
972 * FIXME we need to iterate over the list of requests
973 * here and stop, unmap, free and del each of the linked
974 * requests instead of what we do now.
976 usb_gadget_unmap_request(&dwc->gadget, &req->request,
978 list_del(&req->list);
982 dep->flags |= DWC3_EP_BUSY;
985 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
987 WARN_ON_ONCE(!dep->res_trans_idx);
993 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
994 struct dwc3_ep *dep, u32 cur_uf)
998 if (list_empty(&dep->request_list)) {
999 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1004 /* 4 micro frames in the future */
1005 uf = cur_uf + dep->interval * 4;
1007 __dwc3_gadget_kick_transfer(dep, uf, 1);
1010 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1011 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1015 mask = ~(dep->interval - 1);
1016 cur_uf = event->parameters & mask;
1018 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1021 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1023 struct dwc3 *dwc = dep->dwc;
1026 req->request.actual = 0;
1027 req->request.status = -EINPROGRESS;
1028 req->direction = dep->direction;
1029 req->epnum = dep->number;
1032 * We only add to our list of requests now and
1033 * start consuming the list once we get XferNotReady
1036 * That way, we avoid doing anything that we don't need
1037 * to do now and defer it until the point we receive a
1038 * particular token from the Host side.
1040 * This will also avoid Host cancelling URBs due to too
1043 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1048 list_add_tail(&req->list, &dep->request_list);
1050 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1051 if (dep->flags & DWC3_EP_BUSY) {
1052 dep->flags |= DWC3_EP_PENDING_REQUEST;
1053 } else if (dep->flags & DWC3_EP_MISSED_ISOC) {
1054 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1055 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1060 * There are two special cases:
1062 * 1. XferNotReady with empty list of requests. We need to kick the
1063 * transfer here in that situation, otherwise we will be NAKing
1064 * forever. If we get XferNotReady before gadget driver has a
1065 * chance to queue a request, we will ACK the IRQ but won't be
1066 * able to receive the data until the next request is queued.
1067 * The following code is handling exactly that.
1069 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1070 * kick the transfer here after queuing a request, otherwise the
1071 * core may not see the modified TRB(s).
1073 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1075 int start_trans = 1;
1076 u8 trans_idx = dep->res_trans_idx;
1078 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1079 (dep->flags & DWC3_EP_BUSY)) {
1081 WARN_ON_ONCE(!trans_idx);
1086 ret = __dwc3_gadget_kick_transfer(dep, trans_idx, start_trans);
1087 if (ret && ret != -EBUSY) {
1088 struct dwc3 *dwc = dep->dwc;
1090 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1098 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1101 struct dwc3_request *req = to_dwc3_request(request);
1102 struct dwc3_ep *dep = to_dwc3_ep(ep);
1103 struct dwc3 *dwc = dep->dwc;
1105 unsigned long flags;
1109 if (!dep->endpoint.desc) {
1110 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1115 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1116 request, ep->name, request->length);
1118 spin_lock_irqsave(&dwc->lock, flags);
1119 ret = __dwc3_gadget_ep_queue(dep, req);
1120 spin_unlock_irqrestore(&dwc->lock, flags);
1125 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1126 struct usb_request *request)
1128 struct dwc3_request *req = to_dwc3_request(request);
1129 struct dwc3_request *r = NULL;
1131 struct dwc3_ep *dep = to_dwc3_ep(ep);
1132 struct dwc3 *dwc = dep->dwc;
1134 unsigned long flags;
1137 spin_lock_irqsave(&dwc->lock, flags);
1139 list_for_each_entry(r, &dep->request_list, list) {
1145 list_for_each_entry(r, &dep->req_queued, list) {
1150 /* wait until it is processed */
1151 dwc3_stop_active_transfer(dwc, dep->number);
1154 dev_err(dwc->dev, "request %p was not queued to %s\n",
1160 /* giveback the request */
1161 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1164 spin_unlock_irqrestore(&dwc->lock, flags);
1169 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1171 struct dwc3_gadget_ep_cmd_params params;
1172 struct dwc3 *dwc = dep->dwc;
1175 memset(¶ms, 0x00, sizeof(params));
1178 if (dep->number == 0 || dep->number == 1) {
1180 * Whenever EP0 is stalled, we will restart
1181 * the state machine, thus moving back to
1184 dwc->ep0state = EP0_SETUP_PHASE;
1187 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1188 DWC3_DEPCMD_SETSTALL, ¶ms);
1190 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1191 value ? "set" : "clear",
1194 dep->flags |= DWC3_EP_STALL;
1196 if (dep->flags & DWC3_EP_WEDGE)
1199 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1200 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1202 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1203 value ? "set" : "clear",
1206 dep->flags &= ~DWC3_EP_STALL;
1212 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1214 struct dwc3_ep *dep = to_dwc3_ep(ep);
1215 struct dwc3 *dwc = dep->dwc;
1217 unsigned long flags;
1221 spin_lock_irqsave(&dwc->lock, flags);
1223 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1224 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1229 ret = __dwc3_gadget_ep_set_halt(dep, value);
1231 spin_unlock_irqrestore(&dwc->lock, flags);
1236 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1238 struct dwc3_ep *dep = to_dwc3_ep(ep);
1239 struct dwc3 *dwc = dep->dwc;
1240 unsigned long flags;
1242 spin_lock_irqsave(&dwc->lock, flags);
1243 dep->flags |= DWC3_EP_WEDGE;
1244 spin_unlock_irqrestore(&dwc->lock, flags);
1246 return dwc3_gadget_ep_set_halt(ep, 1);
1249 /* -------------------------------------------------------------------------- */
1251 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1252 .bLength = USB_DT_ENDPOINT_SIZE,
1253 .bDescriptorType = USB_DT_ENDPOINT,
1254 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1257 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1258 .enable = dwc3_gadget_ep0_enable,
1259 .disable = dwc3_gadget_ep0_disable,
1260 .alloc_request = dwc3_gadget_ep_alloc_request,
1261 .free_request = dwc3_gadget_ep_free_request,
1262 .queue = dwc3_gadget_ep0_queue,
1263 .dequeue = dwc3_gadget_ep_dequeue,
1264 .set_halt = dwc3_gadget_ep_set_halt,
1265 .set_wedge = dwc3_gadget_ep_set_wedge,
1268 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1269 .enable = dwc3_gadget_ep_enable,
1270 .disable = dwc3_gadget_ep_disable,
1271 .alloc_request = dwc3_gadget_ep_alloc_request,
1272 .free_request = dwc3_gadget_ep_free_request,
1273 .queue = dwc3_gadget_ep_queue,
1274 .dequeue = dwc3_gadget_ep_dequeue,
1275 .set_halt = dwc3_gadget_ep_set_halt,
1276 .set_wedge = dwc3_gadget_ep_set_wedge,
1279 /* -------------------------------------------------------------------------- */
1281 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1283 struct dwc3 *dwc = gadget_to_dwc(g);
1286 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1287 return DWC3_DSTS_SOFFN(reg);
1290 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1292 struct dwc3 *dwc = gadget_to_dwc(g);
1294 unsigned long timeout;
1295 unsigned long flags;
1304 spin_lock_irqsave(&dwc->lock, flags);
1307 * According to the Databook Remote wakeup request should
1308 * be issued only when the device is in early suspend state.
1310 * We can check that via USB Link State bits in DSTS register.
1312 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1314 speed = reg & DWC3_DSTS_CONNECTSPD;
1315 if (speed == DWC3_DSTS_SUPERSPEED) {
1316 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1321 link_state = DWC3_DSTS_USBLNKST(reg);
1323 switch (link_state) {
1324 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1325 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1328 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1334 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1336 dev_err(dwc->dev, "failed to put link in Recovery\n");
1340 /* Recent versions do this automatically */
1341 if (dwc->revision < DWC3_REVISION_194A) {
1342 /* write zeroes to Link Change Request */
1343 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1344 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1345 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1348 /* poll until Link State changes to ON */
1349 timeout = jiffies + msecs_to_jiffies(100);
1351 while (!time_after(jiffies, timeout)) {
1352 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1354 /* in HS, means ON */
1355 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1359 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1360 dev_err(dwc->dev, "failed to send remote wakeup\n");
1365 spin_unlock_irqrestore(&dwc->lock, flags);
1370 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1373 struct dwc3 *dwc = gadget_to_dwc(g);
1374 unsigned long flags;
1376 spin_lock_irqsave(&dwc->lock, flags);
1377 dwc->is_selfpowered = !!is_selfpowered;
1378 spin_unlock_irqrestore(&dwc->lock, flags);
1383 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1388 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1390 if (dwc->revision <= DWC3_REVISION_187A) {
1391 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1392 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1395 if (dwc->revision >= DWC3_REVISION_194A)
1396 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1397 reg |= DWC3_DCTL_RUN_STOP;
1399 reg &= ~DWC3_DCTL_RUN_STOP;
1402 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1405 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1407 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1410 if (reg & DWC3_DSTS_DEVCTRLHLT)
1419 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1421 ? dwc->gadget_driver->function : "no-function",
1422 is_on ? "connect" : "disconnect");
1425 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1427 struct dwc3 *dwc = gadget_to_dwc(g);
1428 unsigned long flags;
1432 spin_lock_irqsave(&dwc->lock, flags);
1433 dwc3_gadget_run_stop(dwc, is_on);
1434 spin_unlock_irqrestore(&dwc->lock, flags);
1439 static int dwc3_gadget_start(struct usb_gadget *g,
1440 struct usb_gadget_driver *driver)
1442 struct dwc3 *dwc = gadget_to_dwc(g);
1443 struct dwc3_ep *dep;
1444 unsigned long flags;
1448 spin_lock_irqsave(&dwc->lock, flags);
1450 if (dwc->gadget_driver) {
1451 dev_err(dwc->dev, "%s is already bound to %s\n",
1453 dwc->gadget_driver->driver.name);
1458 dwc->gadget_driver = driver;
1459 dwc->gadget.dev.driver = &driver->driver;
1461 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1462 reg &= ~(DWC3_DCFG_SPEED_MASK);
1465 * WORKAROUND: DWC3 revision < 2.20a have an issue
1466 * which would cause metastability state on Run/Stop
1467 * bit if we try to force the IP to USB2-only mode.
1469 * Because of that, we cannot configure the IP to any
1470 * speed other than the SuperSpeed
1474 * STAR#9000525659: Clock Domain Crossing on DCTL in
1477 if (dwc->revision < DWC3_REVISION_220A)
1478 reg |= DWC3_DCFG_SUPERSPEED;
1480 reg |= dwc->maximum_speed;
1481 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1483 dwc->start_config_issued = false;
1485 /* Start with SuperSpeed Default */
1486 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1489 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1491 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1496 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1498 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1502 /* begin to receive SETUP packets */
1503 dwc->ep0state = EP0_SETUP_PHASE;
1504 dwc3_ep0_out_start(dwc);
1506 spin_unlock_irqrestore(&dwc->lock, flags);
1511 __dwc3_gadget_ep_disable(dwc->eps[0]);
1514 spin_unlock_irqrestore(&dwc->lock, flags);
1519 static int dwc3_gadget_stop(struct usb_gadget *g,
1520 struct usb_gadget_driver *driver)
1522 struct dwc3 *dwc = gadget_to_dwc(g);
1523 unsigned long flags;
1525 spin_lock_irqsave(&dwc->lock, flags);
1527 __dwc3_gadget_ep_disable(dwc->eps[0]);
1528 __dwc3_gadget_ep_disable(dwc->eps[1]);
1530 dwc->gadget_driver = NULL;
1531 dwc->gadget.dev.driver = NULL;
1533 spin_unlock_irqrestore(&dwc->lock, flags);
1538 static const struct usb_gadget_ops dwc3_gadget_ops = {
1539 .get_frame = dwc3_gadget_get_frame,
1540 .wakeup = dwc3_gadget_wakeup,
1541 .set_selfpowered = dwc3_gadget_set_selfpowered,
1542 .pullup = dwc3_gadget_pullup,
1543 .udc_start = dwc3_gadget_start,
1544 .udc_stop = dwc3_gadget_stop,
1547 /* -------------------------------------------------------------------------- */
1549 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1551 struct dwc3_ep *dep;
1554 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1556 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1557 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1559 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1565 dep->number = epnum;
1566 dwc->eps[epnum] = dep;
1568 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1569 (epnum & 1) ? "in" : "out");
1570 dep->endpoint.name = dep->name;
1571 dep->direction = (epnum & 1);
1573 if (epnum == 0 || epnum == 1) {
1574 dep->endpoint.maxpacket = 512;
1575 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1577 dwc->gadget.ep0 = &dep->endpoint;
1581 dep->endpoint.maxpacket = 1024;
1582 dep->endpoint.max_streams = 15;
1583 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1584 list_add_tail(&dep->endpoint.ep_list,
1585 &dwc->gadget.ep_list);
1587 ret = dwc3_alloc_trb_pool(dep);
1592 INIT_LIST_HEAD(&dep->request_list);
1593 INIT_LIST_HEAD(&dep->req_queued);
1599 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1601 struct dwc3_ep *dep;
1604 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1605 dep = dwc->eps[epnum];
1606 dwc3_free_trb_pool(dep);
1608 if (epnum != 0 && epnum != 1)
1609 list_del(&dep->endpoint.ep_list);
1615 static void dwc3_gadget_release(struct device *dev)
1617 dev_dbg(dev, "%s\n", __func__);
1620 /* -------------------------------------------------------------------------- */
1621 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1622 const struct dwc3_event_depevt *event, int status)
1624 struct dwc3_request *req;
1625 struct dwc3_trb *trb;
1627 unsigned int s_pkt = 0;
1628 unsigned int trb_status;
1631 req = next_request(&dep->req_queued);
1639 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1641 * We continue despite the error. There is not much we
1642 * can do. If we don't clean it up we loop forever. If
1643 * we skip the TRB then it gets overwritten after a
1644 * while since we use them in a ring buffer. A BUG()
1645 * would help. Lets hope that if this occurs, someone
1646 * fixes the root cause instead of looking away :)
1648 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1649 dep->name, req->trb);
1650 count = trb->size & DWC3_TRB_SIZE_MASK;
1652 if (dep->direction) {
1654 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1655 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1656 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1658 dep->current_uf = event->parameters &
1659 ~(dep->interval - 1);
1660 dep->flags |= DWC3_EP_MISSED_ISOC;
1662 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1664 status = -ECONNRESET;
1668 if (count && (event->status & DEPEVT_STATUS_SHORT))
1673 * We assume here we will always receive the entire data block
1674 * which we should receive. Meaning, if we program RX to
1675 * receive 4K but we receive only 2K, we assume that's all we
1676 * should receive and we simply bounce the request back to the
1677 * gadget driver for further processing.
1679 req->request.actual += req->request.length - count;
1680 dwc3_gadget_giveback(dep, req, status);
1683 if ((event->status & DEPEVT_STATUS_LST) &&
1684 (trb->ctrl & DWC3_TRB_CTRL_LST))
1686 if ((event->status & DEPEVT_STATUS_IOC) &&
1687 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1691 if ((event->status & DEPEVT_STATUS_IOC) &&
1692 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1697 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1698 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1701 unsigned status = 0;
1704 if (event->status & DEPEVT_STATUS_BUSERR)
1705 status = -ECONNRESET;
1707 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1709 dep->flags &= ~DWC3_EP_BUSY;
1712 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1713 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1715 if (dwc->revision < DWC3_REVISION_183A) {
1719 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1720 struct dwc3_ep *dep = dwc->eps[i];
1722 if (!(dep->flags & DWC3_EP_ENABLED))
1725 if (!list_empty(&dep->req_queued))
1729 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1731 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1737 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1738 const struct dwc3_event_depevt *event)
1740 struct dwc3 *dwc = dep->dwc;
1741 struct dwc3_event_depevt mod_ev = *event;
1744 * We were asked to remove one request. It is possible that this
1745 * request and a few others were started together and have the same
1746 * transfer index. Since we stopped the complete endpoint we don't
1747 * know how many requests were already completed (and not yet)
1748 * reported and how could be done (later). We purge them all until
1749 * the end of the list.
1751 mod_ev.status = DEPEVT_STATUS_LST;
1752 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1753 dep->flags &= ~DWC3_EP_BUSY;
1754 /* pending requests are ignored and are queued on XferNotReady */
1757 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1758 const struct dwc3_event_depevt *event)
1760 u32 param = event->parameters;
1761 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1764 case DWC3_DEPCMD_ENDTRANSFER:
1765 dwc3_process_ep_cmd_complete(dep, event);
1767 case DWC3_DEPCMD_STARTTRANSFER:
1768 dep->res_trans_idx = param & 0x7f;
1771 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1772 __func__, cmd_type);
1777 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1778 const struct dwc3_event_depevt *event)
1780 struct dwc3_ep *dep;
1781 u8 epnum = event->endpoint_number;
1783 dep = dwc->eps[epnum];
1785 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1786 dwc3_ep_event_string(event->endpoint_event));
1788 if (epnum == 0 || epnum == 1) {
1789 dwc3_ep0_interrupt(dwc, event);
1793 switch (event->endpoint_event) {
1794 case DWC3_DEPEVT_XFERCOMPLETE:
1795 dep->res_trans_idx = 0;
1797 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1798 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1803 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1805 case DWC3_DEPEVT_XFERINPROGRESS:
1806 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1807 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1812 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1814 case DWC3_DEPEVT_XFERNOTREADY:
1815 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1816 dwc3_gadget_start_isoc(dwc, dep, event);
1820 dev_vdbg(dwc->dev, "%s: reason %s\n",
1821 dep->name, event->status &
1822 DEPEVT_STATUS_TRANSFER_ACTIVE
1824 : "Transfer Not Active");
1826 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1827 if (!ret || ret == -EBUSY)
1830 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1835 case DWC3_DEPEVT_STREAMEVT:
1836 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1837 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1842 switch (event->status) {
1843 case DEPEVT_STREAMEVT_FOUND:
1844 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1848 case DEPEVT_STREAMEVT_NOTFOUND:
1851 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1854 case DWC3_DEPEVT_RXTXFIFOEVT:
1855 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1857 case DWC3_DEPEVT_EPCMDCMPLT:
1858 dwc3_ep_cmd_compl(dep, event);
1863 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1865 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1866 spin_unlock(&dwc->lock);
1867 dwc->gadget_driver->disconnect(&dwc->gadget);
1868 spin_lock(&dwc->lock);
1872 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1874 struct dwc3_ep *dep;
1875 struct dwc3_gadget_ep_cmd_params params;
1879 dep = dwc->eps[epnum];
1881 WARN_ON(!dep->res_trans_idx);
1882 if (dep->res_trans_idx) {
1883 cmd = DWC3_DEPCMD_ENDTRANSFER;
1884 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1885 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1886 memset(¶ms, 0, sizeof(params));
1887 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1889 dep->res_trans_idx = 0;
1893 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1897 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1898 struct dwc3_ep *dep;
1900 dep = dwc->eps[epnum];
1901 if (!(dep->flags & DWC3_EP_ENABLED))
1904 dwc3_remove_requests(dwc, dep);
1908 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1912 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1913 struct dwc3_ep *dep;
1914 struct dwc3_gadget_ep_cmd_params params;
1917 dep = dwc->eps[epnum];
1919 if (!(dep->flags & DWC3_EP_STALL))
1922 dep->flags &= ~DWC3_EP_STALL;
1924 memset(¶ms, 0, sizeof(params));
1925 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1926 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1931 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1935 dev_vdbg(dwc->dev, "%s\n", __func__);
1937 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1938 reg &= ~DWC3_DCTL_INITU1ENA;
1939 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1941 reg &= ~DWC3_DCTL_INITU2ENA;
1942 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1944 dwc3_stop_active_transfers(dwc);
1945 dwc3_disconnect_gadget(dwc);
1946 dwc->start_config_issued = false;
1948 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1949 dwc->setup_packet_pending = false;
1952 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
1956 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1959 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1961 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1963 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1966 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
1970 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1973 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1975 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1977 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1980 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1984 dev_vdbg(dwc->dev, "%s\n", __func__);
1987 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1988 * would cause a missing Disconnect Event if there's a
1989 * pending Setup Packet in the FIFO.
1991 * There's no suggested workaround on the official Bug
1992 * report, which states that "unless the driver/application
1993 * is doing any special handling of a disconnect event,
1994 * there is no functional issue".
1996 * Unfortunately, it turns out that we _do_ some special
1997 * handling of a disconnect event, namely complete all
1998 * pending transfers, notify gadget driver of the
1999 * disconnection, and so on.
2001 * Our suggested workaround is to follow the Disconnect
2002 * Event steps here, instead, based on a setup_packet_pending
2003 * flag. Such flag gets set whenever we have a XferNotReady
2004 * event on EP0 and gets cleared on XferComplete for the
2009 * STAR#9000466709: RTL: Device : Disconnect event not
2010 * generated if setup packet pending in FIFO
2012 if (dwc->revision < DWC3_REVISION_188A) {
2013 if (dwc->setup_packet_pending)
2014 dwc3_gadget_disconnect_interrupt(dwc);
2017 /* after reset -> Default State */
2018 dwc->dev_state = DWC3_DEFAULT_STATE;
2020 /* Recent versions support automatic phy suspend and don't need this */
2021 if (dwc->revision < DWC3_REVISION_194A) {
2023 dwc3_gadget_usb2_phy_suspend(dwc, false);
2024 dwc3_gadget_usb3_phy_suspend(dwc, false);
2027 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2028 dwc3_disconnect_gadget(dwc);
2030 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2031 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2032 reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
2033 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
2034 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2035 dwc->test_mode = false;
2037 dwc3_stop_active_transfers(dwc);
2038 dwc3_clear_stall_all_ep(dwc);
2039 dwc->start_config_issued = false;
2041 /* Reset device address to zero */
2042 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2043 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2044 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2047 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2050 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2053 * We change the clock only at SS but I dunno why I would want to do
2054 * this. Maybe it becomes part of the power saving plan.
2057 if (speed != DWC3_DSTS_SUPERSPEED)
2061 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2062 * each time on Connect Done.
2067 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2068 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2069 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2072 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2075 case USB_SPEED_SUPER:
2076 dwc3_gadget_usb2_phy_suspend(dwc, true);
2078 case USB_SPEED_HIGH:
2079 case USB_SPEED_FULL:
2081 dwc3_gadget_usb3_phy_suspend(dwc, true);
2086 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2088 struct dwc3_gadget_ep_cmd_params params;
2089 struct dwc3_ep *dep;
2094 dev_vdbg(dwc->dev, "%s\n", __func__);
2096 memset(¶ms, 0x00, sizeof(params));
2098 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2099 speed = reg & DWC3_DSTS_CONNECTSPD;
2102 dwc3_update_ram_clk_sel(dwc, speed);
2105 case DWC3_DCFG_SUPERSPEED:
2107 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2108 * would cause a missing USB3 Reset event.
2110 * In such situations, we should force a USB3 Reset
2111 * event by calling our dwc3_gadget_reset_interrupt()
2116 * STAR#9000483510: RTL: SS : USB3 reset event may
2117 * not be generated always when the link enters poll
2119 if (dwc->revision < DWC3_REVISION_190A)
2120 dwc3_gadget_reset_interrupt(dwc);
2122 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2123 dwc->gadget.ep0->maxpacket = 512;
2124 dwc->gadget.speed = USB_SPEED_SUPER;
2126 case DWC3_DCFG_HIGHSPEED:
2127 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2128 dwc->gadget.ep0->maxpacket = 64;
2129 dwc->gadget.speed = USB_SPEED_HIGH;
2131 case DWC3_DCFG_FULLSPEED2:
2132 case DWC3_DCFG_FULLSPEED1:
2133 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2134 dwc->gadget.ep0->maxpacket = 64;
2135 dwc->gadget.speed = USB_SPEED_FULL;
2137 case DWC3_DCFG_LOWSPEED:
2138 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2139 dwc->gadget.ep0->maxpacket = 8;
2140 dwc->gadget.speed = USB_SPEED_LOW;
2144 /* Recent versions support automatic phy suspend and don't need this */
2145 if (dwc->revision < DWC3_REVISION_194A) {
2146 /* Suspend unneeded PHY */
2147 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2151 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2153 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2158 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2160 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2165 * Configure PHY via GUSB3PIPECTLn if required.
2167 * Update GTXFIFOSIZn
2169 * In both cases reset values should be sufficient.
2173 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2175 dev_vdbg(dwc->dev, "%s\n", __func__);
2178 * TODO take core out of low power mode when that's
2182 dwc->gadget_driver->resume(&dwc->gadget);
2185 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2186 unsigned int evtinfo)
2188 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2191 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2192 * on the link partner, the USB session might do multiple entry/exit
2193 * of low power states before a transfer takes place.
2195 * Due to this problem, we might experience lower throughput. The
2196 * suggested workaround is to disable DCTL[12:9] bits if we're
2197 * transitioning from U1/U2 to U0 and enable those bits again
2198 * after a transfer completes and there are no pending transfers
2199 * on any of the enabled endpoints.
2201 * This is the first half of that workaround.
2205 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2206 * core send LGO_Ux entering U0
2208 if (dwc->revision < DWC3_REVISION_183A) {
2209 if (next == DWC3_LINK_STATE_U0) {
2213 switch (dwc->link_state) {
2214 case DWC3_LINK_STATE_U1:
2215 case DWC3_LINK_STATE_U2:
2216 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2217 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2218 | DWC3_DCTL_ACCEPTU2ENA
2219 | DWC3_DCTL_INITU1ENA
2220 | DWC3_DCTL_ACCEPTU1ENA);
2223 dwc->u1u2 = reg & u1u2;
2227 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2236 dwc->link_state = next;
2238 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2241 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2242 const struct dwc3_event_devt *event)
2244 switch (event->type) {
2245 case DWC3_DEVICE_EVENT_DISCONNECT:
2246 dwc3_gadget_disconnect_interrupt(dwc);
2248 case DWC3_DEVICE_EVENT_RESET:
2249 dwc3_gadget_reset_interrupt(dwc);
2251 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2252 dwc3_gadget_conndone_interrupt(dwc);
2254 case DWC3_DEVICE_EVENT_WAKEUP:
2255 dwc3_gadget_wakeup_interrupt(dwc);
2257 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2258 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2260 case DWC3_DEVICE_EVENT_EOPF:
2261 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2263 case DWC3_DEVICE_EVENT_SOF:
2264 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2266 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2267 dev_vdbg(dwc->dev, "Erratic Error\n");
2269 case DWC3_DEVICE_EVENT_CMD_CMPL:
2270 dev_vdbg(dwc->dev, "Command Complete\n");
2272 case DWC3_DEVICE_EVENT_OVERFLOW:
2273 dev_vdbg(dwc->dev, "Overflow\n");
2276 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2280 static void dwc3_process_event_entry(struct dwc3 *dwc,
2281 const union dwc3_event *event)
2283 /* Endpoint IRQ, handle it and return early */
2284 if (event->type.is_devspec == 0) {
2286 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2289 switch (event->type.type) {
2290 case DWC3_EVENT_TYPE_DEV:
2291 dwc3_gadget_interrupt(dwc, &event->devt);
2293 /* REVISIT what to do with Carkit and I2C events ? */
2295 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2299 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2301 struct dwc3_event_buffer *evt;
2305 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2306 count &= DWC3_GEVNTCOUNT_MASK;
2310 evt = dwc->ev_buffs[buf];
2314 union dwc3_event event;
2316 event.raw = *(u32 *) (evt->buf + evt->lpos);
2318 dwc3_process_event_entry(dwc, &event);
2320 * XXX we wrap around correctly to the next entry as almost all
2321 * entries are 4 bytes in size. There is one entry which has 12
2322 * bytes which is a regular entry followed by 8 bytes data. ATM
2323 * I don't know how things are organized if were get next to the
2324 * a boundary so I worry about that once we try to handle that.
2326 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2329 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2335 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2337 struct dwc3 *dwc = _dwc;
2339 irqreturn_t ret = IRQ_NONE;
2341 spin_lock(&dwc->lock);
2343 for (i = 0; i < dwc->num_event_buffers; i++) {
2346 status = dwc3_process_event_buf(dwc, i);
2347 if (status == IRQ_HANDLED)
2351 spin_unlock(&dwc->lock);
2357 * dwc3_gadget_init - Initializes gadget related registers
2358 * @dwc: pointer to our controller context structure
2360 * Returns 0 on success otherwise negative errno.
2362 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2368 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2369 &dwc->ctrl_req_addr, GFP_KERNEL);
2370 if (!dwc->ctrl_req) {
2371 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2376 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2377 &dwc->ep0_trb_addr, GFP_KERNEL);
2378 if (!dwc->ep0_trb) {
2379 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2384 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2385 if (!dwc->setup_buf) {
2386 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2391 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2392 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2394 if (!dwc->ep0_bounce) {
2395 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2400 dev_set_name(&dwc->gadget.dev, "gadget");
2402 dwc->gadget.ops = &dwc3_gadget_ops;
2403 dwc->gadget.max_speed = USB_SPEED_SUPER;
2404 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2405 dwc->gadget.dev.parent = dwc->dev;
2406 dwc->gadget.sg_supported = true;
2408 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2410 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2411 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2412 dwc->gadget.dev.release = dwc3_gadget_release;
2413 dwc->gadget.name = "dwc3-gadget";
2416 * REVISIT: Here we should clear all pending IRQs to be
2417 * sure we're starting from a well known location.
2420 ret = dwc3_gadget_init_endpoints(dwc);
2424 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2426 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2429 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2434 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2435 reg |= DWC3_DCFG_LPM_CAP;
2436 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2438 /* Enable all but Start and End of Frame IRQs */
2439 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2440 DWC3_DEVTEN_EVNTOVERFLOWEN |
2441 DWC3_DEVTEN_CMDCMPLTEN |
2442 DWC3_DEVTEN_ERRTICERREN |
2443 DWC3_DEVTEN_WKUPEVTEN |
2444 DWC3_DEVTEN_ULSTCNGEN |
2445 DWC3_DEVTEN_CONNECTDONEEN |
2446 DWC3_DEVTEN_USBRSTEN |
2447 DWC3_DEVTEN_DISCONNEVTEN);
2448 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2450 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2451 if (dwc->revision >= DWC3_REVISION_194A) {
2452 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2453 reg |= DWC3_DCFG_LPM_CAP;
2454 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2456 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2457 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2459 /* TODO: This should be configurable */
2460 reg |= DWC3_DCTL_HIRD_THRES(31);
2462 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2464 dwc3_gadget_usb2_phy_suspend(dwc, true);
2465 dwc3_gadget_usb3_phy_suspend(dwc, true);
2468 ret = device_register(&dwc->gadget.dev);
2470 dev_err(dwc->dev, "failed to register gadget device\n");
2471 put_device(&dwc->gadget.dev);
2475 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2477 dev_err(dwc->dev, "failed to register udc\n");
2484 device_unregister(&dwc->gadget.dev);
2487 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2491 dwc3_gadget_free_endpoints(dwc);
2494 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2495 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2498 kfree(dwc->setup_buf);
2501 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2502 dwc->ep0_trb, dwc->ep0_trb_addr);
2505 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2506 dwc->ctrl_req, dwc->ctrl_req_addr);
2512 void dwc3_gadget_exit(struct dwc3 *dwc)
2516 usb_del_gadget_udc(&dwc->gadget);
2517 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2519 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2522 dwc3_gadget_free_endpoints(dwc);
2524 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2525 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2527 kfree(dwc->setup_buf);
2529 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2530 dwc->ep0_trb, dwc->ep0_trb_addr);
2532 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2533 dwc->ctrl_req, dwc->ctrl_req_addr);
2535 device_unregister(&dwc->gadget.dev);