2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
156 static void dwc3_ep_inc_trb(u8 *index)
159 if (*index == (DWC3_TRB_NUM - 1))
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
170 dwc3_ep_inc_trb(&dep->trb_dequeue);
173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
176 struct dwc3 *dwc = dep->dwc;
182 dwc3_ep_inc_deq(dep);
183 } while(++i < req->request.num_mapped_sgs);
184 req->started = false;
186 list_del(&req->list);
189 if (req->request.status == -EINPROGRESS)
190 req->request.status = status;
192 if (dwc->ep0_bounced && dep->number == 0)
193 dwc->ep0_bounced = false;
195 usb_gadget_unmap_request(&dwc->gadget, &req->request,
198 trace_dwc3_gadget_giveback(req);
200 spin_unlock(&dwc->lock);
201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
202 spin_lock(&dwc->lock);
205 pm_runtime_put(dwc->dev);
208 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
215 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
216 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
219 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
220 if (!(reg & DWC3_DGCMD_CMDACT)) {
221 status = DWC3_DGCMD_STATUS(reg);
233 trace_dwc3_gadget_generic_cmd(cmd, param, status);
238 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
241 struct dwc3_gadget_ep_cmd_params *params)
243 struct dwc3 *dwc = dep->dwc;
252 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
253 * we're issuing an endpoint command, we must check if
254 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
256 * We will also set SUSPHY bit to what it was before returning as stated
257 * by the same section on Synopsys databook.
259 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
260 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
261 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
263 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
264 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
268 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
271 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
272 dwc->link_state == DWC3_LINK_STATE_U2 ||
273 dwc->link_state == DWC3_LINK_STATE_U3);
275 if (unlikely(needs_wakeup)) {
276 ret = __dwc3_gadget_wakeup(dwc);
277 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
282 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
283 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
284 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
286 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
288 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
289 if (!(reg & DWC3_DEPCMD_CMDACT)) {
290 cmd_status = DWC3_DEPCMD_STATUS(reg);
292 switch (cmd_status) {
296 case DEPEVT_TRANSFER_NO_RESOURCE:
299 case DEPEVT_TRANSFER_BUS_EXPIRY:
301 * SW issues START TRANSFER command to
302 * isochronous ep with future frame interval. If
303 * future interval time has already passed when
304 * core receives the command, it will respond
305 * with an error status of 'Bus Expiry'.
307 * Instead of always returning -EINVAL, let's
308 * give a hint to the gadget driver that this is
309 * the case by returning -EAGAIN.
314 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
323 cmd_status = -ETIMEDOUT;
326 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
328 if (unlikely(susphy)) {
329 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
330 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
331 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
339 struct dwc3 *dwc = dep->dwc;
340 struct dwc3_gadget_ep_cmd_params params;
341 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
344 * As of core revision 2.60a the recommended programming model
345 * is to set the ClearPendIN bit when issuing a Clear Stall EP
346 * command for IN endpoints. This is to prevent an issue where
347 * some (non-compliant) hosts may not send ACK TPs for pending
348 * IN transfers due to a mishandled error condition. Synopsys
351 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
352 cmd |= DWC3_DEPCMD_CLEARPENDIN;
354 memset(¶ms, 0, sizeof(params));
356 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
359 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
360 struct dwc3_trb *trb)
362 u32 offset = (char *) trb - (char *) dep->trb_pool;
364 return dep->trb_pool_dma + offset;
367 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
369 struct dwc3 *dwc = dep->dwc;
374 dep->trb_pool = dma_alloc_coherent(dwc->dev,
375 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
376 &dep->trb_pool_dma, GFP_KERNEL);
377 if (!dep->trb_pool) {
378 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
386 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
388 struct dwc3 *dwc = dep->dwc;
390 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
391 dep->trb_pool, dep->trb_pool_dma);
393 dep->trb_pool = NULL;
394 dep->trb_pool_dma = 0;
397 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
400 * dwc3_gadget_start_config - Configure EP resources
401 * @dwc: pointer to our controller context structure
402 * @dep: endpoint that is being enabled
404 * The assignment of transfer resources cannot perfectly follow the
405 * data book due to the fact that the controller driver does not have
406 * all knowledge of the configuration in advance. It is given this
407 * information piecemeal by the composite gadget framework after every
408 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
409 * programming model in this scenario can cause errors. For two
412 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
413 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
414 * multiple interfaces.
416 * 2) The databook does not mention doing more DEPXFERCFG for new
417 * endpoint on alt setting (8.1.6).
419 * The following simplified method is used instead:
421 * All hardware endpoints can be assigned a transfer resource and this
422 * setting will stay persistent until either a core reset or
423 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
424 * do DEPXFERCFG for every hardware endpoint as well. We are
425 * guaranteed that there are as many transfer resources as endpoints.
427 * This function is called for each endpoint when it is being enabled
428 * but is triggered only when called for EP0-out, which always happens
429 * first, and which should only happen in one of the above conditions.
431 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
433 struct dwc3_gadget_ep_cmd_params params;
441 memset(¶ms, 0x00, sizeof(params));
442 cmd = DWC3_DEPCMD_DEPSTARTCFG;
444 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
448 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
449 struct dwc3_ep *dep = dwc->eps[i];
454 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
462 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
463 const struct usb_endpoint_descriptor *desc,
464 const struct usb_ss_ep_comp_descriptor *comp_desc,
465 bool modify, bool restore)
467 struct dwc3_gadget_ep_cmd_params params;
469 if (dev_WARN_ONCE(dwc->dev, modify && restore,
470 "Can't modify and restore\n"))
473 memset(¶ms, 0x00, sizeof(params));
475 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
476 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
478 /* Burst size is only needed in SuperSpeed mode */
479 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
480 u32 burst = dep->endpoint.maxburst;
481 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
485 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
486 } else if (restore) {
487 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
488 params.param2 |= dep->saved_state;
490 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
493 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
495 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
496 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
498 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
499 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
500 | DWC3_DEPCFG_STREAM_EVENT_EN;
501 dep->stream_capable = true;
504 if (!usb_endpoint_xfer_control(desc))
505 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
508 * We are doing 1:1 mapping for endpoints, meaning
509 * Physical Endpoints 2 maps to Logical Endpoint 2 and
510 * so on. We consider the direction bit as part of the physical
511 * endpoint number. So USB endpoint 0x81 is 0x03.
513 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
516 * We must use the lower 16 TX FIFOs even though
520 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
522 if (desc->bInterval) {
523 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
524 dep->interval = 1 << (desc->bInterval - 1);
527 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
530 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
532 struct dwc3_gadget_ep_cmd_params params;
534 memset(¶ms, 0x00, sizeof(params));
536 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
538 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
543 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
544 * @dep: endpoint to be initialized
545 * @desc: USB Endpoint Descriptor
547 * Caller should take care of locking
549 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
550 const struct usb_endpoint_descriptor *desc,
551 const struct usb_ss_ep_comp_descriptor *comp_desc,
552 bool modify, bool restore)
554 struct dwc3 *dwc = dep->dwc;
558 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
560 if (!(dep->flags & DWC3_EP_ENABLED)) {
561 ret = dwc3_gadget_start_config(dwc, dep);
566 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
571 if (!(dep->flags & DWC3_EP_ENABLED)) {
572 struct dwc3_trb *trb_st_hw;
573 struct dwc3_trb *trb_link;
575 dep->endpoint.desc = desc;
576 dep->comp_desc = comp_desc;
577 dep->type = usb_endpoint_type(desc);
578 dep->flags |= DWC3_EP_ENABLED;
580 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
581 reg |= DWC3_DALEPENA_EP(dep->number);
582 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
584 if (usb_endpoint_xfer_control(desc))
587 /* Initialize the TRB ring */
588 dep->trb_dequeue = 0;
589 dep->trb_enqueue = 0;
590 memset(dep->trb_pool, 0,
591 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
593 /* Link TRB. The HWO bit is never reset */
594 trb_st_hw = &dep->trb_pool[0];
596 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
597 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
598 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
599 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
600 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
606 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
607 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
609 struct dwc3_request *req;
610 struct dwc3_trb *current_trb;
611 unsigned transfer_in_flight;
614 current_trb = &dep->trb_pool[dep->trb_enqueue];
616 current_trb = &dwc->ep0_trb[dep->trb_enqueue];
617 transfer_in_flight = current_trb->ctrl & DWC3_TRB_CTRL_HWO;
619 if (transfer_in_flight && !list_empty(&dep->started_list)) {
620 dwc3_stop_active_transfer(dwc, dep->number, true);
622 /* - giveback all requests to gadget driver */
623 while (!list_empty(&dep->started_list)) {
624 req = next_request(&dep->started_list);
626 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
630 while (!list_empty(&dep->pending_list)) {
631 req = next_request(&dep->pending_list);
633 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
638 * __dwc3_gadget_ep_disable - Disables a HW endpoint
639 * @dep: the endpoint to disable
641 * This function also removes requests which are currently processed ny the
642 * hardware and those which are not yet scheduled.
643 * Caller should take care of locking.
645 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
647 struct dwc3 *dwc = dep->dwc;
650 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
652 dwc3_remove_requests(dwc, dep);
654 /* make sure HW endpoint isn't stalled */
655 if (dep->flags & DWC3_EP_STALL)
656 __dwc3_gadget_ep_set_halt(dep, 0, false);
658 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
659 reg &= ~DWC3_DALEPENA_EP(dep->number);
660 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
662 dep->stream_capable = false;
663 dep->endpoint.desc = NULL;
664 dep->comp_desc = NULL;
671 /* -------------------------------------------------------------------------- */
673 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
674 const struct usb_endpoint_descriptor *desc)
679 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
684 /* -------------------------------------------------------------------------- */
686 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
687 const struct usb_endpoint_descriptor *desc)
694 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
695 pr_debug("dwc3: invalid parameters\n");
699 if (!desc->wMaxPacketSize) {
700 pr_debug("dwc3: missing wMaxPacketSize\n");
704 dep = to_dwc3_ep(ep);
707 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
708 "%s is already enabled\n",
712 spin_lock_irqsave(&dwc->lock, flags);
713 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
714 spin_unlock_irqrestore(&dwc->lock, flags);
719 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
727 pr_debug("dwc3: invalid parameters\n");
731 dep = to_dwc3_ep(ep);
734 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
735 "%s is already disabled\n",
739 spin_lock_irqsave(&dwc->lock, flags);
740 ret = __dwc3_gadget_ep_disable(dep);
741 spin_unlock_irqrestore(&dwc->lock, flags);
746 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
749 struct dwc3_request *req;
750 struct dwc3_ep *dep = to_dwc3_ep(ep);
752 req = kzalloc(sizeof(*req), gfp_flags);
756 req->epnum = dep->number;
759 dep->allocated_requests++;
761 trace_dwc3_alloc_request(req);
763 return &req->request;
766 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
767 struct usb_request *request)
769 struct dwc3_request *req = to_dwc3_request(request);
770 struct dwc3_ep *dep = to_dwc3_ep(ep);
772 dep->allocated_requests--;
773 trace_dwc3_free_request(req);
778 * dwc3_prepare_one_trb - setup one TRB from one request
779 * @dep: endpoint for which this request is prepared
780 * @req: dwc3_request pointer
782 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
783 struct dwc3_request *req, dma_addr_t dma,
784 unsigned length, unsigned last, unsigned chain, unsigned node)
786 struct dwc3_trb *trb;
788 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
789 dep->name, req, (unsigned long long) dma,
790 length, last ? " last" : "",
791 chain ? " chain" : "");
794 trb = &dep->trb_pool[dep->trb_enqueue];
797 dwc3_gadget_move_started_request(req);
799 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
800 req->first_trb_index = dep->trb_enqueue;
803 dwc3_ep_inc_enq(dep);
805 trb->size = DWC3_TRB_SIZE_LENGTH(length);
806 trb->bpl = lower_32_bits(dma);
807 trb->bph = upper_32_bits(dma);
809 switch (usb_endpoint_type(dep->endpoint.desc)) {
810 case USB_ENDPOINT_XFER_CONTROL:
811 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
814 case USB_ENDPOINT_XFER_ISOC:
816 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
818 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
820 /* always enable Interrupt on Missed ISOC */
821 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
824 case USB_ENDPOINT_XFER_BULK:
825 case USB_ENDPOINT_XFER_INT:
826 trb->ctrl = DWC3_TRBCTL_NORMAL;
830 * This is only possible with faulty memory because we
831 * checked it already :)
836 /* always enable Continue on Short Packet */
837 trb->ctrl |= DWC3_TRB_CTRL_CSP;
839 if (!req->request.no_interrupt && !chain)
840 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
843 trb->ctrl |= DWC3_TRB_CTRL_LST;
846 trb->ctrl |= DWC3_TRB_CTRL_CHN;
848 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
849 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
851 trb->ctrl |= DWC3_TRB_CTRL_HWO;
853 dep->queued_requests++;
855 trace_dwc3_prepare_trb(dep, trb);
859 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
860 * @dep: The endpoint with the TRB ring
861 * @index: The index of the current TRB in the ring
863 * Returns the TRB prior to the one pointed to by the index. If the
864 * index is 0, we will wrap backwards, skip the link TRB, and return
865 * the one just before that.
867 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
870 index = DWC3_TRB_NUM - 2;
872 index = dep->trb_enqueue - 1;
874 return &dep->trb_pool[index];
877 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
879 struct dwc3_trb *tmp;
883 * If enqueue & dequeue are equal than it is either full or empty.
885 * One way to know for sure is if the TRB right before us has HWO bit
886 * set or not. If it has, then we're definitely full and can't fit any
887 * more transfers in our ring.
889 if (dep->trb_enqueue == dep->trb_dequeue) {
890 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
891 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
894 return DWC3_TRB_NUM - 1;
897 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
898 trbs_left &= (DWC3_TRB_NUM - 1);
900 if (dep->trb_dequeue < dep->trb_enqueue)
906 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
907 struct dwc3_request *req, unsigned int trbs_left,
908 unsigned int more_coming)
910 struct usb_request *request = &req->request;
911 struct scatterlist *sg = request->sg;
912 struct scatterlist *s;
913 unsigned int last = false;
918 for_each_sg(sg, s, request->num_mapped_sgs, i) {
919 unsigned chain = true;
921 length = sg_dma_len(s);
922 dma = sg_dma_address(s);
925 if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
938 dwc3_prepare_one_trb(dep, req, dma, length,
946 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
947 struct dwc3_request *req, unsigned int trbs_left,
948 unsigned int more_coming)
950 unsigned int last = false;
954 dma = req->request.dma;
955 length = req->request.length;
960 /* Is this the last request? */
961 if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
964 dwc3_prepare_one_trb(dep, req, dma, length,
969 * dwc3_prepare_trbs - setup TRBs from requests
970 * @dep: endpoint for which requests are being prepared
972 * The function goes through the requests list and sets up TRBs for the
973 * transfers. The function returns once there are no more TRBs available or
974 * it runs out of requests.
976 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
978 struct dwc3_request *req, *n;
979 unsigned int more_coming;
982 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
984 trbs_left = dwc3_calc_trbs_left(dep);
988 more_coming = dep->allocated_requests - dep->queued_requests;
990 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
991 if (req->request.num_mapped_sgs > 0)
992 dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
995 dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
1003 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1005 struct dwc3_gadget_ep_cmd_params params;
1006 struct dwc3_request *req;
1007 struct dwc3 *dwc = dep->dwc;
1012 starting = !(dep->flags & DWC3_EP_BUSY);
1014 dwc3_prepare_trbs(dep);
1015 req = next_request(&dep->started_list);
1017 dep->flags |= DWC3_EP_PENDING_REQUEST;
1021 memset(¶ms, 0, sizeof(params));
1024 params.param0 = upper_32_bits(req->trb_dma);
1025 params.param1 = lower_32_bits(req->trb_dma);
1026 cmd = DWC3_DEPCMD_STARTTRANSFER |
1027 DWC3_DEPCMD_PARAM(cmd_param);
1029 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1030 DWC3_DEPCMD_PARAM(dep->resource_index);
1033 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1036 * FIXME we need to iterate over the list of requests
1037 * here and stop, unmap, free and del each of the linked
1038 * requests instead of what we do now.
1040 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1042 list_del(&req->list);
1046 dep->flags |= DWC3_EP_BUSY;
1049 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1050 WARN_ON_ONCE(!dep->resource_index);
1056 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1057 struct dwc3_ep *dep, u32 cur_uf)
1061 if (list_empty(&dep->pending_list)) {
1062 dwc3_trace(trace_dwc3_gadget,
1063 "ISOC ep %s run out for requests",
1065 dep->flags |= DWC3_EP_PENDING_REQUEST;
1069 /* 4 micro frames in the future */
1070 uf = cur_uf + dep->interval * 4;
1072 __dwc3_gadget_kick_transfer(dep, uf);
1075 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1076 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1080 mask = ~(dep->interval - 1);
1081 cur_uf = event->parameters & mask;
1083 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1086 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1088 struct dwc3 *dwc = dep->dwc;
1091 if (!dep->endpoint.desc) {
1092 dwc3_trace(trace_dwc3_gadget,
1093 "trying to queue request %p to disabled %s",
1094 &req->request, dep->endpoint.name);
1098 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1099 &req->request, req->dep->name)) {
1100 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1101 &req->request, req->dep->name);
1105 pm_runtime_get(dwc->dev);
1107 req->request.actual = 0;
1108 req->request.status = -EINPROGRESS;
1109 req->direction = dep->direction;
1110 req->epnum = dep->number;
1112 trace_dwc3_ep_queue(req);
1115 * Per databook, the total size of buffer must be a multiple
1116 * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1117 * configed for endpoints in dwc3_gadget_set_ep_config(),
1118 * set to usb_endpoint_descriptor->wMaxPacketSize.
1120 if (dep->direction == 0 &&
1121 req->request.length % dep->endpoint.desc->wMaxPacketSize)
1122 req->request.length = roundup(req->request.length,
1123 dep->endpoint.desc->wMaxPacketSize);
1126 * We only add to our list of requests now and
1127 * start consuming the list once we get XferNotReady
1130 * That way, we avoid doing anything that we don't need
1131 * to do now and defer it until the point we receive a
1132 * particular token from the Host side.
1134 * This will also avoid Host cancelling URBs due to too
1137 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1142 list_add_tail(&req->list, &dep->pending_list);
1145 * If there are no pending requests and the endpoint isn't already
1146 * busy, we will just start the request straight away.
1148 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1149 * little bit faster.
1151 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1152 !usb_endpoint_xfer_int(dep->endpoint.desc)) {
1153 ret = __dwc3_gadget_kick_transfer(dep, 0);
1158 * There are a few special cases:
1160 * 1. XferNotReady with empty list of requests. We need to kick the
1161 * transfer here in that situation, otherwise we will be NAKing
1162 * forever. If we get XferNotReady before gadget driver has a
1163 * chance to queue a request, we will ACK the IRQ but won't be
1164 * able to receive the data until the next request is queued.
1165 * The following code is handling exactly that.
1168 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1170 * If xfernotready is already elapsed and it is a case
1171 * of isoc transfer, then issue END TRANSFER, so that
1172 * you can receive xfernotready again and can have
1173 * notion of current microframe.
1175 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1176 if (list_empty(&dep->started_list)) {
1177 dwc3_stop_active_transfer(dwc, dep->number, true);
1178 dep->flags = DWC3_EP_ENABLED;
1183 ret = __dwc3_gadget_kick_transfer(dep, 0);
1185 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1191 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1192 * kick the transfer here after queuing a request, otherwise the
1193 * core may not see the modified TRB(s).
1195 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1196 (dep->flags & DWC3_EP_BUSY) &&
1197 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1198 WARN_ON_ONCE(!dep->resource_index);
1199 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1204 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1205 * right away, otherwise host will not know we have streams to be
1208 if (dep->stream_capable)
1209 ret = __dwc3_gadget_kick_transfer(dep, 0);
1212 if (ret && ret != -EBUSY)
1213 dwc3_trace(trace_dwc3_gadget,
1214 "%s: failed to kick transfers",
1222 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1223 struct usb_request *request)
1225 dwc3_gadget_ep_free_request(ep, request);
1228 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1230 struct dwc3_request *req;
1231 struct usb_request *request;
1232 struct usb_ep *ep = &dep->endpoint;
1234 dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1235 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1239 request->length = 0;
1240 request->buf = dwc->zlp_buf;
1241 request->complete = __dwc3_gadget_ep_zlp_complete;
1243 req = to_dwc3_request(request);
1245 return __dwc3_gadget_ep_queue(dep, req);
1248 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1251 struct dwc3_request *req = to_dwc3_request(request);
1252 struct dwc3_ep *dep = to_dwc3_ep(ep);
1253 struct dwc3 *dwc = dep->dwc;
1255 unsigned long flags;
1259 spin_lock_irqsave(&dwc->lock, flags);
1260 ret = __dwc3_gadget_ep_queue(dep, req);
1263 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1264 * setting request->zero, instead of doing magic, we will just queue an
1265 * extra usb_request ourselves so that it gets handled the same way as
1266 * any other request.
1268 if (ret == 0 && request->zero && request->length &&
1269 (request->length % ep->desc->wMaxPacketSize == 0))
1270 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1272 spin_unlock_irqrestore(&dwc->lock, flags);
1277 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1278 struct usb_request *request)
1280 struct dwc3_request *req = to_dwc3_request(request);
1281 struct dwc3_request *r = NULL;
1283 struct dwc3_ep *dep = to_dwc3_ep(ep);
1284 struct dwc3 *dwc = dep->dwc;
1286 unsigned long flags;
1289 trace_dwc3_ep_dequeue(req);
1291 spin_lock_irqsave(&dwc->lock, flags);
1293 list_for_each_entry(r, &dep->pending_list, list) {
1299 list_for_each_entry(r, &dep->started_list, list) {
1304 /* wait until it is processed */
1305 dwc3_stop_active_transfer(dwc, dep->number, true);
1308 dev_err(dwc->dev, "request %p was not queued to %s\n",
1315 /* giveback the request */
1316 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1319 spin_unlock_irqrestore(&dwc->lock, flags);
1324 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1326 struct dwc3_gadget_ep_cmd_params params;
1327 struct dwc3 *dwc = dep->dwc;
1330 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1331 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1335 memset(¶ms, 0x00, sizeof(params));
1338 struct dwc3_trb *trb;
1340 unsigned transfer_in_flight;
1343 if (dep->number > 1)
1344 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1346 trb = &dwc->ep0_trb[dep->trb_enqueue];
1348 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1349 started = !list_empty(&dep->started_list);
1351 if (!protocol && ((dep->direction && transfer_in_flight) ||
1352 (!dep->direction && started))) {
1353 dwc3_trace(trace_dwc3_gadget,
1354 "%s: pending request, cannot halt",
1359 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1362 dev_err(dwc->dev, "failed to set STALL on %s\n",
1365 dep->flags |= DWC3_EP_STALL;
1368 ret = dwc3_send_clear_stall_ep_cmd(dep);
1370 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1373 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1379 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1381 struct dwc3_ep *dep = to_dwc3_ep(ep);
1382 struct dwc3 *dwc = dep->dwc;
1384 unsigned long flags;
1388 spin_lock_irqsave(&dwc->lock, flags);
1389 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1390 spin_unlock_irqrestore(&dwc->lock, flags);
1395 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1397 struct dwc3_ep *dep = to_dwc3_ep(ep);
1398 struct dwc3 *dwc = dep->dwc;
1399 unsigned long flags;
1402 spin_lock_irqsave(&dwc->lock, flags);
1403 dep->flags |= DWC3_EP_WEDGE;
1405 if (dep->number == 0 || dep->number == 1)
1406 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1408 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1409 spin_unlock_irqrestore(&dwc->lock, flags);
1414 /* -------------------------------------------------------------------------- */
1416 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1417 .bLength = USB_DT_ENDPOINT_SIZE,
1418 .bDescriptorType = USB_DT_ENDPOINT,
1419 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1422 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1423 .enable = dwc3_gadget_ep0_enable,
1424 .disable = dwc3_gadget_ep0_disable,
1425 .alloc_request = dwc3_gadget_ep_alloc_request,
1426 .free_request = dwc3_gadget_ep_free_request,
1427 .queue = dwc3_gadget_ep0_queue,
1428 .dequeue = dwc3_gadget_ep_dequeue,
1429 .set_halt = dwc3_gadget_ep0_set_halt,
1430 .set_wedge = dwc3_gadget_ep_set_wedge,
1433 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1434 .enable = dwc3_gadget_ep_enable,
1435 .disable = dwc3_gadget_ep_disable,
1436 .alloc_request = dwc3_gadget_ep_alloc_request,
1437 .free_request = dwc3_gadget_ep_free_request,
1438 .queue = dwc3_gadget_ep_queue,
1439 .dequeue = dwc3_gadget_ep_dequeue,
1440 .set_halt = dwc3_gadget_ep_set_halt,
1441 .set_wedge = dwc3_gadget_ep_set_wedge,
1444 /* -------------------------------------------------------------------------- */
1446 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1448 struct dwc3 *dwc = gadget_to_dwc(g);
1451 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1452 return DWC3_DSTS_SOFFN(reg);
1455 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1457 unsigned long timeout;
1466 * According to the Databook Remote wakeup request should
1467 * be issued only when the device is in early suspend state.
1469 * We can check that via USB Link State bits in DSTS register.
1471 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1473 speed = reg & DWC3_DSTS_CONNECTSPD;
1474 if (speed == DWC3_DSTS_SUPERSPEED) {
1475 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1479 link_state = DWC3_DSTS_USBLNKST(reg);
1481 switch (link_state) {
1482 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1483 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1486 dwc3_trace(trace_dwc3_gadget,
1487 "can't wakeup from '%s'",
1488 dwc3_gadget_link_string(link_state));
1492 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1494 dev_err(dwc->dev, "failed to put link in Recovery\n");
1498 /* Recent versions do this automatically */
1499 if (dwc->revision < DWC3_REVISION_194A) {
1500 /* write zeroes to Link Change Request */
1501 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1502 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1503 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1506 /* poll until Link State changes to ON */
1507 timeout = jiffies + msecs_to_jiffies(100);
1509 while (!time_after(jiffies, timeout)) {
1510 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1512 /* in HS, means ON */
1513 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1517 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1518 dev_err(dwc->dev, "failed to send remote wakeup\n");
1525 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1527 struct dwc3 *dwc = gadget_to_dwc(g);
1528 unsigned long flags;
1531 spin_lock_irqsave(&dwc->lock, flags);
1532 ret = __dwc3_gadget_wakeup(dwc);
1533 spin_unlock_irqrestore(&dwc->lock, flags);
1538 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1541 struct dwc3 *dwc = gadget_to_dwc(g);
1542 unsigned long flags;
1544 spin_lock_irqsave(&dwc->lock, flags);
1545 g->is_selfpowered = !!is_selfpowered;
1546 spin_unlock_irqrestore(&dwc->lock, flags);
1551 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1556 if (pm_runtime_suspended(dwc->dev))
1559 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1561 if (dwc->revision <= DWC3_REVISION_187A) {
1562 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1563 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1566 if (dwc->revision >= DWC3_REVISION_194A)
1567 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1568 reg |= DWC3_DCTL_RUN_STOP;
1570 if (dwc->has_hibernation)
1571 reg |= DWC3_DCTL_KEEP_CONNECT;
1573 dwc->pullups_connected = true;
1575 reg &= ~DWC3_DCTL_RUN_STOP;
1577 if (dwc->has_hibernation && !suspend)
1578 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1580 dwc->pullups_connected = false;
1583 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1586 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1588 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1591 if (reg & DWC3_DSTS_DEVCTRLHLT)
1599 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1601 ? dwc->gadget_driver->function : "no-function",
1602 is_on ? "connect" : "disconnect");
1607 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1609 struct dwc3 *dwc = gadget_to_dwc(g);
1610 unsigned long flags;
1615 spin_lock_irqsave(&dwc->lock, flags);
1616 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1617 spin_unlock_irqrestore(&dwc->lock, flags);
1622 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1626 /* Enable all but Start and End of Frame IRQs */
1627 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1628 DWC3_DEVTEN_EVNTOVERFLOWEN |
1629 DWC3_DEVTEN_CMDCMPLTEN |
1630 DWC3_DEVTEN_ERRTICERREN |
1631 DWC3_DEVTEN_WKUPEVTEN |
1632 DWC3_DEVTEN_ULSTCNGEN |
1633 DWC3_DEVTEN_CONNECTDONEEN |
1634 DWC3_DEVTEN_USBRSTEN |
1635 DWC3_DEVTEN_DISCONNEVTEN);
1637 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1640 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1642 /* mask all interrupts */
1643 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1646 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1647 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1650 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1651 * dwc: pointer to our context structure
1653 * The following looks like complex but it's actually very simple. In order to
1654 * calculate the number of packets we can burst at once on OUT transfers, we're
1655 * gonna use RxFIFO size.
1657 * To calculate RxFIFO size we need two numbers:
1658 * MDWIDTH = size, in bits, of the internal memory bus
1659 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1661 * Given these two numbers, the formula is simple:
1663 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1665 * 24 bytes is for 3x SETUP packets
1666 * 16 bytes is a clock domain crossing tolerance
1668 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1670 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1677 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1678 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1680 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1681 nump = min_t(u32, nump, 16);
1684 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1685 reg &= ~DWC3_DCFG_NUMP_MASK;
1686 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1687 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1690 static int __dwc3_gadget_start(struct dwc3 *dwc)
1692 struct dwc3_ep *dep;
1696 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1697 reg &= ~(DWC3_DCFG_SPEED_MASK);
1700 * WORKAROUND: DWC3 revision < 2.20a have an issue
1701 * which would cause metastability state on Run/Stop
1702 * bit if we try to force the IP to USB2-only mode.
1704 * Because of that, we cannot configure the IP to any
1705 * speed other than the SuperSpeed
1709 * STAR#9000525659: Clock Domain Crossing on DCTL in
1712 if (dwc->revision < DWC3_REVISION_220A) {
1713 reg |= DWC3_DCFG_SUPERSPEED;
1715 switch (dwc->maximum_speed) {
1717 reg |= DWC3_DCFG_LOWSPEED;
1719 case USB_SPEED_FULL:
1720 reg |= DWC3_DCFG_FULLSPEED1;
1722 case USB_SPEED_HIGH:
1723 reg |= DWC3_DCFG_HIGHSPEED;
1725 case USB_SPEED_SUPER: /* FALLTHROUGH */
1726 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1728 reg |= DWC3_DCFG_SUPERSPEED;
1731 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1734 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1735 * field instead of letting dwc3 itself calculate that automatically.
1737 * This way, we maximize the chances that we'll be able to get several
1738 * bursts of data without going through any sort of endpoint throttling.
1740 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1741 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1742 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1744 dwc3_gadget_setup_nump(dwc);
1746 /* Start with SuperSpeed Default */
1747 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1750 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1753 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1758 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1761 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1765 /* begin to receive SETUP packets */
1766 dwc->ep0state = EP0_SETUP_PHASE;
1767 dwc3_ep0_out_start(dwc);
1769 dwc3_gadget_enable_irq(dwc);
1774 __dwc3_gadget_ep_disable(dwc->eps[0]);
1780 static int dwc3_gadget_start(struct usb_gadget *g,
1781 struct usb_gadget_driver *driver)
1783 struct dwc3 *dwc = gadget_to_dwc(g);
1784 unsigned long flags;
1788 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1789 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1790 IRQF_SHARED, "dwc3", dwc->ev_buf);
1792 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1796 dwc->irq_gadget = irq;
1798 spin_lock_irqsave(&dwc->lock, flags);
1799 if (dwc->gadget_driver) {
1800 dev_err(dwc->dev, "%s is already bound to %s\n",
1802 dwc->gadget_driver->driver.name);
1807 dwc->gadget_driver = driver;
1809 if (pm_runtime_active(dwc->dev))
1810 __dwc3_gadget_start(dwc);
1812 spin_unlock_irqrestore(&dwc->lock, flags);
1817 spin_unlock_irqrestore(&dwc->lock, flags);
1824 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1826 dwc3_gadget_disable_irq(dwc);
1827 __dwc3_gadget_ep_disable(dwc->eps[0]);
1828 __dwc3_gadget_ep_disable(dwc->eps[1]);
1831 static int dwc3_gadget_stop(struct usb_gadget *g)
1833 struct dwc3 *dwc = gadget_to_dwc(g);
1834 unsigned long flags;
1836 spin_lock_irqsave(&dwc->lock, flags);
1837 __dwc3_gadget_stop(dwc);
1838 dwc->gadget_driver = NULL;
1839 spin_unlock_irqrestore(&dwc->lock, flags);
1841 free_irq(dwc->irq_gadget, dwc->ev_buf);
1846 static const struct usb_gadget_ops dwc3_gadget_ops = {
1847 .get_frame = dwc3_gadget_get_frame,
1848 .wakeup = dwc3_gadget_wakeup,
1849 .set_selfpowered = dwc3_gadget_set_selfpowered,
1850 .pullup = dwc3_gadget_pullup,
1851 .udc_start = dwc3_gadget_start,
1852 .udc_stop = dwc3_gadget_stop,
1855 /* -------------------------------------------------------------------------- */
1857 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1858 u8 num, u32 direction)
1860 struct dwc3_ep *dep;
1863 for (i = 0; i < num; i++) {
1864 u8 epnum = (i << 1) | (direction ? 1 : 0);
1866 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1871 dep->number = epnum;
1872 dep->direction = !!direction;
1873 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1874 dwc->eps[epnum] = dep;
1876 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1877 (epnum & 1) ? "in" : "out");
1879 dep->endpoint.name = dep->name;
1880 spin_lock_init(&dep->lock);
1882 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1884 if (epnum == 0 || epnum == 1) {
1885 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1886 dep->endpoint.maxburst = 1;
1887 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1889 dwc->gadget.ep0 = &dep->endpoint;
1893 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1894 dep->endpoint.max_streams = 15;
1895 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1896 list_add_tail(&dep->endpoint.ep_list,
1897 &dwc->gadget.ep_list);
1899 ret = dwc3_alloc_trb_pool(dep);
1904 if (epnum == 0 || epnum == 1) {
1905 dep->endpoint.caps.type_control = true;
1907 dep->endpoint.caps.type_iso = true;
1908 dep->endpoint.caps.type_bulk = true;
1909 dep->endpoint.caps.type_int = true;
1912 dep->endpoint.caps.dir_in = !!direction;
1913 dep->endpoint.caps.dir_out = !direction;
1915 INIT_LIST_HEAD(&dep->pending_list);
1916 INIT_LIST_HEAD(&dep->started_list);
1922 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1926 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1928 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1930 dwc3_trace(trace_dwc3_gadget,
1931 "failed to allocate OUT endpoints");
1935 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1937 dwc3_trace(trace_dwc3_gadget,
1938 "failed to allocate IN endpoints");
1945 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1947 struct dwc3_ep *dep;
1950 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1951 dep = dwc->eps[epnum];
1955 * Physical endpoints 0 and 1 are special; they form the
1956 * bi-directional USB endpoint 0.
1958 * For those two physical endpoints, we don't allocate a TRB
1959 * pool nor do we add them the endpoints list. Due to that, we
1960 * shouldn't do these two operations otherwise we would end up
1961 * with all sorts of bugs when removing dwc3.ko.
1963 if (epnum != 0 && epnum != 1) {
1964 dwc3_free_trb_pool(dep);
1965 list_del(&dep->endpoint.ep_list);
1972 /* -------------------------------------------------------------------------- */
1974 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1975 struct dwc3_request *req, struct dwc3_trb *trb,
1976 const struct dwc3_event_depevt *event, int status)
1979 unsigned int s_pkt = 0;
1980 unsigned int trb_status;
1982 dep->queued_requests--;
1983 trace_dwc3_complete_trb(dep, trb);
1985 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1987 * We continue despite the error. There is not much we
1988 * can do. If we don't clean it up we loop forever. If
1989 * we skip the TRB then it gets overwritten after a
1990 * while since we use them in a ring buffer. A BUG()
1991 * would help. Lets hope that if this occurs, someone
1992 * fixes the root cause instead of looking away :)
1994 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1996 count = trb->size & DWC3_TRB_SIZE_MASK;
1998 if (dep->direction) {
2000 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2001 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2002 dwc3_trace(trace_dwc3_gadget,
2003 "%s: incomplete IN transfer",
2006 * If missed isoc occurred and there is
2007 * no request queued then issue END
2008 * TRANSFER, so that core generates
2009 * next xfernotready and we will issue
2010 * a fresh START TRANSFER.
2011 * If there are still queued request
2012 * then wait, do not issue either END
2013 * or UPDATE TRANSFER, just attach next
2014 * request in pending_list during
2015 * giveback.If any future queued request
2016 * is successfully transferred then we
2017 * will issue UPDATE TRANSFER for all
2018 * request in the pending_list.
2020 dep->flags |= DWC3_EP_MISSED_ISOC;
2022 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2024 status = -ECONNRESET;
2027 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2030 if (count && (event->status & DEPEVT_STATUS_SHORT))
2035 * We assume here we will always receive the entire data block
2036 * which we should receive. Meaning, if we program RX to
2037 * receive 4K but we receive only 2K, we assume that's all we
2038 * should receive and we simply bounce the request back to the
2039 * gadget driver for further processing.
2041 req->request.actual += req->request.length - count;
2044 if ((event->status & DEPEVT_STATUS_LST) &&
2045 (trb->ctrl & (DWC3_TRB_CTRL_LST |
2046 DWC3_TRB_CTRL_HWO)))
2048 if ((event->status & DEPEVT_STATUS_IOC) &&
2049 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2054 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2055 const struct dwc3_event_depevt *event, int status)
2057 struct dwc3_request *req;
2058 struct dwc3_trb *trb;
2064 req = next_request(&dep->started_list);
2065 if (WARN_ON_ONCE(!req))
2070 slot = req->first_trb_index + i;
2071 if (slot == DWC3_TRB_NUM - 1)
2073 slot %= DWC3_TRB_NUM;
2074 trb = &dep->trb_pool[slot];
2076 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2080 } while (++i < req->request.num_mapped_sgs);
2082 dwc3_gadget_giveback(dep, req, status);
2089 * Our endpoint might get disabled by another thread during
2090 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2091 * early on so DWC3_EP_BUSY flag gets cleared
2093 if (!dep->endpoint.desc)
2096 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2097 list_empty(&dep->started_list)) {
2098 if (list_empty(&dep->pending_list)) {
2100 * If there is no entry in request list then do
2101 * not issue END TRANSFER now. Just set PENDING
2102 * flag, so that END TRANSFER is issued when an
2103 * entry is added into request list.
2105 dep->flags = DWC3_EP_PENDING_REQUEST;
2107 dwc3_stop_active_transfer(dwc, dep->number, true);
2108 dep->flags = DWC3_EP_ENABLED;
2113 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2114 if ((event->status & DEPEVT_STATUS_IOC) &&
2115 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2120 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2121 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2123 unsigned status = 0;
2125 u32 is_xfer_complete;
2127 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2129 if (event->status & DEPEVT_STATUS_BUSERR)
2130 status = -ECONNRESET;
2132 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2133 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2134 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2135 dep->flags &= ~DWC3_EP_BUSY;
2138 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2139 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2141 if (dwc->revision < DWC3_REVISION_183A) {
2145 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2148 if (!(dep->flags & DWC3_EP_ENABLED))
2151 if (!list_empty(&dep->started_list))
2155 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2157 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2163 * Our endpoint might get disabled by another thread during
2164 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2165 * early on so DWC3_EP_BUSY flag gets cleared
2167 if (!dep->endpoint.desc)
2170 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2173 ret = __dwc3_gadget_kick_transfer(dep, 0);
2174 if (!ret || ret == -EBUSY)
2179 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2180 const struct dwc3_event_depevt *event)
2182 struct dwc3_ep *dep;
2183 u8 epnum = event->endpoint_number;
2185 dep = dwc->eps[epnum];
2187 if (!(dep->flags & DWC3_EP_ENABLED))
2190 if (epnum == 0 || epnum == 1) {
2191 dwc3_ep0_interrupt(dwc, event);
2195 switch (event->endpoint_event) {
2196 case DWC3_DEPEVT_XFERCOMPLETE:
2197 dep->resource_index = 0;
2199 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2200 dwc3_trace(trace_dwc3_gadget,
2201 "%s is an Isochronous endpoint",
2206 dwc3_endpoint_transfer_complete(dwc, dep, event);
2208 case DWC3_DEPEVT_XFERINPROGRESS:
2209 dwc3_endpoint_transfer_complete(dwc, dep, event);
2211 case DWC3_DEPEVT_XFERNOTREADY:
2212 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2213 dwc3_gadget_start_isoc(dwc, dep, event);
2218 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2220 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2221 dep->name, active ? "Transfer Active"
2222 : "Transfer Not Active");
2224 ret = __dwc3_gadget_kick_transfer(dep, 0);
2225 if (!ret || ret == -EBUSY)
2228 dwc3_trace(trace_dwc3_gadget,
2229 "%s: failed to kick transfers",
2234 case DWC3_DEPEVT_STREAMEVT:
2235 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2236 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2241 switch (event->status) {
2242 case DEPEVT_STREAMEVT_FOUND:
2243 dwc3_trace(trace_dwc3_gadget,
2244 "Stream %d found and started",
2248 case DEPEVT_STREAMEVT_NOTFOUND:
2251 dwc3_trace(trace_dwc3_gadget,
2252 "unable to find suitable stream");
2255 case DWC3_DEPEVT_RXTXFIFOEVT:
2256 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2258 case DWC3_DEPEVT_EPCMDCMPLT:
2259 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2264 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2266 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2267 spin_unlock(&dwc->lock);
2268 dwc->gadget_driver->disconnect(&dwc->gadget);
2269 spin_lock(&dwc->lock);
2273 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2275 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2276 spin_unlock(&dwc->lock);
2277 dwc->gadget_driver->suspend(&dwc->gadget);
2278 spin_lock(&dwc->lock);
2282 static void dwc3_resume_gadget(struct dwc3 *dwc)
2284 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2285 spin_unlock(&dwc->lock);
2286 dwc->gadget_driver->resume(&dwc->gadget);
2287 spin_lock(&dwc->lock);
2291 static void dwc3_reset_gadget(struct dwc3 *dwc)
2293 if (!dwc->gadget_driver)
2296 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2297 spin_unlock(&dwc->lock);
2298 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2299 spin_lock(&dwc->lock);
2303 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2305 struct dwc3_ep *dep;
2306 struct dwc3_gadget_ep_cmd_params params;
2310 dep = dwc->eps[epnum];
2312 if (!dep->resource_index)
2316 * NOTICE: We are violating what the Databook says about the
2317 * EndTransfer command. Ideally we would _always_ wait for the
2318 * EndTransfer Command Completion IRQ, but that's causing too
2319 * much trouble synchronizing between us and gadget driver.
2321 * We have discussed this with the IP Provider and it was
2322 * suggested to giveback all requests here, but give HW some
2323 * extra time to synchronize with the interconnect. We're using
2324 * an arbitrary 100us delay for that.
2326 * Note also that a similar handling was tested by Synopsys
2327 * (thanks a lot Paul) and nothing bad has come out of it.
2328 * In short, what we're doing is:
2330 * - Issue EndTransfer WITH CMDIOC bit set
2334 cmd = DWC3_DEPCMD_ENDTRANSFER;
2335 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2336 cmd |= DWC3_DEPCMD_CMDIOC;
2337 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2338 memset(¶ms, 0, sizeof(params));
2339 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2341 dep->resource_index = 0;
2342 dep->flags &= ~DWC3_EP_BUSY;
2346 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2350 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2351 struct dwc3_ep *dep;
2353 dep = dwc->eps[epnum];
2357 if (!(dep->flags & DWC3_EP_ENABLED))
2360 dwc3_remove_requests(dwc, dep);
2364 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2368 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2369 struct dwc3_ep *dep;
2372 dep = dwc->eps[epnum];
2376 if (!(dep->flags & DWC3_EP_STALL))
2379 dep->flags &= ~DWC3_EP_STALL;
2381 ret = dwc3_send_clear_stall_ep_cmd(dep);
2386 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2390 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2391 reg &= ~DWC3_DCTL_INITU1ENA;
2392 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2394 reg &= ~DWC3_DCTL_INITU2ENA;
2395 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2397 dwc3_disconnect_gadget(dwc);
2399 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2400 dwc->setup_packet_pending = false;
2401 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2403 dwc->connected = false;
2406 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2410 dwc->connected = true;
2413 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2414 * would cause a missing Disconnect Event if there's a
2415 * pending Setup Packet in the FIFO.
2417 * There's no suggested workaround on the official Bug
2418 * report, which states that "unless the driver/application
2419 * is doing any special handling of a disconnect event,
2420 * there is no functional issue".
2422 * Unfortunately, it turns out that we _do_ some special
2423 * handling of a disconnect event, namely complete all
2424 * pending transfers, notify gadget driver of the
2425 * disconnection, and so on.
2427 * Our suggested workaround is to follow the Disconnect
2428 * Event steps here, instead, based on a setup_packet_pending
2429 * flag. Such flag gets set whenever we have a SETUP_PENDING
2430 * status for EP0 TRBs and gets cleared on XferComplete for the
2435 * STAR#9000466709: RTL: Device : Disconnect event not
2436 * generated if setup packet pending in FIFO
2438 if (dwc->revision < DWC3_REVISION_188A) {
2439 if (dwc->setup_packet_pending)
2440 dwc3_gadget_disconnect_interrupt(dwc);
2443 dwc3_reset_gadget(dwc);
2445 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2446 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2447 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2448 dwc->test_mode = false;
2450 dwc3_stop_active_transfers(dwc);
2451 dwc3_clear_stall_all_ep(dwc);
2453 /* Reset device address to zero */
2454 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2455 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2456 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2459 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2462 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2465 * We change the clock only at SS but I dunno why I would want to do
2466 * this. Maybe it becomes part of the power saving plan.
2469 if (speed != DWC3_DSTS_SUPERSPEED)
2473 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2474 * each time on Connect Done.
2479 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2480 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2481 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2484 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2486 struct dwc3_ep *dep;
2491 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2492 speed = reg & DWC3_DSTS_CONNECTSPD;
2495 dwc3_update_ram_clk_sel(dwc, speed);
2498 case DWC3_DSTS_SUPERSPEED:
2500 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2501 * would cause a missing USB3 Reset event.
2503 * In such situations, we should force a USB3 Reset
2504 * event by calling our dwc3_gadget_reset_interrupt()
2509 * STAR#9000483510: RTL: SS : USB3 reset event may
2510 * not be generated always when the link enters poll
2512 if (dwc->revision < DWC3_REVISION_190A)
2513 dwc3_gadget_reset_interrupt(dwc);
2515 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2516 dwc->gadget.ep0->maxpacket = 512;
2517 dwc->gadget.speed = USB_SPEED_SUPER;
2519 case DWC3_DSTS_HIGHSPEED:
2520 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2521 dwc->gadget.ep0->maxpacket = 64;
2522 dwc->gadget.speed = USB_SPEED_HIGH;
2524 case DWC3_DSTS_FULLSPEED2:
2525 case DWC3_DSTS_FULLSPEED1:
2526 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2527 dwc->gadget.ep0->maxpacket = 64;
2528 dwc->gadget.speed = USB_SPEED_FULL;
2530 case DWC3_DSTS_LOWSPEED:
2531 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2532 dwc->gadget.ep0->maxpacket = 8;
2533 dwc->gadget.speed = USB_SPEED_LOW;
2537 /* Enable USB2 LPM Capability */
2539 if ((dwc->revision > DWC3_REVISION_194A) &&
2540 (speed != DWC3_DSTS_SUPERSPEED)) {
2541 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2542 reg |= DWC3_DCFG_LPM_CAP;
2543 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2545 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2546 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2548 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2551 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2552 * DCFG.LPMCap is set, core responses with an ACK and the
2553 * BESL value in the LPM token is less than or equal to LPM
2556 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2557 && dwc->has_lpm_erratum,
2558 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2560 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2561 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2563 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2565 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2566 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2567 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2571 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2574 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2579 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2582 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2587 * Configure PHY via GUSB3PIPECTLn if required.
2589 * Update GTXFIFOSIZn
2591 * In both cases reset values should be sufficient.
2595 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2598 * TODO take core out of low power mode when that's
2602 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2603 spin_unlock(&dwc->lock);
2604 dwc->gadget_driver->resume(&dwc->gadget);
2605 spin_lock(&dwc->lock);
2609 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2610 unsigned int evtinfo)
2612 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2613 unsigned int pwropt;
2616 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2617 * Hibernation mode enabled which would show up when device detects
2618 * host-initiated U3 exit.
2620 * In that case, device will generate a Link State Change Interrupt
2621 * from U3 to RESUME which is only necessary if Hibernation is
2624 * There are no functional changes due to such spurious event and we
2625 * just need to ignore it.
2629 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2632 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2633 if ((dwc->revision < DWC3_REVISION_250A) &&
2634 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2635 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2636 (next == DWC3_LINK_STATE_RESUME)) {
2637 dwc3_trace(trace_dwc3_gadget,
2638 "ignoring transition U3 -> Resume");
2644 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2645 * on the link partner, the USB session might do multiple entry/exit
2646 * of low power states before a transfer takes place.
2648 * Due to this problem, we might experience lower throughput. The
2649 * suggested workaround is to disable DCTL[12:9] bits if we're
2650 * transitioning from U1/U2 to U0 and enable those bits again
2651 * after a transfer completes and there are no pending transfers
2652 * on any of the enabled endpoints.
2654 * This is the first half of that workaround.
2658 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2659 * core send LGO_Ux entering U0
2661 if (dwc->revision < DWC3_REVISION_183A) {
2662 if (next == DWC3_LINK_STATE_U0) {
2666 switch (dwc->link_state) {
2667 case DWC3_LINK_STATE_U1:
2668 case DWC3_LINK_STATE_U2:
2669 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2670 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2671 | DWC3_DCTL_ACCEPTU2ENA
2672 | DWC3_DCTL_INITU1ENA
2673 | DWC3_DCTL_ACCEPTU1ENA);
2676 dwc->u1u2 = reg & u1u2;
2680 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2690 case DWC3_LINK_STATE_U1:
2691 if (dwc->speed == USB_SPEED_SUPER)
2692 dwc3_suspend_gadget(dwc);
2694 case DWC3_LINK_STATE_U2:
2695 case DWC3_LINK_STATE_U3:
2696 dwc3_suspend_gadget(dwc);
2698 case DWC3_LINK_STATE_RESUME:
2699 dwc3_resume_gadget(dwc);
2706 dwc->link_state = next;
2709 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2710 unsigned int evtinfo)
2712 unsigned int is_ss = evtinfo & BIT(4);
2715 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2716 * have a known issue which can cause USB CV TD.9.23 to fail
2719 * Because of this issue, core could generate bogus hibernation
2720 * events which SW needs to ignore.
2724 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2725 * Device Fallback from SuperSpeed
2727 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2730 /* enter hibernation here */
2733 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2734 const struct dwc3_event_devt *event)
2736 switch (event->type) {
2737 case DWC3_DEVICE_EVENT_DISCONNECT:
2738 dwc3_gadget_disconnect_interrupt(dwc);
2740 case DWC3_DEVICE_EVENT_RESET:
2741 dwc3_gadget_reset_interrupt(dwc);
2743 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2744 dwc3_gadget_conndone_interrupt(dwc);
2746 case DWC3_DEVICE_EVENT_WAKEUP:
2747 dwc3_gadget_wakeup_interrupt(dwc);
2749 case DWC3_DEVICE_EVENT_HIBER_REQ:
2750 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2751 "unexpected hibernation event\n"))
2754 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2756 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2757 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2759 case DWC3_DEVICE_EVENT_EOPF:
2760 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2762 case DWC3_DEVICE_EVENT_SOF:
2763 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2765 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2766 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2768 case DWC3_DEVICE_EVENT_CMD_CMPL:
2769 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2771 case DWC3_DEVICE_EVENT_OVERFLOW:
2772 dwc3_trace(trace_dwc3_gadget, "Overflow");
2775 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2779 static void dwc3_process_event_entry(struct dwc3 *dwc,
2780 const union dwc3_event *event)
2782 trace_dwc3_event(event->raw);
2784 /* Endpoint IRQ, handle it and return early */
2785 if (event->type.is_devspec == 0) {
2787 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2790 switch (event->type.type) {
2791 case DWC3_EVENT_TYPE_DEV:
2792 dwc3_gadget_interrupt(dwc, &event->devt);
2794 /* REVISIT what to do with Carkit and I2C events ? */
2796 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2800 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2802 struct dwc3 *dwc = evt->dwc;
2803 irqreturn_t ret = IRQ_NONE;
2809 if (!(evt->flags & DWC3_EVENT_PENDING))
2813 union dwc3_event event;
2815 event.raw = *(u32 *) (evt->buf + evt->lpos);
2817 dwc3_process_event_entry(dwc, &event);
2820 * FIXME we wrap around correctly to the next entry as
2821 * almost all entries are 4 bytes in size. There is one
2822 * entry which has 12 bytes which is a regular entry
2823 * followed by 8 bytes data. ATM I don't know how
2824 * things are organized if we get next to the a
2825 * boundary so I worry about that once we try to handle
2828 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2831 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2835 evt->flags &= ~DWC3_EVENT_PENDING;
2838 /* Unmask interrupt */
2839 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2840 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2841 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2846 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2848 struct dwc3_event_buffer *evt = _evt;
2849 struct dwc3 *dwc = evt->dwc;
2850 unsigned long flags;
2851 irqreturn_t ret = IRQ_NONE;
2853 spin_lock_irqsave(&dwc->lock, flags);
2854 ret = dwc3_process_event_buf(evt);
2855 spin_unlock_irqrestore(&dwc->lock, flags);
2860 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2862 struct dwc3 *dwc = evt->dwc;
2866 if (pm_runtime_suspended(dwc->dev)) {
2867 pm_runtime_get(dwc->dev);
2868 disable_irq_nosync(dwc->irq_gadget);
2869 dwc->pending_events = true;
2873 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2874 count &= DWC3_GEVNTCOUNT_MASK;
2879 evt->flags |= DWC3_EVENT_PENDING;
2881 /* Mask interrupt */
2882 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2883 reg |= DWC3_GEVNTSIZ_INTMASK;
2884 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2886 return IRQ_WAKE_THREAD;
2889 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2891 struct dwc3_event_buffer *evt = _evt;
2893 return dwc3_check_event_buf(evt);
2897 * dwc3_gadget_init - Initializes gadget related registers
2898 * @dwc: pointer to our controller context structure
2900 * Returns 0 on success otherwise negative errno.
2902 int dwc3_gadget_init(struct dwc3 *dwc)
2906 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2907 &dwc->ctrl_req_addr, GFP_KERNEL);
2908 if (!dwc->ctrl_req) {
2909 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2914 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2915 &dwc->ep0_trb_addr, GFP_KERNEL);
2916 if (!dwc->ep0_trb) {
2917 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2922 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2923 if (!dwc->setup_buf) {
2928 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2929 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2931 if (!dwc->ep0_bounce) {
2932 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2937 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2938 if (!dwc->zlp_buf) {
2943 dwc->gadget.ops = &dwc3_gadget_ops;
2944 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2945 dwc->gadget.sg_supported = true;
2946 dwc->gadget.name = "dwc3-gadget";
2947 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2950 * FIXME We might be setting max_speed to <SUPER, however versions
2951 * <2.20a of dwc3 have an issue with metastability (documented
2952 * elsewhere in this driver) which tells us we can't set max speed to
2953 * anything lower than SUPER.
2955 * Because gadget.max_speed is only used by composite.c and function
2956 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2957 * to happen so we avoid sending SuperSpeed Capability descriptor
2958 * together with our BOS descriptor as that could confuse host into
2959 * thinking we can handle super speed.
2961 * Note that, in fact, we won't even support GetBOS requests when speed
2962 * is less than super speed because we don't have means, yet, to tell
2963 * composite.c that we are USB 2.0 + LPM ECN.
2965 if (dwc->revision < DWC3_REVISION_220A)
2966 dwc3_trace(trace_dwc3_gadget,
2967 "Changing max_speed on rev %08x",
2970 dwc->gadget.max_speed = dwc->maximum_speed;
2973 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2976 dwc->gadget.quirk_ep_out_aligned_size = true;
2979 * REVISIT: Here we should clear all pending IRQs to be
2980 * sure we're starting from a well known location.
2983 ret = dwc3_gadget_init_endpoints(dwc);
2987 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2989 dev_err(dwc->dev, "failed to register udc\n");
2996 kfree(dwc->zlp_buf);
2999 dwc3_gadget_free_endpoints(dwc);
3000 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3001 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3004 kfree(dwc->setup_buf);
3007 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3008 dwc->ep0_trb, dwc->ep0_trb_addr);
3011 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3012 dwc->ctrl_req, dwc->ctrl_req_addr);
3018 /* -------------------------------------------------------------------------- */
3020 void dwc3_gadget_exit(struct dwc3 *dwc)
3022 usb_del_gadget_udc(&dwc->gadget);
3024 dwc3_gadget_free_endpoints(dwc);
3026 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3027 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3029 kfree(dwc->setup_buf);
3030 kfree(dwc->zlp_buf);
3032 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3033 dwc->ep0_trb, dwc->ep0_trb_addr);
3035 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3036 dwc->ctrl_req, dwc->ctrl_req_addr);
3039 int dwc3_gadget_suspend(struct dwc3 *dwc)
3043 if (!dwc->gadget_driver)
3046 ret = dwc3_gadget_run_stop(dwc, false, false);
3050 dwc3_disconnect_gadget(dwc);
3051 __dwc3_gadget_stop(dwc);
3056 int dwc3_gadget_resume(struct dwc3 *dwc)
3060 if (!dwc->gadget_driver)
3063 ret = __dwc3_gadget_start(dwc);
3067 ret = dwc3_gadget_run_stop(dwc, true, false);
3074 __dwc3_gadget_stop(dwc);
3080 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3082 if (dwc->pending_events) {
3083 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3084 dwc->pending_events = false;
3085 enable_irq(dwc->irq_gadget);