2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
57 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
60 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
61 * @dwc: pointer to our context structure
62 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
64 * Caller should take care of locking. This function will
65 * return 0 on success or -EINVAL if wrong Test Selector
68 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
72 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
73 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
87 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
93 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
94 * @dwc: pointer to our context structure
95 * @state: the state to put link into
97 * Caller should take care of locking. This function will
98 * return 0 on success or -EINVAL.
100 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
105 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
106 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
108 /* set requested state */
109 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
110 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
112 /* wait for a change in DSTS */
114 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
116 /* in HS, means ON */
117 if (DWC3_DSTS_USBLNKST(reg) == state)
123 dev_vdbg(dwc->dev, "link state change request timed out\n");
129 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
130 * @dwc: pointer to our context structure
132 * This function will a best effort FIFO allocation in order
133 * to improve FIFO usage and throughput, while still allowing
134 * us to enable as many endpoints as possible.
136 * Keep in mind that this operation will be highly dependent
137 * on the configured size for RAM1 - which contains TxFifo -,
138 * the amount of endpoints enabled on coreConsultant tool, and
139 * the width of the Master Bus.
141 * In the ideal world, we would always be able to satisfy the
142 * following equation:
144 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
145 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
147 * Unfortunately, due to many variables that's not always the case.
149 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
151 int last_fifo_depth = 0;
157 if (!dwc->needs_fifo_resize)
160 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
161 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
163 /* MDWIDTH is represented in bits, we need it in bytes */
167 * FIXME For now we will only allocate 1 wMaxPacketSize space
168 * for each enabled endpoint, later patches will come to
169 * improve this algorithm so that we better use the internal
172 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
173 struct dwc3_ep *dep = dwc->eps[num];
174 int fifo_number = dep->number >> 1;
178 if (!(dep->number & 1))
181 if (!(dep->flags & DWC3_EP_ENABLED))
184 if (usb_endpoint_xfer_bulk(dep->desc)
185 || usb_endpoint_xfer_isoc(dep->desc))
189 * REVISIT: the following assumes we will always have enough
190 * space available on the FIFO RAM for all possible use cases.
191 * Make sure that's true somehow and change FIFO allocation
194 * If we have Bulk or Isochronous endpoints, we want
195 * them to be able to be very, very fast. So we're giving
196 * those endpoints a fifo_size which is enough for 3 full
199 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
202 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
204 fifo_size |= (last_fifo_depth << 16);
206 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
207 dep->name, last_fifo_depth, fifo_size & 0xffff);
209 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
212 last_fifo_depth += (fifo_size & 0xffff);
218 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
220 struct dwc3 *dwc = req->dep->dwc;
222 if (req->request.length == 0) {
223 /* req->request.dma = dwc->setup_buf_addr; */
227 if (req->request.num_sgs) {
230 mapped = dma_map_sg(dwc->dev, req->request.sg,
231 req->request.num_sgs,
232 req->direction ? DMA_TO_DEVICE
235 dev_err(dwc->dev, "failed to map SGs\n");
239 req->request.num_mapped_sgs = mapped;
243 if (req->request.dma == DMA_ADDR_INVALID) {
244 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
245 req->request.length, req->direction
246 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
251 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
253 struct dwc3 *dwc = req->dep->dwc;
255 if (req->request.length == 0) {
256 req->request.dma = DMA_ADDR_INVALID;
260 if (req->request.num_mapped_sgs) {
261 req->request.dma = DMA_ADDR_INVALID;
262 dma_unmap_sg(dwc->dev, req->request.sg,
263 req->request.num_mapped_sgs,
264 req->direction ? DMA_TO_DEVICE
267 req->request.num_mapped_sgs = 0;
272 dma_unmap_single(dwc->dev, req->request.dma,
273 req->request.length, req->direction
274 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
276 req->request.dma = DMA_ADDR_INVALID;
280 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
283 struct dwc3 *dwc = dep->dwc;
286 if (req->request.num_mapped_sgs)
287 dep->busy_slot += req->request.num_mapped_sgs;
292 * Skip LINK TRB. We can't use req->trb and check for
293 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
294 * completed (not the LINK TRB).
296 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
297 usb_endpoint_xfer_isoc(dep->desc))
300 list_del(&req->list);
303 if (req->request.status == -EINPROGRESS)
304 req->request.status = status;
306 dwc3_unmap_buffer_from_dma(req);
308 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
309 req, dep->name, req->request.actual,
310 req->request.length, status);
312 spin_unlock(&dwc->lock);
313 req->request.complete(&req->dep->endpoint, &req->request);
314 spin_lock(&dwc->lock);
317 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
320 case DWC3_DEPCMD_DEPSTARTCFG:
321 return "Start New Configuration";
322 case DWC3_DEPCMD_ENDTRANSFER:
323 return "End Transfer";
324 case DWC3_DEPCMD_UPDATETRANSFER:
325 return "Update Transfer";
326 case DWC3_DEPCMD_STARTTRANSFER:
327 return "Start Transfer";
328 case DWC3_DEPCMD_CLEARSTALL:
329 return "Clear Stall";
330 case DWC3_DEPCMD_SETSTALL:
332 case DWC3_DEPCMD_GETSEQNUMBER:
333 return "Get Data Sequence Number";
334 case DWC3_DEPCMD_SETTRANSFRESOURCE:
335 return "Set Endpoint Transfer Resource";
336 case DWC3_DEPCMD_SETEPCONFIG:
337 return "Set Endpoint Configuration";
339 return "UNKNOWN command";
343 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
344 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
346 struct dwc3_ep *dep = dwc->eps[ep];
350 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
352 dwc3_gadget_ep_cmd_string(cmd), params->param0,
353 params->param1, params->param2);
355 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
356 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
357 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
359 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
361 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
362 if (!(reg & DWC3_DEPCMD_CMDACT)) {
363 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
364 DWC3_DEPCMD_STATUS(reg));
369 * We can't sleep here, because it is also called from
380 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
381 struct dwc3_trb *trb)
383 u32 offset = (char *) trb - (char *) dep->trb_pool;
385 return dep->trb_pool_dma + offset;
388 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
390 struct dwc3 *dwc = dep->dwc;
395 if (dep->number == 0 || dep->number == 1)
398 dep->trb_pool = dma_alloc_coherent(dwc->dev,
399 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
400 &dep->trb_pool_dma, GFP_KERNEL);
401 if (!dep->trb_pool) {
402 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
410 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
412 struct dwc3 *dwc = dep->dwc;
414 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
415 dep->trb_pool, dep->trb_pool_dma);
417 dep->trb_pool = NULL;
418 dep->trb_pool_dma = 0;
421 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423 struct dwc3_gadget_ep_cmd_params params;
426 memset(¶ms, 0x00, sizeof(params));
428 if (dep->number != 1) {
429 cmd = DWC3_DEPCMD_DEPSTARTCFG;
430 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
431 if (dep->number > 1) {
432 if (dwc->start_config_issued)
434 dwc->start_config_issued = true;
435 cmd |= DWC3_DEPCMD_PARAM(2);
438 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
444 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
445 const struct usb_endpoint_descriptor *desc,
446 const struct usb_ss_ep_comp_descriptor *comp_desc)
448 struct dwc3_gadget_ep_cmd_params params;
450 memset(¶ms, 0x00, sizeof(params));
452 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
453 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
454 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
456 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
457 | DWC3_DEPCFG_XFER_NOT_READY_EN;
459 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
460 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
461 | DWC3_DEPCFG_STREAM_EVENT_EN;
462 dep->stream_capable = true;
465 if (usb_endpoint_xfer_isoc(desc))
466 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
469 * We are doing 1:1 mapping for endpoints, meaning
470 * Physical Endpoints 2 maps to Logical Endpoint 2 and
471 * so on. We consider the direction bit as part of the physical
472 * endpoint number. So USB endpoint 0x81 is 0x03.
474 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
477 * We must use the lower 16 TX FIFOs even though
481 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
483 if (desc->bInterval) {
484 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
485 dep->interval = 1 << (desc->bInterval - 1);
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
492 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
494 struct dwc3_gadget_ep_cmd_params params;
496 memset(¶ms, 0x00, sizeof(params));
498 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
500 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
501 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
505 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
506 * @dep: endpoint to be initialized
507 * @desc: USB Endpoint Descriptor
509 * Caller should take care of locking
511 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
512 const struct usb_endpoint_descriptor *desc,
513 const struct usb_ss_ep_comp_descriptor *comp_desc)
515 struct dwc3 *dwc = dep->dwc;
519 if (!(dep->flags & DWC3_EP_ENABLED)) {
520 ret = dwc3_gadget_start_config(dwc, dep);
525 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
529 if (!(dep->flags & DWC3_EP_ENABLED)) {
530 struct dwc3_trb *trb_st_hw;
531 struct dwc3_trb *trb_link;
533 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
538 dep->comp_desc = comp_desc;
539 dep->type = usb_endpoint_type(desc);
540 dep->flags |= DWC3_EP_ENABLED;
542 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
543 reg |= DWC3_DALEPENA_EP(dep->number);
544 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
546 if (!usb_endpoint_xfer_isoc(desc))
549 memset(&trb_link, 0, sizeof(trb_link));
551 /* Link TRB for ISOC. The HWO bit is never reset */
552 trb_st_hw = &dep->trb_pool[0];
554 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
556 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
557 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
558 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
559 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
565 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
566 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
568 struct dwc3_request *req;
570 if (!list_empty(&dep->req_queued))
571 dwc3_stop_active_transfer(dwc, dep->number);
573 while (!list_empty(&dep->request_list)) {
574 req = next_request(&dep->request_list);
576 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
581 * __dwc3_gadget_ep_disable - Disables a HW endpoint
582 * @dep: the endpoint to disable
584 * This function also removes requests which are currently processed ny the
585 * hardware and those which are not yet scheduled.
586 * Caller should take care of locking.
588 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
590 struct dwc3 *dwc = dep->dwc;
593 dwc3_remove_requests(dwc, dep);
595 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
596 reg &= ~DWC3_DALEPENA_EP(dep->number);
597 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
599 dep->stream_capable = false;
601 dep->comp_desc = NULL;
608 /* -------------------------------------------------------------------------- */
610 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
611 const struct usb_endpoint_descriptor *desc)
616 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
621 /* -------------------------------------------------------------------------- */
623 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
624 const struct usb_endpoint_descriptor *desc)
631 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
632 pr_debug("dwc3: invalid parameters\n");
636 if (!desc->wMaxPacketSize) {
637 pr_debug("dwc3: missing wMaxPacketSize\n");
641 dep = to_dwc3_ep(ep);
644 switch (usb_endpoint_type(desc)) {
645 case USB_ENDPOINT_XFER_CONTROL:
646 strncat(dep->name, "-control", sizeof(dep->name));
648 case USB_ENDPOINT_XFER_ISOC:
649 strncat(dep->name, "-isoc", sizeof(dep->name));
651 case USB_ENDPOINT_XFER_BULK:
652 strncat(dep->name, "-bulk", sizeof(dep->name));
654 case USB_ENDPOINT_XFER_INT:
655 strncat(dep->name, "-int", sizeof(dep->name));
658 dev_err(dwc->dev, "invalid endpoint transfer type\n");
661 if (dep->flags & DWC3_EP_ENABLED) {
662 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
667 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
669 spin_lock_irqsave(&dwc->lock, flags);
670 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
671 spin_unlock_irqrestore(&dwc->lock, flags);
676 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
684 pr_debug("dwc3: invalid parameters\n");
688 dep = to_dwc3_ep(ep);
691 if (!(dep->flags & DWC3_EP_ENABLED)) {
692 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
697 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
699 (dep->number & 1) ? "in" : "out");
701 spin_lock_irqsave(&dwc->lock, flags);
702 ret = __dwc3_gadget_ep_disable(dep);
703 spin_unlock_irqrestore(&dwc->lock, flags);
708 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
711 struct dwc3_request *req;
712 struct dwc3_ep *dep = to_dwc3_ep(ep);
713 struct dwc3 *dwc = dep->dwc;
715 req = kzalloc(sizeof(*req), gfp_flags);
717 dev_err(dwc->dev, "not enough memory\n");
721 req->epnum = dep->number;
723 req->request.dma = DMA_ADDR_INVALID;
725 return &req->request;
728 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
729 struct usb_request *request)
731 struct dwc3_request *req = to_dwc3_request(request);
737 * dwc3_prepare_one_trb - setup one TRB from one request
738 * @dep: endpoint for which this request is prepared
739 * @req: dwc3_request pointer
741 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
742 struct dwc3_request *req, dma_addr_t dma,
743 unsigned length, unsigned last, unsigned chain)
745 struct dwc3 *dwc = dep->dwc;
746 struct dwc3_trb *trb;
748 unsigned int cur_slot;
750 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
751 dep->name, req, (unsigned long long) dma,
752 length, last ? " last" : "",
753 chain ? " chain" : "");
755 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
756 cur_slot = dep->free_slot;
759 /* Skip the LINK-TRB on ISOC */
760 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
761 usb_endpoint_xfer_isoc(dep->desc))
765 dwc3_gadget_move_request_queued(req);
767 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
770 trb->size = DWC3_TRB_SIZE_LENGTH(length);
771 trb->bpl = lower_32_bits(dma);
772 trb->bph = upper_32_bits(dma);
774 switch (usb_endpoint_type(dep->desc)) {
775 case USB_ENDPOINT_XFER_CONTROL:
776 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
779 case USB_ENDPOINT_XFER_ISOC:
780 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
782 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
783 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
784 trb->ctrl |= DWC3_TRB_CTRL_IOC;
787 case USB_ENDPOINT_XFER_BULK:
788 case USB_ENDPOINT_XFER_INT:
789 trb->ctrl = DWC3_TRBCTL_NORMAL;
793 * This is only possible with faulty memory because we
794 * checked it already :)
799 if (usb_endpoint_xfer_isoc(dep->desc)) {
800 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
801 trb->ctrl |= DWC3_TRB_CTRL_CSP;
804 trb->ctrl |= DWC3_TRB_CTRL_CHN;
807 trb->ctrl |= DWC3_TRB_CTRL_LST;
810 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
811 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
813 trb->ctrl |= DWC3_TRB_CTRL_HWO;
817 * dwc3_prepare_trbs - setup TRBs from requests
818 * @dep: endpoint for which requests are being prepared
819 * @starting: true if the endpoint is idle and no requests are queued.
821 * The function goes through the requests list and sets up TRBs for the
822 * transfers. The function returns once there are no more TRBs available or
823 * it runs out of requests.
825 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
827 struct dwc3_request *req, *n;
829 unsigned int last_one = 0;
831 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
833 /* the first request must not be queued */
834 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
837 * If busy & slot are equal than it is either full or empty. If we are
838 * starting to process requests then we are empty. Otherwise we are
839 * full and don't do anything
844 trbs_left = DWC3_TRB_NUM;
846 * In case we start from scratch, we queue the ISOC requests
847 * starting from slot 1. This is done because we use ring
848 * buffer and have no LST bit to stop us. Instead, we place
849 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
850 * after the first request so we start at slot 1 and have
851 * 7 requests proceed before we hit the first IOC.
852 * Other transfer types don't use the ring buffer and are
853 * processed from the first TRB until the last one. Since we
854 * don't wrap around we have to start at the beginning.
856 if (usb_endpoint_xfer_isoc(dep->desc)) {
865 /* The last TRB is a link TRB, not used for xfer */
866 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
869 list_for_each_entry_safe(req, n, &dep->request_list, list) {
873 if (req->request.num_mapped_sgs > 0) {
874 struct usb_request *request = &req->request;
875 struct scatterlist *sg = request->sg;
876 struct scatterlist *s;
879 for_each_sg(sg, s, request->num_mapped_sgs, i) {
880 unsigned chain = true;
882 length = sg_dma_len(s);
883 dma = sg_dma_address(s);
885 if (i == (request->num_mapped_sgs - 1) ||
898 dwc3_prepare_one_trb(dep, req, dma, length,
905 dma = req->request.dma;
906 length = req->request.length;
912 /* Is this the last request? */
913 if (list_is_last(&req->list, &dep->request_list))
916 dwc3_prepare_one_trb(dep, req, dma, length,
925 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
928 struct dwc3_gadget_ep_cmd_params params;
929 struct dwc3_request *req;
930 struct dwc3 *dwc = dep->dwc;
934 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
935 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
938 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
941 * If we are getting here after a short-out-packet we don't enqueue any
942 * new requests as we try to set the IOC bit only on the last request.
945 if (list_empty(&dep->req_queued))
946 dwc3_prepare_trbs(dep, start_new);
948 /* req points to the first request which will be sent */
949 req = next_request(&dep->req_queued);
951 dwc3_prepare_trbs(dep, start_new);
954 * req points to the first request where HWO changed from 0 to 1
956 req = next_request(&dep->req_queued);
959 dep->flags |= DWC3_EP_PENDING_REQUEST;
963 memset(¶ms, 0, sizeof(params));
964 params.param0 = upper_32_bits(req->trb_dma);
965 params.param1 = lower_32_bits(req->trb_dma);
968 cmd = DWC3_DEPCMD_STARTTRANSFER;
970 cmd = DWC3_DEPCMD_UPDATETRANSFER;
972 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
973 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
975 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
978 * FIXME we need to iterate over the list of requests
979 * here and stop, unmap, free and del each of the linked
980 * requests instead of what we do now.
982 dwc3_unmap_buffer_from_dma(req);
983 list_del(&req->list);
987 dep->flags |= DWC3_EP_BUSY;
988 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
991 WARN_ON_ONCE(!dep->res_trans_idx);
996 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
998 req->request.actual = 0;
999 req->request.status = -EINPROGRESS;
1000 req->direction = dep->direction;
1001 req->epnum = dep->number;
1004 * We only add to our list of requests now and
1005 * start consuming the list once we get XferNotReady
1008 * That way, we avoid doing anything that we don't need
1009 * to do now and defer it until the point we receive a
1010 * particular token from the Host side.
1012 * This will also avoid Host cancelling URBs due to too
1015 dwc3_map_buffer_to_dma(req);
1016 list_add_tail(&req->list, &dep->request_list);
1019 * There is one special case: XferNotReady with
1020 * empty list of requests. We need to kick the
1021 * transfer here in that situation, otherwise
1022 * we will be NAKing forever.
1024 * If we get XferNotReady before gadget driver
1025 * has a chance to queue a request, we will ACK
1026 * the IRQ but won't be able to receive the data
1027 * until the next request is queued. The following
1028 * code is handling exactly that.
1030 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1035 if (usb_endpoint_xfer_isoc(dep->desc) &&
1036 (dep->flags & DWC3_EP_BUSY))
1039 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
1040 if (ret && ret != -EBUSY) {
1041 struct dwc3 *dwc = dep->dwc;
1043 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1051 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1054 struct dwc3_request *req = to_dwc3_request(request);
1055 struct dwc3_ep *dep = to_dwc3_ep(ep);
1056 struct dwc3 *dwc = dep->dwc;
1058 unsigned long flags;
1063 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1068 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1069 request, ep->name, request->length);
1071 spin_lock_irqsave(&dwc->lock, flags);
1072 ret = __dwc3_gadget_ep_queue(dep, req);
1073 spin_unlock_irqrestore(&dwc->lock, flags);
1078 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1079 struct usb_request *request)
1081 struct dwc3_request *req = to_dwc3_request(request);
1082 struct dwc3_request *r = NULL;
1084 struct dwc3_ep *dep = to_dwc3_ep(ep);
1085 struct dwc3 *dwc = dep->dwc;
1087 unsigned long flags;
1090 spin_lock_irqsave(&dwc->lock, flags);
1092 list_for_each_entry(r, &dep->request_list, list) {
1098 list_for_each_entry(r, &dep->req_queued, list) {
1103 /* wait until it is processed */
1104 dwc3_stop_active_transfer(dwc, dep->number);
1107 dev_err(dwc->dev, "request %p was not queued to %s\n",
1113 /* giveback the request */
1114 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1117 spin_unlock_irqrestore(&dwc->lock, flags);
1122 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1124 struct dwc3_gadget_ep_cmd_params params;
1125 struct dwc3 *dwc = dep->dwc;
1128 memset(¶ms, 0x00, sizeof(params));
1131 if (dep->number == 0 || dep->number == 1) {
1133 * Whenever EP0 is stalled, we will restart
1134 * the state machine, thus moving back to
1137 dwc->ep0state = EP0_SETUP_PHASE;
1140 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1141 DWC3_DEPCMD_SETSTALL, ¶ms);
1143 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1144 value ? "set" : "clear",
1147 dep->flags |= DWC3_EP_STALL;
1149 if (dep->flags & DWC3_EP_WEDGE)
1152 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1153 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1155 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1156 value ? "set" : "clear",
1159 dep->flags &= ~DWC3_EP_STALL;
1165 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1167 struct dwc3_ep *dep = to_dwc3_ep(ep);
1168 struct dwc3 *dwc = dep->dwc;
1170 unsigned long flags;
1174 spin_lock_irqsave(&dwc->lock, flags);
1176 if (usb_endpoint_xfer_isoc(dep->desc)) {
1177 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1182 ret = __dwc3_gadget_ep_set_halt(dep, value);
1184 spin_unlock_irqrestore(&dwc->lock, flags);
1189 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1191 struct dwc3_ep *dep = to_dwc3_ep(ep);
1193 dep->flags |= DWC3_EP_WEDGE;
1195 return dwc3_gadget_ep_set_halt(ep, 1);
1198 /* -------------------------------------------------------------------------- */
1200 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1201 .bLength = USB_DT_ENDPOINT_SIZE,
1202 .bDescriptorType = USB_DT_ENDPOINT,
1203 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1206 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1207 .enable = dwc3_gadget_ep0_enable,
1208 .disable = dwc3_gadget_ep0_disable,
1209 .alloc_request = dwc3_gadget_ep_alloc_request,
1210 .free_request = dwc3_gadget_ep_free_request,
1211 .queue = dwc3_gadget_ep0_queue,
1212 .dequeue = dwc3_gadget_ep_dequeue,
1213 .set_halt = dwc3_gadget_ep_set_halt,
1214 .set_wedge = dwc3_gadget_ep_set_wedge,
1217 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1218 .enable = dwc3_gadget_ep_enable,
1219 .disable = dwc3_gadget_ep_disable,
1220 .alloc_request = dwc3_gadget_ep_alloc_request,
1221 .free_request = dwc3_gadget_ep_free_request,
1222 .queue = dwc3_gadget_ep_queue,
1223 .dequeue = dwc3_gadget_ep_dequeue,
1224 .set_halt = dwc3_gadget_ep_set_halt,
1225 .set_wedge = dwc3_gadget_ep_set_wedge,
1228 /* -------------------------------------------------------------------------- */
1230 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1232 struct dwc3 *dwc = gadget_to_dwc(g);
1235 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1236 return DWC3_DSTS_SOFFN(reg);
1239 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1241 struct dwc3 *dwc = gadget_to_dwc(g);
1243 unsigned long timeout;
1244 unsigned long flags;
1253 spin_lock_irqsave(&dwc->lock, flags);
1256 * According to the Databook Remote wakeup request should
1257 * be issued only when the device is in early suspend state.
1259 * We can check that via USB Link State bits in DSTS register.
1261 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1263 speed = reg & DWC3_DSTS_CONNECTSPD;
1264 if (speed == DWC3_DSTS_SUPERSPEED) {
1265 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1270 link_state = DWC3_DSTS_USBLNKST(reg);
1272 switch (link_state) {
1273 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1274 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1277 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1283 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1285 dev_err(dwc->dev, "failed to put link in Recovery\n");
1289 /* write zeroes to Link Change Request */
1290 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1291 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1293 /* poll until Link State changes to ON */
1294 timeout = jiffies + msecs_to_jiffies(100);
1296 while (!time_after(jiffies, timeout)) {
1297 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1299 /* in HS, means ON */
1300 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1304 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1305 dev_err(dwc->dev, "failed to send remote wakeup\n");
1310 spin_unlock_irqrestore(&dwc->lock, flags);
1315 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1318 struct dwc3 *dwc = gadget_to_dwc(g);
1320 dwc->is_selfpowered = !!is_selfpowered;
1325 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1330 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1332 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1333 reg |= (DWC3_DCTL_RUN_STOP
1334 | DWC3_DCTL_TRGTULST_RX_DET);
1336 reg &= ~DWC3_DCTL_RUN_STOP;
1339 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1342 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1344 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1347 if (reg & DWC3_DSTS_DEVCTRLHLT)
1356 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1358 ? dwc->gadget_driver->function : "no-function",
1359 is_on ? "connect" : "disconnect");
1362 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1364 struct dwc3 *dwc = gadget_to_dwc(g);
1365 unsigned long flags;
1369 spin_lock_irqsave(&dwc->lock, flags);
1370 dwc3_gadget_run_stop(dwc, is_on);
1371 spin_unlock_irqrestore(&dwc->lock, flags);
1376 static int dwc3_gadget_start(struct usb_gadget *g,
1377 struct usb_gadget_driver *driver)
1379 struct dwc3 *dwc = gadget_to_dwc(g);
1380 struct dwc3_ep *dep;
1381 unsigned long flags;
1385 spin_lock_irqsave(&dwc->lock, flags);
1387 if (dwc->gadget_driver) {
1388 dev_err(dwc->dev, "%s is already bound to %s\n",
1390 dwc->gadget_driver->driver.name);
1395 dwc->gadget_driver = driver;
1396 dwc->gadget.dev.driver = &driver->driver;
1398 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1399 reg &= ~(DWC3_DCFG_SPEED_MASK);
1400 reg |= dwc->maximum_speed;
1401 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1403 dwc->start_config_issued = false;
1405 /* Start with SuperSpeed Default */
1406 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1409 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1411 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1416 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1418 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1422 /* begin to receive SETUP packets */
1423 dwc->ep0state = EP0_SETUP_PHASE;
1424 dwc3_ep0_out_start(dwc);
1426 spin_unlock_irqrestore(&dwc->lock, flags);
1431 __dwc3_gadget_ep_disable(dwc->eps[0]);
1434 spin_unlock_irqrestore(&dwc->lock, flags);
1439 static int dwc3_gadget_stop(struct usb_gadget *g,
1440 struct usb_gadget_driver *driver)
1442 struct dwc3 *dwc = gadget_to_dwc(g);
1443 unsigned long flags;
1445 spin_lock_irqsave(&dwc->lock, flags);
1447 __dwc3_gadget_ep_disable(dwc->eps[0]);
1448 __dwc3_gadget_ep_disable(dwc->eps[1]);
1450 dwc->gadget_driver = NULL;
1451 dwc->gadget.dev.driver = NULL;
1453 spin_unlock_irqrestore(&dwc->lock, flags);
1457 static const struct usb_gadget_ops dwc3_gadget_ops = {
1458 .get_frame = dwc3_gadget_get_frame,
1459 .wakeup = dwc3_gadget_wakeup,
1460 .set_selfpowered = dwc3_gadget_set_selfpowered,
1461 .pullup = dwc3_gadget_pullup,
1462 .udc_start = dwc3_gadget_start,
1463 .udc_stop = dwc3_gadget_stop,
1466 /* -------------------------------------------------------------------------- */
1468 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1470 struct dwc3_ep *dep;
1473 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1475 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1476 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1478 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1484 dep->number = epnum;
1485 dwc->eps[epnum] = dep;
1487 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1488 (epnum & 1) ? "in" : "out");
1489 dep->endpoint.name = dep->name;
1490 dep->direction = (epnum & 1);
1492 if (epnum == 0 || epnum == 1) {
1493 dep->endpoint.maxpacket = 512;
1494 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1496 dwc->gadget.ep0 = &dep->endpoint;
1500 dep->endpoint.maxpacket = 1024;
1501 dep->endpoint.max_streams = 15;
1502 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1503 list_add_tail(&dep->endpoint.ep_list,
1504 &dwc->gadget.ep_list);
1506 ret = dwc3_alloc_trb_pool(dep);
1511 INIT_LIST_HEAD(&dep->request_list);
1512 INIT_LIST_HEAD(&dep->req_queued);
1518 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1520 struct dwc3_ep *dep;
1523 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1524 dep = dwc->eps[epnum];
1525 dwc3_free_trb_pool(dep);
1527 if (epnum != 0 && epnum != 1)
1528 list_del(&dep->endpoint.ep_list);
1534 static void dwc3_gadget_release(struct device *dev)
1536 dev_dbg(dev, "%s\n", __func__);
1539 /* -------------------------------------------------------------------------- */
1540 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1541 const struct dwc3_event_depevt *event, int status)
1543 struct dwc3_request *req;
1544 struct dwc3_trb *trb;
1546 unsigned int s_pkt = 0;
1549 req = next_request(&dep->req_queued);
1557 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1559 * We continue despite the error. There is not much we
1560 * can do. If we don't clean it up we loop forever. If
1561 * we skip the TRB then it gets overwritten after a
1562 * while since we use them in a ring buffer. A BUG()
1563 * would help. Lets hope that if this occurs, someone
1564 * fixes the root cause instead of looking away :)
1566 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1567 dep->name, req->trb);
1568 count = trb->size & DWC3_TRB_SIZE_MASK;
1570 if (dep->direction) {
1572 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1574 status = -ECONNRESET;
1577 if (count && (event->status & DEPEVT_STATUS_SHORT))
1582 * We assume here we will always receive the entire data block
1583 * which we should receive. Meaning, if we program RX to
1584 * receive 4K but we receive only 2K, we assume that's all we
1585 * should receive and we simply bounce the request back to the
1586 * gadget driver for further processing.
1588 req->request.actual += req->request.length - count;
1589 dwc3_gadget_giveback(dep, req, status);
1592 if ((event->status & DEPEVT_STATUS_LST) &&
1593 (trb->ctrl & DWC3_TRB_CTRL_LST))
1595 if ((event->status & DEPEVT_STATUS_IOC) &&
1596 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1600 if ((event->status & DEPEVT_STATUS_IOC) &&
1601 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1606 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1607 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1610 unsigned status = 0;
1613 if (event->status & DEPEVT_STATUS_BUSERR)
1614 status = -ECONNRESET;
1616 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1618 dep->flags &= ~DWC3_EP_BUSY;
1619 dep->res_trans_idx = 0;
1623 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1624 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1626 if (dwc->revision < DWC3_REVISION_183A) {
1630 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1631 struct dwc3_ep *dep = dwc->eps[i];
1633 if (!(dep->flags & DWC3_EP_ENABLED))
1636 if (!list_empty(&dep->req_queued))
1640 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1642 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1648 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1649 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1653 if (list_empty(&dep->request_list)) {
1654 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1659 if (event->parameters) {
1662 mask = ~(dep->interval - 1);
1663 uf = event->parameters & mask;
1664 /* 4 micro frames in the future */
1665 uf += dep->interval * 4;
1670 __dwc3_gadget_kick_transfer(dep, uf, 1);
1673 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1674 const struct dwc3_event_depevt *event)
1676 struct dwc3 *dwc = dep->dwc;
1677 struct dwc3_event_depevt mod_ev = *event;
1680 * We were asked to remove one request. It is possible that this
1681 * request and a few others were started together and have the same
1682 * transfer index. Since we stopped the complete endpoint we don't
1683 * know how many requests were already completed (and not yet)
1684 * reported and how could be done (later). We purge them all until
1685 * the end of the list.
1687 mod_ev.status = DEPEVT_STATUS_LST;
1688 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1689 dep->flags &= ~DWC3_EP_BUSY;
1690 /* pending requests are ignored and are queued on XferNotReady */
1693 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1694 const struct dwc3_event_depevt *event)
1696 u32 param = event->parameters;
1697 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1700 case DWC3_DEPCMD_ENDTRANSFER:
1701 dwc3_process_ep_cmd_complete(dep, event);
1703 case DWC3_DEPCMD_STARTTRANSFER:
1704 dep->res_trans_idx = param & 0x7f;
1707 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1708 __func__, cmd_type);
1713 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1714 const struct dwc3_event_depevt *event)
1716 struct dwc3_ep *dep;
1717 u8 epnum = event->endpoint_number;
1719 dep = dwc->eps[epnum];
1721 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1722 dwc3_ep_event_string(event->endpoint_event));
1724 if (epnum == 0 || epnum == 1) {
1725 dwc3_ep0_interrupt(dwc, event);
1729 switch (event->endpoint_event) {
1730 case DWC3_DEPEVT_XFERCOMPLETE:
1731 if (usb_endpoint_xfer_isoc(dep->desc)) {
1732 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1737 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1739 case DWC3_DEPEVT_XFERINPROGRESS:
1740 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1741 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1746 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1748 case DWC3_DEPEVT_XFERNOTREADY:
1749 if (usb_endpoint_xfer_isoc(dep->desc)) {
1750 dwc3_gadget_start_isoc(dwc, dep, event);
1754 dev_vdbg(dwc->dev, "%s: reason %s\n",
1755 dep->name, event->status &
1756 DEPEVT_STATUS_TRANSFER_ACTIVE
1758 : "Transfer Not Active");
1760 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1761 if (!ret || ret == -EBUSY)
1764 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1769 case DWC3_DEPEVT_STREAMEVT:
1770 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1771 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1776 switch (event->status) {
1777 case DEPEVT_STREAMEVT_FOUND:
1778 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1782 case DEPEVT_STREAMEVT_NOTFOUND:
1785 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1788 case DWC3_DEPEVT_RXTXFIFOEVT:
1789 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1791 case DWC3_DEPEVT_EPCMDCMPLT:
1792 dwc3_ep_cmd_compl(dep, event);
1797 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1799 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1800 spin_unlock(&dwc->lock);
1801 dwc->gadget_driver->disconnect(&dwc->gadget);
1802 spin_lock(&dwc->lock);
1806 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1808 struct dwc3_ep *dep;
1809 struct dwc3_gadget_ep_cmd_params params;
1813 dep = dwc->eps[epnum];
1815 WARN_ON(!dep->res_trans_idx);
1816 if (dep->res_trans_idx) {
1817 cmd = DWC3_DEPCMD_ENDTRANSFER;
1818 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1819 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1820 memset(¶ms, 0, sizeof(params));
1821 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1823 dep->res_trans_idx = 0;
1827 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1831 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1832 struct dwc3_ep *dep;
1834 dep = dwc->eps[epnum];
1835 if (!(dep->flags & DWC3_EP_ENABLED))
1838 dwc3_remove_requests(dwc, dep);
1842 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1846 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1847 struct dwc3_ep *dep;
1848 struct dwc3_gadget_ep_cmd_params params;
1851 dep = dwc->eps[epnum];
1853 if (!(dep->flags & DWC3_EP_STALL))
1856 dep->flags &= ~DWC3_EP_STALL;
1858 memset(¶ms, 0, sizeof(params));
1859 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1860 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1865 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1867 dev_vdbg(dwc->dev, "%s\n", __func__);
1870 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1871 enable it before we can disable it.
1873 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1874 reg &= ~DWC3_DCTL_INITU1ENA;
1875 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1877 reg &= ~DWC3_DCTL_INITU2ENA;
1878 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1881 dwc3_stop_active_transfers(dwc);
1882 dwc3_disconnect_gadget(dwc);
1883 dwc->start_config_issued = false;
1885 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1886 dwc->setup_packet_pending = false;
1889 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1893 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1896 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1898 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1900 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1903 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1907 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1910 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1912 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1914 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1917 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1921 dev_vdbg(dwc->dev, "%s\n", __func__);
1924 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1925 * would cause a missing Disconnect Event if there's a
1926 * pending Setup Packet in the FIFO.
1928 * There's no suggested workaround on the official Bug
1929 * report, which states that "unless the driver/application
1930 * is doing any special handling of a disconnect event,
1931 * there is no functional issue".
1933 * Unfortunately, it turns out that we _do_ some special
1934 * handling of a disconnect event, namely complete all
1935 * pending transfers, notify gadget driver of the
1936 * disconnection, and so on.
1938 * Our suggested workaround is to follow the Disconnect
1939 * Event steps here, instead, based on a setup_packet_pending
1940 * flag. Such flag gets set whenever we have a XferNotReady
1941 * event on EP0 and gets cleared on XferComplete for the
1946 * STAR#9000466709: RTL: Device : Disconnect event not
1947 * generated if setup packet pending in FIFO
1949 if (dwc->revision < DWC3_REVISION_188A) {
1950 if (dwc->setup_packet_pending)
1951 dwc3_gadget_disconnect_interrupt(dwc);
1954 /* after reset -> Default State */
1955 dwc->dev_state = DWC3_DEFAULT_STATE;
1958 dwc3_gadget_usb2_phy_power(dwc, true);
1959 dwc3_gadget_usb3_phy_power(dwc, true);
1961 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1962 dwc3_disconnect_gadget(dwc);
1964 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1965 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1966 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1967 dwc->test_mode = false;
1969 dwc3_stop_active_transfers(dwc);
1970 dwc3_clear_stall_all_ep(dwc);
1971 dwc->start_config_issued = false;
1973 /* Reset device address to zero */
1974 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1975 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1976 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1979 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1982 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1985 * We change the clock only at SS but I dunno why I would want to do
1986 * this. Maybe it becomes part of the power saving plan.
1989 if (speed != DWC3_DSTS_SUPERSPEED)
1993 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1994 * each time on Connect Done.
1999 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2000 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2001 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2004 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
2007 case USB_SPEED_SUPER:
2008 dwc3_gadget_usb2_phy_power(dwc, false);
2010 case USB_SPEED_HIGH:
2011 case USB_SPEED_FULL:
2013 dwc3_gadget_usb3_phy_power(dwc, false);
2018 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2020 struct dwc3_gadget_ep_cmd_params params;
2021 struct dwc3_ep *dep;
2026 dev_vdbg(dwc->dev, "%s\n", __func__);
2028 memset(¶ms, 0x00, sizeof(params));
2030 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2031 speed = reg & DWC3_DSTS_CONNECTSPD;
2034 dwc3_update_ram_clk_sel(dwc, speed);
2037 case DWC3_DCFG_SUPERSPEED:
2039 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2040 * would cause a missing USB3 Reset event.
2042 * In such situations, we should force a USB3 Reset
2043 * event by calling our dwc3_gadget_reset_interrupt()
2048 * STAR#9000483510: RTL: SS : USB3 reset event may
2049 * not be generated always when the link enters poll
2051 if (dwc->revision < DWC3_REVISION_190A)
2052 dwc3_gadget_reset_interrupt(dwc);
2054 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2055 dwc->gadget.ep0->maxpacket = 512;
2056 dwc->gadget.speed = USB_SPEED_SUPER;
2058 case DWC3_DCFG_HIGHSPEED:
2059 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2060 dwc->gadget.ep0->maxpacket = 64;
2061 dwc->gadget.speed = USB_SPEED_HIGH;
2063 case DWC3_DCFG_FULLSPEED2:
2064 case DWC3_DCFG_FULLSPEED1:
2065 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2066 dwc->gadget.ep0->maxpacket = 64;
2067 dwc->gadget.speed = USB_SPEED_FULL;
2069 case DWC3_DCFG_LOWSPEED:
2070 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2071 dwc->gadget.ep0->maxpacket = 8;
2072 dwc->gadget.speed = USB_SPEED_LOW;
2076 /* Disable unneded PHY */
2077 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
2080 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2082 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2087 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2089 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2094 * Configure PHY via GUSB3PIPECTLn if required.
2096 * Update GTXFIFOSIZn
2098 * In both cases reset values should be sufficient.
2102 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2104 dev_vdbg(dwc->dev, "%s\n", __func__);
2107 * TODO take core out of low power mode when that's
2111 dwc->gadget_driver->resume(&dwc->gadget);
2114 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2115 unsigned int evtinfo)
2117 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2120 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2121 * on the link partner, the USB session might do multiple entry/exit
2122 * of low power states before a transfer takes place.
2124 * Due to this problem, we might experience lower throughput. The
2125 * suggested workaround is to disable DCTL[12:9] bits if we're
2126 * transitioning from U1/U2 to U0 and enable those bits again
2127 * after a transfer completes and there are no pending transfers
2128 * on any of the enabled endpoints.
2130 * This is the first half of that workaround.
2134 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2135 * core send LGO_Ux entering U0
2137 if (dwc->revision < DWC3_REVISION_183A) {
2138 if (next == DWC3_LINK_STATE_U0) {
2142 switch (dwc->link_state) {
2143 case DWC3_LINK_STATE_U1:
2144 case DWC3_LINK_STATE_U2:
2145 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2146 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2147 | DWC3_DCTL_ACCEPTU2ENA
2148 | DWC3_DCTL_INITU1ENA
2149 | DWC3_DCTL_ACCEPTU1ENA);
2152 dwc->u1u2 = reg & u1u2;
2156 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2165 dwc->link_state = next;
2167 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2170 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2171 const struct dwc3_event_devt *event)
2173 switch (event->type) {
2174 case DWC3_DEVICE_EVENT_DISCONNECT:
2175 dwc3_gadget_disconnect_interrupt(dwc);
2177 case DWC3_DEVICE_EVENT_RESET:
2178 dwc3_gadget_reset_interrupt(dwc);
2180 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2181 dwc3_gadget_conndone_interrupt(dwc);
2183 case DWC3_DEVICE_EVENT_WAKEUP:
2184 dwc3_gadget_wakeup_interrupt(dwc);
2186 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2187 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2189 case DWC3_DEVICE_EVENT_EOPF:
2190 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2192 case DWC3_DEVICE_EVENT_SOF:
2193 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2195 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2196 dev_vdbg(dwc->dev, "Erratic Error\n");
2198 case DWC3_DEVICE_EVENT_CMD_CMPL:
2199 dev_vdbg(dwc->dev, "Command Complete\n");
2201 case DWC3_DEVICE_EVENT_OVERFLOW:
2202 dev_vdbg(dwc->dev, "Overflow\n");
2205 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2209 static void dwc3_process_event_entry(struct dwc3 *dwc,
2210 const union dwc3_event *event)
2212 /* Endpoint IRQ, handle it and return early */
2213 if (event->type.is_devspec == 0) {
2215 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2218 switch (event->type.type) {
2219 case DWC3_EVENT_TYPE_DEV:
2220 dwc3_gadget_interrupt(dwc, &event->devt);
2222 /* REVISIT what to do with Carkit and I2C events ? */
2224 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2228 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2230 struct dwc3_event_buffer *evt;
2234 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2235 count &= DWC3_GEVNTCOUNT_MASK;
2239 evt = dwc->ev_buffs[buf];
2243 union dwc3_event event;
2245 event.raw = *(u32 *) (evt->buf + evt->lpos);
2247 dwc3_process_event_entry(dwc, &event);
2249 * XXX we wrap around correctly to the next entry as almost all
2250 * entries are 4 bytes in size. There is one entry which has 12
2251 * bytes which is a regular entry followed by 8 bytes data. ATM
2252 * I don't know how things are organized if were get next to the
2253 * a boundary so I worry about that once we try to handle that.
2255 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2258 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2264 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2266 struct dwc3 *dwc = _dwc;
2268 irqreturn_t ret = IRQ_NONE;
2270 spin_lock(&dwc->lock);
2272 for (i = 0; i < dwc->num_event_buffers; i++) {
2275 status = dwc3_process_event_buf(dwc, i);
2276 if (status == IRQ_HANDLED)
2280 spin_unlock(&dwc->lock);
2286 * dwc3_gadget_init - Initializes gadget related registers
2287 * @dwc: pointer to our controller context structure
2289 * Returns 0 on success otherwise negative errno.
2291 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2297 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2298 &dwc->ctrl_req_addr, GFP_KERNEL);
2299 if (!dwc->ctrl_req) {
2300 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2305 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2306 &dwc->ep0_trb_addr, GFP_KERNEL);
2307 if (!dwc->ep0_trb) {
2308 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2313 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
2314 sizeof(*dwc->setup_buf) * 2,
2315 &dwc->setup_buf_addr, GFP_KERNEL);
2316 if (!dwc->setup_buf) {
2317 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2322 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2323 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
2324 if (!dwc->ep0_bounce) {
2325 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2330 dev_set_name(&dwc->gadget.dev, "gadget");
2332 dwc->gadget.ops = &dwc3_gadget_ops;
2333 dwc->gadget.max_speed = USB_SPEED_SUPER;
2334 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2335 dwc->gadget.dev.parent = dwc->dev;
2336 dwc->gadget.sg_supported = true;
2338 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2340 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2341 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2342 dwc->gadget.dev.release = dwc3_gadget_release;
2343 dwc->gadget.name = "dwc3-gadget";
2346 * REVISIT: Here we should clear all pending IRQs to be
2347 * sure we're starting from a well known location.
2350 ret = dwc3_gadget_init_endpoints(dwc);
2354 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2356 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2359 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2364 /* Enable all but Start and End of Frame IRQs */
2365 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2366 DWC3_DEVTEN_EVNTOVERFLOWEN |
2367 DWC3_DEVTEN_CMDCMPLTEN |
2368 DWC3_DEVTEN_ERRTICERREN |
2369 DWC3_DEVTEN_WKUPEVTEN |
2370 DWC3_DEVTEN_ULSTCNGEN |
2371 DWC3_DEVTEN_CONNECTDONEEN |
2372 DWC3_DEVTEN_USBRSTEN |
2373 DWC3_DEVTEN_DISCONNEVTEN);
2374 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2376 ret = device_register(&dwc->gadget.dev);
2378 dev_err(dwc->dev, "failed to register gadget device\n");
2379 put_device(&dwc->gadget.dev);
2383 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2385 dev_err(dwc->dev, "failed to register udc\n");
2392 device_unregister(&dwc->gadget.dev);
2395 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2399 dwc3_gadget_free_endpoints(dwc);
2402 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2403 dwc->ep0_bounce_addr);
2406 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2407 dwc->setup_buf, dwc->setup_buf_addr);
2410 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2411 dwc->ep0_trb, dwc->ep0_trb_addr);
2414 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2415 dwc->ctrl_req, dwc->ctrl_req_addr);
2421 void dwc3_gadget_exit(struct dwc3 *dwc)
2425 usb_del_gadget_udc(&dwc->gadget);
2426 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2428 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2431 dwc3_gadget_free_endpoints(dwc);
2433 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2434 dwc->ep0_bounce_addr);
2436 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2437 dwc->setup_buf, dwc->setup_buf_addr);
2439 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2440 dwc->ep0_trb, dwc->ep0_trb_addr);
2442 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2443 dwc->ctrl_req, dwc->ctrl_req_addr);
2445 device_unregister(&dwc->gadget.dev);