drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 /**
  58  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  59  * @dwc: pointer to our context structure
  60  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  61  *
  62  * Caller should take care of locking. This function will
  63  * return 0 on success or -EINVAL if wrong Test Selector
  64  * is passed
  65  */
  66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  67 {
  68         u32             reg;
  69
  70         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  71         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  72
  73         switch (mode) {
  74         case TEST_J:
  75         case TEST_K:
  76         case TEST_SE0_NAK:
  77         case TEST_PACKET:
  78         case TEST_FORCE_EN:
  79                 reg |= mode << 1;
  80                 break;
  81         default:
  82                 return -EINVAL;
  83         }
  84
  85         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  86
  87         return 0;
  88 }
  89
  90 /**
  91  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  92  * @dwc: pointer to our context structure
  93  * @state: the state to put link into
  94  *
  95  * Caller should take care of locking. This function will
  96  * return 0 on success or -ETIMEDOUT.
  97  */
  98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  99 {
 100         int             retries = 10000;
 101         u32             reg;
 102
 103         /*
 104          * Wait until device controller is ready. Only applies to 1.94a and
 105          * later RTL.
 106          */
 107         if (dwc->revision >= DWC3_REVISION_194A) {
 108                 while (--retries) {
 109                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 110                         if (reg & DWC3_DSTS_DCNRD)
 111                                 udelay(5);
 112                         else
 113                                 break;
 114                 }
 115
 116                 if (retries <= 0)
 117                         return -ETIMEDOUT;
 118         }
 119
 120         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 122
 123         /* set requested state */
 124         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 125         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 126
 127         /*
 128          * The following code is racy when called from dwc3_gadget_wakeup,
 129          * and is not needed, at least on newer versions
 130          */
 131         if (dwc->revision >= DWC3_REVISION_194A)
 132                 return 0;
 133
 134         /* wait for a change in DSTS */
 135         retries = 10000;
 136         while (--retries) {
 137                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 138
 139                 if (DWC3_DSTS_USBLNKST(reg) == state)
 140                         return 0;
 141
 142                 udelay(5);
 143         }
 144
 145         dev_vdbg(dwc->dev, "link state change request timed out\n");
 146
 147         return -ETIMEDOUT;
 148 }
 149
 150 /**
 151  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 152  * @dwc: pointer to our context structure
 153  *
 154  * This function will a best effort FIFO allocation in order
 155  * to improve FIFO usage and throughput, while still allowing
 156  * us to enable as many endpoints as possible.
 157  *
 158  * Keep in mind that this operation will be highly dependent
 159  * on the configured size for RAM1 - which contains TxFifo -,
 160  * the amount of endpoints enabled on coreConsultant tool, and
 161  * the width of the Master Bus.
 162  *
 163  * In the ideal world, we would always be able to satisfy the
 164  * following equation:
 165  *
 166  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 167  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 168  *
 169  * Unfortunately, due to many variables that's not always the case.
 170  */
 171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 172 {
 173         int             last_fifo_depth = 0;
 174         int             ram1_depth;
 175         int             fifo_size;
 176         int             mdwidth;
 177         int             num;
 178
 179         if (!dwc->needs_fifo_resize)
 180                 return 0;
 181
 182         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 183         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 184
 185         /* MDWIDTH is represented in bits, we need it in bytes */
 186         mdwidth >>= 3;
 187
 188         /*
 189          * FIXME For now we will only allocate 1 wMaxPacketSize space
 190          * for each enabled endpoint, later patches will come to
 191          * improve this algorithm so that we better use the internal
 192          * FIFO space
 193          */
 194         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 195                 struct dwc3_ep  *dep = dwc->eps[num];
 196                 int             fifo_number = dep->number >> 1;
 197                 int             mult = 1;
 198                 int             tmp;
 199
 200                 if (!(dep->number & 1))
 201                         continue;
 202
 203                 if (!(dep->flags & DWC3_EP_ENABLED))
 204                         continue;
 205
 206                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 207                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 208                         mult = 3;
 209
 210                 /*
 211                  * REVISIT: the following assumes we will always have enough
 212                  * space available on the FIFO RAM for all possible use cases.
 213                  * Make sure that's true somehow and change FIFO allocation
 214                  * accordingly.
 215                  *
 216                  * If we have Bulk or Isochronous endpoints, we want
 217                  * them to be able to be very, very fast. So we're giving
 218                  * those endpoints a fifo_size which is enough for 3 full
 219                  * packets
 220                  */
 221                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 222                 tmp += mdwidth;
 223
 224                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 225
 226                 fifo_size |= (last_fifo_depth << 16);
 227
 228                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 229                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 230
 231                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 232                                 fifo_size);
 233
 234                 last_fifo_depth += (fifo_size & 0xffff);
 235         }
 236
 237         return 0;
 238 }
 239
 240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 241                 int status)
 242 {
 243         struct dwc3                     *dwc = dep->dwc;
 244
 245         if (req->queued) {
 246                 if (req->request.num_mapped_sgs)
 247                         dep->busy_slot += req->request.num_mapped_sgs;
 248                 else
 249                         dep->busy_slot++;
 250
 251                 /*
 252                  * Skip LINK TRB. We can't use req->trb and check for
 253                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
 254                  * completed (not the LINK TRB).
 255                  */
 256                 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 257                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 258                         dep->busy_slot++;
 259         }
 260         list_del(&req->list);
 261         req->trb = NULL;
 262
 263         if (req->request.status == -EINPROGRESS)
 264                 req->request.status = status;
 265
 266         if (dwc->ep0_bounced && dep->number == 0)
 267                 dwc->ep0_bounced = false;
 268         else
 269                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 270                                 req->direction);
 271
 272         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 273                         req, dep->name, req->request.actual,
 274                         req->request.length, status);
 275
 276         spin_unlock(&dwc->lock);
 277         req->request.complete(&dep->endpoint, &req->request);
 278         spin_lock(&dwc->lock);
 279 }
 280
 281 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 282 {
 283         switch (cmd) {
 284         case DWC3_DEPCMD_DEPSTARTCFG:
 285                 return "Start New Configuration";
 286         case DWC3_DEPCMD_ENDTRANSFER:
 287                 return "End Transfer";
 288         case DWC3_DEPCMD_UPDATETRANSFER:
 289                 return "Update Transfer";
 290         case DWC3_DEPCMD_STARTTRANSFER:
 291                 return "Start Transfer";
 292         case DWC3_DEPCMD_CLEARSTALL:
 293                 return "Clear Stall";
 294         case DWC3_DEPCMD_SETSTALL:
 295                 return "Set Stall";
 296         case DWC3_DEPCMD_GETEPSTATE:
 297                 return "Get Endpoint State";
 298         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 299                 return "Set Endpoint Transfer Resource";
 300         case DWC3_DEPCMD_SETEPCONFIG:
 301                 return "Set Endpoint Configuration";
 302         default:
 303                 return "UNKNOWN command";
 304         }
 305 }
 306
 307 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 308 {
 309         u32             timeout = 500;
 310         u32             reg;
 311
 312         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 313         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 314
 315         do {
 316                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 317                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 318                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 319                                         DWC3_DGCMD_STATUS(reg));
 320                         return 0;
 321                 }
 322
 323                 /*
 324                  * We can't sleep here, because it's also called from
 325                  * interrupt context.
 326                  */
 327                 timeout--;
 328                 if (!timeout)
 329                         return -ETIMEDOUT;
 330                 udelay(1);
 331         } while (1);
 332 }
 333
 334 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 335                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 336 {
 337         struct dwc3_ep          *dep = dwc->eps[ep];
 338         u32                     timeout = 500;
 339         u32                     reg;
 340
 341         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 342                         dep->name,
 343                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 344                         params->param1, params->param2);
 345
 346         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 347         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 348         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 349
 350         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 351         do {
 352                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 353                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 354                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 355                                         DWC3_DEPCMD_STATUS(reg));
 356                         return 0;
 357                 }
 358
 359                 /*
 360                  * We can't sleep here, because it is also called from
 361                  * interrupt context.
 362                  */
 363                 timeout--;
 364                 if (!timeout)
 365                         return -ETIMEDOUT;
 366
 367                 udelay(1);
 368         } while (1);
 369 }
 370
 371 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 372                 struct dwc3_trb *trb)
 373 {
 374         u32             offset = (char *) trb - (char *) dep->trb_pool;
 375
 376         return dep->trb_pool_dma + offset;
 377 }
 378
 379 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 380 {
 381         struct dwc3             *dwc = dep->dwc;
 382
 383         if (dep->trb_pool)
 384                 return 0;
 385
 386         if (dep->number == 0 || dep->number == 1)
 387                 return 0;
 388
 389         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 390                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 391                         &dep->trb_pool_dma, GFP_KERNEL);
 392         if (!dep->trb_pool) {
 393                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 394                                 dep->name);
 395                 return -ENOMEM;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 402 {
 403         struct dwc3             *dwc = dep->dwc;
 404
 405         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 406                         dep->trb_pool, dep->trb_pool_dma);
 407
 408         dep->trb_pool = NULL;
 409         dep->trb_pool_dma = 0;
 410 }
 411
 412 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 413 {
 414         struct dwc3_gadget_ep_cmd_params params;
 415         u32                     cmd;
 416
 417         memset(&params, 0x00, sizeof(params));
 418
 419         if (dep->number != 1) {
 420                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 421                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 422                 if (dep->number > 1) {
 423                         if (dwc->start_config_issued)
 424                                 return 0;
 425                         dwc->start_config_issued = true;
 426                         cmd |= DWC3_DEPCMD_PARAM(2);
 427                 }
 428
 429                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 430         }
 431
 432         return 0;
 433 }
 434
 435 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 436                 const struct usb_endpoint_descriptor *desc,
 437                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 438                 bool ignore)
 439 {
 440         struct dwc3_gadget_ep_cmd_params params;
 441
 442         memset(&params, 0x00, sizeof(params));
 443
 444         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 445                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 446
 447         /* Burst size is only needed in SuperSpeed mode */
 448         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 449                 u32 burst = dep->endpoint.maxburst - 1;
 450
 451                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 452         }
 453
 454         if (ignore)
 455                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 456
 457         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 458                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 459
 460         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 461                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 462                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 463                 dep->stream_capable = true;
 464         }
 465
 466         if (usb_endpoint_xfer_isoc(desc))
 467                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 468
 469         /*
 470          * We are doing 1:1 mapping for endpoints, meaning
 471          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 472          * so on. We consider the direction bit as part of the physical
 473          * endpoint number. So USB endpoint 0x81 is 0x03.
 474          */
 475         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 476
 477         /*
 478          * We must use the lower 16 TX FIFOs even though
 479          * HW might have more
 480          */
 481         if (dep->direction)
 482                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 483
 484         if (desc->bInterval) {
 485                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 486                 dep->interval = 1 << (desc->bInterval - 1);
 487         }
 488
 489         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 490                         DWC3_DEPCMD_SETEPCONFIG, &params);
 491 }
 492
 493 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 494 {
 495         struct dwc3_gadget_ep_cmd_params params;
 496
 497         memset(&params, 0x00, sizeof(params));
 498
 499         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 500
 501         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 502                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 503 }
 504
 505 /**
 506  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 507  * @dep: endpoint to be initialized
 508  * @desc: USB Endpoint Descriptor
 509  *
 510  * Caller should take care of locking
 511  */
 512 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 513                 const struct usb_endpoint_descriptor *desc,
 514                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 515                 bool ignore)
 516 {
 517         struct dwc3             *dwc = dep->dwc;
 518         u32                     reg;
 519         int                     ret = -ENOMEM;
 520
 521         if (!(dep->flags & DWC3_EP_ENABLED)) {
 522                 ret = dwc3_gadget_start_config(dwc, dep);
 523                 if (ret)
 524                         return ret;
 525         }
 526
 527         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
 528         if (ret)
 529                 return ret;
 530
 531         if (!(dep->flags & DWC3_EP_ENABLED)) {
 532                 struct dwc3_trb *trb_st_hw;
 533                 struct dwc3_trb *trb_link;
 534
 535                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 536                 if (ret)
 537                         return ret;
 538
 539                 dep->endpoint.desc = desc;
 540                 dep->comp_desc = comp_desc;
 541                 dep->type = usb_endpoint_type(desc);
 542                 dep->flags |= DWC3_EP_ENABLED;
 543
 544                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 545                 reg |= DWC3_DALEPENA_EP(dep->number);
 546                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 547
 548                 if (!usb_endpoint_xfer_isoc(desc))
 549                         return 0;
 550
 551                 memset(&trb_link, 0, sizeof(trb_link));
 552
 553                 /* Link TRB for ISOC. The HWO bit is never reset */
 554                 trb_st_hw = &dep->trb_pool[0];
 555
 556                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 557
 558                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 559                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 560                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 561                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 562         }
 563
 564         return 0;
 565 }
 566
 567 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 568 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 569 {
 570         struct dwc3_request             *req;
 571
 572         if (!list_empty(&dep->req_queued)) {
 573                 dwc3_stop_active_transfer(dwc, dep->number);
 574
 575                 /* - giveback all requests to gadget driver */
 576                 while (!list_empty(&dep->req_queued)) {
 577                         req = next_request(&dep->req_queued);
 578
 579                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 580                 }
 581         }
 582
 583         while (!list_empty(&dep->request_list)) {
 584                 req = next_request(&dep->request_list);
 585
 586                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 587         }
 588 }
 589
 590 /**
 591  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 592  * @dep: the endpoint to disable
 593  *
 594  * This function also removes requests which are currently processed ny the
 595  * hardware and those which are not yet scheduled.
 596  * Caller should take care of locking.
 597  */
 598 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 599 {
 600         struct dwc3             *dwc = dep->dwc;
 601         u32                     reg;
 602
 603         dwc3_remove_requests(dwc, dep);
 604
 605         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 606         reg &= ~DWC3_DALEPENA_EP(dep->number);
 607         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 608
 609         dep->stream_capable = false;
 610         dep->endpoint.desc = NULL;
 611         dep->comp_desc = NULL;
 612         dep->type = 0;
 613         dep->flags = 0;
 614
 615         return 0;
 616 }
 617
 618 /* -------------------------------------------------------------------------- */
 619
 620 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 621                 const struct usb_endpoint_descriptor *desc)
 622 {
 623         return -EINVAL;
 624 }
 625
 626 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 627 {
 628         return -EINVAL;
 629 }
 630
 631 /* -------------------------------------------------------------------------- */
 632
 633 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 634                 const struct usb_endpoint_descriptor *desc)
 635 {
 636         struct dwc3_ep                  *dep;
 637         struct dwc3                     *dwc;
 638         unsigned long                   flags;
 639         int                             ret;
 640
 641         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 642                 pr_debug("dwc3: invalid parameters\n");
 643                 return -EINVAL;
 644         }
 645
 646         if (!desc->wMaxPacketSize) {
 647                 pr_debug("dwc3: missing wMaxPacketSize\n");
 648                 return -EINVAL;
 649         }
 650
 651         dep = to_dwc3_ep(ep);
 652         dwc = dep->dwc;
 653
 654         if (dep->flags & DWC3_EP_ENABLED) {
 655                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 656                                 dep->name);
 657                 return 0;
 658         }
 659
 660         switch (usb_endpoint_type(desc)) {
 661         case USB_ENDPOINT_XFER_CONTROL:
 662                 strlcat(dep->name, "-control", sizeof(dep->name));
 663                 break;
 664         case USB_ENDPOINT_XFER_ISOC:
 665                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 666                 break;
 667         case USB_ENDPOINT_XFER_BULK:
 668                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 669                 break;
 670         case USB_ENDPOINT_XFER_INT:
 671                 strlcat(dep->name, "-int", sizeof(dep->name));
 672                 break;
 673         default:
 674                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 675         }
 676
 677         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 678
 679         spin_lock_irqsave(&dwc->lock, flags);
 680         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
 681         spin_unlock_irqrestore(&dwc->lock, flags);
 682
 683         return ret;
 684 }
 685
 686 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 687 {
 688         struct dwc3_ep                  *dep;
 689         struct dwc3                     *dwc;
 690         unsigned long                   flags;
 691         int                             ret;
 692
 693         if (!ep) {
 694                 pr_debug("dwc3: invalid parameters\n");
 695                 return -EINVAL;
 696         }
 697
 698         dep = to_dwc3_ep(ep);
 699         dwc = dep->dwc;
 700
 701         if (!(dep->flags & DWC3_EP_ENABLED)) {
 702                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 703                                 dep->name);
 704                 return 0;
 705         }
 706
 707         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 708                         dep->number >> 1,
 709                         (dep->number & 1) ? "in" : "out");
 710
 711         spin_lock_irqsave(&dwc->lock, flags);
 712         ret = __dwc3_gadget_ep_disable(dep);
 713         spin_unlock_irqrestore(&dwc->lock, flags);
 714
 715         return ret;
 716 }
 717
 718 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 719         gfp_t gfp_flags)
 720 {
 721         struct dwc3_request             *req;
 722         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 723         struct dwc3                     *dwc = dep->dwc;
 724
 725         req = kzalloc(sizeof(*req), gfp_flags);
 726         if (!req) {
 727                 dev_err(dwc->dev, "not enough memory\n");
 728                 return NULL;
 729         }
 730
 731         req->epnum      = dep->number;
 732         req->dep        = dep;
 733
 734         return &req->request;
 735 }
 736
 737 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 738                 struct usb_request *request)
 739 {
 740         struct dwc3_request             *req = to_dwc3_request(request);
 741
 742         kfree(req);
 743 }
 744
 745 /**
 746  * dwc3_prepare_one_trb - setup one TRB from one request
 747  * @dep: endpoint for which this request is prepared
 748  * @req: dwc3_request pointer
 749  */
 750 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 751                 struct dwc3_request *req, dma_addr_t dma,
 752                 unsigned length, unsigned last, unsigned chain)
 753 {
 754         struct dwc3             *dwc = dep->dwc;
 755         struct dwc3_trb         *trb;
 756
 757         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 758                         dep->name, req, (unsigned long long) dma,
 759                         length, last ? " last" : "",
 760                         chain ? " chain" : "");
 761
 762         /* Skip the LINK-TRB on ISOC */
 763         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 764                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 765                 dep->free_slot++;
 766
 767         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 768         dep->free_slot++;
 769
 770         if (!req->trb) {
 771                 dwc3_gadget_move_request_queued(req);
 772                 req->trb = trb;
 773                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 774         }
 775
 776         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 777         trb->bpl = lower_32_bits(dma);
 778         trb->bph = upper_32_bits(dma);
 779
 780         switch (usb_endpoint_type(dep->endpoint.desc)) {
 781         case USB_ENDPOINT_XFER_CONTROL:
 782                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 783                 break;
 784
 785         case USB_ENDPOINT_XFER_ISOC:
 786                 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 787
 788                 if (!req->request.no_interrupt)
 789                         trb->ctrl |= DWC3_TRB_CTRL_IOC;
 790                 break;
 791
 792         case USB_ENDPOINT_XFER_BULK:
 793         case USB_ENDPOINT_XFER_INT:
 794                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 795                 break;
 796         default:
 797                 /*
 798                  * This is only possible with faulty memory because we
 799                  * checked it already :)
 800                  */
 801                 BUG();
 802         }
 803
 804         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 805                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 806                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 807         } else {
 808                 if (chain)
 809                         trb->ctrl |= DWC3_TRB_CTRL_CHN;
 810
 811                 if (last)
 812                         trb->ctrl |= DWC3_TRB_CTRL_LST;
 813         }
 814
 815         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 816                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 817
 818         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 819 }
 820
 821 /*
 822  * dwc3_prepare_trbs - setup TRBs from requests
 823  * @dep: endpoint for which requests are being prepared
 824  * @starting: true if the endpoint is idle and no requests are queued.
 825  *
 826  * The function goes through the requests list and sets up TRBs for the
 827  * transfers. The function returns once there are no more TRBs available or
 828  * it runs out of requests.
 829  */
 830 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 831 {
 832         struct dwc3_request     *req, *n;
 833         u32                     trbs_left;
 834         u32                     max;
 835         unsigned int            last_one = 0;
 836
 837         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 838
 839         /* the first request must not be queued */
 840         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 841
 842         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 843         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 844                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 845                 if (trbs_left > max)
 846                         trbs_left = max;
 847         }
 848
 849         /*
 850          * If busy & slot are equal than it is either full or empty. If we are
 851          * starting to process requests then we are empty. Otherwise we are
 852          * full and don't do anything
 853          */
 854         if (!trbs_left) {
 855                 if (!starting)
 856                         return;
 857                 trbs_left = DWC3_TRB_NUM;
 858                 /*
 859                  * In case we start from scratch, we queue the ISOC requests
 860                  * starting from slot 1. This is done because we use ring
 861                  * buffer and have no LST bit to stop us. Instead, we place
 862                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 863                  * after the first request so we start at slot 1 and have
 864                  * 7 requests proceed before we hit the first IOC.
 865                  * Other transfer types don't use the ring buffer and are
 866                  * processed from the first TRB until the last one. Since we
 867                  * don't wrap around we have to start at the beginning.
 868                  */
 869                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 870                         dep->busy_slot = 1;
 871                         dep->free_slot = 1;
 872                 } else {
 873                         dep->busy_slot = 0;
 874                         dep->free_slot = 0;
 875                 }
 876         }
 877
 878         /* The last TRB is a link TRB, not used for xfer */
 879         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 880                 return;
 881
 882         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 883                 unsigned        length;
 884                 dma_addr_t      dma;
 885
 886                 if (req->request.num_mapped_sgs > 0) {
 887                         struct usb_request *request = &req->request;
 888                         struct scatterlist *sg = request->sg;
 889                         struct scatterlist *s;
 890                         int             i;
 891
 892                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 893                                 unsigned chain = true;
 894
 895                                 length = sg_dma_len(s);
 896                                 dma = sg_dma_address(s);
 897
 898                                 if (i == (request->num_mapped_sgs - 1) ||
 899                                                 sg_is_last(s)) {
 900                                         last_one = true;
 901                                         chain = false;
 902                                 }
 903
 904                                 trbs_left--;
 905                                 if (!trbs_left)
 906                                         last_one = true;
 907
 908                                 if (last_one)
 909                                         chain = false;
 910
 911                                 dwc3_prepare_one_trb(dep, req, dma, length,
 912                                                 last_one, chain);
 913
 914                                 if (last_one)
 915                                         break;
 916                         }
 917                 } else {
 918                         dma = req->request.dma;
 919                         length = req->request.length;
 920                         trbs_left--;
 921
 922                         if (!trbs_left)
 923                                 last_one = 1;
 924
 925                         /* Is this the last request? */
 926                         if (list_is_last(&req->list, &dep->request_list))
 927                                 last_one = 1;
 928
 929                         dwc3_prepare_one_trb(dep, req, dma, length,
 930                                         last_one, false);
 931
 932                         if (last_one)
 933                                 break;
 934                 }
 935         }
 936 }
 937
 938 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 939                 int start_new)
 940 {
 941         struct dwc3_gadget_ep_cmd_params params;
 942         struct dwc3_request             *req;
 943         struct dwc3                     *dwc = dep->dwc;
 944         int                             ret;
 945         u32                             cmd;
 946
 947         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 948                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 949                 return -EBUSY;
 950         }
 951         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 952
 953         /*
 954          * If we are getting here after a short-out-packet we don't enqueue any
 955          * new requests as we try to set the IOC bit only on the last request.
 956          */
 957         if (start_new) {
 958                 if (list_empty(&dep->req_queued))
 959                         dwc3_prepare_trbs(dep, start_new);
 960
 961                 /* req points to the first request which will be sent */
 962                 req = next_request(&dep->req_queued);
 963         } else {
 964                 dwc3_prepare_trbs(dep, start_new);
 965
 966                 /*
 967                  * req points to the first request where HWO changed from 0 to 1
 968                  */
 969                 req = next_request(&dep->req_queued);
 970         }
 971         if (!req) {
 972                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 973                 return 0;
 974         }
 975
 976         memset(&params, 0, sizeof(params));
 977         params.param0 = upper_32_bits(req->trb_dma);
 978         params.param1 = lower_32_bits(req->trb_dma);
 979
 980         if (start_new)
 981                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 982         else
 983                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 984
 985         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 986         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 987         if (ret < 0) {
 988                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 989
 990                 /*
 991                  * FIXME we need to iterate over the list of requests
 992                  * here and stop, unmap, free and del each of the linked
 993                  * requests instead of what we do now.
 994                  */
 995                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 996                                 req->direction);
 997                 list_del(&req->list);
 998                 return ret;
 999         }
1000
1001         dep->flags |= DWC3_EP_BUSY;
1002
1003         if (start_new) {
1004                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1005                                 dep->number);
1006                 WARN_ON_ONCE(!dep->resource_index);
1007         }
1008
1009         return 0;
1010 }
1011
1012 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1013                 struct dwc3_ep *dep, u32 cur_uf)
1014 {
1015         u32 uf;
1016
1017         if (list_empty(&dep->request_list)) {
1018                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1019                         dep->name);
1020                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1021                 return;
1022         }
1023
1024         /* 4 micro frames in the future */
1025         uf = cur_uf + dep->interval * 4;
1026
1027         __dwc3_gadget_kick_transfer(dep, uf, 1);
1028 }
1029
1030 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1031                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1032 {
1033         u32 cur_uf, mask;
1034
1035         mask = ~(dep->interval - 1);
1036         cur_uf = event->parameters & mask;
1037
1038         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1039 }
1040
1041 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1042 {
1043         struct dwc3             *dwc = dep->dwc;
1044         int                     ret;
1045
1046         req->request.actual     = 0;
1047         req->request.status     = -EINPROGRESS;
1048         req->direction          = dep->direction;
1049         req->epnum              = dep->number;
1050
1051         /*
1052          * We only add to our list of requests now and
1053          * start consuming the list once we get XferNotReady
1054          * IRQ.
1055          *
1056          * That way, we avoid doing anything that we don't need
1057          * to do now and defer it until the point we receive a
1058          * particular token from the Host side.
1059          *
1060          * This will also avoid Host cancelling URBs due to too
1061          * many NAKs.
1062          */
1063         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1064                         dep->direction);
1065         if (ret)
1066                 return ret;
1067
1068         list_add_tail(&req->list, &dep->request_list);
1069
1070         /*
1071          * There are a few special cases:
1072          *
1073          * 1. XferNotReady with empty list of requests. We need to kick the
1074          *    transfer here in that situation, otherwise we will be NAKing
1075          *    forever. If we get XferNotReady before gadget driver has a
1076          *    chance to queue a request, we will ACK the IRQ but won't be
1077          *    able to receive the data until the next request is queued.
1078          *    The following code is handling exactly that.
1079          *
1080          */
1081         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1082                 /*
1083                  * If xfernotready is already elapsed and it is a case
1084                  * of isoc transfer, then issue END TRANSFER, so that
1085                  * you can receive xfernotready again and can have
1086                  * notion of current microframe.
1087                  */
1088                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1089                         if (list_empty(&dep->req_queued)) {
1090                                 dwc3_stop_active_transfer(dwc, dep->number);
1091                                 dep->flags = DWC3_EP_ENABLED;
1092                         }
1093                         return 0;
1094                 }
1095
1096                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1097                 if (ret && ret != -EBUSY)
1098                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1099                                         dep->name);
1100                 return ret;
1101         }
1102
1103         /*
1104          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1105          *    kick the transfer here after queuing a request, otherwise the
1106          *    core may not see the modified TRB(s).
1107          */
1108         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1109                         (dep->flags & DWC3_EP_BUSY) &&
1110                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1111                 WARN_ON_ONCE(!dep->resource_index);
1112                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1113                                 false);
1114                 if (ret && ret != -EBUSY)
1115                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1116                                         dep->name);
1117                 return ret;
1118         }
1119
1120         return 0;
1121 }
1122
1123 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1124         gfp_t gfp_flags)
1125 {
1126         struct dwc3_request             *req = to_dwc3_request(request);
1127         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1128         struct dwc3                     *dwc = dep->dwc;
1129
1130         unsigned long                   flags;
1131
1132         int                             ret;
1133
1134         if (!dep->endpoint.desc) {
1135                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1136                                 request, ep->name);
1137                 return -ESHUTDOWN;
1138         }
1139
1140         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1141                         request, ep->name, request->length);
1142
1143         spin_lock_irqsave(&dwc->lock, flags);
1144         ret = __dwc3_gadget_ep_queue(dep, req);
1145         spin_unlock_irqrestore(&dwc->lock, flags);
1146
1147         return ret;
1148 }
1149
1150 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1151                 struct usb_request *request)
1152 {
1153         struct dwc3_request             *req = to_dwc3_request(request);
1154         struct dwc3_request             *r = NULL;
1155
1156         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1157         struct dwc3                     *dwc = dep->dwc;
1158
1159         unsigned long                   flags;
1160         int                             ret = 0;
1161
1162         spin_lock_irqsave(&dwc->lock, flags);
1163
1164         list_for_each_entry(r, &dep->request_list, list) {
1165                 if (r == req)
1166                         break;
1167         }
1168
1169         if (r != req) {
1170                 list_for_each_entry(r, &dep->req_queued, list) {
1171                         if (r == req)
1172                                 break;
1173                 }
1174                 if (r == req) {
1175                         /* wait until it is processed */
1176                         dwc3_stop_active_transfer(dwc, dep->number);
1177                         goto out1;
1178                 }
1179                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1180                                 request, ep->name);
1181                 ret = -EINVAL;
1182                 goto out0;
1183         }
1184
1185 out1:
1186         /* giveback the request */
1187         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1188
1189 out0:
1190         spin_unlock_irqrestore(&dwc->lock, flags);
1191
1192         return ret;
1193 }
1194
1195 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1196 {
1197         struct dwc3_gadget_ep_cmd_params        params;
1198         struct dwc3                             *dwc = dep->dwc;
1199         int                                     ret;
1200
1201         memset(&params, 0x00, sizeof(params));
1202
1203         if (value) {
1204                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1205                         DWC3_DEPCMD_SETSTALL, &params);
1206                 if (ret)
1207                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1208                                         value ? "set" : "clear",
1209                                         dep->name);
1210                 else
1211                         dep->flags |= DWC3_EP_STALL;
1212         } else {
1213                 if (dep->flags & DWC3_EP_WEDGE)
1214                         return 0;
1215
1216                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1217                         DWC3_DEPCMD_CLEARSTALL, &params);
1218                 if (ret)
1219                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1220                                         value ? "set" : "clear",
1221                                         dep->name);
1222                 else
1223                         dep->flags &= ~DWC3_EP_STALL;
1224         }
1225
1226         return ret;
1227 }
1228
1229 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1230 {
1231         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1232         struct dwc3                     *dwc = dep->dwc;
1233
1234         unsigned long                   flags;
1235
1236         int                             ret;
1237
1238         spin_lock_irqsave(&dwc->lock, flags);
1239
1240         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1241                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1242                 ret = -EINVAL;
1243                 goto out;
1244         }
1245
1246         ret = __dwc3_gadget_ep_set_halt(dep, value);
1247 out:
1248         spin_unlock_irqrestore(&dwc->lock, flags);
1249
1250         return ret;
1251 }
1252
1253 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1254 {
1255         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1256         struct dwc3                     *dwc = dep->dwc;
1257         unsigned long                   flags;
1258
1259         spin_lock_irqsave(&dwc->lock, flags);
1260         dep->flags |= DWC3_EP_WEDGE;
1261         spin_unlock_irqrestore(&dwc->lock, flags);
1262
1263         if (dep->number == 0 || dep->number == 1)
1264                 return dwc3_gadget_ep0_set_halt(ep, 1);
1265         else
1266                 return dwc3_gadget_ep_set_halt(ep, 1);
1267 }
1268
1269 /* -------------------------------------------------------------------------- */
1270
1271 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1272         .bLength        = USB_DT_ENDPOINT_SIZE,
1273         .bDescriptorType = USB_DT_ENDPOINT,
1274         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1275 };
1276
1277 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1278         .enable         = dwc3_gadget_ep0_enable,
1279         .disable        = dwc3_gadget_ep0_disable,
1280         .alloc_request  = dwc3_gadget_ep_alloc_request,
1281         .free_request   = dwc3_gadget_ep_free_request,
1282         .queue          = dwc3_gadget_ep0_queue,
1283         .dequeue        = dwc3_gadget_ep_dequeue,
1284         .set_halt       = dwc3_gadget_ep0_set_halt,
1285         .set_wedge      = dwc3_gadget_ep_set_wedge,
1286 };
1287
1288 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1289         .enable         = dwc3_gadget_ep_enable,
1290         .disable        = dwc3_gadget_ep_disable,
1291         .alloc_request  = dwc3_gadget_ep_alloc_request,
1292         .free_request   = dwc3_gadget_ep_free_request,
1293         .queue          = dwc3_gadget_ep_queue,
1294         .dequeue        = dwc3_gadget_ep_dequeue,
1295         .set_halt       = dwc3_gadget_ep_set_halt,
1296         .set_wedge      = dwc3_gadget_ep_set_wedge,
1297 };
1298
1299 /* -------------------------------------------------------------------------- */
1300
1301 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1302 {
1303         struct dwc3             *dwc = gadget_to_dwc(g);
1304         u32                     reg;
1305
1306         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1307         return DWC3_DSTS_SOFFN(reg);
1308 }
1309
1310 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1311 {
1312         struct dwc3             *dwc = gadget_to_dwc(g);
1313
1314         unsigned long           timeout;
1315         unsigned long           flags;
1316
1317         u32                     reg;
1318
1319         int                     ret = 0;
1320
1321         u8                      link_state;
1322         u8                      speed;
1323
1324         spin_lock_irqsave(&dwc->lock, flags);
1325
1326         /*
1327          * According to the Databook Remote wakeup request should
1328          * be issued only when the device is in early suspend state.
1329          *
1330          * We can check that via USB Link State bits in DSTS register.
1331          */
1332         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1333
1334         speed = reg & DWC3_DSTS_CONNECTSPD;
1335         if (speed == DWC3_DSTS_SUPERSPEED) {
1336                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1337                 ret = -EINVAL;
1338                 goto out;
1339         }
1340
1341         link_state = DWC3_DSTS_USBLNKST(reg);
1342
1343         switch (link_state) {
1344         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1345         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1346                 break;
1347         default:
1348                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1349                                 link_state);
1350                 ret = -EINVAL;
1351                 goto out;
1352         }
1353
1354         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1355         if (ret < 0) {
1356                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1357                 goto out;
1358         }
1359
1360         /* Recent versions do this automatically */
1361         if (dwc->revision < DWC3_REVISION_194A) {
1362                 /* write zeroes to Link Change Request */
1363                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1364                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1365                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1366         }
1367
1368         /* poll until Link State changes to ON */
1369         timeout = jiffies + msecs_to_jiffies(100);
1370
1371         while (!time_after(jiffies, timeout)) {
1372                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1373
1374                 /* in HS, means ON */
1375                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1376                         break;
1377         }
1378
1379         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1380                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1381                 ret = -EINVAL;
1382         }
1383
1384 out:
1385         spin_unlock_irqrestore(&dwc->lock, flags);
1386
1387         return ret;
1388 }
1389
1390 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1391                 int is_selfpowered)
1392 {
1393         struct dwc3             *dwc = gadget_to_dwc(g);
1394         unsigned long           flags;
1395
1396         spin_lock_irqsave(&dwc->lock, flags);
1397         dwc->is_selfpowered = !!is_selfpowered;
1398         spin_unlock_irqrestore(&dwc->lock, flags);
1399
1400         return 0;
1401 }
1402
1403 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1404 {
1405         u32                     reg;
1406         u32                     timeout = 500;
1407
1408         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1409         if (is_on) {
1410                 if (dwc->revision <= DWC3_REVISION_187A) {
1411                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1412                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1413                 }
1414
1415                 if (dwc->revision >= DWC3_REVISION_194A)
1416                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1417                 reg |= DWC3_DCTL_RUN_STOP;
1418         } else {
1419                 reg &= ~DWC3_DCTL_RUN_STOP;
1420         }
1421
1422         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1423
1424         do {
1425                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1426                 if (is_on) {
1427                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1428                                 break;
1429                 } else {
1430                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1431                                 break;
1432                 }
1433                 timeout--;
1434                 if (!timeout)
1435                         return -ETIMEDOUT;
1436                 udelay(1);
1437         } while (1);
1438
1439         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1440                         dwc->gadget_driver
1441                         ? dwc->gadget_driver->function : "no-function",
1442                         is_on ? "connect" : "disconnect");
1443
1444         return 0;
1445 }
1446
1447 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1448 {
1449         struct dwc3             *dwc = gadget_to_dwc(g);
1450         unsigned long           flags;
1451         int                     ret;
1452
1453         is_on = !!is_on;
1454
1455         spin_lock_irqsave(&dwc->lock, flags);
1456         ret = dwc3_gadget_run_stop(dwc, is_on);
1457         spin_unlock_irqrestore(&dwc->lock, flags);
1458
1459         return ret;
1460 }
1461
1462 static int dwc3_gadget_start(struct usb_gadget *g,
1463                 struct usb_gadget_driver *driver)
1464 {
1465         struct dwc3             *dwc = gadget_to_dwc(g);
1466         struct dwc3_ep          *dep;
1467         unsigned long           flags;
1468         int                     ret = 0;
1469         u32                     reg;
1470
1471         spin_lock_irqsave(&dwc->lock, flags);
1472
1473         if (dwc->gadget_driver) {
1474                 dev_err(dwc->dev, "%s is already bound to %s\n",
1475                                 dwc->gadget.name,
1476                                 dwc->gadget_driver->driver.name);
1477                 ret = -EBUSY;
1478                 goto err0;
1479         }
1480
1481         dwc->gadget_driver      = driver;
1482         dwc->gadget.dev.driver  = &driver->driver;
1483
1484         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1485         reg &= ~(DWC3_DCFG_SPEED_MASK);
1486
1487         /**
1488          * WORKAROUND: DWC3 revision < 2.20a have an issue
1489          * which would cause metastability state on Run/Stop
1490          * bit if we try to force the IP to USB2-only mode.
1491          *
1492          * Because of that, we cannot configure the IP to any
1493          * speed other than the SuperSpeed
1494          *
1495          * Refers to:
1496          *
1497          * STAR#9000525659: Clock Domain Crossing on DCTL in
1498          * USB 2.0 Mode
1499          */
1500         if (dwc->revision < DWC3_REVISION_220A)
1501                 reg |= DWC3_DCFG_SUPERSPEED;
1502         else
1503                 reg |= dwc->maximum_speed;
1504         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1505
1506         dwc->start_config_issued = false;
1507
1508         /* Start with SuperSpeed Default */
1509         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1510
1511         dep = dwc->eps[0];
1512         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1513         if (ret) {
1514                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1515                 goto err0;
1516         }
1517
1518         dep = dwc->eps[1];
1519         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1520         if (ret) {
1521                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1522                 goto err1;
1523         }
1524
1525         /* begin to receive SETUP packets */
1526         dwc->ep0state = EP0_SETUP_PHASE;
1527         dwc3_ep0_out_start(dwc);
1528
1529         spin_unlock_irqrestore(&dwc->lock, flags);
1530
1531         return 0;
1532
1533 err1:
1534         __dwc3_gadget_ep_disable(dwc->eps[0]);
1535
1536 err0:
1537         spin_unlock_irqrestore(&dwc->lock, flags);
1538
1539         return ret;
1540 }
1541
1542 static int dwc3_gadget_stop(struct usb_gadget *g,
1543                 struct usb_gadget_driver *driver)
1544 {
1545         struct dwc3             *dwc = gadget_to_dwc(g);
1546         unsigned long           flags;
1547
1548         spin_lock_irqsave(&dwc->lock, flags);
1549
1550         __dwc3_gadget_ep_disable(dwc->eps[0]);
1551         __dwc3_gadget_ep_disable(dwc->eps[1]);
1552
1553         dwc->gadget_driver      = NULL;
1554         dwc->gadget.dev.driver  = NULL;
1555
1556         spin_unlock_irqrestore(&dwc->lock, flags);
1557
1558         return 0;
1559 }
1560
1561 static const struct usb_gadget_ops dwc3_gadget_ops = {
1562         .get_frame              = dwc3_gadget_get_frame,
1563         .wakeup                 = dwc3_gadget_wakeup,
1564         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1565         .pullup                 = dwc3_gadget_pullup,
1566         .udc_start              = dwc3_gadget_start,
1567         .udc_stop               = dwc3_gadget_stop,
1568 };
1569
1570 /* -------------------------------------------------------------------------- */
1571
1572 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1573 {
1574         struct dwc3_ep                  *dep;
1575         u8                              epnum;
1576
1577         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1578
1579         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1580                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1581                 if (!dep) {
1582                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1583                                         epnum);
1584                         return -ENOMEM;
1585                 }
1586
1587                 dep->dwc = dwc;
1588                 dep->number = epnum;
1589                 dwc->eps[epnum] = dep;
1590
1591                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1592                                 (epnum & 1) ? "in" : "out");
1593                 dep->endpoint.name = dep->name;
1594                 dep->direction = (epnum & 1);
1595
1596                 if (epnum == 0 || epnum == 1) {
1597                         dep->endpoint.maxpacket = 512;
1598                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1599                         if (!epnum)
1600                                 dwc->gadget.ep0 = &dep->endpoint;
1601                 } else {
1602                         int             ret;
1603
1604                         dep->endpoint.maxpacket = 1024;
1605                         dep->endpoint.max_streams = 15;
1606                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1607                         list_add_tail(&dep->endpoint.ep_list,
1608                                         &dwc->gadget.ep_list);
1609
1610                         ret = dwc3_alloc_trb_pool(dep);
1611                         if (ret)
1612                                 return ret;
1613                 }
1614
1615                 INIT_LIST_HEAD(&dep->request_list);
1616                 INIT_LIST_HEAD(&dep->req_queued);
1617         }
1618
1619         return 0;
1620 }
1621
1622 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1623 {
1624         struct dwc3_ep                  *dep;
1625         u8                              epnum;
1626
1627         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1628                 dep = dwc->eps[epnum];
1629                 dwc3_free_trb_pool(dep);
1630
1631                 if (epnum != 0 && epnum != 1)
1632                         list_del(&dep->endpoint.ep_list);
1633
1634                 kfree(dep);
1635         }
1636 }
1637
1638 static void dwc3_gadget_release(struct device *dev)
1639 {
1640         dev_dbg(dev, "%s\n", __func__);
1641 }
1642
1643 /* -------------------------------------------------------------------------- */
1644 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1645                 const struct dwc3_event_depevt *event, int status)
1646 {
1647         struct dwc3_request     *req;
1648         struct dwc3_trb         *trb;
1649         unsigned int            count;
1650         unsigned int            s_pkt = 0;
1651         unsigned int            trb_status;
1652
1653         do {
1654                 req = next_request(&dep->req_queued);
1655                 if (!req) {
1656                         WARN_ON_ONCE(1);
1657                         return 1;
1658                 }
1659
1660                 trb = req->trb;
1661
1662                 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1663                         /*
1664                          * We continue despite the error. There is not much we
1665                          * can do. If we don't clean it up we loop forever. If
1666                          * we skip the TRB then it gets overwritten after a
1667                          * while since we use them in a ring buffer. A BUG()
1668                          * would help. Lets hope that if this occurs, someone
1669                          * fixes the root cause instead of looking away :)
1670                          */
1671                         dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1672                                         dep->name, req->trb);
1673                 count = trb->size & DWC3_TRB_SIZE_MASK;
1674
1675                 if (dep->direction) {
1676                         if (count) {
1677                                 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1678                                 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1679                                         dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1680                                                         dep->name);
1681                                         /*
1682                                          * If missed isoc occurred and there is
1683                                          * no request queued then issue END
1684                                          * TRANSFER, so that core generates
1685                                          * next xfernotready and we will issue
1686                                          * a fresh START TRANSFER.
1687                                          * If there are still queued request
1688                                          * then wait, do not issue either END
1689                                          * or UPDATE TRANSFER, just attach next
1690                                          * request in request_list during
1691                                          * giveback.If any future queued request
1692                                          * is successfully transferred then we
1693                                          * will issue UPDATE TRANSFER for all
1694                                          * request in the request_list.
1695                                          */
1696                                         dep->flags |= DWC3_EP_MISSED_ISOC;
1697                                 } else {
1698                                         dev_err(dwc->dev, "incomplete IN transfer %s\n",
1699                                                         dep->name);
1700                                         status = -ECONNRESET;
1701                                 }
1702                         } else {
1703                                 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1704                         }
1705                 } else {
1706                         if (count && (event->status & DEPEVT_STATUS_SHORT))
1707                                 s_pkt = 1;
1708                 }
1709
1710                 /*
1711                  * We assume here we will always receive the entire data block
1712                  * which we should receive. Meaning, if we program RX to
1713                  * receive 4K but we receive only 2K, we assume that's all we
1714                  * should receive and we simply bounce the request back to the
1715                  * gadget driver for further processing.
1716                  */
1717                 req->request.actual += req->request.length - count;
1718                 dwc3_gadget_giveback(dep, req, status);
1719                 if (s_pkt)
1720                         break;
1721                 if ((event->status & DEPEVT_STATUS_LST) &&
1722                                 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1723                                                 DWC3_TRB_CTRL_HWO)))
1724                         break;
1725                 if ((event->status & DEPEVT_STATUS_IOC) &&
1726                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1727                         break;
1728         } while (1);
1729
1730         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1731                         list_empty(&dep->req_queued)) {
1732                 if (list_empty(&dep->request_list)) {
1733                         /*
1734                          * If there is no entry in request list then do
1735                          * not issue END TRANSFER now. Just set PENDING
1736                          * flag, so that END TRANSFER is issued when an
1737                          * entry is added into request list.
1738                          */
1739                         dep->flags = DWC3_EP_PENDING_REQUEST;
1740                 } else {
1741                         dwc3_stop_active_transfer(dwc, dep->number);
1742                         dep->flags = DWC3_EP_ENABLED;
1743                 }
1744                 return 1;
1745         }
1746
1747         if ((event->status & DEPEVT_STATUS_IOC) &&
1748                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1749                 return 0;
1750         return 1;
1751 }
1752
1753 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1754                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1755                 int start_new)
1756 {
1757         unsigned                status = 0;
1758         int                     clean_busy;
1759
1760         if (event->status & DEPEVT_STATUS_BUSERR)
1761                 status = -ECONNRESET;
1762
1763         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1764         if (clean_busy)
1765                 dep->flags &= ~DWC3_EP_BUSY;
1766
1767         /*
1768          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1769          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1770          */
1771         if (dwc->revision < DWC3_REVISION_183A) {
1772                 u32             reg;
1773                 int             i;
1774
1775                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1776                         dep = dwc->eps[i];
1777
1778                         if (!(dep->flags & DWC3_EP_ENABLED))
1779                                 continue;
1780
1781                         if (!list_empty(&dep->req_queued))
1782                                 return;
1783                 }
1784
1785                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1786                 reg |= dwc->u1u2;
1787                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1788
1789                 dwc->u1u2 = 0;
1790         }
1791 }
1792
1793 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1794                 const struct dwc3_event_depevt *event)
1795 {
1796         struct dwc3_ep          *dep;
1797         u8                      epnum = event->endpoint_number;
1798
1799         dep = dwc->eps[epnum];
1800
1801         if (!(dep->flags & DWC3_EP_ENABLED))
1802                 return;
1803
1804         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1805                         dwc3_ep_event_string(event->endpoint_event));
1806
1807         if (epnum == 0 || epnum == 1) {
1808                 dwc3_ep0_interrupt(dwc, event);
1809                 return;
1810         }
1811
1812         switch (event->endpoint_event) {
1813         case DWC3_DEPEVT_XFERCOMPLETE:
1814                 dep->resource_index = 0;
1815
1816                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1817                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1818                                         dep->name);
1819                         return;
1820                 }
1821
1822                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1823                 break;
1824         case DWC3_DEPEVT_XFERINPROGRESS:
1825                 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1826                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1827                                         dep->name);
1828                         return;
1829                 }
1830
1831                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1832                 break;
1833         case DWC3_DEPEVT_XFERNOTREADY:
1834                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1835                         dwc3_gadget_start_isoc(dwc, dep, event);
1836                 } else {
1837                         int ret;
1838
1839                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1840                                         dep->name, event->status &
1841                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1842                                         ? "Transfer Active"
1843                                         : "Transfer Not Active");
1844
1845                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1846                         if (!ret || ret == -EBUSY)
1847                                 return;
1848
1849                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1850                                         dep->name);
1851                 }
1852
1853                 break;
1854         case DWC3_DEPEVT_STREAMEVT:
1855                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1856                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1857                                         dep->name);
1858                         return;
1859                 }
1860
1861                 switch (event->status) {
1862                 case DEPEVT_STREAMEVT_FOUND:
1863                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1864                                         event->parameters);
1865
1866                         break;
1867                 case DEPEVT_STREAMEVT_NOTFOUND:
1868                         /* FALLTHROUGH */
1869                 default:
1870                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1871                 }
1872                 break;
1873         case DWC3_DEPEVT_RXTXFIFOEVT:
1874                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1875                 break;
1876         case DWC3_DEPEVT_EPCMDCMPLT:
1877                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1878                 break;
1879         }
1880 }
1881
1882 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1883 {
1884         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1885                 spin_unlock(&dwc->lock);
1886                 dwc->gadget_driver->disconnect(&dwc->gadget);
1887                 spin_lock(&dwc->lock);
1888         }
1889 }
1890
1891 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1892 {
1893         struct dwc3_ep *dep;
1894         struct dwc3_gadget_ep_cmd_params params;
1895         u32 cmd;
1896         int ret;
1897
1898         dep = dwc->eps[epnum];
1899
1900         if (!dep->resource_index)
1901                 return;
1902
1903         /*
1904          * NOTICE: We are violating what the Databook says about the
1905          * EndTransfer command. Ideally we would _always_ wait for the
1906          * EndTransfer Command Completion IRQ, but that's causing too
1907          * much trouble synchronizing between us and gadget driver.
1908          *
1909          * We have discussed this with the IP Provider and it was
1910          * suggested to giveback all requests here, but give HW some
1911          * extra time to synchronize with the interconnect. We're using
1912          * an arbitraty 100us delay for that.
1913          *
1914          * Note also that a similar handling was tested by Synopsys
1915          * (thanks a lot Paul) and nothing bad has come out of it.
1916          * In short, what we're doing is:
1917          *
1918          * - Issue EndTransfer WITH CMDIOC bit set
1919          * - Wait 100us
1920          */
1921
1922         cmd = DWC3_DEPCMD_ENDTRANSFER;
1923         cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1924         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1925         memset(&params, 0, sizeof(params));
1926         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1927         WARN_ON_ONCE(ret);
1928         dep->resource_index = 0;
1929         dep->flags &= ~DWC3_EP_BUSY;
1930         udelay(100);
1931 }
1932
1933 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1934 {
1935         u32 epnum;
1936
1937         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1938                 struct dwc3_ep *dep;
1939
1940                 dep = dwc->eps[epnum];
1941                 if (!(dep->flags & DWC3_EP_ENABLED))
1942                         continue;
1943
1944                 dwc3_remove_requests(dwc, dep);
1945         }
1946 }
1947
1948 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1949 {
1950         u32 epnum;
1951
1952         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1953                 struct dwc3_ep *dep;
1954                 struct dwc3_gadget_ep_cmd_params params;
1955                 int ret;
1956
1957                 dep = dwc->eps[epnum];
1958
1959                 if (!(dep->flags & DWC3_EP_STALL))
1960                         continue;
1961
1962                 dep->flags &= ~DWC3_EP_STALL;
1963
1964                 memset(&params, 0, sizeof(params));
1965                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1966                                 DWC3_DEPCMD_CLEARSTALL, &params);
1967                 WARN_ON_ONCE(ret);
1968         }
1969 }
1970
1971 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1972 {
1973         int                     reg;
1974
1975         dev_vdbg(dwc->dev, "%s\n", __func__);
1976
1977         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1978         reg &= ~DWC3_DCTL_INITU1ENA;
1979         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1980
1981         reg &= ~DWC3_DCTL_INITU2ENA;
1982         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1983
1984         dwc3_disconnect_gadget(dwc);
1985         dwc->start_config_issued = false;
1986
1987         dwc->gadget.speed = USB_SPEED_UNKNOWN;
1988         dwc->setup_packet_pending = false;
1989 }
1990
1991 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
1992 {
1993         u32                     reg;
1994
1995         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1996
1997         if (suspend)
1998                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1999         else
2000                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
2001
2002         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
2003 }
2004
2005 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
2006 {
2007         u32                     reg;
2008
2009         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2010
2011         if (suspend)
2012                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
2013         else
2014                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2015
2016         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2017 }
2018
2019 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2020 {
2021         u32                     reg;
2022
2023         dev_vdbg(dwc->dev, "%s\n", __func__);
2024
2025         /*
2026          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2027          * would cause a missing Disconnect Event if there's a
2028          * pending Setup Packet in the FIFO.
2029          *
2030          * There's no suggested workaround on the official Bug
2031          * report, which states that "unless the driver/application
2032          * is doing any special handling of a disconnect event,
2033          * there is no functional issue".
2034          *
2035          * Unfortunately, it turns out that we _do_ some special
2036          * handling of a disconnect event, namely complete all
2037          * pending transfers, notify gadget driver of the
2038          * disconnection, and so on.
2039          *
2040          * Our suggested workaround is to follow the Disconnect
2041          * Event steps here, instead, based on a setup_packet_pending
2042          * flag. Such flag gets set whenever we have a XferNotReady
2043          * event on EP0 and gets cleared on XferComplete for the
2044          * same endpoint.
2045          *
2046          * Refers to:
2047          *
2048          * STAR#9000466709: RTL: Device : Disconnect event not
2049          * generated if setup packet pending in FIFO
2050          */
2051         if (dwc->revision < DWC3_REVISION_188A) {
2052                 if (dwc->setup_packet_pending)
2053                         dwc3_gadget_disconnect_interrupt(dwc);
2054         }
2055
2056         /* after reset -> Default State */
2057         dwc->dev_state = DWC3_DEFAULT_STATE;
2058
2059         /* Recent versions support automatic phy suspend and don't need this */
2060         if (dwc->revision < DWC3_REVISION_194A) {
2061                 /* Resume PHYs */
2062                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2063                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2064         }
2065
2066         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2067                 dwc3_disconnect_gadget(dwc);
2068
2069         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2070         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2071         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2072         dwc->test_mode = false;
2073
2074         dwc3_stop_active_transfers(dwc);
2075         dwc3_clear_stall_all_ep(dwc);
2076         dwc->start_config_issued = false;
2077
2078         /* Reset device address to zero */
2079         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2080         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2081         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2082 }
2083
2084 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2085 {
2086         u32 reg;
2087         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2088
2089         /*
2090          * We change the clock only at SS but I dunno why I would want to do
2091          * this. Maybe it becomes part of the power saving plan.
2092          */
2093
2094         if (speed != DWC3_DSTS_SUPERSPEED)
2095                 return;
2096
2097         /*
2098          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2099          * each time on Connect Done.
2100          */
2101         if (!usb30_clock)
2102                 return;
2103
2104         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2105         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2106         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2107 }
2108
2109 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2110 {
2111         switch (speed) {
2112         case USB_SPEED_SUPER:
2113                 dwc3_gadget_usb2_phy_suspend(dwc, true);
2114                 break;
2115         case USB_SPEED_HIGH:
2116         case USB_SPEED_FULL:
2117         case USB_SPEED_LOW:
2118                 dwc3_gadget_usb3_phy_suspend(dwc, true);
2119                 break;
2120         }
2121 }
2122
2123 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2124 {
2125         struct dwc3_gadget_ep_cmd_params params;
2126         struct dwc3_ep          *dep;
2127         int                     ret;
2128         u32                     reg;
2129         u8                      speed;
2130
2131         dev_vdbg(dwc->dev, "%s\n", __func__);
2132
2133         memset(&params, 0x00, sizeof(params));
2134
2135         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2136         speed = reg & DWC3_DSTS_CONNECTSPD;
2137         dwc->speed = speed;
2138
2139         dwc3_update_ram_clk_sel(dwc, speed);
2140
2141         switch (speed) {
2142         case DWC3_DCFG_SUPERSPEED:
2143                 /*
2144                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2145                  * would cause a missing USB3 Reset event.
2146                  *
2147                  * In such situations, we should force a USB3 Reset
2148                  * event by calling our dwc3_gadget_reset_interrupt()
2149                  * routine.
2150                  *
2151                  * Refers to:
2152                  *
2153                  * STAR#9000483510: RTL: SS : USB3 reset event may
2154                  * not be generated always when the link enters poll
2155                  */
2156                 if (dwc->revision < DWC3_REVISION_190A)
2157                         dwc3_gadget_reset_interrupt(dwc);
2158
2159                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2160                 dwc->gadget.ep0->maxpacket = 512;
2161                 dwc->gadget.speed = USB_SPEED_SUPER;
2162                 break;
2163         case DWC3_DCFG_HIGHSPEED:
2164                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2165                 dwc->gadget.ep0->maxpacket = 64;
2166                 dwc->gadget.speed = USB_SPEED_HIGH;
2167                 break;
2168         case DWC3_DCFG_FULLSPEED2:
2169         case DWC3_DCFG_FULLSPEED1:
2170                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2171                 dwc->gadget.ep0->maxpacket = 64;
2172                 dwc->gadget.speed = USB_SPEED_FULL;
2173                 break;
2174         case DWC3_DCFG_LOWSPEED:
2175                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2176                 dwc->gadget.ep0->maxpacket = 8;
2177                 dwc->gadget.speed = USB_SPEED_LOW;
2178                 break;
2179         }
2180
2181         /* Enable USB2 LPM Capability */
2182
2183         if ((dwc->revision > DWC3_REVISION_194A)
2184                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2185                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2186                 reg |= DWC3_DCFG_LPM_CAP;
2187                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2188
2189                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2190                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2191
2192                 /* TODO: This should be configurable */
2193                 reg |= DWC3_DCTL_HIRD_THRES(28);
2194
2195                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2196         }
2197
2198         /* Recent versions support automatic phy suspend and don't need this */
2199         if (dwc->revision < DWC3_REVISION_194A) {
2200                 /* Suspend unneeded PHY */
2201                 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2202         }
2203
2204         dep = dwc->eps[0];
2205         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2206         if (ret) {
2207                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2208                 return;
2209         }
2210
2211         dep = dwc->eps[1];
2212         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2213         if (ret) {
2214                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2215                 return;
2216         }
2217
2218         /*
2219          * Configure PHY via GUSB3PIPECTLn if required.
2220          *
2221          * Update GTXFIFOSIZn
2222          *
2223          * In both cases reset values should be sufficient.
2224          */
2225 }
2226
2227 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2228 {
2229         dev_vdbg(dwc->dev, "%s\n", __func__);
2230
2231         /*
2232          * TODO take core out of low power mode when that's
2233          * implemented.
2234          */
2235
2236         dwc->gadget_driver->resume(&dwc->gadget);
2237 }
2238
2239 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2240                 unsigned int evtinfo)
2241 {
2242         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2243
2244         /*
2245          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2246          * on the link partner, the USB session might do multiple entry/exit
2247          * of low power states before a transfer takes place.
2248          *
2249          * Due to this problem, we might experience lower throughput. The
2250          * suggested workaround is to disable DCTL[12:9] bits if we're
2251          * transitioning from U1/U2 to U0 and enable those bits again
2252          * after a transfer completes and there are no pending transfers
2253          * on any of the enabled endpoints.
2254          *
2255          * This is the first half of that workaround.
2256          *
2257          * Refers to:
2258          *
2259          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2260          * core send LGO_Ux entering U0
2261          */
2262         if (dwc->revision < DWC3_REVISION_183A) {
2263                 if (next == DWC3_LINK_STATE_U0) {
2264                         u32     u1u2;
2265                         u32     reg;
2266
2267                         switch (dwc->link_state) {
2268                         case DWC3_LINK_STATE_U1:
2269                         case DWC3_LINK_STATE_U2:
2270                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2271                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2272                                                 | DWC3_DCTL_ACCEPTU2ENA
2273                                                 | DWC3_DCTL_INITU1ENA
2274                                                 | DWC3_DCTL_ACCEPTU1ENA);
2275
2276                                 if (!dwc->u1u2)
2277                                         dwc->u1u2 = reg & u1u2;
2278
2279                                 reg &= ~u1u2;
2280
2281                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2282                                 break;
2283                         default:
2284                                 /* do nothing */
2285                                 break;
2286                         }
2287                 }
2288         }
2289
2290         dwc->link_state = next;
2291
2292         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2293 }
2294
2295 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2296                 const struct dwc3_event_devt *event)
2297 {
2298         switch (event->type) {
2299         case DWC3_DEVICE_EVENT_DISCONNECT:
2300                 dwc3_gadget_disconnect_interrupt(dwc);
2301                 break;
2302         case DWC3_DEVICE_EVENT_RESET:
2303                 dwc3_gadget_reset_interrupt(dwc);
2304                 break;
2305         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2306                 dwc3_gadget_conndone_interrupt(dwc);
2307                 break;
2308         case DWC3_DEVICE_EVENT_WAKEUP:
2309                 dwc3_gadget_wakeup_interrupt(dwc);
2310                 break;
2311         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2312                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2313                 break;
2314         case DWC3_DEVICE_EVENT_EOPF:
2315                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2316                 break;
2317         case DWC3_DEVICE_EVENT_SOF:
2318                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2319                 break;
2320         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2321                 dev_vdbg(dwc->dev, "Erratic Error\n");
2322                 break;
2323         case DWC3_DEVICE_EVENT_CMD_CMPL:
2324                 dev_vdbg(dwc->dev, "Command Complete\n");
2325                 break;
2326         case DWC3_DEVICE_EVENT_OVERFLOW:
2327                 dev_vdbg(dwc->dev, "Overflow\n");
2328                 break;
2329         default:
2330                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2331         }
2332 }
2333
2334 static void dwc3_process_event_entry(struct dwc3 *dwc,
2335                 const union dwc3_event *event)
2336 {
2337         /* Endpoint IRQ, handle it and return early */
2338         if (event->type.is_devspec == 0) {
2339                 /* depevt */
2340                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2341         }
2342
2343         switch (event->type.type) {
2344         case DWC3_EVENT_TYPE_DEV:
2345                 dwc3_gadget_interrupt(dwc, &event->devt);
2346                 break;
2347         /* REVISIT what to do with Carkit and I2C events ? */
2348         default:
2349                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2350         }
2351 }
2352
2353 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2354 {
2355         struct dwc3_event_buffer *evt;
2356         int left;
2357         u32 count;
2358
2359         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2360         count &= DWC3_GEVNTCOUNT_MASK;
2361         if (!count)
2362                 return IRQ_NONE;
2363
2364         evt = dwc->ev_buffs[buf];
2365         left = count;
2366
2367         while (left > 0) {
2368                 union dwc3_event event;
2369
2370                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2371
2372                 dwc3_process_event_entry(dwc, &event);
2373                 /*
2374                  * XXX we wrap around correctly to the next entry as almost all
2375                  * entries are 4 bytes in size. There is one entry which has 12
2376                  * bytes which is a regular entry followed by 8 bytes data. ATM
2377                  * I don't know how things are organized if were get next to the
2378                  * a boundary so I worry about that once we try to handle that.
2379                  */
2380                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2381                 left -= 4;
2382
2383                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2384         }
2385
2386         return IRQ_HANDLED;
2387 }
2388
2389 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2390 {
2391         struct dwc3                     *dwc = _dwc;
2392         int                             i;
2393         irqreturn_t                     ret = IRQ_NONE;
2394
2395         spin_lock(&dwc->lock);
2396
2397         for (i = 0; i < dwc->num_event_buffers; i++) {
2398                 irqreturn_t status;
2399
2400                 status = dwc3_process_event_buf(dwc, i);
2401                 if (status == IRQ_HANDLED)
2402                         ret = status;
2403         }
2404
2405         spin_unlock(&dwc->lock);
2406
2407         return ret;
2408 }
2409
2410 /**
2411  * dwc3_gadget_init - Initializes gadget related registers
2412  * @dwc: pointer to our controller context structure
2413  *
2414  * Returns 0 on success otherwise negative errno.
2415  */
2416 int dwc3_gadget_init(struct dwc3 *dwc)
2417 {
2418         u32                                     reg;
2419         int                                     ret;
2420         int                                     irq;
2421
2422         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2423                         &dwc->ctrl_req_addr, GFP_KERNEL);
2424         if (!dwc->ctrl_req) {
2425                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2426                 ret = -ENOMEM;
2427                 goto err0;
2428         }
2429
2430         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2431                         &dwc->ep0_trb_addr, GFP_KERNEL);
2432         if (!dwc->ep0_trb) {
2433                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2434                 ret = -ENOMEM;
2435                 goto err1;
2436         }
2437
2438         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2439         if (!dwc->setup_buf) {
2440                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2441                 ret = -ENOMEM;
2442                 goto err2;
2443         }
2444
2445         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2446                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2447                         GFP_KERNEL);
2448         if (!dwc->ep0_bounce) {
2449                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2450                 ret = -ENOMEM;
2451                 goto err3;
2452         }
2453
2454         dev_set_name(&dwc->gadget.dev, "gadget");
2455
2456         dwc->gadget.ops                 = &dwc3_gadget_ops;
2457         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2458         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2459         dwc->gadget.dev.parent          = dwc->dev;
2460         dwc->gadget.sg_supported        = true;
2461
2462         dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2463
2464         dwc->gadget.dev.dma_parms       = dwc->dev->dma_parms;
2465         dwc->gadget.dev.dma_mask        = dwc->dev->dma_mask;
2466         dwc->gadget.dev.release         = dwc3_gadget_release;
2467         dwc->gadget.name                = "dwc3-gadget";
2468
2469         /*
2470          * REVISIT: Here we should clear all pending IRQs to be
2471          * sure we're starting from a well known location.
2472          */
2473
2474         ret = dwc3_gadget_init_endpoints(dwc);
2475         if (ret)
2476                 goto err4;
2477
2478         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2479
2480         ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2481                         "dwc3", dwc);
2482         if (ret) {
2483                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2484                                 irq, ret);
2485                 goto err5;
2486         }
2487
2488         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2489         reg |= DWC3_DCFG_LPM_CAP;
2490         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2491
2492         /* Enable all but Start and End of Frame IRQs */
2493         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2494                         DWC3_DEVTEN_EVNTOVERFLOWEN |
2495                         DWC3_DEVTEN_CMDCMPLTEN |
2496                         DWC3_DEVTEN_ERRTICERREN |
2497                         DWC3_DEVTEN_WKUPEVTEN |
2498                         DWC3_DEVTEN_ULSTCNGEN |
2499                         DWC3_DEVTEN_CONNECTDONEEN |
2500                         DWC3_DEVTEN_USBRSTEN |
2501                         DWC3_DEVTEN_DISCONNEVTEN);
2502         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2503
2504         /* automatic phy suspend only on recent versions */
2505         if (dwc->revision >= DWC3_REVISION_194A) {
2506                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2507                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2508         }
2509
2510         ret = device_register(&dwc->gadget.dev);
2511         if (ret) {
2512                 dev_err(dwc->dev, "failed to register gadget device\n");
2513                 put_device(&dwc->gadget.dev);
2514                 goto err6;
2515         }
2516
2517         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2518         if (ret) {
2519                 dev_err(dwc->dev, "failed to register udc\n");
2520                 goto err7;
2521         }
2522
2523         return 0;
2524
2525 err7:
2526         device_unregister(&dwc->gadget.dev);
2527
2528 err6:
2529         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2530         free_irq(irq, dwc);
2531
2532 err5:
2533         dwc3_gadget_free_endpoints(dwc);
2534
2535 err4:
2536         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2537                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2538
2539 err3:
2540         kfree(dwc->setup_buf);
2541
2542 err2:
2543         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2544                         dwc->ep0_trb, dwc->ep0_trb_addr);
2545
2546 err1:
2547         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2548                         dwc->ctrl_req, dwc->ctrl_req_addr);
2549
2550 err0:
2551         return ret;
2552 }
2553
2554 void dwc3_gadget_exit(struct dwc3 *dwc)
2555 {
2556         int                     irq;
2557
2558         usb_del_gadget_udc(&dwc->gadget);
2559         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2560
2561         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2562         free_irq(irq, dwc);
2563
2564         dwc3_gadget_free_endpoints(dwc);
2565
2566         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2567                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2568
2569         kfree(dwc->setup_buf);
2570
2571         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2572                         dwc->ep0_trb, dwc->ep0_trb_addr);
2573
2574         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2575                         dwc->ctrl_req, dwc->ctrl_req_addr);
2576
2577         device_unregister(&dwc->gadget.dev);
2578 }