2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
167 * Unfortunately, due to many variables that's not always the case.
169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
171 int last_fifo_depth = 0;
177 if (!dwc->needs_fifo_resize)
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
183 /* MDWIDTH is represented in bits, we need it in bytes */
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
198 if (!(dep->flags & DWC3_EP_ENABLED))
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
221 fifo_size |= (last_fifo_depth << 16);
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
228 last_fifo_depth += (fifo_size & 0xffff);
234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
237 struct dwc3 *dwc = dep->dwc;
238 unsigned int unmap_after_complete = false;
246 * Skip LINK TRB. We can't use req->trb and check for
247 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
248 * just completed (not the LINK TRB).
250 if (((dep->busy_slot & DWC3_TRB_MASK) ==
252 usb_endpoint_xfer_isoc(dep->endpoint.desc))
254 } while(++i < req->request.num_mapped_sgs);
257 list_del(&req->list);
260 if (req->request.status == -EINPROGRESS)
261 req->request.status = status;
264 * NOTICE we don't want to unmap before calling ->complete() if we're
265 * dealing with a bounced ep0 request. If we unmap it here, we would end
266 * up overwritting the contents of req->buf and this could confuse the
269 if (dwc->ep0_bounced && dep->number <= 1) {
270 dwc->ep0_bounced = false;
271 unmap_after_complete = true;
273 usb_gadget_unmap_request(&dwc->gadget,
274 &req->request, req->direction);
277 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
278 req, dep->name, req->request.actual,
279 req->request.length, status);
280 trace_dwc3_gadget_giveback(req);
282 spin_unlock(&dwc->lock);
283 usb_gadget_giveback_request(&dep->endpoint, &req->request);
284 spin_lock(&dwc->lock);
286 if (unmap_after_complete)
287 usb_gadget_unmap_request(&dwc->gadget,
288 &req->request, req->direction);
291 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
296 trace_dwc3_gadget_generic_cmd(cmd, param);
298 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
299 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
302 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
303 if (!(reg & DWC3_DGCMD_CMDACT)) {
304 dwc3_trace(trace_dwc3_gadget,
305 "Command Complete --> %d",
306 DWC3_DGCMD_STATUS(reg));
307 if (DWC3_DGCMD_STATUS(reg))
313 * We can't sleep here, because it's also called from
318 dwc3_trace(trace_dwc3_gadget,
319 "Command Timed Out");
326 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
327 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
329 struct dwc3_ep *dep = dwc->eps[ep];
333 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
335 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
336 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
337 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
339 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
341 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
342 if (!(reg & DWC3_DEPCMD_CMDACT)) {
343 dwc3_trace(trace_dwc3_gadget,
344 "Command Complete --> %d",
345 DWC3_DEPCMD_STATUS(reg));
346 if (DWC3_DEPCMD_STATUS(reg))
352 * We can't sleep here, because it is also called from
357 dwc3_trace(trace_dwc3_gadget,
358 "Command Timed Out");
366 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
367 struct dwc3_trb *trb)
369 u32 offset = (char *) trb - (char *) dep->trb_pool;
371 return dep->trb_pool_dma + offset;
374 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
376 struct dwc3 *dwc = dep->dwc;
381 dep->trb_pool = dma_alloc_coherent(dwc->dev,
382 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
383 &dep->trb_pool_dma, GFP_KERNEL);
384 if (!dep->trb_pool) {
385 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
393 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
395 struct dwc3 *dwc = dep->dwc;
397 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
398 dep->trb_pool, dep->trb_pool_dma);
400 dep->trb_pool = NULL;
401 dep->trb_pool_dma = 0;
404 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
407 * dwc3_gadget_start_config - Configure EP resources
408 * @dwc: pointer to our controller context structure
409 * @dep: endpoint that is being enabled
411 * The assignment of transfer resources cannot perfectly follow the
412 * data book due to the fact that the controller driver does not have
413 * all knowledge of the configuration in advance. It is given this
414 * information piecemeal by the composite gadget framework after every
415 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
416 * programming model in this scenario can cause errors. For two
419 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
420 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
421 * multiple interfaces.
423 * 2) The databook does not mention doing more DEPXFERCFG for new
424 * endpoint on alt setting (8.1.6).
426 * The following simplified method is used instead:
428 * All hardware endpoints can be assigned a transfer resource and this
429 * setting will stay persistent until either a core reset or
430 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
431 * do DEPXFERCFG for every hardware endpoint as well. We are
432 * guaranteed that there are as many transfer resources as endpoints.
434 * This function is called for each endpoint when it is being enabled
435 * but is triggered only when called for EP0-out, which always happens
436 * first, and which should only happen in one of the above conditions.
438 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
440 struct dwc3_gadget_ep_cmd_params params;
448 memset(¶ms, 0x00, sizeof(params));
449 cmd = DWC3_DEPCMD_DEPSTARTCFG;
451 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
455 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
456 struct dwc3_ep *dep = dwc->eps[i];
461 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
469 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
470 const struct usb_endpoint_descriptor *desc,
471 const struct usb_ss_ep_comp_descriptor *comp_desc,
472 bool ignore, bool restore)
474 struct dwc3_gadget_ep_cmd_params params;
476 memset(¶ms, 0x00, sizeof(params));
478 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
479 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
481 /* Burst size is only needed in SuperSpeed mode */
482 if (dwc->gadget.speed == USB_SPEED_SUPER) {
483 u32 burst = dep->endpoint.maxburst - 1;
485 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
489 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
492 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
493 params.param2 |= dep->saved_state;
496 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
497 | DWC3_DEPCFG_XFER_NOT_READY_EN;
499 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
500 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
501 | DWC3_DEPCFG_STREAM_EVENT_EN;
502 dep->stream_capable = true;
505 if (!usb_endpoint_xfer_control(desc))
506 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
509 * We are doing 1:1 mapping for endpoints, meaning
510 * Physical Endpoints 2 maps to Logical Endpoint 2 and
511 * so on. We consider the direction bit as part of the physical
512 * endpoint number. So USB endpoint 0x81 is 0x03.
514 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
517 * We must use the lower 16 TX FIFOs even though
521 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
523 if (desc->bInterval) {
524 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
525 dep->interval = 1 << (desc->bInterval - 1);
528 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
529 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
532 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
534 struct dwc3_gadget_ep_cmd_params params;
536 memset(¶ms, 0x00, sizeof(params));
538 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
540 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
541 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
545 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
546 * @dep: endpoint to be initialized
547 * @desc: USB Endpoint Descriptor
549 * Caller should take care of locking
551 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
552 const struct usb_endpoint_descriptor *desc,
553 const struct usb_ss_ep_comp_descriptor *comp_desc,
554 bool ignore, bool restore)
556 struct dwc3 *dwc = dep->dwc;
560 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
562 if (!(dep->flags & DWC3_EP_ENABLED)) {
563 ret = dwc3_gadget_start_config(dwc, dep);
568 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
573 if (!(dep->flags & DWC3_EP_ENABLED)) {
574 struct dwc3_trb *trb_st_hw;
575 struct dwc3_trb *trb_link;
577 dep->endpoint.desc = desc;
578 dep->comp_desc = comp_desc;
579 dep->type = usb_endpoint_type(desc);
580 dep->flags |= DWC3_EP_ENABLED;
582 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
583 reg |= DWC3_DALEPENA_EP(dep->number);
584 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
586 if (!usb_endpoint_xfer_isoc(desc))
589 /* Link TRB for ISOC. The HWO bit is never reset */
590 trb_st_hw = &dep->trb_pool[0];
592 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
593 memset(trb_link, 0, sizeof(*trb_link));
595 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
596 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
597 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
598 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
601 switch (usb_endpoint_type(desc)) {
602 case USB_ENDPOINT_XFER_CONTROL:
603 strlcat(dep->name, "-control", sizeof(dep->name));
605 case USB_ENDPOINT_XFER_ISOC:
606 strlcat(dep->name, "-isoc", sizeof(dep->name));
608 case USB_ENDPOINT_XFER_BULK:
609 strlcat(dep->name, "-bulk", sizeof(dep->name));
611 case USB_ENDPOINT_XFER_INT:
612 strlcat(dep->name, "-int", sizeof(dep->name));
615 dev_err(dwc->dev, "invalid endpoint transfer type\n");
621 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
622 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
624 struct dwc3_request *req;
626 if (!list_empty(&dep->req_queued)) {
627 dwc3_stop_active_transfer(dwc, dep->number, true);
629 /* - giveback all requests to gadget driver */
630 while (!list_empty(&dep->req_queued)) {
631 req = next_request(&dep->req_queued);
633 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
637 while (!list_empty(&dep->request_list)) {
638 req = next_request(&dep->request_list);
640 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
645 * __dwc3_gadget_ep_disable - Disables a HW endpoint
646 * @dep: the endpoint to disable
648 * This function also removes requests which are currently processed ny the
649 * hardware and those which are not yet scheduled.
650 * Caller should take care of locking.
652 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
654 struct dwc3 *dwc = dep->dwc;
657 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
659 dwc3_remove_requests(dwc, dep);
661 /* make sure HW endpoint isn't stalled */
662 if (dep->flags & DWC3_EP_STALL)
663 __dwc3_gadget_ep_set_halt(dep, 0, false);
665 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
666 reg &= ~DWC3_DALEPENA_EP(dep->number);
667 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
669 dep->stream_capable = false;
670 dep->endpoint.desc = NULL;
671 dep->comp_desc = NULL;
675 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
677 (dep->number & 1) ? "in" : "out");
682 /* -------------------------------------------------------------------------- */
684 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
685 const struct usb_endpoint_descriptor *desc)
690 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
695 /* -------------------------------------------------------------------------- */
697 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
698 const struct usb_endpoint_descriptor *desc)
705 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
706 pr_debug("dwc3: invalid parameters\n");
710 if (!desc->wMaxPacketSize) {
711 pr_debug("dwc3: missing wMaxPacketSize\n");
715 dep = to_dwc3_ep(ep);
718 if (dep->flags & DWC3_EP_ENABLED) {
719 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
724 spin_lock_irqsave(&dwc->lock, flags);
725 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
726 spin_unlock_irqrestore(&dwc->lock, flags);
731 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
739 pr_debug("dwc3: invalid parameters\n");
743 dep = to_dwc3_ep(ep);
746 if (!(dep->flags & DWC3_EP_ENABLED)) {
747 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
752 spin_lock_irqsave(&dwc->lock, flags);
753 ret = __dwc3_gadget_ep_disable(dep);
754 spin_unlock_irqrestore(&dwc->lock, flags);
759 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
762 struct dwc3_request *req;
763 struct dwc3_ep *dep = to_dwc3_ep(ep);
765 req = kzalloc(sizeof(*req), gfp_flags);
769 req->epnum = dep->number;
772 trace_dwc3_alloc_request(req);
774 return &req->request;
777 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
778 struct usb_request *request)
780 struct dwc3_request *req = to_dwc3_request(request);
782 trace_dwc3_free_request(req);
787 * dwc3_prepare_one_trb - setup one TRB from one request
788 * @dep: endpoint for which this request is prepared
789 * @req: dwc3_request pointer
791 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
792 struct dwc3_request *req, dma_addr_t dma,
793 unsigned length, unsigned last, unsigned chain, unsigned node)
795 struct dwc3_trb *trb;
797 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
798 dep->name, req, (unsigned long long) dma,
799 length, last ? " last" : "",
800 chain ? " chain" : "");
803 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
806 dwc3_gadget_move_request_queued(req);
808 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
809 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
813 /* Skip the LINK-TRB on ISOC */
814 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
815 usb_endpoint_xfer_isoc(dep->endpoint.desc))
818 trb->size = DWC3_TRB_SIZE_LENGTH(length);
819 trb->bpl = lower_32_bits(dma);
820 trb->bph = upper_32_bits(dma);
822 switch (usb_endpoint_type(dep->endpoint.desc)) {
823 case USB_ENDPOINT_XFER_CONTROL:
824 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
827 case USB_ENDPOINT_XFER_ISOC:
829 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
831 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
834 case USB_ENDPOINT_XFER_BULK:
835 case USB_ENDPOINT_XFER_INT:
836 trb->ctrl = DWC3_TRBCTL_NORMAL;
840 * This is only possible with faulty memory because we
841 * checked it already :)
846 if (!req->request.no_interrupt && !chain)
847 trb->ctrl |= DWC3_TRB_CTRL_IOC;
849 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
850 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
851 trb->ctrl |= DWC3_TRB_CTRL_CSP;
853 trb->ctrl |= DWC3_TRB_CTRL_LST;
857 trb->ctrl |= DWC3_TRB_CTRL_CHN;
859 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
860 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
862 trb->ctrl |= DWC3_TRB_CTRL_HWO;
864 trace_dwc3_prepare_trb(dep, trb);
868 * dwc3_prepare_trbs - setup TRBs from requests
869 * @dep: endpoint for which requests are being prepared
870 * @starting: true if the endpoint is idle and no requests are queued.
872 * The function goes through the requests list and sets up TRBs for the
873 * transfers. The function returns once there are no more TRBs available or
874 * it runs out of requests.
876 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
878 struct dwc3_request *req, *n;
881 unsigned int last_one = 0;
883 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
885 /* the first request must not be queued */
886 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
888 /* Can't wrap around on a non-isoc EP since there's no link TRB */
889 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
890 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
896 * If busy & slot are equal than it is either full or empty. If we are
897 * starting to process requests then we are empty. Otherwise we are
898 * full and don't do anything
903 trbs_left = DWC3_TRB_NUM;
905 * In case we start from scratch, we queue the ISOC requests
906 * starting from slot 1. This is done because we use ring
907 * buffer and have no LST bit to stop us. Instead, we place
908 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
909 * after the first request so we start at slot 1 and have
910 * 7 requests proceed before we hit the first IOC.
911 * Other transfer types don't use the ring buffer and are
912 * processed from the first TRB until the last one. Since we
913 * don't wrap around we have to start at the beginning.
915 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
924 /* The last TRB is a link TRB, not used for xfer */
925 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
928 list_for_each_entry_safe(req, n, &dep->request_list, list) {
933 if (req->request.num_mapped_sgs > 0) {
934 struct usb_request *request = &req->request;
935 struct scatterlist *sg = request->sg;
936 struct scatterlist *s;
939 for_each_sg(sg, s, request->num_mapped_sgs, i) {
940 unsigned chain = true;
942 length = sg_dma_len(s);
943 dma = sg_dma_address(s);
945 if (i == (request->num_mapped_sgs - 1) ||
947 if (list_empty(&dep->request_list))
959 dwc3_prepare_one_trb(dep, req, dma, length,
969 dma = req->request.dma;
970 length = req->request.length;
976 /* Is this the last request? */
977 if (list_is_last(&req->list, &dep->request_list))
980 dwc3_prepare_one_trb(dep, req, dma, length,
989 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
992 struct dwc3_gadget_ep_cmd_params params;
993 struct dwc3_request *req;
994 struct dwc3 *dwc = dep->dwc;
998 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
999 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
1004 * If we are getting here after a short-out-packet we don't enqueue any
1005 * new requests as we try to set the IOC bit only on the last request.
1008 if (list_empty(&dep->req_queued))
1009 dwc3_prepare_trbs(dep, start_new);
1011 /* req points to the first request which will be sent */
1012 req = next_request(&dep->req_queued);
1014 dwc3_prepare_trbs(dep, start_new);
1017 * req points to the first request where HWO changed from 0 to 1
1019 req = next_request(&dep->req_queued);
1022 dep->flags |= DWC3_EP_PENDING_REQUEST;
1026 memset(¶ms, 0, sizeof(params));
1029 params.param0 = upper_32_bits(req->trb_dma);
1030 params.param1 = lower_32_bits(req->trb_dma);
1031 cmd = DWC3_DEPCMD_STARTTRANSFER;
1033 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1036 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1037 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1039 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1042 * FIXME we need to iterate over the list of requests
1043 * here and stop, unmap, free and del each of the linked
1044 * requests instead of what we do now.
1046 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1048 list_del(&req->list);
1052 dep->flags |= DWC3_EP_BUSY;
1055 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1057 WARN_ON_ONCE(!dep->resource_index);
1063 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1064 struct dwc3_ep *dep, u32 cur_uf)
1068 if (list_empty(&dep->request_list)) {
1069 dwc3_trace(trace_dwc3_gadget,
1070 "ISOC ep %s run out for requests",
1072 dep->flags |= DWC3_EP_PENDING_REQUEST;
1076 /* 4 micro frames in the future */
1077 uf = cur_uf + dep->interval * 4;
1079 __dwc3_gadget_kick_transfer(dep, uf, 1);
1082 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1083 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1087 mask = ~(dep->interval - 1);
1088 cur_uf = event->parameters & mask;
1090 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1093 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1095 struct dwc3 *dwc = dep->dwc;
1098 req->request.actual = 0;
1099 req->request.status = -EINPROGRESS;
1100 req->direction = dep->direction;
1101 req->epnum = dep->number;
1103 trace_dwc3_ep_queue(req);
1106 * We only add to our list of requests now and
1107 * start consuming the list once we get XferNotReady
1110 * That way, we avoid doing anything that we don't need
1111 * to do now and defer it until the point we receive a
1112 * particular token from the Host side.
1114 * This will also avoid Host cancelling URBs due to too
1117 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1122 list_add_tail(&req->list, &dep->request_list);
1125 * If there are no pending requests and the endpoint isn't already
1126 * busy, we will just start the request straight away.
1128 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1129 * little bit faster.
1131 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1132 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1133 !(dep->flags & DWC3_EP_BUSY)) {
1134 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1139 * There are a few special cases:
1141 * 1. XferNotReady with empty list of requests. We need to kick the
1142 * transfer here in that situation, otherwise we will be NAKing
1143 * forever. If we get XferNotReady before gadget driver has a
1144 * chance to queue a request, we will ACK the IRQ but won't be
1145 * able to receive the data until the next request is queued.
1146 * The following code is handling exactly that.
1149 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1151 * If xfernotready is already elapsed and it is a case
1152 * of isoc transfer, then issue END TRANSFER, so that
1153 * you can receive xfernotready again and can have
1154 * notion of current microframe.
1156 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1157 if (list_empty(&dep->req_queued)) {
1158 dwc3_stop_active_transfer(dwc, dep->number, true);
1159 dep->flags = DWC3_EP_ENABLED;
1164 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1166 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1172 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1173 * kick the transfer here after queuing a request, otherwise the
1174 * core may not see the modified TRB(s).
1176 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1177 (dep->flags & DWC3_EP_BUSY) &&
1178 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1179 WARN_ON_ONCE(!dep->resource_index);
1180 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1186 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1187 * right away, otherwise host will not know we have streams to be
1190 if (dep->stream_capable)
1191 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1194 if (ret && ret != -EBUSY)
1195 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1203 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1206 struct dwc3_request *req = to_dwc3_request(request);
1207 struct dwc3_ep *dep = to_dwc3_ep(ep);
1208 struct dwc3 *dwc = dep->dwc;
1210 unsigned long flags;
1214 spin_lock_irqsave(&dwc->lock, flags);
1215 if (!dep->endpoint.desc) {
1216 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1222 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1223 request, req->dep->name)) {
1228 ret = __dwc3_gadget_ep_queue(dep, req);
1231 spin_unlock_irqrestore(&dwc->lock, flags);
1236 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1237 struct usb_request *request)
1239 struct dwc3_request *req = to_dwc3_request(request);
1240 struct dwc3_request *r = NULL;
1242 struct dwc3_ep *dep = to_dwc3_ep(ep);
1243 struct dwc3 *dwc = dep->dwc;
1245 unsigned long flags;
1248 trace_dwc3_ep_dequeue(req);
1250 spin_lock_irqsave(&dwc->lock, flags);
1252 list_for_each_entry(r, &dep->request_list, list) {
1258 list_for_each_entry(r, &dep->req_queued, list) {
1263 /* wait until it is processed */
1264 dwc3_stop_active_transfer(dwc, dep->number, true);
1267 dev_err(dwc->dev, "request %p was not queued to %s\n",
1274 /* giveback the request */
1275 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1278 spin_unlock_irqrestore(&dwc->lock, flags);
1283 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1285 struct dwc3_gadget_ep_cmd_params params;
1286 struct dwc3 *dwc = dep->dwc;
1289 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1290 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1294 memset(¶ms, 0x00, sizeof(params));
1297 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1298 (!list_empty(&dep->req_queued) ||
1299 !list_empty(&dep->request_list)))) {
1300 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1305 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1306 DWC3_DEPCMD_SETSTALL, ¶ms);
1308 dev_err(dwc->dev, "failed to set STALL on %s\n",
1311 dep->flags |= DWC3_EP_STALL;
1313 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1314 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1316 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1319 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1325 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1327 struct dwc3_ep *dep = to_dwc3_ep(ep);
1328 struct dwc3 *dwc = dep->dwc;
1330 unsigned long flags;
1334 spin_lock_irqsave(&dwc->lock, flags);
1335 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1336 spin_unlock_irqrestore(&dwc->lock, flags);
1341 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1343 struct dwc3_ep *dep = to_dwc3_ep(ep);
1344 struct dwc3 *dwc = dep->dwc;
1345 unsigned long flags;
1348 spin_lock_irqsave(&dwc->lock, flags);
1349 dep->flags |= DWC3_EP_WEDGE;
1351 if (dep->number == 0 || dep->number == 1)
1352 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1354 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1355 spin_unlock_irqrestore(&dwc->lock, flags);
1360 /* -------------------------------------------------------------------------- */
1362 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1363 .bLength = USB_DT_ENDPOINT_SIZE,
1364 .bDescriptorType = USB_DT_ENDPOINT,
1365 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1368 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1369 .enable = dwc3_gadget_ep0_enable,
1370 .disable = dwc3_gadget_ep0_disable,
1371 .alloc_request = dwc3_gadget_ep_alloc_request,
1372 .free_request = dwc3_gadget_ep_free_request,
1373 .queue = dwc3_gadget_ep0_queue,
1374 .dequeue = dwc3_gadget_ep_dequeue,
1375 .set_halt = dwc3_gadget_ep0_set_halt,
1376 .set_wedge = dwc3_gadget_ep_set_wedge,
1379 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1380 .enable = dwc3_gadget_ep_enable,
1381 .disable = dwc3_gadget_ep_disable,
1382 .alloc_request = dwc3_gadget_ep_alloc_request,
1383 .free_request = dwc3_gadget_ep_free_request,
1384 .queue = dwc3_gadget_ep_queue,
1385 .dequeue = dwc3_gadget_ep_dequeue,
1386 .set_halt = dwc3_gadget_ep_set_halt,
1387 .set_wedge = dwc3_gadget_ep_set_wedge,
1390 /* -------------------------------------------------------------------------- */
1392 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1394 struct dwc3 *dwc = gadget_to_dwc(g);
1397 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1398 return DWC3_DSTS_SOFFN(reg);
1401 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1403 struct dwc3 *dwc = gadget_to_dwc(g);
1405 unsigned long timeout;
1406 unsigned long flags;
1415 spin_lock_irqsave(&dwc->lock, flags);
1418 * According to the Databook Remote wakeup request should
1419 * be issued only when the device is in early suspend state.
1421 * We can check that via USB Link State bits in DSTS register.
1423 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1425 speed = reg & DWC3_DSTS_CONNECTSPD;
1426 if (speed == DWC3_DSTS_SUPERSPEED) {
1427 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1432 link_state = DWC3_DSTS_USBLNKST(reg);
1434 switch (link_state) {
1435 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1436 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1439 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1445 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1447 dev_err(dwc->dev, "failed to put link in Recovery\n");
1451 /* Recent versions do this automatically */
1452 if (dwc->revision < DWC3_REVISION_194A) {
1453 /* write zeroes to Link Change Request */
1454 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1455 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1456 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1459 /* poll until Link State changes to ON */
1460 timeout = jiffies + msecs_to_jiffies(100);
1462 while (!time_after(jiffies, timeout)) {
1463 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1465 /* in HS, means ON */
1466 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1470 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1471 dev_err(dwc->dev, "failed to send remote wakeup\n");
1476 spin_unlock_irqrestore(&dwc->lock, flags);
1481 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1484 struct dwc3 *dwc = gadget_to_dwc(g);
1485 unsigned long flags;
1487 spin_lock_irqsave(&dwc->lock, flags);
1488 g->is_selfpowered = !!is_selfpowered;
1489 spin_unlock_irqrestore(&dwc->lock, flags);
1494 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1499 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1501 if (dwc->revision <= DWC3_REVISION_187A) {
1502 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1503 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1506 if (dwc->revision >= DWC3_REVISION_194A)
1507 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1508 reg |= DWC3_DCTL_RUN_STOP;
1510 if (dwc->has_hibernation)
1511 reg |= DWC3_DCTL_KEEP_CONNECT;
1513 dwc->pullups_connected = true;
1515 reg &= ~DWC3_DCTL_RUN_STOP;
1517 if (dwc->has_hibernation && !suspend)
1518 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1520 dwc->pullups_connected = false;
1523 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1526 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1528 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1531 if (reg & DWC3_DSTS_DEVCTRLHLT)
1540 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1542 ? dwc->gadget_driver->function : "no-function",
1543 is_on ? "connect" : "disconnect");
1548 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1550 struct dwc3 *dwc = gadget_to_dwc(g);
1551 unsigned long flags;
1556 spin_lock_irqsave(&dwc->lock, flags);
1557 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1558 spin_unlock_irqrestore(&dwc->lock, flags);
1563 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1567 /* Enable all but Start and End of Frame IRQs */
1568 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1569 DWC3_DEVTEN_EVNTOVERFLOWEN |
1570 DWC3_DEVTEN_CMDCMPLTEN |
1571 DWC3_DEVTEN_ERRTICERREN |
1572 DWC3_DEVTEN_WKUPEVTEN |
1573 DWC3_DEVTEN_ULSTCNGEN |
1574 DWC3_DEVTEN_CONNECTDONEEN |
1575 DWC3_DEVTEN_USBRSTEN |
1576 DWC3_DEVTEN_DISCONNEVTEN);
1578 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1581 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1583 /* mask all interrupts */
1584 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1587 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1588 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1590 static int dwc3_gadget_start(struct usb_gadget *g,
1591 struct usb_gadget_driver *driver)
1593 struct dwc3 *dwc = gadget_to_dwc(g);
1594 struct dwc3_ep *dep;
1595 unsigned long flags;
1600 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1601 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1602 IRQF_SHARED, "dwc3", dwc);
1604 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1609 spin_lock_irqsave(&dwc->lock, flags);
1611 if (dwc->gadget_driver) {
1612 dev_err(dwc->dev, "%s is already bound to %s\n",
1614 dwc->gadget_driver->driver.name);
1619 dwc->gadget_driver = driver;
1621 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1622 reg &= ~(DWC3_DCFG_SPEED_MASK);
1625 * WORKAROUND: DWC3 revision < 2.20a have an issue
1626 * which would cause metastability state on Run/Stop
1627 * bit if we try to force the IP to USB2-only mode.
1629 * Because of that, we cannot configure the IP to any
1630 * speed other than the SuperSpeed
1634 * STAR#9000525659: Clock Domain Crossing on DCTL in
1637 if (dwc->revision < DWC3_REVISION_220A) {
1638 reg |= DWC3_DCFG_SUPERSPEED;
1640 switch (dwc->maximum_speed) {
1642 reg |= DWC3_DSTS_LOWSPEED;
1644 case USB_SPEED_FULL:
1645 reg |= DWC3_DSTS_FULLSPEED1;
1647 case USB_SPEED_HIGH:
1648 reg |= DWC3_DSTS_HIGHSPEED;
1650 case USB_SPEED_SUPER: /* FALLTHROUGH */
1651 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1653 reg |= DWC3_DSTS_SUPERSPEED;
1656 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1658 /* Start with SuperSpeed Default */
1659 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1662 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1665 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1670 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1673 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1677 /* begin to receive SETUP packets */
1678 dwc->ep0state = EP0_SETUP_PHASE;
1679 dwc3_ep0_out_start(dwc);
1681 dwc3_gadget_enable_irq(dwc);
1683 spin_unlock_irqrestore(&dwc->lock, flags);
1688 __dwc3_gadget_ep_disable(dwc->eps[0]);
1691 dwc->gadget_driver = NULL;
1694 spin_unlock_irqrestore(&dwc->lock, flags);
1702 static int dwc3_gadget_stop(struct usb_gadget *g)
1704 struct dwc3 *dwc = gadget_to_dwc(g);
1705 unsigned long flags;
1708 spin_lock_irqsave(&dwc->lock, flags);
1710 dwc3_gadget_disable_irq(dwc);
1711 __dwc3_gadget_ep_disable(dwc->eps[0]);
1712 __dwc3_gadget_ep_disable(dwc->eps[1]);
1714 dwc->gadget_driver = NULL;
1716 spin_unlock_irqrestore(&dwc->lock, flags);
1718 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1724 static const struct usb_gadget_ops dwc3_gadget_ops = {
1725 .get_frame = dwc3_gadget_get_frame,
1726 .wakeup = dwc3_gadget_wakeup,
1727 .set_selfpowered = dwc3_gadget_set_selfpowered,
1728 .pullup = dwc3_gadget_pullup,
1729 .udc_start = dwc3_gadget_start,
1730 .udc_stop = dwc3_gadget_stop,
1733 /* -------------------------------------------------------------------------- */
1735 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1736 u8 num, u32 direction)
1738 struct dwc3_ep *dep;
1741 for (i = 0; i < num; i++) {
1742 u8 epnum = (i << 1) | (!!direction);
1744 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1749 dep->number = epnum;
1750 dep->direction = !!direction;
1751 dwc->eps[epnum] = dep;
1753 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1754 (epnum & 1) ? "in" : "out");
1756 dep->endpoint.name = dep->name;
1758 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1760 if (epnum == 0 || epnum == 1) {
1761 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1762 dep->endpoint.maxburst = 1;
1763 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1765 dwc->gadget.ep0 = &dep->endpoint;
1769 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1770 dep->endpoint.max_streams = 15;
1771 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1772 list_add_tail(&dep->endpoint.ep_list,
1773 &dwc->gadget.ep_list);
1775 ret = dwc3_alloc_trb_pool(dep);
1780 if (epnum == 0 || epnum == 1) {
1781 dep->endpoint.caps.type_control = true;
1783 dep->endpoint.caps.type_iso = true;
1784 dep->endpoint.caps.type_bulk = true;
1785 dep->endpoint.caps.type_int = true;
1788 dep->endpoint.caps.dir_in = !!direction;
1789 dep->endpoint.caps.dir_out = !direction;
1791 INIT_LIST_HEAD(&dep->request_list);
1792 INIT_LIST_HEAD(&dep->req_queued);
1798 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1802 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1804 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1806 dwc3_trace(trace_dwc3_gadget,
1807 "failed to allocate OUT endpoints");
1811 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1813 dwc3_trace(trace_dwc3_gadget,
1814 "failed to allocate IN endpoints");
1821 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1823 struct dwc3_ep *dep;
1826 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1827 dep = dwc->eps[epnum];
1831 * Physical endpoints 0 and 1 are special; they form the
1832 * bi-directional USB endpoint 0.
1834 * For those two physical endpoints, we don't allocate a TRB
1835 * pool nor do we add them the endpoints list. Due to that, we
1836 * shouldn't do these two operations otherwise we would end up
1837 * with all sorts of bugs when removing dwc3.ko.
1839 if (epnum != 0 && epnum != 1) {
1840 dwc3_free_trb_pool(dep);
1841 list_del(&dep->endpoint.ep_list);
1848 /* -------------------------------------------------------------------------- */
1850 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1851 struct dwc3_request *req, struct dwc3_trb *trb,
1852 const struct dwc3_event_depevt *event, int status)
1855 unsigned int s_pkt = 0;
1856 unsigned int trb_status;
1858 trace_dwc3_complete_trb(dep, trb);
1860 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1862 * We continue despite the error. There is not much we
1863 * can do. If we don't clean it up we loop forever. If
1864 * we skip the TRB then it gets overwritten after a
1865 * while since we use them in a ring buffer. A BUG()
1866 * would help. Lets hope that if this occurs, someone
1867 * fixes the root cause instead of looking away :)
1869 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1871 count = trb->size & DWC3_TRB_SIZE_MASK;
1873 if (dep->direction) {
1875 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1876 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1877 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1880 * If missed isoc occurred and there is
1881 * no request queued then issue END
1882 * TRANSFER, so that core generates
1883 * next xfernotready and we will issue
1884 * a fresh START TRANSFER.
1885 * If there are still queued request
1886 * then wait, do not issue either END
1887 * or UPDATE TRANSFER, just attach next
1888 * request in request_list during
1889 * giveback.If any future queued request
1890 * is successfully transferred then we
1891 * will issue UPDATE TRANSFER for all
1892 * request in the request_list.
1894 dep->flags |= DWC3_EP_MISSED_ISOC;
1896 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1898 status = -ECONNRESET;
1901 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1904 if (count && (event->status & DEPEVT_STATUS_SHORT))
1910 if ((event->status & DEPEVT_STATUS_LST) &&
1911 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1912 DWC3_TRB_CTRL_HWO)))
1914 if ((event->status & DEPEVT_STATUS_IOC) &&
1915 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1920 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1921 const struct dwc3_event_depevt *event, int status)
1923 struct dwc3_request *req;
1924 struct dwc3_trb *trb;
1931 req = next_request(&dep->req_queued);
1938 slot = req->start_slot + i;
1939 if ((slot == DWC3_TRB_NUM - 1) &&
1940 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1942 slot %= DWC3_TRB_NUM;
1943 trb = &dep->trb_pool[slot];
1944 count += trb->size & DWC3_TRB_SIZE_MASK;
1947 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1951 } while (++i < req->request.num_mapped_sgs);
1954 * We assume here we will always receive the entire data block
1955 * which we should receive. Meaning, if we program RX to
1956 * receive 4K but we receive only 2K, we assume that's all we
1957 * should receive and we simply bounce the request back to the
1958 * gadget driver for further processing.
1960 req->request.actual += req->request.length - count;
1961 dwc3_gadget_giveback(dep, req, status);
1967 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1968 list_empty(&dep->req_queued)) {
1969 if (list_empty(&dep->request_list)) {
1971 * If there is no entry in request list then do
1972 * not issue END TRANSFER now. Just set PENDING
1973 * flag, so that END TRANSFER is issued when an
1974 * entry is added into request list.
1976 dep->flags = DWC3_EP_PENDING_REQUEST;
1978 dwc3_stop_active_transfer(dwc, dep->number, true);
1979 dep->flags = DWC3_EP_ENABLED;
1984 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1985 if ((event->status & DEPEVT_STATUS_IOC) &&
1986 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1991 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1992 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1994 unsigned status = 0;
1996 u32 is_xfer_complete;
1998 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2000 if (event->status & DEPEVT_STATUS_BUSERR)
2001 status = -ECONNRESET;
2003 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2004 if (clean_busy && (is_xfer_complete ||
2005 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2006 dep->flags &= ~DWC3_EP_BUSY;
2009 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2010 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2012 if (dwc->revision < DWC3_REVISION_183A) {
2016 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2019 if (!(dep->flags & DWC3_EP_ENABLED))
2022 if (!list_empty(&dep->req_queued))
2026 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2028 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2033 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2036 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2037 if (!ret || ret == -EBUSY)
2042 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2043 const struct dwc3_event_depevt *event)
2045 struct dwc3_ep *dep;
2046 u8 epnum = event->endpoint_number;
2048 dep = dwc->eps[epnum];
2050 if (!(dep->flags & DWC3_EP_ENABLED))
2053 if (epnum == 0 || epnum == 1) {
2054 dwc3_ep0_interrupt(dwc, event);
2058 switch (event->endpoint_event) {
2059 case DWC3_DEPEVT_XFERCOMPLETE:
2060 dep->resource_index = 0;
2062 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2063 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
2068 dwc3_endpoint_transfer_complete(dwc, dep, event);
2070 case DWC3_DEPEVT_XFERINPROGRESS:
2071 dwc3_endpoint_transfer_complete(dwc, dep, event);
2073 case DWC3_DEPEVT_XFERNOTREADY:
2074 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2075 dwc3_gadget_start_isoc(dwc, dep, event);
2080 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2082 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2083 dep->name, active ? "Transfer Active"
2084 : "Transfer Not Active");
2086 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2087 if (!ret || ret == -EBUSY)
2090 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2095 case DWC3_DEPEVT_STREAMEVT:
2096 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2097 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2102 switch (event->status) {
2103 case DEPEVT_STREAMEVT_FOUND:
2104 dwc3_trace(trace_dwc3_gadget,
2105 "Stream %d found and started",
2109 case DEPEVT_STREAMEVT_NOTFOUND:
2112 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2115 case DWC3_DEPEVT_RXTXFIFOEVT:
2116 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2118 case DWC3_DEPEVT_EPCMDCMPLT:
2119 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2124 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2126 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2127 spin_unlock(&dwc->lock);
2128 dwc->gadget_driver->disconnect(&dwc->gadget);
2129 spin_lock(&dwc->lock);
2133 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2135 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2136 spin_unlock(&dwc->lock);
2137 dwc->gadget_driver->suspend(&dwc->gadget);
2138 spin_lock(&dwc->lock);
2142 static void dwc3_resume_gadget(struct dwc3 *dwc)
2144 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2145 spin_unlock(&dwc->lock);
2146 dwc->gadget_driver->resume(&dwc->gadget);
2147 spin_lock(&dwc->lock);
2151 static void dwc3_reset_gadget(struct dwc3 *dwc)
2153 if (!dwc->gadget_driver)
2156 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2157 spin_unlock(&dwc->lock);
2158 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2159 spin_lock(&dwc->lock);
2163 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2165 struct dwc3_ep *dep;
2166 struct dwc3_gadget_ep_cmd_params params;
2170 dep = dwc->eps[epnum];
2172 if (!dep->resource_index)
2176 * NOTICE: We are violating what the Databook says about the
2177 * EndTransfer command. Ideally we would _always_ wait for the
2178 * EndTransfer Command Completion IRQ, but that's causing too
2179 * much trouble synchronizing between us and gadget driver.
2181 * We have discussed this with the IP Provider and it was
2182 * suggested to giveback all requests here, but give HW some
2183 * extra time to synchronize with the interconnect. We're using
2184 * an arbitrary 100us delay for that.
2186 * Note also that a similar handling was tested by Synopsys
2187 * (thanks a lot Paul) and nothing bad has come out of it.
2188 * In short, what we're doing is:
2190 * - Issue EndTransfer WITH CMDIOC bit set
2194 cmd = DWC3_DEPCMD_ENDTRANSFER;
2195 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2196 cmd |= DWC3_DEPCMD_CMDIOC;
2197 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2198 memset(¶ms, 0, sizeof(params));
2199 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2201 dep->resource_index = 0;
2202 dep->flags &= ~DWC3_EP_BUSY;
2206 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2210 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2211 struct dwc3_ep *dep;
2213 dep = dwc->eps[epnum];
2217 if (!(dep->flags & DWC3_EP_ENABLED))
2220 dwc3_remove_requests(dwc, dep);
2224 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2228 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2229 struct dwc3_ep *dep;
2230 struct dwc3_gadget_ep_cmd_params params;
2233 dep = dwc->eps[epnum];
2237 if (!(dep->flags & DWC3_EP_STALL))
2240 dep->flags &= ~DWC3_EP_STALL;
2242 memset(¶ms, 0, sizeof(params));
2243 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2244 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2249 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2253 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2254 reg &= ~DWC3_DCTL_INITU1ENA;
2255 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2257 reg &= ~DWC3_DCTL_INITU2ENA;
2258 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2260 dwc3_disconnect_gadget(dwc);
2262 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2263 dwc->setup_packet_pending = false;
2264 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2267 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2272 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2273 * would cause a missing Disconnect Event if there's a
2274 * pending Setup Packet in the FIFO.
2276 * There's no suggested workaround on the official Bug
2277 * report, which states that "unless the driver/application
2278 * is doing any special handling of a disconnect event,
2279 * there is no functional issue".
2281 * Unfortunately, it turns out that we _do_ some special
2282 * handling of a disconnect event, namely complete all
2283 * pending transfers, notify gadget driver of the
2284 * disconnection, and so on.
2286 * Our suggested workaround is to follow the Disconnect
2287 * Event steps here, instead, based on a setup_packet_pending
2288 * flag. Such flag gets set whenever we have a XferNotReady
2289 * event on EP0 and gets cleared on XferComplete for the
2294 * STAR#9000466709: RTL: Device : Disconnect event not
2295 * generated if setup packet pending in FIFO
2297 if (dwc->revision < DWC3_REVISION_188A) {
2298 if (dwc->setup_packet_pending)
2299 dwc3_gadget_disconnect_interrupt(dwc);
2302 dwc3_reset_gadget(dwc);
2304 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2305 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2306 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2307 dwc->test_mode = false;
2309 dwc3_stop_active_transfers(dwc);
2310 dwc3_clear_stall_all_ep(dwc);
2312 /* Reset device address to zero */
2313 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2314 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2315 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2318 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2321 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2324 * We change the clock only at SS but I dunno why I would want to do
2325 * this. Maybe it becomes part of the power saving plan.
2328 if (speed != DWC3_DSTS_SUPERSPEED)
2332 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2333 * each time on Connect Done.
2338 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2339 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2340 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2343 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2345 struct dwc3_ep *dep;
2350 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2351 speed = reg & DWC3_DSTS_CONNECTSPD;
2354 dwc3_update_ram_clk_sel(dwc, speed);
2357 case DWC3_DCFG_SUPERSPEED:
2359 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2360 * would cause a missing USB3 Reset event.
2362 * In such situations, we should force a USB3 Reset
2363 * event by calling our dwc3_gadget_reset_interrupt()
2368 * STAR#9000483510: RTL: SS : USB3 reset event may
2369 * not be generated always when the link enters poll
2371 if (dwc->revision < DWC3_REVISION_190A)
2372 dwc3_gadget_reset_interrupt(dwc);
2374 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2375 dwc->gadget.ep0->maxpacket = 512;
2376 dwc->gadget.speed = USB_SPEED_SUPER;
2378 case DWC3_DCFG_HIGHSPEED:
2379 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2380 dwc->gadget.ep0->maxpacket = 64;
2381 dwc->gadget.speed = USB_SPEED_HIGH;
2383 case DWC3_DCFG_FULLSPEED2:
2384 case DWC3_DCFG_FULLSPEED1:
2385 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2386 dwc->gadget.ep0->maxpacket = 64;
2387 dwc->gadget.speed = USB_SPEED_FULL;
2389 case DWC3_DCFG_LOWSPEED:
2390 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2391 dwc->gadget.ep0->maxpacket = 8;
2392 dwc->gadget.speed = USB_SPEED_LOW;
2396 /* Enable USB2 LPM Capability */
2398 if ((dwc->revision > DWC3_REVISION_194A)
2399 && (speed != DWC3_DCFG_SUPERSPEED)) {
2400 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2401 reg |= DWC3_DCFG_LPM_CAP;
2402 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2404 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2405 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2407 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2410 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2411 * DCFG.LPMCap is set, core responses with an ACK and the
2412 * BESL value in the LPM token is less than or equal to LPM
2415 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2416 && dwc->has_lpm_erratum,
2417 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2419 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2420 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2422 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2424 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2425 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2426 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2430 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2433 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2438 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2441 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2446 * Configure PHY via GUSB3PIPECTLn if required.
2448 * Update GTXFIFOSIZn
2450 * In both cases reset values should be sufficient.
2454 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2457 * TODO take core out of low power mode when that's
2461 dwc->gadget_driver->resume(&dwc->gadget);
2464 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2465 unsigned int evtinfo)
2467 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2468 unsigned int pwropt;
2471 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2472 * Hibernation mode enabled which would show up when device detects
2473 * host-initiated U3 exit.
2475 * In that case, device will generate a Link State Change Interrupt
2476 * from U3 to RESUME which is only necessary if Hibernation is
2479 * There are no functional changes due to such spurious event and we
2480 * just need to ignore it.
2484 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2487 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2488 if ((dwc->revision < DWC3_REVISION_250A) &&
2489 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2490 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2491 (next == DWC3_LINK_STATE_RESUME)) {
2492 dwc3_trace(trace_dwc3_gadget,
2493 "ignoring transition U3 -> Resume");
2499 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2500 * on the link partner, the USB session might do multiple entry/exit
2501 * of low power states before a transfer takes place.
2503 * Due to this problem, we might experience lower throughput. The
2504 * suggested workaround is to disable DCTL[12:9] bits if we're
2505 * transitioning from U1/U2 to U0 and enable those bits again
2506 * after a transfer completes and there are no pending transfers
2507 * on any of the enabled endpoints.
2509 * This is the first half of that workaround.
2513 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2514 * core send LGO_Ux entering U0
2516 if (dwc->revision < DWC3_REVISION_183A) {
2517 if (next == DWC3_LINK_STATE_U0) {
2521 switch (dwc->link_state) {
2522 case DWC3_LINK_STATE_U1:
2523 case DWC3_LINK_STATE_U2:
2524 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2525 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2526 | DWC3_DCTL_ACCEPTU2ENA
2527 | DWC3_DCTL_INITU1ENA
2528 | DWC3_DCTL_ACCEPTU1ENA);
2531 dwc->u1u2 = reg & u1u2;
2535 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2545 case DWC3_LINK_STATE_U1:
2546 if (dwc->speed == USB_SPEED_SUPER)
2547 dwc3_suspend_gadget(dwc);
2549 case DWC3_LINK_STATE_U2:
2550 case DWC3_LINK_STATE_U3:
2551 dwc3_suspend_gadget(dwc);
2553 case DWC3_LINK_STATE_RESUME:
2554 dwc3_resume_gadget(dwc);
2561 dwc->link_state = next;
2564 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2565 unsigned int evtinfo)
2567 unsigned int is_ss = evtinfo & BIT(4);
2570 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2571 * have a known issue which can cause USB CV TD.9.23 to fail
2574 * Because of this issue, core could generate bogus hibernation
2575 * events which SW needs to ignore.
2579 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2580 * Device Fallback from SuperSpeed
2582 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2585 /* enter hibernation here */
2588 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2589 const struct dwc3_event_devt *event)
2591 switch (event->type) {
2592 case DWC3_DEVICE_EVENT_DISCONNECT:
2593 dwc3_gadget_disconnect_interrupt(dwc);
2595 case DWC3_DEVICE_EVENT_RESET:
2596 dwc3_gadget_reset_interrupt(dwc);
2598 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2599 dwc3_gadget_conndone_interrupt(dwc);
2601 case DWC3_DEVICE_EVENT_WAKEUP:
2602 dwc3_gadget_wakeup_interrupt(dwc);
2604 case DWC3_DEVICE_EVENT_HIBER_REQ:
2605 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2606 "unexpected hibernation event\n"))
2609 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2611 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2612 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2614 case DWC3_DEVICE_EVENT_EOPF:
2615 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2617 case DWC3_DEVICE_EVENT_SOF:
2618 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2620 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2621 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2623 case DWC3_DEVICE_EVENT_CMD_CMPL:
2624 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2626 case DWC3_DEVICE_EVENT_OVERFLOW:
2627 dwc3_trace(trace_dwc3_gadget, "Overflow");
2630 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2634 static void dwc3_process_event_entry(struct dwc3 *dwc,
2635 const union dwc3_event *event)
2637 trace_dwc3_event(event->raw);
2639 /* Endpoint IRQ, handle it and return early */
2640 if (event->type.is_devspec == 0) {
2642 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2645 switch (event->type.type) {
2646 case DWC3_EVENT_TYPE_DEV:
2647 dwc3_gadget_interrupt(dwc, &event->devt);
2649 /* REVISIT what to do with Carkit and I2C events ? */
2651 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2655 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2657 struct dwc3_event_buffer *evt;
2658 irqreturn_t ret = IRQ_NONE;
2662 evt = dwc->ev_buffs[buf];
2665 if (!(evt->flags & DWC3_EVENT_PENDING))
2669 union dwc3_event event;
2671 event.raw = *(u32 *) (evt->buf + evt->lpos);
2673 dwc3_process_event_entry(dwc, &event);
2676 * FIXME we wrap around correctly to the next entry as
2677 * almost all entries are 4 bytes in size. There is one
2678 * entry which has 12 bytes which is a regular entry
2679 * followed by 8 bytes data. ATM I don't know how
2680 * things are organized if we get next to the a
2681 * boundary so I worry about that once we try to handle
2684 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2687 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2691 evt->flags &= ~DWC3_EVENT_PENDING;
2694 /* Unmask interrupt */
2695 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2696 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2697 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2702 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2704 struct dwc3 *dwc = _dwc;
2705 unsigned long flags;
2706 irqreturn_t ret = IRQ_NONE;
2709 spin_lock_irqsave(&dwc->lock, flags);
2711 for (i = 0; i < dwc->num_event_buffers; i++)
2712 ret |= dwc3_process_event_buf(dwc, i);
2714 spin_unlock_irqrestore(&dwc->lock, flags);
2719 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2721 struct dwc3_event_buffer *evt;
2725 evt = dwc->ev_buffs[buf];
2727 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2728 count &= DWC3_GEVNTCOUNT_MASK;
2733 evt->flags |= DWC3_EVENT_PENDING;
2735 /* Mask interrupt */
2736 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2737 reg |= DWC3_GEVNTSIZ_INTMASK;
2738 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2740 return IRQ_WAKE_THREAD;
2743 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2745 struct dwc3 *dwc = _dwc;
2747 irqreturn_t ret = IRQ_NONE;
2749 for (i = 0; i < dwc->num_event_buffers; i++) {
2752 status = dwc3_check_event_buf(dwc, i);
2753 if (status == IRQ_WAKE_THREAD)
2761 * dwc3_gadget_init - Initializes gadget related registers
2762 * @dwc: pointer to our controller context structure
2764 * Returns 0 on success otherwise negative errno.
2766 int dwc3_gadget_init(struct dwc3 *dwc)
2770 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2771 &dwc->ctrl_req_addr, GFP_KERNEL);
2772 if (!dwc->ctrl_req) {
2773 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2778 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2779 &dwc->ep0_trb_addr, GFP_KERNEL);
2780 if (!dwc->ep0_trb) {
2781 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2786 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2787 if (!dwc->setup_buf) {
2792 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2793 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2795 if (!dwc->ep0_bounce) {
2796 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2801 dwc->gadget.ops = &dwc3_gadget_ops;
2802 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2803 dwc->gadget.sg_supported = true;
2804 dwc->gadget.name = "dwc3-gadget";
2807 * FIXME We might be setting max_speed to <SUPER, however versions
2808 * <2.20a of dwc3 have an issue with metastability (documented
2809 * elsewhere in this driver) which tells us we can't set max speed to
2810 * anything lower than SUPER.
2812 * Because gadget.max_speed is only used by composite.c and function
2813 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2814 * to happen so we avoid sending SuperSpeed Capability descriptor
2815 * together with our BOS descriptor as that could confuse host into
2816 * thinking we can handle super speed.
2818 * Note that, in fact, we won't even support GetBOS requests when speed
2819 * is less than super speed because we don't have means, yet, to tell
2820 * composite.c that we are USB 2.0 + LPM ECN.
2822 if (dwc->revision < DWC3_REVISION_220A)
2823 dwc3_trace(trace_dwc3_gadget,
2824 "Changing max_speed on rev %08x\n",
2827 dwc->gadget.max_speed = dwc->maximum_speed;
2830 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2833 dwc->gadget.quirk_ep_out_aligned_size = true;
2836 * REVISIT: Here we should clear all pending IRQs to be
2837 * sure we're starting from a well known location.
2840 ret = dwc3_gadget_init_endpoints(dwc);
2844 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2846 dev_err(dwc->dev, "failed to register udc\n");
2853 dwc3_gadget_free_endpoints(dwc);
2854 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2855 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2858 kfree(dwc->setup_buf);
2861 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2862 dwc->ep0_trb, dwc->ep0_trb_addr);
2865 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2866 dwc->ctrl_req, dwc->ctrl_req_addr);
2872 /* -------------------------------------------------------------------------- */
2874 void dwc3_gadget_exit(struct dwc3 *dwc)
2876 usb_del_gadget_udc(&dwc->gadget);
2878 dwc3_gadget_free_endpoints(dwc);
2880 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2881 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2883 kfree(dwc->setup_buf);
2885 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2886 dwc->ep0_trb, dwc->ep0_trb_addr);
2888 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2889 dwc->ctrl_req, dwc->ctrl_req_addr);
2892 int dwc3_gadget_suspend(struct dwc3 *dwc)
2894 if (dwc->pullups_connected) {
2895 dwc3_gadget_disable_irq(dwc);
2896 dwc3_gadget_run_stop(dwc, true, true);
2899 __dwc3_gadget_ep_disable(dwc->eps[0]);
2900 __dwc3_gadget_ep_disable(dwc->eps[1]);
2902 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2907 int dwc3_gadget_resume(struct dwc3 *dwc)
2909 struct dwc3_ep *dep;
2912 /* Start with SuperSpeed Default */
2913 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2916 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2922 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2927 /* begin to receive SETUP packets */
2928 dwc->ep0state = EP0_SETUP_PHASE;
2929 dwc3_ep0_out_start(dwc);
2931 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2933 if (dwc->pullups_connected) {
2934 dwc3_gadget_enable_irq(dwc);
2935 dwc3_gadget_run_stop(dwc, true, false);
2941 __dwc3_gadget_ep_disable(dwc->eps[0]);