2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc->revision >= DWC3_REVISION_194A) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc->revision >= DWC3_REVISION_194A)
134 /* wait for a change in DSTS */
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
139 if (DWC3_DSTS_USBLNKST(reg) == state)
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
173 int last_fifo_depth = 0;
179 if (!dwc->needs_fifo_resize)
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
200 if (!(dep->number & 1))
203 if (!(dep->flags & DWC3_EP_ENABLED))
206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
226 fifo_size |= (last_fifo_depth << 16);
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
234 last_fifo_depth += (fifo_size & 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
243 struct dwc3 *dwc = dep->dwc;
251 * Skip LINK TRB. We can't use req->trb and check for
252 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
253 * just completed (not the LINK TRB).
255 if (((dep->busy_slot & DWC3_TRB_MASK) ==
257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
259 } while(++i < req->request.num_mapped_sgs);
262 list_del(&req->list);
265 if (req->request.status == -EINPROGRESS)
266 req->request.status = status;
268 if (dwc->ep0_bounced && dep->number == 0)
269 dwc->ep0_bounced = false;
271 usb_gadget_unmap_request(&dwc->gadget, &req->request,
274 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
275 req, dep->name, req->request.actual,
276 req->request.length, status);
278 spin_unlock(&dwc->lock);
279 req->request.complete(&dep->endpoint, &req->request);
280 spin_lock(&dwc->lock);
283 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
286 case DWC3_DEPCMD_DEPSTARTCFG:
287 return "Start New Configuration";
288 case DWC3_DEPCMD_ENDTRANSFER:
289 return "End Transfer";
290 case DWC3_DEPCMD_UPDATETRANSFER:
291 return "Update Transfer";
292 case DWC3_DEPCMD_STARTTRANSFER:
293 return "Start Transfer";
294 case DWC3_DEPCMD_CLEARSTALL:
295 return "Clear Stall";
296 case DWC3_DEPCMD_SETSTALL:
298 case DWC3_DEPCMD_GETEPSTATE:
299 return "Get Endpoint State";
300 case DWC3_DEPCMD_SETTRANSFRESOURCE:
301 return "Set Endpoint Transfer Resource";
302 case DWC3_DEPCMD_SETEPCONFIG:
303 return "Set Endpoint Configuration";
305 return "UNKNOWN command";
309 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
314 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
315 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
318 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
319 if (!(reg & DWC3_DGCMD_CMDACT)) {
320 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
321 DWC3_DGCMD_STATUS(reg));
326 * We can't sleep here, because it's also called from
336 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
337 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
339 struct dwc3_ep *dep = dwc->eps[ep];
343 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
345 dwc3_gadget_ep_cmd_string(cmd), params->param0,
346 params->param1, params->param2);
348 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
349 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
350 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
352 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
354 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
355 if (!(reg & DWC3_DEPCMD_CMDACT)) {
356 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
357 DWC3_DEPCMD_STATUS(reg));
362 * We can't sleep here, because it is also called from
373 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
374 struct dwc3_trb *trb)
376 u32 offset = (char *) trb - (char *) dep->trb_pool;
378 return dep->trb_pool_dma + offset;
381 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
383 struct dwc3 *dwc = dep->dwc;
388 if (dep->number == 0 || dep->number == 1)
391 dep->trb_pool = dma_alloc_coherent(dwc->dev,
392 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
393 &dep->trb_pool_dma, GFP_KERNEL);
394 if (!dep->trb_pool) {
395 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
403 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
405 struct dwc3 *dwc = dep->dwc;
407 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
408 dep->trb_pool, dep->trb_pool_dma);
410 dep->trb_pool = NULL;
411 dep->trb_pool_dma = 0;
414 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
416 struct dwc3_gadget_ep_cmd_params params;
419 memset(¶ms, 0x00, sizeof(params));
421 if (dep->number != 1) {
422 cmd = DWC3_DEPCMD_DEPSTARTCFG;
423 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
424 if (dep->number > 1) {
425 if (dwc->start_config_issued)
427 dwc->start_config_issued = true;
428 cmd |= DWC3_DEPCMD_PARAM(2);
431 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
437 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
438 const struct usb_endpoint_descriptor *desc,
439 const struct usb_ss_ep_comp_descriptor *comp_desc,
442 struct dwc3_gadget_ep_cmd_params params;
444 memset(¶ms, 0x00, sizeof(params));
446 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
447 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
449 /* Burst size is only needed in SuperSpeed mode */
450 if (dwc->gadget.speed == USB_SPEED_SUPER) {
451 u32 burst = dep->endpoint.maxburst - 1;
453 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
457 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
459 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
460 | DWC3_DEPCFG_XFER_NOT_READY_EN;
462 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
463 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
464 | DWC3_DEPCFG_STREAM_EVENT_EN;
465 dep->stream_capable = true;
468 if (usb_endpoint_xfer_isoc(desc))
469 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
472 * We are doing 1:1 mapping for endpoints, meaning
473 * Physical Endpoints 2 maps to Logical Endpoint 2 and
474 * so on. We consider the direction bit as part of the physical
475 * endpoint number. So USB endpoint 0x81 is 0x03.
477 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
480 * We must use the lower 16 TX FIFOs even though
484 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
486 if (desc->bInterval) {
487 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
488 dep->interval = 1 << (desc->bInterval - 1);
491 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
492 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
495 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
497 struct dwc3_gadget_ep_cmd_params params;
499 memset(¶ms, 0x00, sizeof(params));
501 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
503 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
504 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
508 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
509 * @dep: endpoint to be initialized
510 * @desc: USB Endpoint Descriptor
512 * Caller should take care of locking
514 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
515 const struct usb_endpoint_descriptor *desc,
516 const struct usb_ss_ep_comp_descriptor *comp_desc,
519 struct dwc3 *dwc = dep->dwc;
523 if (!(dep->flags & DWC3_EP_ENABLED)) {
524 ret = dwc3_gadget_start_config(dwc, dep);
529 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
533 if (!(dep->flags & DWC3_EP_ENABLED)) {
534 struct dwc3_trb *trb_st_hw;
535 struct dwc3_trb *trb_link;
537 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
541 dep->endpoint.desc = desc;
542 dep->comp_desc = comp_desc;
543 dep->type = usb_endpoint_type(desc);
544 dep->flags |= DWC3_EP_ENABLED;
546 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
547 reg |= DWC3_DALEPENA_EP(dep->number);
548 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
550 if (!usb_endpoint_xfer_isoc(desc))
553 memset(&trb_link, 0, sizeof(trb_link));
555 /* Link TRB for ISOC. The HWO bit is never reset */
556 trb_st_hw = &dep->trb_pool[0];
558 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
560 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
561 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
562 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
563 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
569 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
570 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
572 struct dwc3_request *req;
574 if (!list_empty(&dep->req_queued)) {
575 dwc3_stop_active_transfer(dwc, dep->number);
577 /* - giveback all requests to gadget driver */
578 while (!list_empty(&dep->req_queued)) {
579 req = next_request(&dep->req_queued);
581 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
585 while (!list_empty(&dep->request_list)) {
586 req = next_request(&dep->request_list);
588 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
593 * __dwc3_gadget_ep_disable - Disables a HW endpoint
594 * @dep: the endpoint to disable
596 * This function also removes requests which are currently processed ny the
597 * hardware and those which are not yet scheduled.
598 * Caller should take care of locking.
600 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
602 struct dwc3 *dwc = dep->dwc;
605 dwc3_remove_requests(dwc, dep);
607 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
608 reg &= ~DWC3_DALEPENA_EP(dep->number);
609 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
611 dep->stream_capable = false;
612 dep->endpoint.desc = NULL;
613 dep->comp_desc = NULL;
620 /* -------------------------------------------------------------------------- */
622 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
623 const struct usb_endpoint_descriptor *desc)
628 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
633 /* -------------------------------------------------------------------------- */
635 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
636 const struct usb_endpoint_descriptor *desc)
643 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
644 pr_debug("dwc3: invalid parameters\n");
648 if (!desc->wMaxPacketSize) {
649 pr_debug("dwc3: missing wMaxPacketSize\n");
653 dep = to_dwc3_ep(ep);
656 if (dep->flags & DWC3_EP_ENABLED) {
657 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
662 switch (usb_endpoint_type(desc)) {
663 case USB_ENDPOINT_XFER_CONTROL:
664 strlcat(dep->name, "-control", sizeof(dep->name));
666 case USB_ENDPOINT_XFER_ISOC:
667 strlcat(dep->name, "-isoc", sizeof(dep->name));
669 case USB_ENDPOINT_XFER_BULK:
670 strlcat(dep->name, "-bulk", sizeof(dep->name));
672 case USB_ENDPOINT_XFER_INT:
673 strlcat(dep->name, "-int", sizeof(dep->name));
676 dev_err(dwc->dev, "invalid endpoint transfer type\n");
679 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
681 spin_lock_irqsave(&dwc->lock, flags);
682 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
683 spin_unlock_irqrestore(&dwc->lock, flags);
688 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
696 pr_debug("dwc3: invalid parameters\n");
700 dep = to_dwc3_ep(ep);
703 if (!(dep->flags & DWC3_EP_ENABLED)) {
704 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
709 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
711 (dep->number & 1) ? "in" : "out");
713 spin_lock_irqsave(&dwc->lock, flags);
714 ret = __dwc3_gadget_ep_disable(dep);
715 spin_unlock_irqrestore(&dwc->lock, flags);
720 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
723 struct dwc3_request *req;
724 struct dwc3_ep *dep = to_dwc3_ep(ep);
725 struct dwc3 *dwc = dep->dwc;
727 req = kzalloc(sizeof(*req), gfp_flags);
729 dev_err(dwc->dev, "not enough memory\n");
733 req->epnum = dep->number;
736 return &req->request;
739 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
740 struct usb_request *request)
742 struct dwc3_request *req = to_dwc3_request(request);
748 * dwc3_prepare_one_trb - setup one TRB from one request
749 * @dep: endpoint for which this request is prepared
750 * @req: dwc3_request pointer
752 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
753 struct dwc3_request *req, dma_addr_t dma,
754 unsigned length, unsigned last, unsigned chain, unsigned node)
756 struct dwc3 *dwc = dep->dwc;
757 struct dwc3_trb *trb;
759 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
760 dep->name, req, (unsigned long long) dma,
761 length, last ? " last" : "",
762 chain ? " chain" : "");
764 /* Skip the LINK-TRB on ISOC */
765 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
766 usb_endpoint_xfer_isoc(dep->endpoint.desc))
769 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
772 dwc3_gadget_move_request_queued(req);
774 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
775 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
780 trb->size = DWC3_TRB_SIZE_LENGTH(length);
781 trb->bpl = lower_32_bits(dma);
782 trb->bph = upper_32_bits(dma);
784 switch (usb_endpoint_type(dep->endpoint.desc)) {
785 case USB_ENDPOINT_XFER_CONTROL:
786 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
789 case USB_ENDPOINT_XFER_ISOC:
791 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
793 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
795 if (!req->request.no_interrupt && !chain)
796 trb->ctrl |= DWC3_TRB_CTRL_IOC;
799 case USB_ENDPOINT_XFER_BULK:
800 case USB_ENDPOINT_XFER_INT:
801 trb->ctrl = DWC3_TRBCTL_NORMAL;
805 * This is only possible with faulty memory because we
806 * checked it already :)
811 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
812 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
813 trb->ctrl |= DWC3_TRB_CTRL_CSP;
815 trb->ctrl |= DWC3_TRB_CTRL_LST;
819 trb->ctrl |= DWC3_TRB_CTRL_CHN;
821 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
822 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
824 trb->ctrl |= DWC3_TRB_CTRL_HWO;
828 * dwc3_prepare_trbs - setup TRBs from requests
829 * @dep: endpoint for which requests are being prepared
830 * @starting: true if the endpoint is idle and no requests are queued.
832 * The function goes through the requests list and sets up TRBs for the
833 * transfers. The function returns once there are no more TRBs available or
834 * it runs out of requests.
836 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
838 struct dwc3_request *req, *n;
841 unsigned int last_one = 0;
843 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
845 /* the first request must not be queued */
846 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
848 /* Can't wrap around on a non-isoc EP since there's no link TRB */
849 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
850 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
856 * If busy & slot are equal than it is either full or empty. If we are
857 * starting to process requests then we are empty. Otherwise we are
858 * full and don't do anything
863 trbs_left = DWC3_TRB_NUM;
865 * In case we start from scratch, we queue the ISOC requests
866 * starting from slot 1. This is done because we use ring
867 * buffer and have no LST bit to stop us. Instead, we place
868 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
869 * after the first request so we start at slot 1 and have
870 * 7 requests proceed before we hit the first IOC.
871 * Other transfer types don't use the ring buffer and are
872 * processed from the first TRB until the last one. Since we
873 * don't wrap around we have to start at the beginning.
875 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
884 /* The last TRB is a link TRB, not used for xfer */
885 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
888 list_for_each_entry_safe(req, n, &dep->request_list, list) {
893 if (req->request.num_mapped_sgs > 0) {
894 struct usb_request *request = &req->request;
895 struct scatterlist *sg = request->sg;
896 struct scatterlist *s;
899 for_each_sg(sg, s, request->num_mapped_sgs, i) {
900 unsigned chain = true;
902 length = sg_dma_len(s);
903 dma = sg_dma_address(s);
905 if (i == (request->num_mapped_sgs - 1) ||
907 if (list_is_last(&req->list,
920 dwc3_prepare_one_trb(dep, req, dma, length,
927 dma = req->request.dma;
928 length = req->request.length;
934 /* Is this the last request? */
935 if (list_is_last(&req->list, &dep->request_list))
938 dwc3_prepare_one_trb(dep, req, dma, length,
947 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
950 struct dwc3_gadget_ep_cmd_params params;
951 struct dwc3_request *req;
952 struct dwc3 *dwc = dep->dwc;
956 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
957 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
960 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
963 * If we are getting here after a short-out-packet we don't enqueue any
964 * new requests as we try to set the IOC bit only on the last request.
967 if (list_empty(&dep->req_queued))
968 dwc3_prepare_trbs(dep, start_new);
970 /* req points to the first request which will be sent */
971 req = next_request(&dep->req_queued);
973 dwc3_prepare_trbs(dep, start_new);
976 * req points to the first request where HWO changed from 0 to 1
978 req = next_request(&dep->req_queued);
981 dep->flags |= DWC3_EP_PENDING_REQUEST;
985 memset(¶ms, 0, sizeof(params));
988 params.param0 = upper_32_bits(req->trb_dma);
989 params.param1 = lower_32_bits(req->trb_dma);
990 cmd = DWC3_DEPCMD_STARTTRANSFER;
992 cmd = DWC3_DEPCMD_UPDATETRANSFER;
995 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
996 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
998 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1001 * FIXME we need to iterate over the list of requests
1002 * here and stop, unmap, free and del each of the linked
1003 * requests instead of what we do now.
1005 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1007 list_del(&req->list);
1011 dep->flags |= DWC3_EP_BUSY;
1014 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1016 WARN_ON_ONCE(!dep->resource_index);
1022 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1023 struct dwc3_ep *dep, u32 cur_uf)
1027 if (list_empty(&dep->request_list)) {
1028 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1030 dep->flags |= DWC3_EP_PENDING_REQUEST;
1034 /* 4 micro frames in the future */
1035 uf = cur_uf + dep->interval * 4;
1037 __dwc3_gadget_kick_transfer(dep, uf, 1);
1040 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1041 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1045 mask = ~(dep->interval - 1);
1046 cur_uf = event->parameters & mask;
1048 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1051 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1053 struct dwc3 *dwc = dep->dwc;
1056 req->request.actual = 0;
1057 req->request.status = -EINPROGRESS;
1058 req->direction = dep->direction;
1059 req->epnum = dep->number;
1062 * We only add to our list of requests now and
1063 * start consuming the list once we get XferNotReady
1066 * That way, we avoid doing anything that we don't need
1067 * to do now and defer it until the point we receive a
1068 * particular token from the Host side.
1070 * This will also avoid Host cancelling URBs due to too
1073 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1078 list_add_tail(&req->list, &dep->request_list);
1081 * There are a few special cases:
1083 * 1. XferNotReady with empty list of requests. We need to kick the
1084 * transfer here in that situation, otherwise we will be NAKing
1085 * forever. If we get XferNotReady before gadget driver has a
1086 * chance to queue a request, we will ACK the IRQ but won't be
1087 * able to receive the data until the next request is queued.
1088 * The following code is handling exactly that.
1091 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1093 * If xfernotready is already elapsed and it is a case
1094 * of isoc transfer, then issue END TRANSFER, so that
1095 * you can receive xfernotready again and can have
1096 * notion of current microframe.
1098 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1099 if (list_empty(&dep->req_queued)) {
1100 dwc3_stop_active_transfer(dwc, dep->number);
1101 dep->flags = DWC3_EP_ENABLED;
1106 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1107 if (ret && ret != -EBUSY)
1108 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1114 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1115 * kick the transfer here after queuing a request, otherwise the
1116 * core may not see the modified TRB(s).
1118 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1119 (dep->flags & DWC3_EP_BUSY) &&
1120 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1121 WARN_ON_ONCE(!dep->resource_index);
1122 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1124 if (ret && ret != -EBUSY)
1125 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1133 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1136 struct dwc3_request *req = to_dwc3_request(request);
1137 struct dwc3_ep *dep = to_dwc3_ep(ep);
1138 struct dwc3 *dwc = dep->dwc;
1140 unsigned long flags;
1144 if (!dep->endpoint.desc) {
1145 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1150 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1151 request, ep->name, request->length);
1153 spin_lock_irqsave(&dwc->lock, flags);
1154 ret = __dwc3_gadget_ep_queue(dep, req);
1155 spin_unlock_irqrestore(&dwc->lock, flags);
1160 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1161 struct usb_request *request)
1163 struct dwc3_request *req = to_dwc3_request(request);
1164 struct dwc3_request *r = NULL;
1166 struct dwc3_ep *dep = to_dwc3_ep(ep);
1167 struct dwc3 *dwc = dep->dwc;
1169 unsigned long flags;
1172 spin_lock_irqsave(&dwc->lock, flags);
1174 list_for_each_entry(r, &dep->request_list, list) {
1180 list_for_each_entry(r, &dep->req_queued, list) {
1185 /* wait until it is processed */
1186 dwc3_stop_active_transfer(dwc, dep->number);
1189 dev_err(dwc->dev, "request %p was not queued to %s\n",
1196 /* giveback the request */
1197 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1200 spin_unlock_irqrestore(&dwc->lock, flags);
1205 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1207 struct dwc3_gadget_ep_cmd_params params;
1208 struct dwc3 *dwc = dep->dwc;
1211 memset(¶ms, 0x00, sizeof(params));
1214 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1215 DWC3_DEPCMD_SETSTALL, ¶ms);
1217 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1218 value ? "set" : "clear",
1221 dep->flags |= DWC3_EP_STALL;
1223 if (dep->flags & DWC3_EP_WEDGE)
1226 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1227 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1229 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1230 value ? "set" : "clear",
1233 dep->flags &= ~DWC3_EP_STALL;
1239 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1241 struct dwc3_ep *dep = to_dwc3_ep(ep);
1242 struct dwc3 *dwc = dep->dwc;
1244 unsigned long flags;
1248 spin_lock_irqsave(&dwc->lock, flags);
1250 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1251 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1256 ret = __dwc3_gadget_ep_set_halt(dep, value);
1258 spin_unlock_irqrestore(&dwc->lock, flags);
1263 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1265 struct dwc3_ep *dep = to_dwc3_ep(ep);
1266 struct dwc3 *dwc = dep->dwc;
1267 unsigned long flags;
1269 spin_lock_irqsave(&dwc->lock, flags);
1270 dep->flags |= DWC3_EP_WEDGE;
1271 spin_unlock_irqrestore(&dwc->lock, flags);
1273 if (dep->number == 0 || dep->number == 1)
1274 return dwc3_gadget_ep0_set_halt(ep, 1);
1276 return dwc3_gadget_ep_set_halt(ep, 1);
1279 /* -------------------------------------------------------------------------- */
1281 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1282 .bLength = USB_DT_ENDPOINT_SIZE,
1283 .bDescriptorType = USB_DT_ENDPOINT,
1284 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1287 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1288 .enable = dwc3_gadget_ep0_enable,
1289 .disable = dwc3_gadget_ep0_disable,
1290 .alloc_request = dwc3_gadget_ep_alloc_request,
1291 .free_request = dwc3_gadget_ep_free_request,
1292 .queue = dwc3_gadget_ep0_queue,
1293 .dequeue = dwc3_gadget_ep_dequeue,
1294 .set_halt = dwc3_gadget_ep0_set_halt,
1295 .set_wedge = dwc3_gadget_ep_set_wedge,
1298 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1299 .enable = dwc3_gadget_ep_enable,
1300 .disable = dwc3_gadget_ep_disable,
1301 .alloc_request = dwc3_gadget_ep_alloc_request,
1302 .free_request = dwc3_gadget_ep_free_request,
1303 .queue = dwc3_gadget_ep_queue,
1304 .dequeue = dwc3_gadget_ep_dequeue,
1305 .set_halt = dwc3_gadget_ep_set_halt,
1306 .set_wedge = dwc3_gadget_ep_set_wedge,
1309 /* -------------------------------------------------------------------------- */
1311 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1313 struct dwc3 *dwc = gadget_to_dwc(g);
1316 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1317 return DWC3_DSTS_SOFFN(reg);
1320 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1322 struct dwc3 *dwc = gadget_to_dwc(g);
1324 unsigned long timeout;
1325 unsigned long flags;
1334 spin_lock_irqsave(&dwc->lock, flags);
1337 * According to the Databook Remote wakeup request should
1338 * be issued only when the device is in early suspend state.
1340 * We can check that via USB Link State bits in DSTS register.
1342 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1344 speed = reg & DWC3_DSTS_CONNECTSPD;
1345 if (speed == DWC3_DSTS_SUPERSPEED) {
1346 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1351 link_state = DWC3_DSTS_USBLNKST(reg);
1353 switch (link_state) {
1354 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1355 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1358 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1364 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1366 dev_err(dwc->dev, "failed to put link in Recovery\n");
1370 /* Recent versions do this automatically */
1371 if (dwc->revision < DWC3_REVISION_194A) {
1372 /* write zeroes to Link Change Request */
1373 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1374 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1375 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1378 /* poll until Link State changes to ON */
1379 timeout = jiffies + msecs_to_jiffies(100);
1381 while (!time_after(jiffies, timeout)) {
1382 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1384 /* in HS, means ON */
1385 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1389 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1390 dev_err(dwc->dev, "failed to send remote wakeup\n");
1395 spin_unlock_irqrestore(&dwc->lock, flags);
1400 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1403 struct dwc3 *dwc = gadget_to_dwc(g);
1404 unsigned long flags;
1406 spin_lock_irqsave(&dwc->lock, flags);
1407 dwc->is_selfpowered = !!is_selfpowered;
1408 spin_unlock_irqrestore(&dwc->lock, flags);
1413 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1418 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1420 if (dwc->revision <= DWC3_REVISION_187A) {
1421 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1422 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1425 if (dwc->revision >= DWC3_REVISION_194A)
1426 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1427 reg |= DWC3_DCTL_RUN_STOP;
1428 dwc->pullups_connected = true;
1430 reg &= ~DWC3_DCTL_RUN_STOP;
1431 dwc->pullups_connected = false;
1434 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1437 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1439 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1442 if (reg & DWC3_DSTS_DEVCTRLHLT)
1451 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1453 ? dwc->gadget_driver->function : "no-function",
1454 is_on ? "connect" : "disconnect");
1459 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1461 struct dwc3 *dwc = gadget_to_dwc(g);
1462 unsigned long flags;
1467 spin_lock_irqsave(&dwc->lock, flags);
1468 ret = dwc3_gadget_run_stop(dwc, is_on);
1469 spin_unlock_irqrestore(&dwc->lock, flags);
1474 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1478 /* Enable all but Start and End of Frame IRQs */
1479 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1480 DWC3_DEVTEN_EVNTOVERFLOWEN |
1481 DWC3_DEVTEN_CMDCMPLTEN |
1482 DWC3_DEVTEN_ERRTICERREN |
1483 DWC3_DEVTEN_WKUPEVTEN |
1484 DWC3_DEVTEN_ULSTCNGEN |
1485 DWC3_DEVTEN_CONNECTDONEEN |
1486 DWC3_DEVTEN_USBRSTEN |
1487 DWC3_DEVTEN_DISCONNEVTEN);
1489 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1492 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1494 /* mask all interrupts */
1495 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1498 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1499 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1501 static int dwc3_gadget_start(struct usb_gadget *g,
1502 struct usb_gadget_driver *driver)
1504 struct dwc3 *dwc = gadget_to_dwc(g);
1505 struct dwc3_ep *dep;
1506 unsigned long flags;
1511 spin_lock_irqsave(&dwc->lock, flags);
1513 if (dwc->gadget_driver) {
1514 dev_err(dwc->dev, "%s is already bound to %s\n",
1516 dwc->gadget_driver->driver.name);
1521 dwc->gadget_driver = driver;
1523 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1524 reg &= ~(DWC3_DCFG_SPEED_MASK);
1527 * WORKAROUND: DWC3 revision < 2.20a have an issue
1528 * which would cause metastability state on Run/Stop
1529 * bit if we try to force the IP to USB2-only mode.
1531 * Because of that, we cannot configure the IP to any
1532 * speed other than the SuperSpeed
1536 * STAR#9000525659: Clock Domain Crossing on DCTL in
1539 if (dwc->revision < DWC3_REVISION_220A)
1540 reg |= DWC3_DCFG_SUPERSPEED;
1542 reg |= dwc->maximum_speed;
1543 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1545 dwc->start_config_issued = false;
1547 /* Start with SuperSpeed Default */
1548 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1551 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1553 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1558 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1560 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1564 /* begin to receive SETUP packets */
1565 dwc->ep0state = EP0_SETUP_PHASE;
1566 dwc3_ep0_out_start(dwc);
1568 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1569 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1570 IRQF_SHARED | IRQF_ONESHOT, "dwc3", dwc);
1572 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1577 dwc3_gadget_enable_irq(dwc);
1579 spin_unlock_irqrestore(&dwc->lock, flags);
1584 __dwc3_gadget_ep_disable(dwc->eps[0]);
1587 spin_unlock_irqrestore(&dwc->lock, flags);
1592 static int dwc3_gadget_stop(struct usb_gadget *g,
1593 struct usb_gadget_driver *driver)
1595 struct dwc3 *dwc = gadget_to_dwc(g);
1596 unsigned long flags;
1599 spin_lock_irqsave(&dwc->lock, flags);
1601 dwc3_gadget_disable_irq(dwc);
1602 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1605 __dwc3_gadget_ep_disable(dwc->eps[0]);
1606 __dwc3_gadget_ep_disable(dwc->eps[1]);
1608 dwc->gadget_driver = NULL;
1610 spin_unlock_irqrestore(&dwc->lock, flags);
1615 static const struct usb_gadget_ops dwc3_gadget_ops = {
1616 .get_frame = dwc3_gadget_get_frame,
1617 .wakeup = dwc3_gadget_wakeup,
1618 .set_selfpowered = dwc3_gadget_set_selfpowered,
1619 .pullup = dwc3_gadget_pullup,
1620 .udc_start = dwc3_gadget_start,
1621 .udc_stop = dwc3_gadget_stop,
1624 /* -------------------------------------------------------------------------- */
1626 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1627 u8 num, u32 direction)
1629 struct dwc3_ep *dep;
1632 for (i = 0; i < num; i++) {
1633 u8 epnum = (i << 1) | (!!direction);
1635 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1637 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1643 dep->number = epnum;
1644 dwc->eps[epnum] = dep;
1646 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1647 (epnum & 1) ? "in" : "out");
1649 dep->endpoint.name = dep->name;
1650 dep->direction = (epnum & 1);
1652 if (epnum == 0 || epnum == 1) {
1653 dep->endpoint.maxpacket = 512;
1654 dep->endpoint.maxburst = 1;
1655 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1657 dwc->gadget.ep0 = &dep->endpoint;
1661 dep->endpoint.maxpacket = 1024;
1662 dep->endpoint.max_streams = 15;
1663 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1664 list_add_tail(&dep->endpoint.ep_list,
1665 &dwc->gadget.ep_list);
1667 ret = dwc3_alloc_trb_pool(dep);
1672 INIT_LIST_HEAD(&dep->request_list);
1673 INIT_LIST_HEAD(&dep->req_queued);
1679 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1683 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1685 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1687 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1691 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1693 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1700 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1702 struct dwc3_ep *dep;
1705 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1706 dep = dwc->eps[epnum];
1710 dwc3_free_trb_pool(dep);
1712 if (epnum != 0 && epnum != 1)
1713 list_del(&dep->endpoint.ep_list);
1719 /* -------------------------------------------------------------------------- */
1721 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1722 struct dwc3_request *req, struct dwc3_trb *trb,
1723 const struct dwc3_event_depevt *event, int status)
1726 unsigned int s_pkt = 0;
1727 unsigned int trb_status;
1729 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1731 * We continue despite the error. There is not much we
1732 * can do. If we don't clean it up we loop forever. If
1733 * we skip the TRB then it gets overwritten after a
1734 * while since we use them in a ring buffer. A BUG()
1735 * would help. Lets hope that if this occurs, someone
1736 * fixes the root cause instead of looking away :)
1738 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1740 count = trb->size & DWC3_TRB_SIZE_MASK;
1742 if (dep->direction) {
1744 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1745 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1746 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1749 * If missed isoc occurred and there is
1750 * no request queued then issue END
1751 * TRANSFER, so that core generates
1752 * next xfernotready and we will issue
1753 * a fresh START TRANSFER.
1754 * If there are still queued request
1755 * then wait, do not issue either END
1756 * or UPDATE TRANSFER, just attach next
1757 * request in request_list during
1758 * giveback.If any future queued request
1759 * is successfully transferred then we
1760 * will issue UPDATE TRANSFER for all
1761 * request in the request_list.
1763 dep->flags |= DWC3_EP_MISSED_ISOC;
1765 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1767 status = -ECONNRESET;
1770 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1773 if (count && (event->status & DEPEVT_STATUS_SHORT))
1778 * We assume here we will always receive the entire data block
1779 * which we should receive. Meaning, if we program RX to
1780 * receive 4K but we receive only 2K, we assume that's all we
1781 * should receive and we simply bounce the request back to the
1782 * gadget driver for further processing.
1784 req->request.actual += req->request.length - count;
1787 if ((event->status & DEPEVT_STATUS_LST) &&
1788 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1789 DWC3_TRB_CTRL_HWO)))
1791 if ((event->status & DEPEVT_STATUS_IOC) &&
1792 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1797 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1798 const struct dwc3_event_depevt *event, int status)
1800 struct dwc3_request *req;
1801 struct dwc3_trb *trb;
1807 req = next_request(&dep->req_queued);
1814 slot = req->start_slot + i;
1815 if ((slot == DWC3_TRB_NUM - 1) &&
1816 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1818 slot %= DWC3_TRB_NUM;
1819 trb = &dep->trb_pool[slot];
1821 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1825 }while (++i < req->request.num_mapped_sgs);
1827 dwc3_gadget_giveback(dep, req, status);
1833 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1834 list_empty(&dep->req_queued)) {
1835 if (list_empty(&dep->request_list)) {
1837 * If there is no entry in request list then do
1838 * not issue END TRANSFER now. Just set PENDING
1839 * flag, so that END TRANSFER is issued when an
1840 * entry is added into request list.
1842 dep->flags = DWC3_EP_PENDING_REQUEST;
1844 dwc3_stop_active_transfer(dwc, dep->number);
1845 dep->flags = DWC3_EP_ENABLED;
1850 if ((event->status & DEPEVT_STATUS_IOC) &&
1851 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1856 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1857 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1860 unsigned status = 0;
1863 if (event->status & DEPEVT_STATUS_BUSERR)
1864 status = -ECONNRESET;
1866 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1868 dep->flags &= ~DWC3_EP_BUSY;
1871 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1872 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1874 if (dwc->revision < DWC3_REVISION_183A) {
1878 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1881 if (!(dep->flags & DWC3_EP_ENABLED))
1884 if (!list_empty(&dep->req_queued))
1888 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1890 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1896 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1897 const struct dwc3_event_depevt *event)
1899 struct dwc3_ep *dep;
1900 u8 epnum = event->endpoint_number;
1902 dep = dwc->eps[epnum];
1904 if (!(dep->flags & DWC3_EP_ENABLED))
1907 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1908 dwc3_ep_event_string(event->endpoint_event));
1910 if (epnum == 0 || epnum == 1) {
1911 dwc3_ep0_interrupt(dwc, event);
1915 switch (event->endpoint_event) {
1916 case DWC3_DEPEVT_XFERCOMPLETE:
1917 dep->resource_index = 0;
1919 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1920 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1925 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1927 case DWC3_DEPEVT_XFERINPROGRESS:
1928 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1929 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1934 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1936 case DWC3_DEPEVT_XFERNOTREADY:
1937 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1938 dwc3_gadget_start_isoc(dwc, dep, event);
1942 dev_vdbg(dwc->dev, "%s: reason %s\n",
1943 dep->name, event->status &
1944 DEPEVT_STATUS_TRANSFER_ACTIVE
1946 : "Transfer Not Active");
1948 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1949 if (!ret || ret == -EBUSY)
1952 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1957 case DWC3_DEPEVT_STREAMEVT:
1958 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1959 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1964 switch (event->status) {
1965 case DEPEVT_STREAMEVT_FOUND:
1966 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1970 case DEPEVT_STREAMEVT_NOTFOUND:
1973 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1976 case DWC3_DEPEVT_RXTXFIFOEVT:
1977 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1979 case DWC3_DEPEVT_EPCMDCMPLT:
1980 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1985 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1987 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1988 spin_unlock(&dwc->lock);
1989 dwc->gadget_driver->disconnect(&dwc->gadget);
1990 spin_lock(&dwc->lock);
1994 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1996 struct dwc3_ep *dep;
1997 struct dwc3_gadget_ep_cmd_params params;
2001 dep = dwc->eps[epnum];
2003 if (!dep->resource_index)
2007 * NOTICE: We are violating what the Databook says about the
2008 * EndTransfer command. Ideally we would _always_ wait for the
2009 * EndTransfer Command Completion IRQ, but that's causing too
2010 * much trouble synchronizing between us and gadget driver.
2012 * We have discussed this with the IP Provider and it was
2013 * suggested to giveback all requests here, but give HW some
2014 * extra time to synchronize with the interconnect. We're using
2015 * an arbitraty 100us delay for that.
2017 * Note also that a similar handling was tested by Synopsys
2018 * (thanks a lot Paul) and nothing bad has come out of it.
2019 * In short, what we're doing is:
2021 * - Issue EndTransfer WITH CMDIOC bit set
2025 cmd = DWC3_DEPCMD_ENDTRANSFER;
2026 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
2027 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2028 memset(¶ms, 0, sizeof(params));
2029 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2031 dep->resource_index = 0;
2032 dep->flags &= ~DWC3_EP_BUSY;
2036 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2040 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2041 struct dwc3_ep *dep;
2043 dep = dwc->eps[epnum];
2047 if (!(dep->flags & DWC3_EP_ENABLED))
2050 dwc3_remove_requests(dwc, dep);
2054 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2058 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2059 struct dwc3_ep *dep;
2060 struct dwc3_gadget_ep_cmd_params params;
2063 dep = dwc->eps[epnum];
2067 if (!(dep->flags & DWC3_EP_STALL))
2070 dep->flags &= ~DWC3_EP_STALL;
2072 memset(¶ms, 0, sizeof(params));
2073 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2074 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2079 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2083 dev_vdbg(dwc->dev, "%s\n", __func__);
2085 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2086 reg &= ~DWC3_DCTL_INITU1ENA;
2087 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2089 reg &= ~DWC3_DCTL_INITU2ENA;
2090 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2092 dwc3_disconnect_gadget(dwc);
2093 dwc->start_config_issued = false;
2095 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2096 dwc->setup_packet_pending = false;
2099 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
2103 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
2106 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
2108 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
2110 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
2113 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
2117 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2120 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
2122 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2124 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2127 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2131 dev_vdbg(dwc->dev, "%s\n", __func__);
2134 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2135 * would cause a missing Disconnect Event if there's a
2136 * pending Setup Packet in the FIFO.
2138 * There's no suggested workaround on the official Bug
2139 * report, which states that "unless the driver/application
2140 * is doing any special handling of a disconnect event,
2141 * there is no functional issue".
2143 * Unfortunately, it turns out that we _do_ some special
2144 * handling of a disconnect event, namely complete all
2145 * pending transfers, notify gadget driver of the
2146 * disconnection, and so on.
2148 * Our suggested workaround is to follow the Disconnect
2149 * Event steps here, instead, based on a setup_packet_pending
2150 * flag. Such flag gets set whenever we have a XferNotReady
2151 * event on EP0 and gets cleared on XferComplete for the
2156 * STAR#9000466709: RTL: Device : Disconnect event not
2157 * generated if setup packet pending in FIFO
2159 if (dwc->revision < DWC3_REVISION_188A) {
2160 if (dwc->setup_packet_pending)
2161 dwc3_gadget_disconnect_interrupt(dwc);
2164 /* after reset -> Default State */
2165 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2167 /* Recent versions support automatic phy suspend and don't need this */
2168 if (dwc->revision < DWC3_REVISION_194A) {
2170 dwc3_gadget_usb2_phy_suspend(dwc, false);
2171 dwc3_gadget_usb3_phy_suspend(dwc, false);
2174 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2175 dwc3_disconnect_gadget(dwc);
2177 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2178 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2179 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2180 dwc->test_mode = false;
2182 dwc3_stop_active_transfers(dwc);
2183 dwc3_clear_stall_all_ep(dwc);
2184 dwc->start_config_issued = false;
2186 /* Reset device address to zero */
2187 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2188 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2189 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2192 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2195 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2198 * We change the clock only at SS but I dunno why I would want to do
2199 * this. Maybe it becomes part of the power saving plan.
2202 if (speed != DWC3_DSTS_SUPERSPEED)
2206 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2207 * each time on Connect Done.
2212 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2213 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2214 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2217 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2220 case USB_SPEED_SUPER:
2221 dwc3_gadget_usb2_phy_suspend(dwc, true);
2223 case USB_SPEED_HIGH:
2224 case USB_SPEED_FULL:
2226 dwc3_gadget_usb3_phy_suspend(dwc, true);
2231 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2233 struct dwc3_ep *dep;
2238 dev_vdbg(dwc->dev, "%s\n", __func__);
2240 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2241 speed = reg & DWC3_DSTS_CONNECTSPD;
2244 dwc3_update_ram_clk_sel(dwc, speed);
2247 case DWC3_DCFG_SUPERSPEED:
2249 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2250 * would cause a missing USB3 Reset event.
2252 * In such situations, we should force a USB3 Reset
2253 * event by calling our dwc3_gadget_reset_interrupt()
2258 * STAR#9000483510: RTL: SS : USB3 reset event may
2259 * not be generated always when the link enters poll
2261 if (dwc->revision < DWC3_REVISION_190A)
2262 dwc3_gadget_reset_interrupt(dwc);
2264 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2265 dwc->gadget.ep0->maxpacket = 512;
2266 dwc->gadget.speed = USB_SPEED_SUPER;
2268 case DWC3_DCFG_HIGHSPEED:
2269 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2270 dwc->gadget.ep0->maxpacket = 64;
2271 dwc->gadget.speed = USB_SPEED_HIGH;
2273 case DWC3_DCFG_FULLSPEED2:
2274 case DWC3_DCFG_FULLSPEED1:
2275 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2276 dwc->gadget.ep0->maxpacket = 64;
2277 dwc->gadget.speed = USB_SPEED_FULL;
2279 case DWC3_DCFG_LOWSPEED:
2280 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2281 dwc->gadget.ep0->maxpacket = 8;
2282 dwc->gadget.speed = USB_SPEED_LOW;
2286 /* Enable USB2 LPM Capability */
2288 if ((dwc->revision > DWC3_REVISION_194A)
2289 && (speed != DWC3_DCFG_SUPERSPEED)) {
2290 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2291 reg |= DWC3_DCFG_LPM_CAP;
2292 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2294 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2295 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2298 * TODO: This should be configurable. For now using
2299 * maximum allowed HIRD threshold value of 0b1100
2301 reg |= DWC3_DCTL_HIRD_THRES(12);
2303 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2306 /* Recent versions support automatic phy suspend and don't need this */
2307 if (dwc->revision < DWC3_REVISION_194A) {
2308 /* Suspend unneeded PHY */
2309 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2313 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2315 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2320 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2322 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2327 * Configure PHY via GUSB3PIPECTLn if required.
2329 * Update GTXFIFOSIZn
2331 * In both cases reset values should be sufficient.
2335 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2337 dev_vdbg(dwc->dev, "%s\n", __func__);
2340 * TODO take core out of low power mode when that's
2344 dwc->gadget_driver->resume(&dwc->gadget);
2347 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2348 unsigned int evtinfo)
2350 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2351 unsigned int pwropt;
2354 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2355 * Hibernation mode enabled which would show up when device detects
2356 * host-initiated U3 exit.
2358 * In that case, device will generate a Link State Change Interrupt
2359 * from U3 to RESUME which is only necessary if Hibernation is
2362 * There are no functional changes due to such spurious event and we
2363 * just need to ignore it.
2367 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2370 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2371 if ((dwc->revision < DWC3_REVISION_250A) &&
2372 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2373 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2374 (next == DWC3_LINK_STATE_RESUME)) {
2375 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2381 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2382 * on the link partner, the USB session might do multiple entry/exit
2383 * of low power states before a transfer takes place.
2385 * Due to this problem, we might experience lower throughput. The
2386 * suggested workaround is to disable DCTL[12:9] bits if we're
2387 * transitioning from U1/U2 to U0 and enable those bits again
2388 * after a transfer completes and there are no pending transfers
2389 * on any of the enabled endpoints.
2391 * This is the first half of that workaround.
2395 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2396 * core send LGO_Ux entering U0
2398 if (dwc->revision < DWC3_REVISION_183A) {
2399 if (next == DWC3_LINK_STATE_U0) {
2403 switch (dwc->link_state) {
2404 case DWC3_LINK_STATE_U1:
2405 case DWC3_LINK_STATE_U2:
2406 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2407 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2408 | DWC3_DCTL_ACCEPTU2ENA
2409 | DWC3_DCTL_INITU1ENA
2410 | DWC3_DCTL_ACCEPTU1ENA);
2413 dwc->u1u2 = reg & u1u2;
2417 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2426 dwc->link_state = next;
2428 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2431 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2432 const struct dwc3_event_devt *event)
2434 switch (event->type) {
2435 case DWC3_DEVICE_EVENT_DISCONNECT:
2436 dwc3_gadget_disconnect_interrupt(dwc);
2438 case DWC3_DEVICE_EVENT_RESET:
2439 dwc3_gadget_reset_interrupt(dwc);
2441 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2442 dwc3_gadget_conndone_interrupt(dwc);
2444 case DWC3_DEVICE_EVENT_WAKEUP:
2445 dwc3_gadget_wakeup_interrupt(dwc);
2447 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2448 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2450 case DWC3_DEVICE_EVENT_EOPF:
2451 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2453 case DWC3_DEVICE_EVENT_SOF:
2454 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2456 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2457 dev_vdbg(dwc->dev, "Erratic Error\n");
2459 case DWC3_DEVICE_EVENT_CMD_CMPL:
2460 dev_vdbg(dwc->dev, "Command Complete\n");
2462 case DWC3_DEVICE_EVENT_OVERFLOW:
2463 dev_vdbg(dwc->dev, "Overflow\n");
2466 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2470 static void dwc3_process_event_entry(struct dwc3 *dwc,
2471 const union dwc3_event *event)
2473 /* Endpoint IRQ, handle it and return early */
2474 if (event->type.is_devspec == 0) {
2476 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2479 switch (event->type.type) {
2480 case DWC3_EVENT_TYPE_DEV:
2481 dwc3_gadget_interrupt(dwc, &event->devt);
2483 /* REVISIT what to do with Carkit and I2C events ? */
2485 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2489 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2491 struct dwc3 *dwc = _dwc;
2492 unsigned long flags;
2493 irqreturn_t ret = IRQ_NONE;
2496 spin_lock_irqsave(&dwc->lock, flags);
2498 for (i = 0; i < dwc->num_event_buffers; i++) {
2499 struct dwc3_event_buffer *evt;
2502 evt = dwc->ev_buffs[i];
2505 if (!(evt->flags & DWC3_EVENT_PENDING))
2509 union dwc3_event event;
2511 event.raw = *(u32 *) (evt->buf + evt->lpos);
2513 dwc3_process_event_entry(dwc, &event);
2516 * FIXME we wrap around correctly to the next entry as
2517 * almost all entries are 4 bytes in size. There is one
2518 * entry which has 12 bytes which is a regular entry
2519 * followed by 8 bytes data. ATM I don't know how
2520 * things are organized if we get next to the a
2521 * boundary so I worry about that once we try to handle
2524 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2527 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), 4);
2531 evt->flags &= ~DWC3_EVENT_PENDING;
2535 spin_unlock_irqrestore(&dwc->lock, flags);
2540 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2542 struct dwc3_event_buffer *evt;
2545 evt = dwc->ev_buffs[buf];
2547 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2548 count &= DWC3_GEVNTCOUNT_MASK;
2553 evt->flags |= DWC3_EVENT_PENDING;
2555 return IRQ_WAKE_THREAD;
2558 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2560 struct dwc3 *dwc = _dwc;
2562 irqreturn_t ret = IRQ_NONE;
2564 spin_lock(&dwc->lock);
2566 for (i = 0; i < dwc->num_event_buffers; i++) {
2569 status = dwc3_process_event_buf(dwc, i);
2570 if (status == IRQ_WAKE_THREAD)
2574 spin_unlock(&dwc->lock);
2580 * dwc3_gadget_init - Initializes gadget related registers
2581 * @dwc: pointer to our controller context structure
2583 * Returns 0 on success otherwise negative errno.
2585 int dwc3_gadget_init(struct dwc3 *dwc)
2590 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2591 &dwc->ctrl_req_addr, GFP_KERNEL);
2592 if (!dwc->ctrl_req) {
2593 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2598 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2599 &dwc->ep0_trb_addr, GFP_KERNEL);
2600 if (!dwc->ep0_trb) {
2601 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2606 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2607 if (!dwc->setup_buf) {
2608 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2613 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2614 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2616 if (!dwc->ep0_bounce) {
2617 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2622 dwc->gadget.ops = &dwc3_gadget_ops;
2623 dwc->gadget.max_speed = USB_SPEED_SUPER;
2624 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2625 dwc->gadget.sg_supported = true;
2626 dwc->gadget.name = "dwc3-gadget";
2629 * REVISIT: Here we should clear all pending IRQs to be
2630 * sure we're starting from a well known location.
2633 ret = dwc3_gadget_init_endpoints(dwc);
2637 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2638 reg |= DWC3_DCFG_LPM_CAP;
2639 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2641 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2642 if (dwc->revision >= DWC3_REVISION_194A) {
2643 dwc3_gadget_usb2_phy_suspend(dwc, false);
2644 dwc3_gadget_usb3_phy_suspend(dwc, false);
2647 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2649 dev_err(dwc->dev, "failed to register udc\n");
2656 dwc3_gadget_free_endpoints(dwc);
2659 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2660 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2663 kfree(dwc->setup_buf);
2666 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2667 dwc->ep0_trb, dwc->ep0_trb_addr);
2670 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2671 dwc->ctrl_req, dwc->ctrl_req_addr);
2677 /* -------------------------------------------------------------------------- */
2679 void dwc3_gadget_exit(struct dwc3 *dwc)
2681 usb_del_gadget_udc(&dwc->gadget);
2683 dwc3_gadget_free_endpoints(dwc);
2685 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2686 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2688 kfree(dwc->setup_buf);
2690 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2691 dwc->ep0_trb, dwc->ep0_trb_addr);
2693 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2694 dwc->ctrl_req, dwc->ctrl_req_addr);
2697 int dwc3_gadget_prepare(struct dwc3 *dwc)
2699 if (dwc->pullups_connected)
2700 dwc3_gadget_disable_irq(dwc);
2705 void dwc3_gadget_complete(struct dwc3 *dwc)
2707 if (dwc->pullups_connected) {
2708 dwc3_gadget_enable_irq(dwc);
2709 dwc3_gadget_run_stop(dwc, true);
2713 int dwc3_gadget_suspend(struct dwc3 *dwc)
2715 __dwc3_gadget_ep_disable(dwc->eps[0]);
2716 __dwc3_gadget_ep_disable(dwc->eps[1]);
2718 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2723 int dwc3_gadget_resume(struct dwc3 *dwc)
2725 struct dwc3_ep *dep;
2728 /* Start with SuperSpeed Default */
2729 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2732 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2737 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2741 /* begin to receive SETUP packets */
2742 dwc->ep0state = EP0_SETUP_PHASE;
2743 dwc3_ep0_out_start(dwc);
2745 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2750 __dwc3_gadget_ep_disable(dwc->eps[0]);