2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
156 static void dwc3_ep_inc_trb(u8 *index)
159 if (*index == (DWC3_TRB_NUM - 1))
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
170 dwc3_ep_inc_trb(&dep->trb_dequeue);
173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
176 struct dwc3 *dwc = dep->dwc;
182 dwc3_ep_inc_deq(dep);
183 } while(++i < req->request.num_mapped_sgs);
184 req->started = false;
186 list_del(&req->list);
189 if (req->request.status == -EINPROGRESS)
190 req->request.status = status;
192 if (dwc->ep0_bounced && dep->number == 0)
193 dwc->ep0_bounced = false;
195 usb_gadget_unmap_request(&dwc->gadget, &req->request,
198 trace_dwc3_gadget_giveback(req);
200 spin_unlock(&dwc->lock);
201 usb_gadget_giveback_request(&dep->endpoint, &req->request);
202 spin_lock(&dwc->lock);
205 pm_runtime_put(dwc->dev);
208 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
215 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
216 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
219 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
220 if (!(reg & DWC3_DGCMD_CMDACT)) {
221 status = DWC3_DGCMD_STATUS(reg);
233 trace_dwc3_gadget_generic_cmd(cmd, param, status);
238 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
241 struct dwc3_gadget_ep_cmd_params *params)
243 struct dwc3 *dwc = dep->dwc;
252 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
253 * we're issuing an endpoint command, we must check if
254 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
256 * We will also set SUSPHY bit to what it was before returning as stated
257 * by the same section on Synopsys databook.
259 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
260 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
261 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
263 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
264 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
268 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
271 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
272 dwc->link_state == DWC3_LINK_STATE_U2 ||
273 dwc->link_state == DWC3_LINK_STATE_U3);
275 if (unlikely(needs_wakeup)) {
276 ret = __dwc3_gadget_wakeup(dwc);
277 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
282 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
283 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
284 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
286 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
288 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
289 if (!(reg & DWC3_DEPCMD_CMDACT)) {
290 cmd_status = DWC3_DEPCMD_STATUS(reg);
292 switch (cmd_status) {
296 case DEPEVT_TRANSFER_NO_RESOURCE:
299 case DEPEVT_TRANSFER_BUS_EXPIRY:
301 * SW issues START TRANSFER command to
302 * isochronous ep with future frame interval. If
303 * future interval time has already passed when
304 * core receives the command, it will respond
305 * with an error status of 'Bus Expiry'.
307 * Instead of always returning -EINVAL, let's
308 * give a hint to the gadget driver that this is
309 * the case by returning -EAGAIN.
314 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
323 cmd_status = -ETIMEDOUT;
326 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
328 if (unlikely(susphy)) {
329 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
330 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
331 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
339 struct dwc3 *dwc = dep->dwc;
340 struct dwc3_gadget_ep_cmd_params params;
341 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
344 * As of core revision 2.60a the recommended programming model
345 * is to set the ClearPendIN bit when issuing a Clear Stall EP
346 * command for IN endpoints. This is to prevent an issue where
347 * some (non-compliant) hosts may not send ACK TPs for pending
348 * IN transfers due to a mishandled error condition. Synopsys
351 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
352 cmd |= DWC3_DEPCMD_CLEARPENDIN;
354 memset(¶ms, 0, sizeof(params));
356 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
359 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
360 struct dwc3_trb *trb)
362 u32 offset = (char *) trb - (char *) dep->trb_pool;
364 return dep->trb_pool_dma + offset;
367 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
369 struct dwc3 *dwc = dep->dwc;
374 dep->trb_pool = dma_alloc_coherent(dwc->dev,
375 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
376 &dep->trb_pool_dma, GFP_KERNEL);
377 if (!dep->trb_pool) {
378 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
386 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
388 struct dwc3 *dwc = dep->dwc;
390 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
391 dep->trb_pool, dep->trb_pool_dma);
393 dep->trb_pool = NULL;
394 dep->trb_pool_dma = 0;
397 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
400 * dwc3_gadget_start_config - Configure EP resources
401 * @dwc: pointer to our controller context structure
402 * @dep: endpoint that is being enabled
404 * The assignment of transfer resources cannot perfectly follow the
405 * data book due to the fact that the controller driver does not have
406 * all knowledge of the configuration in advance. It is given this
407 * information piecemeal by the composite gadget framework after every
408 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
409 * programming model in this scenario can cause errors. For two
412 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
413 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
414 * multiple interfaces.
416 * 2) The databook does not mention doing more DEPXFERCFG for new
417 * endpoint on alt setting (8.1.6).
419 * The following simplified method is used instead:
421 * All hardware endpoints can be assigned a transfer resource and this
422 * setting will stay persistent until either a core reset or
423 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
424 * do DEPXFERCFG for every hardware endpoint as well. We are
425 * guaranteed that there are as many transfer resources as endpoints.
427 * This function is called for each endpoint when it is being enabled
428 * but is triggered only when called for EP0-out, which always happens
429 * first, and which should only happen in one of the above conditions.
431 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
433 struct dwc3_gadget_ep_cmd_params params;
441 memset(¶ms, 0x00, sizeof(params));
442 cmd = DWC3_DEPCMD_DEPSTARTCFG;
444 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
448 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
449 struct dwc3_ep *dep = dwc->eps[i];
454 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
462 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
463 const struct usb_endpoint_descriptor *desc,
464 const struct usb_ss_ep_comp_descriptor *comp_desc,
465 bool modify, bool restore)
467 struct dwc3_gadget_ep_cmd_params params;
469 if (dev_WARN_ONCE(dwc->dev, modify && restore,
470 "Can't modify and restore\n"))
473 memset(¶ms, 0x00, sizeof(params));
475 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
476 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
478 /* Burst size is only needed in SuperSpeed mode */
479 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
480 u32 burst = dep->endpoint.maxburst;
481 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
485 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
486 } else if (restore) {
487 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
488 params.param2 |= dep->saved_state;
490 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
493 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
494 | DWC3_DEPCFG_XFER_NOT_READY_EN;
496 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
497 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
498 | DWC3_DEPCFG_STREAM_EVENT_EN;
499 dep->stream_capable = true;
502 if (!usb_endpoint_xfer_control(desc))
503 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
506 * We are doing 1:1 mapping for endpoints, meaning
507 * Physical Endpoints 2 maps to Logical Endpoint 2 and
508 * so on. We consider the direction bit as part of the physical
509 * endpoint number. So USB endpoint 0x81 is 0x03.
511 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
514 * We must use the lower 16 TX FIFOs even though
518 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
520 if (desc->bInterval) {
521 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
522 dep->interval = 1 << (desc->bInterval - 1);
525 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
528 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
530 struct dwc3_gadget_ep_cmd_params params;
532 memset(¶ms, 0x00, sizeof(params));
534 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
536 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
541 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
542 * @dep: endpoint to be initialized
543 * @desc: USB Endpoint Descriptor
545 * Caller should take care of locking
547 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
548 const struct usb_endpoint_descriptor *desc,
549 const struct usb_ss_ep_comp_descriptor *comp_desc,
550 bool modify, bool restore)
552 struct dwc3 *dwc = dep->dwc;
556 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
558 if (!(dep->flags & DWC3_EP_ENABLED)) {
559 ret = dwc3_gadget_start_config(dwc, dep);
564 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
569 if (!(dep->flags & DWC3_EP_ENABLED)) {
570 struct dwc3_trb *trb_st_hw;
571 struct dwc3_trb *trb_link;
573 dep->endpoint.desc = desc;
574 dep->comp_desc = comp_desc;
575 dep->type = usb_endpoint_type(desc);
576 dep->flags |= DWC3_EP_ENABLED;
578 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
579 reg |= DWC3_DALEPENA_EP(dep->number);
580 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
582 if (usb_endpoint_xfer_control(desc))
585 /* Initialize the TRB ring */
586 dep->trb_dequeue = 0;
587 dep->trb_enqueue = 0;
588 memset(dep->trb_pool, 0,
589 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
591 /* Link TRB. The HWO bit is never reset */
592 trb_st_hw = &dep->trb_pool[0];
594 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
595 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
596 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
597 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
598 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
604 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
605 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
607 struct dwc3_request *req;
609 dwc3_stop_active_transfer(dwc, dep->number, true);
611 /* - giveback all requests to gadget driver */
612 while (!list_empty(&dep->started_list)) {
613 req = next_request(&dep->started_list);
615 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
618 while (!list_empty(&dep->pending_list)) {
619 req = next_request(&dep->pending_list);
621 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
626 * __dwc3_gadget_ep_disable - Disables a HW endpoint
627 * @dep: the endpoint to disable
629 * This function also removes requests which are currently processed ny the
630 * hardware and those which are not yet scheduled.
631 * Caller should take care of locking.
633 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
635 struct dwc3 *dwc = dep->dwc;
638 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
640 dwc3_remove_requests(dwc, dep);
642 /* make sure HW endpoint isn't stalled */
643 if (dep->flags & DWC3_EP_STALL)
644 __dwc3_gadget_ep_set_halt(dep, 0, false);
646 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
647 reg &= ~DWC3_DALEPENA_EP(dep->number);
648 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
650 dep->stream_capable = false;
651 dep->endpoint.desc = NULL;
652 dep->comp_desc = NULL;
659 /* -------------------------------------------------------------------------- */
661 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
662 const struct usb_endpoint_descriptor *desc)
667 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
672 /* -------------------------------------------------------------------------- */
674 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
675 const struct usb_endpoint_descriptor *desc)
682 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
683 pr_debug("dwc3: invalid parameters\n");
687 if (!desc->wMaxPacketSize) {
688 pr_debug("dwc3: missing wMaxPacketSize\n");
692 dep = to_dwc3_ep(ep);
695 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
696 "%s is already enabled\n",
700 spin_lock_irqsave(&dwc->lock, flags);
701 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
702 spin_unlock_irqrestore(&dwc->lock, flags);
707 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
715 pr_debug("dwc3: invalid parameters\n");
719 dep = to_dwc3_ep(ep);
722 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
723 "%s is already disabled\n",
727 spin_lock_irqsave(&dwc->lock, flags);
728 ret = __dwc3_gadget_ep_disable(dep);
729 spin_unlock_irqrestore(&dwc->lock, flags);
734 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
737 struct dwc3_request *req;
738 struct dwc3_ep *dep = to_dwc3_ep(ep);
740 req = kzalloc(sizeof(*req), gfp_flags);
744 req->epnum = dep->number;
747 dep->allocated_requests++;
749 trace_dwc3_alloc_request(req);
751 return &req->request;
754 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
755 struct usb_request *request)
757 struct dwc3_request *req = to_dwc3_request(request);
758 struct dwc3_ep *dep = to_dwc3_ep(ep);
760 dep->allocated_requests--;
761 trace_dwc3_free_request(req);
766 * dwc3_prepare_one_trb - setup one TRB from one request
767 * @dep: endpoint for which this request is prepared
768 * @req: dwc3_request pointer
770 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
771 struct dwc3_request *req, dma_addr_t dma,
772 unsigned length, unsigned last, unsigned chain, unsigned node)
774 struct dwc3_trb *trb;
776 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
777 dep->name, req, (unsigned long long) dma,
778 length, last ? " last" : "",
779 chain ? " chain" : "");
782 trb = &dep->trb_pool[dep->trb_enqueue];
785 dwc3_gadget_move_started_request(req);
787 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
788 req->first_trb_index = dep->trb_enqueue;
791 dwc3_ep_inc_enq(dep);
793 trb->size = DWC3_TRB_SIZE_LENGTH(length);
794 trb->bpl = lower_32_bits(dma);
795 trb->bph = upper_32_bits(dma);
797 switch (usb_endpoint_type(dep->endpoint.desc)) {
798 case USB_ENDPOINT_XFER_CONTROL:
799 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
802 case USB_ENDPOINT_XFER_ISOC:
804 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
806 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
808 /* always enable Interrupt on Missed ISOC */
809 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
812 case USB_ENDPOINT_XFER_BULK:
813 case USB_ENDPOINT_XFER_INT:
814 trb->ctrl = DWC3_TRBCTL_NORMAL;
818 * This is only possible with faulty memory because we
819 * checked it already :)
824 /* always enable Continue on Short Packet */
825 trb->ctrl |= DWC3_TRB_CTRL_CSP;
827 if (!req->request.no_interrupt && !chain)
828 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
831 trb->ctrl |= DWC3_TRB_CTRL_LST;
834 trb->ctrl |= DWC3_TRB_CTRL_CHN;
836 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
837 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
839 trb->ctrl |= DWC3_TRB_CTRL_HWO;
841 dep->queued_requests++;
843 trace_dwc3_prepare_trb(dep, trb);
847 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
848 * @dep: The endpoint with the TRB ring
849 * @index: The index of the current TRB in the ring
851 * Returns the TRB prior to the one pointed to by the index. If the
852 * index is 0, we will wrap backwards, skip the link TRB, and return
853 * the one just before that.
855 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
858 index = DWC3_TRB_NUM - 2;
860 index = dep->trb_enqueue - 1;
862 return &dep->trb_pool[index];
865 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
867 struct dwc3_trb *tmp;
871 * If enqueue & dequeue are equal than it is either full or empty.
873 * One way to know for sure is if the TRB right before us has HWO bit
874 * set or not. If it has, then we're definitely full and can't fit any
875 * more transfers in our ring.
877 if (dep->trb_enqueue == dep->trb_dequeue) {
878 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
880 if (!(tmp->ctrl & DWC3_TRB_CTRL_HWO) ||
881 ((tmp->ctrl & DWC3_TRB_CTRL_HWO) &&
882 (tmp->ctrl & DWC3_TRB_CTRL_CSP) &&
884 return DWC3_TRB_NUM - 1;
889 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
890 trbs_left &= (DWC3_TRB_NUM - 1);
892 if (dep->trb_dequeue < dep->trb_enqueue)
898 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
899 struct dwc3_request *req, unsigned int trbs_left,
900 unsigned int more_coming)
902 struct usb_request *request = &req->request;
903 struct scatterlist *sg = request->sg;
904 struct scatterlist *s;
905 unsigned int last = false;
910 for_each_sg(sg, s, request->num_mapped_sgs, i) {
911 unsigned chain = true;
913 length = sg_dma_len(s);
914 dma = sg_dma_address(s);
917 if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
930 dwc3_prepare_one_trb(dep, req, dma, length,
938 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
939 struct dwc3_request *req, unsigned int trbs_left,
940 unsigned int more_coming)
942 unsigned int last = false;
946 dma = req->request.dma;
947 length = req->request.length;
952 /* Is this the last request? */
953 if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
956 dwc3_prepare_one_trb(dep, req, dma, length,
961 * dwc3_prepare_trbs - setup TRBs from requests
962 * @dep: endpoint for which requests are being prepared
964 * The function goes through the requests list and sets up TRBs for the
965 * transfers. The function returns once there are no more TRBs available or
966 * it runs out of requests.
968 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
970 struct dwc3_request *req, *n;
971 unsigned int more_coming;
974 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
976 trbs_left = dwc3_calc_trbs_left(dep);
980 more_coming = dep->allocated_requests - dep->queued_requests;
982 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
983 if (req->request.num_mapped_sgs > 0)
984 dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
987 dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
995 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
997 struct dwc3_gadget_ep_cmd_params params;
998 struct dwc3_request *req;
999 struct dwc3 *dwc = dep->dwc;
1004 starting = !(dep->flags & DWC3_EP_BUSY);
1006 dwc3_prepare_trbs(dep);
1007 req = next_request(&dep->started_list);
1009 dep->flags |= DWC3_EP_PENDING_REQUEST;
1013 memset(¶ms, 0, sizeof(params));
1016 params.param0 = upper_32_bits(req->trb_dma);
1017 params.param1 = lower_32_bits(req->trb_dma);
1018 cmd = DWC3_DEPCMD_STARTTRANSFER |
1019 DWC3_DEPCMD_PARAM(cmd_param);
1021 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1022 DWC3_DEPCMD_PARAM(dep->resource_index);
1025 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1028 * FIXME we need to iterate over the list of requests
1029 * here and stop, unmap, free and del each of the linked
1030 * requests instead of what we do now.
1032 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1034 list_del(&req->list);
1038 dep->flags |= DWC3_EP_BUSY;
1041 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1042 WARN_ON_ONCE(!dep->resource_index);
1048 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1049 struct dwc3_ep *dep, u32 cur_uf)
1053 if (list_empty(&dep->pending_list)) {
1054 dwc3_trace(trace_dwc3_gadget,
1055 "ISOC ep %s run out for requests",
1057 dep->flags |= DWC3_EP_PENDING_REQUEST;
1061 /* 4 micro frames in the future */
1062 uf = cur_uf + dep->interval * 4;
1064 __dwc3_gadget_kick_transfer(dep, uf);
1067 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1068 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1072 mask = ~(dep->interval - 1);
1073 cur_uf = event->parameters & mask;
1075 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1078 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1080 struct dwc3 *dwc = dep->dwc;
1083 if (!dep->endpoint.desc) {
1084 dwc3_trace(trace_dwc3_gadget,
1085 "trying to queue request %p to disabled %s",
1086 &req->request, dep->endpoint.name);
1090 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1091 &req->request, req->dep->name)) {
1092 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1093 &req->request, req->dep->name);
1097 pm_runtime_get(dwc->dev);
1099 req->request.actual = 0;
1100 req->request.status = -EINPROGRESS;
1101 req->direction = dep->direction;
1102 req->epnum = dep->number;
1104 trace_dwc3_ep_queue(req);
1107 * Per databook, the total size of buffer must be a multiple
1108 * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1109 * configed for endpoints in dwc3_gadget_set_ep_config(),
1110 * set to usb_endpoint_descriptor->wMaxPacketSize.
1112 if (dep->direction == 0 &&
1113 req->request.length % dep->endpoint.desc->wMaxPacketSize)
1114 req->request.length = roundup(req->request.length,
1115 dep->endpoint.desc->wMaxPacketSize);
1118 * We only add to our list of requests now and
1119 * start consuming the list once we get XferNotReady
1122 * That way, we avoid doing anything that we don't need
1123 * to do now and defer it until the point we receive a
1124 * particular token from the Host side.
1126 * This will also avoid Host cancelling URBs due to too
1129 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1134 list_add_tail(&req->list, &dep->pending_list);
1137 * If there are no pending requests and the endpoint isn't already
1138 * busy, we will just start the request straight away.
1140 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1141 * little bit faster.
1143 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1144 !usb_endpoint_xfer_int(dep->endpoint.desc)) {
1145 ret = __dwc3_gadget_kick_transfer(dep, 0);
1150 * There are a few special cases:
1152 * 1. XferNotReady with empty list of requests. We need to kick the
1153 * transfer here in that situation, otherwise we will be NAKing
1154 * forever. If we get XferNotReady before gadget driver has a
1155 * chance to queue a request, we will ACK the IRQ but won't be
1156 * able to receive the data until the next request is queued.
1157 * The following code is handling exactly that.
1160 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1162 * If xfernotready is already elapsed and it is a case
1163 * of isoc transfer, then issue END TRANSFER, so that
1164 * you can receive xfernotready again and can have
1165 * notion of current microframe.
1167 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1168 if (list_empty(&dep->started_list)) {
1169 dwc3_stop_active_transfer(dwc, dep->number, true);
1170 dep->flags = DWC3_EP_ENABLED;
1175 ret = __dwc3_gadget_kick_transfer(dep, 0);
1177 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1183 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1184 * kick the transfer here after queuing a request, otherwise the
1185 * core may not see the modified TRB(s).
1187 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1188 (dep->flags & DWC3_EP_BUSY) &&
1189 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1190 WARN_ON_ONCE(!dep->resource_index);
1191 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1196 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1197 * right away, otherwise host will not know we have streams to be
1200 if (dep->stream_capable)
1201 ret = __dwc3_gadget_kick_transfer(dep, 0);
1204 if (ret && ret != -EBUSY)
1205 dwc3_trace(trace_dwc3_gadget,
1206 "%s: failed to kick transfers",
1214 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1215 struct usb_request *request)
1217 dwc3_gadget_ep_free_request(ep, request);
1220 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1222 struct dwc3_request *req;
1223 struct usb_request *request;
1224 struct usb_ep *ep = &dep->endpoint;
1226 dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1227 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1231 request->length = 0;
1232 request->buf = dwc->zlp_buf;
1233 request->complete = __dwc3_gadget_ep_zlp_complete;
1235 req = to_dwc3_request(request);
1237 return __dwc3_gadget_ep_queue(dep, req);
1240 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1243 struct dwc3_request *req = to_dwc3_request(request);
1244 struct dwc3_ep *dep = to_dwc3_ep(ep);
1245 struct dwc3 *dwc = dep->dwc;
1247 unsigned long flags;
1251 spin_lock_irqsave(&dwc->lock, flags);
1252 ret = __dwc3_gadget_ep_queue(dep, req);
1255 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1256 * setting request->zero, instead of doing magic, we will just queue an
1257 * extra usb_request ourselves so that it gets handled the same way as
1258 * any other request.
1260 if (ret == 0 && request->zero && request->length &&
1261 (request->length % ep->desc->wMaxPacketSize == 0))
1262 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1264 spin_unlock_irqrestore(&dwc->lock, flags);
1269 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1270 struct usb_request *request)
1272 struct dwc3_request *req = to_dwc3_request(request);
1273 struct dwc3_request *r = NULL;
1275 struct dwc3_ep *dep = to_dwc3_ep(ep);
1276 struct dwc3 *dwc = dep->dwc;
1278 unsigned long flags;
1281 trace_dwc3_ep_dequeue(req);
1283 spin_lock_irqsave(&dwc->lock, flags);
1285 list_for_each_entry(r, &dep->pending_list, list) {
1291 list_for_each_entry(r, &dep->started_list, list) {
1296 /* wait until it is processed */
1297 dwc3_stop_active_transfer(dwc, dep->number, true);
1300 dev_err(dwc->dev, "request %p was not queued to %s\n",
1307 /* giveback the request */
1308 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1311 spin_unlock_irqrestore(&dwc->lock, flags);
1316 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1318 struct dwc3_gadget_ep_cmd_params params;
1319 struct dwc3 *dwc = dep->dwc;
1322 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1323 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1327 memset(¶ms, 0x00, sizeof(params));
1330 struct dwc3_trb *trb;
1332 unsigned transfer_in_flight;
1335 if (dep->number > 1)
1336 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1338 trb = &dwc->ep0_trb[dep->trb_enqueue];
1340 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1341 started = !list_empty(&dep->started_list);
1343 if (!protocol && ((dep->direction && transfer_in_flight) ||
1344 (!dep->direction && started))) {
1345 dwc3_trace(trace_dwc3_gadget,
1346 "%s: pending request, cannot halt",
1351 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1354 dev_err(dwc->dev, "failed to set STALL on %s\n",
1357 dep->flags |= DWC3_EP_STALL;
1360 ret = dwc3_send_clear_stall_ep_cmd(dep);
1362 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1365 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1371 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1373 struct dwc3_ep *dep = to_dwc3_ep(ep);
1374 struct dwc3 *dwc = dep->dwc;
1376 unsigned long flags;
1380 spin_lock_irqsave(&dwc->lock, flags);
1381 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1382 spin_unlock_irqrestore(&dwc->lock, flags);
1387 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1389 struct dwc3_ep *dep = to_dwc3_ep(ep);
1390 struct dwc3 *dwc = dep->dwc;
1391 unsigned long flags;
1394 spin_lock_irqsave(&dwc->lock, flags);
1395 dep->flags |= DWC3_EP_WEDGE;
1397 if (dep->number == 0 || dep->number == 1)
1398 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1400 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1401 spin_unlock_irqrestore(&dwc->lock, flags);
1406 /* -------------------------------------------------------------------------- */
1408 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1409 .bLength = USB_DT_ENDPOINT_SIZE,
1410 .bDescriptorType = USB_DT_ENDPOINT,
1411 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1414 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1415 .enable = dwc3_gadget_ep0_enable,
1416 .disable = dwc3_gadget_ep0_disable,
1417 .alloc_request = dwc3_gadget_ep_alloc_request,
1418 .free_request = dwc3_gadget_ep_free_request,
1419 .queue = dwc3_gadget_ep0_queue,
1420 .dequeue = dwc3_gadget_ep_dequeue,
1421 .set_halt = dwc3_gadget_ep0_set_halt,
1422 .set_wedge = dwc3_gadget_ep_set_wedge,
1425 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1426 .enable = dwc3_gadget_ep_enable,
1427 .disable = dwc3_gadget_ep_disable,
1428 .alloc_request = dwc3_gadget_ep_alloc_request,
1429 .free_request = dwc3_gadget_ep_free_request,
1430 .queue = dwc3_gadget_ep_queue,
1431 .dequeue = dwc3_gadget_ep_dequeue,
1432 .set_halt = dwc3_gadget_ep_set_halt,
1433 .set_wedge = dwc3_gadget_ep_set_wedge,
1436 /* -------------------------------------------------------------------------- */
1438 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1440 struct dwc3 *dwc = gadget_to_dwc(g);
1443 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1444 return DWC3_DSTS_SOFFN(reg);
1447 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1449 unsigned long timeout;
1458 * According to the Databook Remote wakeup request should
1459 * be issued only when the device is in early suspend state.
1461 * We can check that via USB Link State bits in DSTS register.
1463 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1465 speed = reg & DWC3_DSTS_CONNECTSPD;
1466 if (speed == DWC3_DSTS_SUPERSPEED) {
1467 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1471 link_state = DWC3_DSTS_USBLNKST(reg);
1473 switch (link_state) {
1474 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1475 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1478 dwc3_trace(trace_dwc3_gadget,
1479 "can't wakeup from '%s'",
1480 dwc3_gadget_link_string(link_state));
1484 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1486 dev_err(dwc->dev, "failed to put link in Recovery\n");
1490 /* Recent versions do this automatically */
1491 if (dwc->revision < DWC3_REVISION_194A) {
1492 /* write zeroes to Link Change Request */
1493 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1494 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1495 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1498 /* poll until Link State changes to ON */
1499 timeout = jiffies + msecs_to_jiffies(100);
1501 while (!time_after(jiffies, timeout)) {
1502 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1504 /* in HS, means ON */
1505 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1509 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1510 dev_err(dwc->dev, "failed to send remote wakeup\n");
1517 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1519 struct dwc3 *dwc = gadget_to_dwc(g);
1520 unsigned long flags;
1523 spin_lock_irqsave(&dwc->lock, flags);
1524 ret = __dwc3_gadget_wakeup(dwc);
1525 spin_unlock_irqrestore(&dwc->lock, flags);
1530 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1533 struct dwc3 *dwc = gadget_to_dwc(g);
1534 unsigned long flags;
1536 spin_lock_irqsave(&dwc->lock, flags);
1537 g->is_selfpowered = !!is_selfpowered;
1538 spin_unlock_irqrestore(&dwc->lock, flags);
1543 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1548 if (pm_runtime_suspended(dwc->dev))
1551 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1553 if (dwc->revision <= DWC3_REVISION_187A) {
1554 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1555 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1558 if (dwc->revision >= DWC3_REVISION_194A)
1559 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1560 reg |= DWC3_DCTL_RUN_STOP;
1562 if (dwc->has_hibernation)
1563 reg |= DWC3_DCTL_KEEP_CONNECT;
1565 dwc->pullups_connected = true;
1567 reg &= ~DWC3_DCTL_RUN_STOP;
1569 if (dwc->has_hibernation && !suspend)
1570 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1572 dwc->pullups_connected = false;
1575 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1578 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1579 reg &= DWC3_DSTS_DEVCTRLHLT;
1580 } while (--timeout && !(!is_on ^ !reg));
1585 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1587 ? dwc->gadget_driver->function : "no-function",
1588 is_on ? "connect" : "disconnect");
1593 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1595 struct dwc3 *dwc = gadget_to_dwc(g);
1596 unsigned long flags;
1601 spin_lock_irqsave(&dwc->lock, flags);
1602 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1603 spin_unlock_irqrestore(&dwc->lock, flags);
1608 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1612 /* Enable all but Start and End of Frame IRQs */
1613 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1614 DWC3_DEVTEN_EVNTOVERFLOWEN |
1615 DWC3_DEVTEN_CMDCMPLTEN |
1616 DWC3_DEVTEN_ERRTICERREN |
1617 DWC3_DEVTEN_WKUPEVTEN |
1618 DWC3_DEVTEN_ULSTCNGEN |
1619 DWC3_DEVTEN_CONNECTDONEEN |
1620 DWC3_DEVTEN_USBRSTEN |
1621 DWC3_DEVTEN_DISCONNEVTEN);
1623 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1626 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1628 /* mask all interrupts */
1629 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1632 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1633 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1636 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1637 * dwc: pointer to our context structure
1639 * The following looks like complex but it's actually very simple. In order to
1640 * calculate the number of packets we can burst at once on OUT transfers, we're
1641 * gonna use RxFIFO size.
1643 * To calculate RxFIFO size we need two numbers:
1644 * MDWIDTH = size, in bits, of the internal memory bus
1645 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1647 * Given these two numbers, the formula is simple:
1649 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1651 * 24 bytes is for 3x SETUP packets
1652 * 16 bytes is a clock domain crossing tolerance
1654 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1656 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1663 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1664 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1666 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1667 nump = min_t(u32, nump, 16);
1670 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1671 reg &= ~DWC3_DCFG_NUMP_MASK;
1672 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1673 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1676 static int __dwc3_gadget_start(struct dwc3 *dwc)
1678 struct dwc3_ep *dep;
1682 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1683 reg &= ~(DWC3_DCFG_SPEED_MASK);
1686 * WORKAROUND: DWC3 revision < 2.20a have an issue
1687 * which would cause metastability state on Run/Stop
1688 * bit if we try to force the IP to USB2-only mode.
1690 * Because of that, we cannot configure the IP to any
1691 * speed other than the SuperSpeed
1695 * STAR#9000525659: Clock Domain Crossing on DCTL in
1698 if (dwc->revision < DWC3_REVISION_220A) {
1699 reg |= DWC3_DCFG_SUPERSPEED;
1701 switch (dwc->maximum_speed) {
1703 reg |= DWC3_DCFG_LOWSPEED;
1705 case USB_SPEED_FULL:
1706 reg |= DWC3_DCFG_FULLSPEED1;
1708 case USB_SPEED_HIGH:
1709 reg |= DWC3_DCFG_HIGHSPEED;
1711 case USB_SPEED_SUPER: /* FALLTHROUGH */
1712 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1714 reg |= DWC3_DCFG_SUPERSPEED;
1717 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1720 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1721 * field instead of letting dwc3 itself calculate that automatically.
1723 * This way, we maximize the chances that we'll be able to get several
1724 * bursts of data without going through any sort of endpoint throttling.
1726 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1727 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1728 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1730 dwc3_gadget_setup_nump(dwc);
1732 /* Start with SuperSpeed Default */
1733 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1736 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1739 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1744 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1747 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1751 /* begin to receive SETUP packets */
1752 dwc->ep0state = EP0_SETUP_PHASE;
1753 dwc3_ep0_out_start(dwc);
1755 dwc3_gadget_enable_irq(dwc);
1760 __dwc3_gadget_ep_disable(dwc->eps[0]);
1766 static int dwc3_gadget_start(struct usb_gadget *g,
1767 struct usb_gadget_driver *driver)
1769 struct dwc3 *dwc = gadget_to_dwc(g);
1770 unsigned long flags;
1774 irq = dwc->irq_gadget;
1775 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1776 IRQF_SHARED, "dwc3", dwc->ev_buf);
1778 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1783 spin_lock_irqsave(&dwc->lock, flags);
1784 if (dwc->gadget_driver) {
1785 dev_err(dwc->dev, "%s is already bound to %s\n",
1787 dwc->gadget_driver->driver.name);
1792 dwc->gadget_driver = driver;
1794 if (pm_runtime_active(dwc->dev))
1795 __dwc3_gadget_start(dwc);
1797 spin_unlock_irqrestore(&dwc->lock, flags);
1802 spin_unlock_irqrestore(&dwc->lock, flags);
1809 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1811 if (pm_runtime_suspended(dwc->dev))
1814 dwc3_gadget_disable_irq(dwc);
1815 __dwc3_gadget_ep_disable(dwc->eps[0]);
1816 __dwc3_gadget_ep_disable(dwc->eps[1]);
1819 static int dwc3_gadget_stop(struct usb_gadget *g)
1821 struct dwc3 *dwc = gadget_to_dwc(g);
1822 unsigned long flags;
1824 spin_lock_irqsave(&dwc->lock, flags);
1825 __dwc3_gadget_stop(dwc);
1826 dwc->gadget_driver = NULL;
1827 spin_unlock_irqrestore(&dwc->lock, flags);
1829 free_irq(dwc->irq_gadget, dwc->ev_buf);
1834 static const struct usb_gadget_ops dwc3_gadget_ops = {
1835 .get_frame = dwc3_gadget_get_frame,
1836 .wakeup = dwc3_gadget_wakeup,
1837 .set_selfpowered = dwc3_gadget_set_selfpowered,
1838 .pullup = dwc3_gadget_pullup,
1839 .udc_start = dwc3_gadget_start,
1840 .udc_stop = dwc3_gadget_stop,
1843 /* -------------------------------------------------------------------------- */
1845 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1846 u8 num, u32 direction)
1848 struct dwc3_ep *dep;
1851 for (i = 0; i < num; i++) {
1852 u8 epnum = (i << 1) | (direction ? 1 : 0);
1854 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1859 dep->number = epnum;
1860 dep->direction = !!direction;
1861 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1862 dwc->eps[epnum] = dep;
1864 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1865 (epnum & 1) ? "in" : "out");
1867 dep->endpoint.name = dep->name;
1868 spin_lock_init(&dep->lock);
1870 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1872 if (epnum == 0 || epnum == 1) {
1873 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1874 dep->endpoint.maxburst = 1;
1875 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1877 dwc->gadget.ep0 = &dep->endpoint;
1881 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1882 dep->endpoint.max_streams = 15;
1883 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1884 list_add_tail(&dep->endpoint.ep_list,
1885 &dwc->gadget.ep_list);
1887 ret = dwc3_alloc_trb_pool(dep);
1892 if (epnum == 0 || epnum == 1) {
1893 dep->endpoint.caps.type_control = true;
1895 dep->endpoint.caps.type_iso = true;
1896 dep->endpoint.caps.type_bulk = true;
1897 dep->endpoint.caps.type_int = true;
1900 dep->endpoint.caps.dir_in = !!direction;
1901 dep->endpoint.caps.dir_out = !direction;
1903 INIT_LIST_HEAD(&dep->pending_list);
1904 INIT_LIST_HEAD(&dep->started_list);
1910 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1914 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1916 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1918 dwc3_trace(trace_dwc3_gadget,
1919 "failed to allocate OUT endpoints");
1923 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1925 dwc3_trace(trace_dwc3_gadget,
1926 "failed to allocate IN endpoints");
1933 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1935 struct dwc3_ep *dep;
1938 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1939 dep = dwc->eps[epnum];
1943 * Physical endpoints 0 and 1 are special; they form the
1944 * bi-directional USB endpoint 0.
1946 * For those two physical endpoints, we don't allocate a TRB
1947 * pool nor do we add them the endpoints list. Due to that, we
1948 * shouldn't do these two operations otherwise we would end up
1949 * with all sorts of bugs when removing dwc3.ko.
1951 if (epnum != 0 && epnum != 1) {
1952 dwc3_free_trb_pool(dep);
1953 list_del(&dep->endpoint.ep_list);
1960 /* -------------------------------------------------------------------------- */
1962 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1963 struct dwc3_request *req, struct dwc3_trb *trb,
1964 const struct dwc3_event_depevt *event, int status)
1967 unsigned int s_pkt = 0;
1968 unsigned int trb_status;
1970 dep->queued_requests--;
1971 trace_dwc3_complete_trb(dep, trb);
1973 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1975 * We continue despite the error. There is not much we
1976 * can do. If we don't clean it up we loop forever. If
1977 * we skip the TRB then it gets overwritten after a
1978 * while since we use them in a ring buffer. A BUG()
1979 * would help. Lets hope that if this occurs, someone
1980 * fixes the root cause instead of looking away :)
1982 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1984 count = trb->size & DWC3_TRB_SIZE_MASK;
1986 if (dep->direction) {
1988 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1989 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1990 dwc3_trace(trace_dwc3_gadget,
1991 "%s: incomplete IN transfer",
1994 * If missed isoc occurred and there is
1995 * no request queued then issue END
1996 * TRANSFER, so that core generates
1997 * next xfernotready and we will issue
1998 * a fresh START TRANSFER.
1999 * If there are still queued request
2000 * then wait, do not issue either END
2001 * or UPDATE TRANSFER, just attach next
2002 * request in pending_list during
2003 * giveback.If any future queued request
2004 * is successfully transferred then we
2005 * will issue UPDATE TRANSFER for all
2006 * request in the pending_list.
2008 dep->flags |= DWC3_EP_MISSED_ISOC;
2010 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2012 status = -ECONNRESET;
2015 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2018 if (count && (event->status & DEPEVT_STATUS_SHORT))
2024 if ((event->status & DEPEVT_STATUS_LST) &&
2025 (trb->ctrl & (DWC3_TRB_CTRL_LST |
2026 DWC3_TRB_CTRL_HWO)))
2028 if ((event->status & DEPEVT_STATUS_IOC) &&
2029 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2034 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2035 const struct dwc3_event_depevt *event, int status)
2037 struct dwc3_request *req;
2038 struct dwc3_trb *trb;
2045 req = next_request(&dep->started_list);
2046 if (WARN_ON_ONCE(!req))
2051 slot = req->first_trb_index + i;
2052 if (slot == DWC3_TRB_NUM - 1)
2054 slot %= DWC3_TRB_NUM;
2055 trb = &dep->trb_pool[slot];
2056 count += trb->size & DWC3_TRB_SIZE_MASK;
2059 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2063 } while (++i < req->request.num_mapped_sgs);
2066 * We assume here we will always receive the entire data block
2067 * which we should receive. Meaning, if we program RX to
2068 * receive 4K but we receive only 2K, we assume that's all we
2069 * should receive and we simply bounce the request back to the
2070 * gadget driver for further processing.
2072 req->request.actual += req->request.length - count;
2073 dwc3_gadget_giveback(dep, req, status);
2080 * Our endpoint might get disabled by another thread during
2081 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2082 * early on so DWC3_EP_BUSY flag gets cleared
2084 if (!dep->endpoint.desc)
2087 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2088 list_empty(&dep->started_list)) {
2089 if (list_empty(&dep->pending_list)) {
2091 * If there is no entry in request list then do
2092 * not issue END TRANSFER now. Just set PENDING
2093 * flag, so that END TRANSFER is issued when an
2094 * entry is added into request list.
2096 dep->flags = DWC3_EP_PENDING_REQUEST;
2098 dwc3_stop_active_transfer(dwc, dep->number, true);
2099 dep->flags = DWC3_EP_ENABLED;
2104 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2105 if ((event->status & DEPEVT_STATUS_IOC) &&
2106 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2111 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2112 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2114 unsigned status = 0;
2116 u32 is_xfer_complete;
2118 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2120 if (event->status & DEPEVT_STATUS_BUSERR)
2121 status = -ECONNRESET;
2123 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2124 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2125 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2126 dep->flags &= ~DWC3_EP_BUSY;
2129 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2130 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2132 if (dwc->revision < DWC3_REVISION_183A) {
2136 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2139 if (!(dep->flags & DWC3_EP_ENABLED))
2142 if (!list_empty(&dep->started_list))
2146 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2148 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2154 * Our endpoint might get disabled by another thread during
2155 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2156 * early on so DWC3_EP_BUSY flag gets cleared
2158 if (!dep->endpoint.desc)
2161 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2164 ret = __dwc3_gadget_kick_transfer(dep, 0);
2165 if (!ret || ret == -EBUSY)
2170 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2171 const struct dwc3_event_depevt *event)
2173 struct dwc3_ep *dep;
2174 u8 epnum = event->endpoint_number;
2176 dep = dwc->eps[epnum];
2178 if (!(dep->flags & DWC3_EP_ENABLED))
2181 if (epnum == 0 || epnum == 1) {
2182 if (!dwc->connected &&
2183 event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE)
2184 dwc->connected = true;
2185 dwc3_ep0_interrupt(dwc, event);
2189 switch (event->endpoint_event) {
2190 case DWC3_DEPEVT_XFERCOMPLETE:
2191 dep->resource_index = 0;
2193 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2194 dwc3_trace(trace_dwc3_gadget,
2195 "%s is an Isochronous endpoint",
2200 dwc3_endpoint_transfer_complete(dwc, dep, event);
2202 case DWC3_DEPEVT_XFERINPROGRESS:
2203 dwc3_endpoint_transfer_complete(dwc, dep, event);
2205 case DWC3_DEPEVT_XFERNOTREADY:
2206 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2207 dwc3_gadget_start_isoc(dwc, dep, event);
2212 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2214 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2215 dep->name, active ? "Transfer Active"
2216 : "Transfer Not Active");
2218 ret = __dwc3_gadget_kick_transfer(dep, 0);
2219 if (!ret || ret == -EBUSY)
2222 dwc3_trace(trace_dwc3_gadget,
2223 "%s: failed to kick transfers",
2228 case DWC3_DEPEVT_STREAMEVT:
2229 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2230 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2235 switch (event->status) {
2236 case DEPEVT_STREAMEVT_FOUND:
2237 dwc3_trace(trace_dwc3_gadget,
2238 "Stream %d found and started",
2242 case DEPEVT_STREAMEVT_NOTFOUND:
2245 dwc3_trace(trace_dwc3_gadget,
2246 "unable to find suitable stream");
2249 case DWC3_DEPEVT_RXTXFIFOEVT:
2250 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2252 case DWC3_DEPEVT_EPCMDCMPLT:
2253 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2258 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2260 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2261 spin_unlock(&dwc->lock);
2262 dwc->gadget_driver->disconnect(&dwc->gadget);
2263 spin_lock(&dwc->lock);
2267 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2269 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2270 spin_unlock(&dwc->lock);
2271 dwc->gadget_driver->suspend(&dwc->gadget);
2272 spin_lock(&dwc->lock);
2276 static void dwc3_resume_gadget(struct dwc3 *dwc)
2278 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2279 spin_unlock(&dwc->lock);
2280 dwc->gadget_driver->resume(&dwc->gadget);
2281 spin_lock(&dwc->lock);
2285 static void dwc3_reset_gadget(struct dwc3 *dwc)
2287 if (!dwc->gadget_driver)
2290 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2291 spin_unlock(&dwc->lock);
2292 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2293 spin_lock(&dwc->lock);
2297 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2299 struct dwc3_ep *dep;
2300 struct dwc3_gadget_ep_cmd_params params;
2304 dep = dwc->eps[epnum];
2306 if (!dep->resource_index)
2310 * NOTICE: We are violating what the Databook says about the
2311 * EndTransfer command. Ideally we would _always_ wait for the
2312 * EndTransfer Command Completion IRQ, but that's causing too
2313 * much trouble synchronizing between us and gadget driver.
2315 * We have discussed this with the IP Provider and it was
2316 * suggested to giveback all requests here, but give HW some
2317 * extra time to synchronize with the interconnect. We're using
2318 * an arbitrary 100us delay for that.
2320 * Note also that a similar handling was tested by Synopsys
2321 * (thanks a lot Paul) and nothing bad has come out of it.
2322 * In short, what we're doing is:
2324 * - Issue EndTransfer WITH CMDIOC bit set
2328 cmd = DWC3_DEPCMD_ENDTRANSFER;
2329 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2330 cmd |= DWC3_DEPCMD_CMDIOC;
2331 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2332 memset(¶ms, 0, sizeof(params));
2333 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2335 dep->resource_index = 0;
2336 dep->flags &= ~DWC3_EP_BUSY;
2340 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2344 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2345 struct dwc3_ep *dep;
2347 dep = dwc->eps[epnum];
2351 if (!(dep->flags & DWC3_EP_ENABLED))
2354 dwc3_remove_requests(dwc, dep);
2358 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2362 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2363 struct dwc3_ep *dep;
2366 dep = dwc->eps[epnum];
2370 if (!(dep->flags & DWC3_EP_STALL))
2373 dep->flags &= ~DWC3_EP_STALL;
2375 ret = dwc3_send_clear_stall_ep_cmd(dep);
2380 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2384 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2385 reg &= ~DWC3_DCTL_INITU1ENA;
2386 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2388 reg &= ~DWC3_DCTL_INITU2ENA;
2389 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2391 dwc3_disconnect_gadget(dwc);
2393 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2394 dwc->setup_packet_pending = false;
2395 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2397 dwc->connected = false;
2400 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2405 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2406 * would cause a missing Disconnect Event if there's a
2407 * pending Setup Packet in the FIFO.
2409 * There's no suggested workaround on the official Bug
2410 * report, which states that "unless the driver/application
2411 * is doing any special handling of a disconnect event,
2412 * there is no functional issue".
2414 * Unfortunately, it turns out that we _do_ some special
2415 * handling of a disconnect event, namely complete all
2416 * pending transfers, notify gadget driver of the
2417 * disconnection, and so on.
2419 * Our suggested workaround is to follow the Disconnect
2420 * Event steps here, instead, based on a setup_packet_pending
2421 * flag. Such flag gets set whenever we have a SETUP_PENDING
2422 * status for EP0 TRBs and gets cleared on XferComplete for the
2427 * STAR#9000466709: RTL: Device : Disconnect event not
2428 * generated if setup packet pending in FIFO
2430 if (dwc->revision < DWC3_REVISION_188A) {
2431 if (dwc->setup_packet_pending)
2432 dwc3_gadget_disconnect_interrupt(dwc);
2435 dwc3_reset_gadget(dwc);
2437 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2438 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2439 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2440 dwc->test_mode = false;
2442 dwc3_stop_active_transfers(dwc);
2443 dwc3_clear_stall_all_ep(dwc);
2445 /* Reset device address to zero */
2446 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2447 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2448 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2451 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2454 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2457 * We change the clock only at SS but I dunno why I would want to do
2458 * this. Maybe it becomes part of the power saving plan.
2461 if (speed != DWC3_DSTS_SUPERSPEED)
2465 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2466 * each time on Connect Done.
2471 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2472 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2473 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2476 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2478 struct dwc3_ep *dep;
2483 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2484 speed = reg & DWC3_DSTS_CONNECTSPD;
2487 dwc3_update_ram_clk_sel(dwc, speed);
2490 case DWC3_DSTS_SUPERSPEED:
2492 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2493 * would cause a missing USB3 Reset event.
2495 * In such situations, we should force a USB3 Reset
2496 * event by calling our dwc3_gadget_reset_interrupt()
2501 * STAR#9000483510: RTL: SS : USB3 reset event may
2502 * not be generated always when the link enters poll
2504 if (dwc->revision < DWC3_REVISION_190A)
2505 dwc3_gadget_reset_interrupt(dwc);
2507 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2508 dwc->gadget.ep0->maxpacket = 512;
2509 dwc->gadget.speed = USB_SPEED_SUPER;
2511 case DWC3_DSTS_HIGHSPEED:
2512 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2513 dwc->gadget.ep0->maxpacket = 64;
2514 dwc->gadget.speed = USB_SPEED_HIGH;
2516 case DWC3_DSTS_FULLSPEED2:
2517 case DWC3_DSTS_FULLSPEED1:
2518 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2519 dwc->gadget.ep0->maxpacket = 64;
2520 dwc->gadget.speed = USB_SPEED_FULL;
2522 case DWC3_DSTS_LOWSPEED:
2523 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2524 dwc->gadget.ep0->maxpacket = 8;
2525 dwc->gadget.speed = USB_SPEED_LOW;
2529 /* Enable USB2 LPM Capability */
2531 if ((dwc->revision > DWC3_REVISION_194A) &&
2532 (speed != DWC3_DSTS_SUPERSPEED)) {
2533 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2534 reg |= DWC3_DCFG_LPM_CAP;
2535 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2537 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2538 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2540 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2543 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2544 * DCFG.LPMCap is set, core responses with an ACK and the
2545 * BESL value in the LPM token is less than or equal to LPM
2548 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2549 && dwc->has_lpm_erratum,
2550 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2552 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2553 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2555 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2557 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2558 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2559 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2563 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2566 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2571 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2574 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2579 * Configure PHY via GUSB3PIPECTLn if required.
2581 * Update GTXFIFOSIZn
2583 * In both cases reset values should be sufficient.
2587 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2590 * TODO take core out of low power mode when that's
2594 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2595 spin_unlock(&dwc->lock);
2596 dwc->gadget_driver->resume(&dwc->gadget);
2597 spin_lock(&dwc->lock);
2601 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2602 unsigned int evtinfo)
2604 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2605 unsigned int pwropt;
2608 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2609 * Hibernation mode enabled which would show up when device detects
2610 * host-initiated U3 exit.
2612 * In that case, device will generate a Link State Change Interrupt
2613 * from U3 to RESUME which is only necessary if Hibernation is
2616 * There are no functional changes due to such spurious event and we
2617 * just need to ignore it.
2621 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2624 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2625 if ((dwc->revision < DWC3_REVISION_250A) &&
2626 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2627 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2628 (next == DWC3_LINK_STATE_RESUME)) {
2629 dwc3_trace(trace_dwc3_gadget,
2630 "ignoring transition U3 -> Resume");
2636 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2637 * on the link partner, the USB session might do multiple entry/exit
2638 * of low power states before a transfer takes place.
2640 * Due to this problem, we might experience lower throughput. The
2641 * suggested workaround is to disable DCTL[12:9] bits if we're
2642 * transitioning from U1/U2 to U0 and enable those bits again
2643 * after a transfer completes and there are no pending transfers
2644 * on any of the enabled endpoints.
2646 * This is the first half of that workaround.
2650 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2651 * core send LGO_Ux entering U0
2653 if (dwc->revision < DWC3_REVISION_183A) {
2654 if (next == DWC3_LINK_STATE_U0) {
2658 switch (dwc->link_state) {
2659 case DWC3_LINK_STATE_U1:
2660 case DWC3_LINK_STATE_U2:
2661 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2662 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2663 | DWC3_DCTL_ACCEPTU2ENA
2664 | DWC3_DCTL_INITU1ENA
2665 | DWC3_DCTL_ACCEPTU1ENA);
2668 dwc->u1u2 = reg & u1u2;
2672 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2682 case DWC3_LINK_STATE_U1:
2683 if (dwc->speed == USB_SPEED_SUPER)
2684 dwc3_suspend_gadget(dwc);
2686 case DWC3_LINK_STATE_U2:
2687 case DWC3_LINK_STATE_U3:
2688 dwc3_suspend_gadget(dwc);
2690 case DWC3_LINK_STATE_RESUME:
2691 dwc3_resume_gadget(dwc);
2698 dwc->link_state = next;
2701 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2702 unsigned int evtinfo)
2704 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2706 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2707 dwc3_suspend_gadget(dwc);
2709 dwc->link_state = next;
2712 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2713 unsigned int evtinfo)
2715 unsigned int is_ss = evtinfo & BIT(4);
2718 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2719 * have a known issue which can cause USB CV TD.9.23 to fail
2722 * Because of this issue, core could generate bogus hibernation
2723 * events which SW needs to ignore.
2727 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2728 * Device Fallback from SuperSpeed
2730 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2733 /* enter hibernation here */
2736 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2737 const struct dwc3_event_devt *event)
2739 switch (event->type) {
2740 case DWC3_DEVICE_EVENT_DISCONNECT:
2741 dwc3_gadget_disconnect_interrupt(dwc);
2743 case DWC3_DEVICE_EVENT_RESET:
2744 dwc3_gadget_reset_interrupt(dwc);
2746 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2747 dwc3_gadget_conndone_interrupt(dwc);
2749 case DWC3_DEVICE_EVENT_WAKEUP:
2750 dwc3_gadget_wakeup_interrupt(dwc);
2752 case DWC3_DEVICE_EVENT_HIBER_REQ:
2753 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2754 "unexpected hibernation event\n"))
2757 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2759 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2760 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2762 case DWC3_DEVICE_EVENT_EOPF:
2763 /* It changed to be suspend event for version 2.30a and above */
2764 if (dwc->revision < DWC3_REVISION_230A) {
2765 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2767 dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event");
2770 * Ignore suspend event until the gadget enters into
2771 * USB_STATE_CONFIGURED state.
2773 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2774 dwc3_gadget_suspend_interrupt(dwc,
2778 case DWC3_DEVICE_EVENT_SOF:
2779 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2781 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2782 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2784 case DWC3_DEVICE_EVENT_CMD_CMPL:
2785 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2787 case DWC3_DEVICE_EVENT_OVERFLOW:
2788 dwc3_trace(trace_dwc3_gadget, "Overflow");
2791 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2795 static void dwc3_process_event_entry(struct dwc3 *dwc,
2796 const union dwc3_event *event)
2798 trace_dwc3_event(event->raw);
2800 /* Endpoint IRQ, handle it and return early */
2801 if (event->type.is_devspec == 0) {
2803 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2806 switch (event->type.type) {
2807 case DWC3_EVENT_TYPE_DEV:
2808 dwc3_gadget_interrupt(dwc, &event->devt);
2810 /* REVISIT what to do with Carkit and I2C events ? */
2812 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2816 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2818 struct dwc3 *dwc = evt->dwc;
2819 irqreturn_t ret = IRQ_NONE;
2825 if (!(evt->flags & DWC3_EVENT_PENDING))
2829 union dwc3_event event;
2831 event.raw = *(u32 *) (evt->buf + evt->lpos);
2833 dwc3_process_event_entry(dwc, &event);
2836 * FIXME we wrap around correctly to the next entry as
2837 * almost all entries are 4 bytes in size. There is one
2838 * entry which has 12 bytes which is a regular entry
2839 * followed by 8 bytes data. ATM I don't know how
2840 * things are organized if we get next to the a
2841 * boundary so I worry about that once we try to handle
2844 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2847 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2851 evt->flags &= ~DWC3_EVENT_PENDING;
2854 /* Unmask interrupt */
2855 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2856 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2857 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2862 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2864 struct dwc3_event_buffer *evt = _evt;
2865 struct dwc3 *dwc = evt->dwc;
2866 unsigned long flags;
2867 irqreturn_t ret = IRQ_NONE;
2869 spin_lock_irqsave(&dwc->lock, flags);
2870 ret = dwc3_process_event_buf(evt);
2871 spin_unlock_irqrestore(&dwc->lock, flags);
2876 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2878 struct dwc3 *dwc = evt->dwc;
2882 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2884 if (pm_runtime_suspended(dwc->dev) &&
2885 DWC3_GCTL_PRTCAP(reg) != DWC3_GCTL_PRTCAP_HOST) {
2886 pm_runtime_get(dwc->dev);
2887 disable_irq_nosync(dwc->irq_gadget);
2888 dwc->pending_events = true;
2892 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2893 count &= DWC3_GEVNTCOUNT_MASK;
2898 evt->flags |= DWC3_EVENT_PENDING;
2900 /* Mask interrupt */
2901 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2902 reg |= DWC3_GEVNTSIZ_INTMASK;
2903 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2905 return IRQ_WAKE_THREAD;
2908 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2910 struct dwc3_event_buffer *evt = _evt;
2912 return dwc3_check_event_buf(evt);
2916 * dwc3_gadget_init - Initializes gadget related registers
2917 * @dwc: pointer to our controller context structure
2919 * Returns 0 on success otherwise negative errno.
2921 int dwc3_gadget_init(struct dwc3 *dwc)
2924 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2926 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2927 if (irq == -EPROBE_DEFER)
2931 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2932 if (irq == -EPROBE_DEFER)
2936 irq = platform_get_irq(dwc3_pdev, 0);
2938 if (irq != -EPROBE_DEFER) {
2940 "missing peripheral IRQ\n");
2949 dwc->irq_gadget = irq;
2951 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2952 &dwc->ctrl_req_addr, GFP_KERNEL);
2953 if (!dwc->ctrl_req) {
2954 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2959 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2960 &dwc->ep0_trb_addr, GFP_KERNEL);
2961 if (!dwc->ep0_trb) {
2962 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2967 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2968 if (!dwc->setup_buf) {
2973 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2974 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2976 if (!dwc->ep0_bounce) {
2977 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2982 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2983 if (!dwc->zlp_buf) {
2988 dwc->gadget.ops = &dwc3_gadget_ops;
2989 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2990 dwc->gadget.sg_supported = true;
2991 dwc->gadget.name = "dwc3-gadget";
2992 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2995 * FIXME We might be setting max_speed to <SUPER, however versions
2996 * <2.20a of dwc3 have an issue with metastability (documented
2997 * elsewhere in this driver) which tells us we can't set max speed to
2998 * anything lower than SUPER.
3000 * Because gadget.max_speed is only used by composite.c and function
3001 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3002 * to happen so we avoid sending SuperSpeed Capability descriptor
3003 * together with our BOS descriptor as that could confuse host into
3004 * thinking we can handle super speed.
3006 * Note that, in fact, we won't even support GetBOS requests when speed
3007 * is less than super speed because we don't have means, yet, to tell
3008 * composite.c that we are USB 2.0 + LPM ECN.
3010 if (dwc->revision < DWC3_REVISION_220A)
3011 dwc3_trace(trace_dwc3_gadget,
3012 "Changing max_speed on rev %08x",
3015 dwc->gadget.max_speed = dwc->maximum_speed;
3018 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3021 dwc->gadget.quirk_ep_out_aligned_size = true;
3024 * REVISIT: Here we should clear all pending IRQs to be
3025 * sure we're starting from a well known location.
3028 ret = dwc3_gadget_init_endpoints(dwc);
3032 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3034 dev_err(dwc->dev, "failed to register udc\n");
3041 kfree(dwc->zlp_buf);
3044 dwc3_gadget_free_endpoints(dwc);
3045 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3046 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3049 kfree(dwc->setup_buf);
3052 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3053 dwc->ep0_trb, dwc->ep0_trb_addr);
3056 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3057 dwc->ctrl_req, dwc->ctrl_req_addr);
3063 /* -------------------------------------------------------------------------- */
3065 void dwc3_gadget_exit(struct dwc3 *dwc)
3067 usb_del_gadget_udc(&dwc->gadget);
3069 dwc3_gadget_free_endpoints(dwc);
3071 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3072 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3074 kfree(dwc->setup_buf);
3075 kfree(dwc->zlp_buf);
3077 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3078 dwc->ep0_trb, dwc->ep0_trb_addr);
3080 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3081 dwc->ctrl_req, dwc->ctrl_req_addr);
3084 int dwc3_gadget_suspend(struct dwc3 *dwc)
3088 if (!dwc->gadget_driver)
3091 ret = dwc3_gadget_run_stop(dwc, false, false);
3093 dev_err(dwc->dev, "dwc3 gadget stop timeout\n");
3095 dwc3_disconnect_gadget(dwc);
3096 __dwc3_gadget_stop(dwc);
3101 int dwc3_gadget_resume(struct dwc3 *dwc)
3105 if (!dwc->gadget_driver)
3108 ret = __dwc3_gadget_start(dwc);
3112 ret = dwc3_gadget_run_stop(dwc, true, false);
3119 __dwc3_gadget_stop(dwc);
3125 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3127 if (dwc->pending_events) {
3128 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3129 dwc->pending_events = false;
3130 enable_irq(dwc->irq_gadget);