2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc->revision >= DWC3_REVISION_194A) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc->revision >= DWC3_REVISION_194A)
134 /* wait for a change in DSTS */
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
139 if (DWC3_DSTS_USBLNKST(reg) == state)
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
173 int last_fifo_depth = 0;
179 if (!dwc->needs_fifo_resize)
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
200 if (!(dep->number & 1))
203 if (!(dep->flags & DWC3_EP_ENABLED))
206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
226 fifo_size |= (last_fifo_depth << 16);
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
234 last_fifo_depth += (fifo_size & 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
243 struct dwc3 *dwc = dep->dwc;
246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
260 list_del(&req->list);
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
266 if (dwc->ep0_bounced && dep->number == 0)
267 dwc->ep0_bounced = false;
269 usb_gadget_unmap_request(&dwc->gadget, &req->request,
272 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
273 req, dep->name, req->request.actual,
274 req->request.length, status);
276 spin_unlock(&dwc->lock);
277 req->request.complete(&dep->endpoint, &req->request);
278 spin_lock(&dwc->lock);
281 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
284 case DWC3_DEPCMD_DEPSTARTCFG:
285 return "Start New Configuration";
286 case DWC3_DEPCMD_ENDTRANSFER:
287 return "End Transfer";
288 case DWC3_DEPCMD_UPDATETRANSFER:
289 return "Update Transfer";
290 case DWC3_DEPCMD_STARTTRANSFER:
291 return "Start Transfer";
292 case DWC3_DEPCMD_CLEARSTALL:
293 return "Clear Stall";
294 case DWC3_DEPCMD_SETSTALL:
296 case DWC3_DEPCMD_GETEPSTATE:
297 return "Get Endpoint State";
298 case DWC3_DEPCMD_SETTRANSFRESOURCE:
299 return "Set Endpoint Transfer Resource";
300 case DWC3_DEPCMD_SETEPCONFIG:
301 return "Set Endpoint Configuration";
303 return "UNKNOWN command";
307 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
312 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
313 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
316 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
317 if (!(reg & DWC3_DGCMD_CMDACT)) {
318 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
319 DWC3_DGCMD_STATUS(reg));
324 * We can't sleep here, because it's also called from
334 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
335 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
337 struct dwc3_ep *dep = dwc->eps[ep];
341 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
343 dwc3_gadget_ep_cmd_string(cmd), params->param0,
344 params->param1, params->param2);
346 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
347 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
348 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
350 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
352 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
353 if (!(reg & DWC3_DEPCMD_CMDACT)) {
354 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
355 DWC3_DEPCMD_STATUS(reg));
360 * We can't sleep here, because it is also called from
371 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
372 struct dwc3_trb *trb)
374 u32 offset = (char *) trb - (char *) dep->trb_pool;
376 return dep->trb_pool_dma + offset;
379 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
381 struct dwc3 *dwc = dep->dwc;
386 if (dep->number == 0 || dep->number == 1)
389 dep->trb_pool = dma_alloc_coherent(dwc->dev,
390 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
391 &dep->trb_pool_dma, GFP_KERNEL);
392 if (!dep->trb_pool) {
393 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
401 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
403 struct dwc3 *dwc = dep->dwc;
405 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
406 dep->trb_pool, dep->trb_pool_dma);
408 dep->trb_pool = NULL;
409 dep->trb_pool_dma = 0;
412 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
414 struct dwc3_gadget_ep_cmd_params params;
417 memset(¶ms, 0x00, sizeof(params));
419 if (dep->number != 1) {
420 cmd = DWC3_DEPCMD_DEPSTARTCFG;
421 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
422 if (dep->number > 1) {
423 if (dwc->start_config_issued)
425 dwc->start_config_issued = true;
426 cmd |= DWC3_DEPCMD_PARAM(2);
429 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
435 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
436 const struct usb_endpoint_descriptor *desc,
437 const struct usb_ss_ep_comp_descriptor *comp_desc,
440 struct dwc3_gadget_ep_cmd_params params;
442 memset(¶ms, 0x00, sizeof(params));
444 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
445 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
447 /* Burst size is only needed in SuperSpeed mode */
448 if (dwc->gadget.speed == USB_SPEED_SUPER) {
449 u32 burst = dep->endpoint.maxburst - 1;
451 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
455 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
457 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
458 | DWC3_DEPCFG_XFER_NOT_READY_EN;
460 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
461 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
462 | DWC3_DEPCFG_STREAM_EVENT_EN;
463 dep->stream_capable = true;
466 if (usb_endpoint_xfer_isoc(desc))
467 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
470 * We are doing 1:1 mapping for endpoints, meaning
471 * Physical Endpoints 2 maps to Logical Endpoint 2 and
472 * so on. We consider the direction bit as part of the physical
473 * endpoint number. So USB endpoint 0x81 is 0x03.
475 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
478 * We must use the lower 16 TX FIFOs even though
482 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
484 if (desc->bInterval) {
485 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
486 dep->interval = 1 << (desc->bInterval - 1);
489 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
490 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
493 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
495 struct dwc3_gadget_ep_cmd_params params;
497 memset(¶ms, 0x00, sizeof(params));
499 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
501 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
502 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
506 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
507 * @dep: endpoint to be initialized
508 * @desc: USB Endpoint Descriptor
510 * Caller should take care of locking
512 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
513 const struct usb_endpoint_descriptor *desc,
514 const struct usb_ss_ep_comp_descriptor *comp_desc,
517 struct dwc3 *dwc = dep->dwc;
521 if (!(dep->flags & DWC3_EP_ENABLED)) {
522 ret = dwc3_gadget_start_config(dwc, dep);
527 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
531 if (!(dep->flags & DWC3_EP_ENABLED)) {
532 struct dwc3_trb *trb_st_hw;
533 struct dwc3_trb *trb_link;
535 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
539 dep->endpoint.desc = desc;
540 dep->comp_desc = comp_desc;
541 dep->type = usb_endpoint_type(desc);
542 dep->flags |= DWC3_EP_ENABLED;
544 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
545 reg |= DWC3_DALEPENA_EP(dep->number);
546 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
548 if (!usb_endpoint_xfer_isoc(desc))
551 memset(&trb_link, 0, sizeof(trb_link));
553 /* Link TRB for ISOC. The HWO bit is never reset */
554 trb_st_hw = &dep->trb_pool[0];
556 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
558 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
559 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
560 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
561 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
567 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
568 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
570 struct dwc3_request *req;
572 if (!list_empty(&dep->req_queued)) {
573 dwc3_stop_active_transfer(dwc, dep->number);
575 /* - giveback all requests to gadget driver */
576 while (!list_empty(&dep->req_queued)) {
577 req = next_request(&dep->req_queued);
579 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
583 while (!list_empty(&dep->request_list)) {
584 req = next_request(&dep->request_list);
586 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
591 * __dwc3_gadget_ep_disable - Disables a HW endpoint
592 * @dep: the endpoint to disable
594 * This function also removes requests which are currently processed ny the
595 * hardware and those which are not yet scheduled.
596 * Caller should take care of locking.
598 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
600 struct dwc3 *dwc = dep->dwc;
603 dwc3_remove_requests(dwc, dep);
605 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
606 reg &= ~DWC3_DALEPENA_EP(dep->number);
607 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
609 dep->stream_capable = false;
610 dep->endpoint.desc = NULL;
611 dep->comp_desc = NULL;
618 /* -------------------------------------------------------------------------- */
620 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
621 const struct usb_endpoint_descriptor *desc)
626 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
631 /* -------------------------------------------------------------------------- */
633 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
634 const struct usb_endpoint_descriptor *desc)
641 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
642 pr_debug("dwc3: invalid parameters\n");
646 if (!desc->wMaxPacketSize) {
647 pr_debug("dwc3: missing wMaxPacketSize\n");
651 dep = to_dwc3_ep(ep);
654 if (dep->flags & DWC3_EP_ENABLED) {
655 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
660 switch (usb_endpoint_type(desc)) {
661 case USB_ENDPOINT_XFER_CONTROL:
662 strlcat(dep->name, "-control", sizeof(dep->name));
664 case USB_ENDPOINT_XFER_ISOC:
665 strlcat(dep->name, "-isoc", sizeof(dep->name));
667 case USB_ENDPOINT_XFER_BULK:
668 strlcat(dep->name, "-bulk", sizeof(dep->name));
670 case USB_ENDPOINT_XFER_INT:
671 strlcat(dep->name, "-int", sizeof(dep->name));
674 dev_err(dwc->dev, "invalid endpoint transfer type\n");
677 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
679 spin_lock_irqsave(&dwc->lock, flags);
680 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
681 spin_unlock_irqrestore(&dwc->lock, flags);
686 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
694 pr_debug("dwc3: invalid parameters\n");
698 dep = to_dwc3_ep(ep);
701 if (!(dep->flags & DWC3_EP_ENABLED)) {
702 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
707 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
709 (dep->number & 1) ? "in" : "out");
711 spin_lock_irqsave(&dwc->lock, flags);
712 ret = __dwc3_gadget_ep_disable(dep);
713 spin_unlock_irqrestore(&dwc->lock, flags);
718 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
721 struct dwc3_request *req;
722 struct dwc3_ep *dep = to_dwc3_ep(ep);
723 struct dwc3 *dwc = dep->dwc;
725 req = kzalloc(sizeof(*req), gfp_flags);
727 dev_err(dwc->dev, "not enough memory\n");
731 req->epnum = dep->number;
734 return &req->request;
737 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
738 struct usb_request *request)
740 struct dwc3_request *req = to_dwc3_request(request);
746 * dwc3_prepare_one_trb - setup one TRB from one request
747 * @dep: endpoint for which this request is prepared
748 * @req: dwc3_request pointer
750 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
751 struct dwc3_request *req, dma_addr_t dma,
752 unsigned length, unsigned last, unsigned chain)
754 struct dwc3 *dwc = dep->dwc;
755 struct dwc3_trb *trb;
757 unsigned int cur_slot;
759 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
760 dep->name, req, (unsigned long long) dma,
761 length, last ? " last" : "",
762 chain ? " chain" : "");
764 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
765 cur_slot = dep->free_slot;
768 /* Skip the LINK-TRB on ISOC */
769 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
770 usb_endpoint_xfer_isoc(dep->endpoint.desc))
774 dwc3_gadget_move_request_queued(req);
776 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
779 trb->size = DWC3_TRB_SIZE_LENGTH(length);
780 trb->bpl = lower_32_bits(dma);
781 trb->bph = upper_32_bits(dma);
783 switch (usb_endpoint_type(dep->endpoint.desc)) {
784 case USB_ENDPOINT_XFER_CONTROL:
785 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
788 case USB_ENDPOINT_XFER_ISOC:
789 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
791 if (!req->request.no_interrupt)
792 trb->ctrl |= DWC3_TRB_CTRL_IOC;
795 case USB_ENDPOINT_XFER_BULK:
796 case USB_ENDPOINT_XFER_INT:
797 trb->ctrl = DWC3_TRBCTL_NORMAL;
801 * This is only possible with faulty memory because we
802 * checked it already :)
807 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
808 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
809 trb->ctrl |= DWC3_TRB_CTRL_CSP;
812 trb->ctrl |= DWC3_TRB_CTRL_CHN;
815 trb->ctrl |= DWC3_TRB_CTRL_LST;
818 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
819 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
821 trb->ctrl |= DWC3_TRB_CTRL_HWO;
825 * dwc3_prepare_trbs - setup TRBs from requests
826 * @dep: endpoint for which requests are being prepared
827 * @starting: true if the endpoint is idle and no requests are queued.
829 * The function goes through the requests list and sets up TRBs for the
830 * transfers. The function returns once there are no more TRBs available or
831 * it runs out of requests.
833 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
835 struct dwc3_request *req, *n;
838 unsigned int last_one = 0;
840 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
842 /* the first request must not be queued */
843 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
845 /* Can't wrap around on a non-isoc EP since there's no link TRB */
846 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
847 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
853 * If busy & slot are equal than it is either full or empty. If we are
854 * starting to process requests then we are empty. Otherwise we are
855 * full and don't do anything
860 trbs_left = DWC3_TRB_NUM;
862 * In case we start from scratch, we queue the ISOC requests
863 * starting from slot 1. This is done because we use ring
864 * buffer and have no LST bit to stop us. Instead, we place
865 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
866 * after the first request so we start at slot 1 and have
867 * 7 requests proceed before we hit the first IOC.
868 * Other transfer types don't use the ring buffer and are
869 * processed from the first TRB until the last one. Since we
870 * don't wrap around we have to start at the beginning.
872 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
881 /* The last TRB is a link TRB, not used for xfer */
882 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
885 list_for_each_entry_safe(req, n, &dep->request_list, list) {
889 if (req->request.num_mapped_sgs > 0) {
890 struct usb_request *request = &req->request;
891 struct scatterlist *sg = request->sg;
892 struct scatterlist *s;
895 for_each_sg(sg, s, request->num_mapped_sgs, i) {
896 unsigned chain = true;
898 length = sg_dma_len(s);
899 dma = sg_dma_address(s);
901 if (i == (request->num_mapped_sgs - 1) ||
914 dwc3_prepare_one_trb(dep, req, dma, length,
921 dma = req->request.dma;
922 length = req->request.length;
928 /* Is this the last request? */
929 if (list_is_last(&req->list, &dep->request_list))
932 dwc3_prepare_one_trb(dep, req, dma, length,
941 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
944 struct dwc3_gadget_ep_cmd_params params;
945 struct dwc3_request *req;
946 struct dwc3 *dwc = dep->dwc;
950 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
951 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
954 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
957 * If we are getting here after a short-out-packet we don't enqueue any
958 * new requests as we try to set the IOC bit only on the last request.
961 if (list_empty(&dep->req_queued))
962 dwc3_prepare_trbs(dep, start_new);
964 /* req points to the first request which will be sent */
965 req = next_request(&dep->req_queued);
967 dwc3_prepare_trbs(dep, start_new);
970 * req points to the first request where HWO changed from 0 to 1
972 req = next_request(&dep->req_queued);
975 dep->flags |= DWC3_EP_PENDING_REQUEST;
979 memset(¶ms, 0, sizeof(params));
980 params.param0 = upper_32_bits(req->trb_dma);
981 params.param1 = lower_32_bits(req->trb_dma);
984 cmd = DWC3_DEPCMD_STARTTRANSFER;
986 cmd = DWC3_DEPCMD_UPDATETRANSFER;
988 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
989 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
991 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
994 * FIXME we need to iterate over the list of requests
995 * here and stop, unmap, free and del each of the linked
996 * requests instead of what we do now.
998 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1000 list_del(&req->list);
1004 dep->flags |= DWC3_EP_BUSY;
1007 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1009 WARN_ON_ONCE(!dep->resource_index);
1015 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1016 struct dwc3_ep *dep, u32 cur_uf)
1020 if (list_empty(&dep->request_list)) {
1021 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1023 dep->flags |= DWC3_EP_PENDING_REQUEST;
1027 /* 4 micro frames in the future */
1028 uf = cur_uf + dep->interval * 4;
1030 __dwc3_gadget_kick_transfer(dep, uf, 1);
1033 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1034 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1038 mask = ~(dep->interval - 1);
1039 cur_uf = event->parameters & mask;
1041 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1044 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1046 struct dwc3 *dwc = dep->dwc;
1049 req->request.actual = 0;
1050 req->request.status = -EINPROGRESS;
1051 req->direction = dep->direction;
1052 req->epnum = dep->number;
1055 * We only add to our list of requests now and
1056 * start consuming the list once we get XferNotReady
1059 * That way, we avoid doing anything that we don't need
1060 * to do now and defer it until the point we receive a
1061 * particular token from the Host side.
1063 * This will also avoid Host cancelling URBs due to too
1066 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1071 list_add_tail(&req->list, &dep->request_list);
1074 * There are a few special cases:
1076 * 1. XferNotReady with empty list of requests. We need to kick the
1077 * transfer here in that situation, otherwise we will be NAKing
1078 * forever. If we get XferNotReady before gadget driver has a
1079 * chance to queue a request, we will ACK the IRQ but won't be
1080 * able to receive the data until the next request is queued.
1081 * The following code is handling exactly that.
1084 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1086 * If xfernotready is already elapsed and it is a case
1087 * of isoc transfer, then issue END TRANSFER, so that
1088 * you can receive xfernotready again and can have
1089 * notion of current microframe.
1091 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1092 dwc3_stop_active_transfer(dwc, dep->number);
1096 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1097 if (ret && ret != -EBUSY)
1098 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1103 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1104 * kick the transfer here after queuing a request, otherwise the
1105 * core may not see the modified TRB(s).
1107 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1108 (dep->flags & DWC3_EP_BUSY) &&
1109 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1110 WARN_ON_ONCE(!dep->resource_index);
1111 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1113 if (ret && ret != -EBUSY)
1114 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1119 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved
1122 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1123 (dep->flags & DWC3_EP_MISSED_ISOC)) {
1124 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1125 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1131 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1134 struct dwc3_request *req = to_dwc3_request(request);
1135 struct dwc3_ep *dep = to_dwc3_ep(ep);
1136 struct dwc3 *dwc = dep->dwc;
1138 unsigned long flags;
1142 if (!dep->endpoint.desc) {
1143 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1148 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1149 request, ep->name, request->length);
1151 spin_lock_irqsave(&dwc->lock, flags);
1152 ret = __dwc3_gadget_ep_queue(dep, req);
1153 spin_unlock_irqrestore(&dwc->lock, flags);
1158 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1159 struct usb_request *request)
1161 struct dwc3_request *req = to_dwc3_request(request);
1162 struct dwc3_request *r = NULL;
1164 struct dwc3_ep *dep = to_dwc3_ep(ep);
1165 struct dwc3 *dwc = dep->dwc;
1167 unsigned long flags;
1170 spin_lock_irqsave(&dwc->lock, flags);
1172 list_for_each_entry(r, &dep->request_list, list) {
1178 list_for_each_entry(r, &dep->req_queued, list) {
1183 /* wait until it is processed */
1184 dwc3_stop_active_transfer(dwc, dep->number);
1187 dev_err(dwc->dev, "request %p was not queued to %s\n",
1194 /* giveback the request */
1195 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1198 spin_unlock_irqrestore(&dwc->lock, flags);
1203 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1205 struct dwc3_gadget_ep_cmd_params params;
1206 struct dwc3 *dwc = dep->dwc;
1209 memset(¶ms, 0x00, sizeof(params));
1212 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1213 DWC3_DEPCMD_SETSTALL, ¶ms);
1215 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1216 value ? "set" : "clear",
1219 dep->flags |= DWC3_EP_STALL;
1221 if (dep->flags & DWC3_EP_WEDGE)
1224 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1225 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1227 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1228 value ? "set" : "clear",
1231 dep->flags &= ~DWC3_EP_STALL;
1237 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1239 struct dwc3_ep *dep = to_dwc3_ep(ep);
1240 struct dwc3 *dwc = dep->dwc;
1242 unsigned long flags;
1246 spin_lock_irqsave(&dwc->lock, flags);
1248 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1249 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1254 ret = __dwc3_gadget_ep_set_halt(dep, value);
1256 spin_unlock_irqrestore(&dwc->lock, flags);
1261 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1263 struct dwc3_ep *dep = to_dwc3_ep(ep);
1264 struct dwc3 *dwc = dep->dwc;
1265 unsigned long flags;
1267 spin_lock_irqsave(&dwc->lock, flags);
1268 dep->flags |= DWC3_EP_WEDGE;
1269 spin_unlock_irqrestore(&dwc->lock, flags);
1271 if (dep->number == 0 || dep->number == 1)
1272 return dwc3_gadget_ep0_set_halt(ep, 1);
1274 return dwc3_gadget_ep_set_halt(ep, 1);
1277 /* -------------------------------------------------------------------------- */
1279 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1280 .bLength = USB_DT_ENDPOINT_SIZE,
1281 .bDescriptorType = USB_DT_ENDPOINT,
1282 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1285 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1286 .enable = dwc3_gadget_ep0_enable,
1287 .disable = dwc3_gadget_ep0_disable,
1288 .alloc_request = dwc3_gadget_ep_alloc_request,
1289 .free_request = dwc3_gadget_ep_free_request,
1290 .queue = dwc3_gadget_ep0_queue,
1291 .dequeue = dwc3_gadget_ep_dequeue,
1292 .set_halt = dwc3_gadget_ep0_set_halt,
1293 .set_wedge = dwc3_gadget_ep_set_wedge,
1296 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1297 .enable = dwc3_gadget_ep_enable,
1298 .disable = dwc3_gadget_ep_disable,
1299 .alloc_request = dwc3_gadget_ep_alloc_request,
1300 .free_request = dwc3_gadget_ep_free_request,
1301 .queue = dwc3_gadget_ep_queue,
1302 .dequeue = dwc3_gadget_ep_dequeue,
1303 .set_halt = dwc3_gadget_ep_set_halt,
1304 .set_wedge = dwc3_gadget_ep_set_wedge,
1307 /* -------------------------------------------------------------------------- */
1309 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1311 struct dwc3 *dwc = gadget_to_dwc(g);
1314 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1315 return DWC3_DSTS_SOFFN(reg);
1318 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1320 struct dwc3 *dwc = gadget_to_dwc(g);
1322 unsigned long timeout;
1323 unsigned long flags;
1332 spin_lock_irqsave(&dwc->lock, flags);
1335 * According to the Databook Remote wakeup request should
1336 * be issued only when the device is in early suspend state.
1338 * We can check that via USB Link State bits in DSTS register.
1340 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1342 speed = reg & DWC3_DSTS_CONNECTSPD;
1343 if (speed == DWC3_DSTS_SUPERSPEED) {
1344 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1349 link_state = DWC3_DSTS_USBLNKST(reg);
1351 switch (link_state) {
1352 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1353 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1356 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1362 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1364 dev_err(dwc->dev, "failed to put link in Recovery\n");
1368 /* Recent versions do this automatically */
1369 if (dwc->revision < DWC3_REVISION_194A) {
1370 /* write zeroes to Link Change Request */
1371 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1372 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1373 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1376 /* poll until Link State changes to ON */
1377 timeout = jiffies + msecs_to_jiffies(100);
1379 while (!time_after(jiffies, timeout)) {
1380 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1382 /* in HS, means ON */
1383 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1387 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1388 dev_err(dwc->dev, "failed to send remote wakeup\n");
1393 spin_unlock_irqrestore(&dwc->lock, flags);
1398 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1401 struct dwc3 *dwc = gadget_to_dwc(g);
1402 unsigned long flags;
1404 spin_lock_irqsave(&dwc->lock, flags);
1405 dwc->is_selfpowered = !!is_selfpowered;
1406 spin_unlock_irqrestore(&dwc->lock, flags);
1411 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1416 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1418 if (dwc->revision <= DWC3_REVISION_187A) {
1419 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1420 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1423 if (dwc->revision >= DWC3_REVISION_194A)
1424 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1425 reg |= DWC3_DCTL_RUN_STOP;
1427 reg &= ~DWC3_DCTL_RUN_STOP;
1430 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1433 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1435 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1438 if (reg & DWC3_DSTS_DEVCTRLHLT)
1447 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1449 ? dwc->gadget_driver->function : "no-function",
1450 is_on ? "connect" : "disconnect");
1455 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1457 struct dwc3 *dwc = gadget_to_dwc(g);
1458 unsigned long flags;
1463 spin_lock_irqsave(&dwc->lock, flags);
1464 ret = dwc3_gadget_run_stop(dwc, is_on);
1465 spin_unlock_irqrestore(&dwc->lock, flags);
1470 static int dwc3_gadget_start(struct usb_gadget *g,
1471 struct usb_gadget_driver *driver)
1473 struct dwc3 *dwc = gadget_to_dwc(g);
1474 struct dwc3_ep *dep;
1475 unsigned long flags;
1479 spin_lock_irqsave(&dwc->lock, flags);
1481 if (dwc->gadget_driver) {
1482 dev_err(dwc->dev, "%s is already bound to %s\n",
1484 dwc->gadget_driver->driver.name);
1489 dwc->gadget_driver = driver;
1490 dwc->gadget.dev.driver = &driver->driver;
1492 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1493 reg &= ~(DWC3_DCFG_SPEED_MASK);
1496 * WORKAROUND: DWC3 revision < 2.20a have an issue
1497 * which would cause metastability state on Run/Stop
1498 * bit if we try to force the IP to USB2-only mode.
1500 * Because of that, we cannot configure the IP to any
1501 * speed other than the SuperSpeed
1505 * STAR#9000525659: Clock Domain Crossing on DCTL in
1508 if (dwc->revision < DWC3_REVISION_220A)
1509 reg |= DWC3_DCFG_SUPERSPEED;
1511 reg |= dwc->maximum_speed;
1512 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1514 dwc->start_config_issued = false;
1516 /* Start with SuperSpeed Default */
1517 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1520 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1522 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1527 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1529 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1533 /* begin to receive SETUP packets */
1534 dwc->ep0state = EP0_SETUP_PHASE;
1535 dwc3_ep0_out_start(dwc);
1537 spin_unlock_irqrestore(&dwc->lock, flags);
1542 __dwc3_gadget_ep_disable(dwc->eps[0]);
1545 spin_unlock_irqrestore(&dwc->lock, flags);
1550 static int dwc3_gadget_stop(struct usb_gadget *g,
1551 struct usb_gadget_driver *driver)
1553 struct dwc3 *dwc = gadget_to_dwc(g);
1554 unsigned long flags;
1556 spin_lock_irqsave(&dwc->lock, flags);
1558 __dwc3_gadget_ep_disable(dwc->eps[0]);
1559 __dwc3_gadget_ep_disable(dwc->eps[1]);
1561 dwc->gadget_driver = NULL;
1562 dwc->gadget.dev.driver = NULL;
1564 spin_unlock_irqrestore(&dwc->lock, flags);
1569 static const struct usb_gadget_ops dwc3_gadget_ops = {
1570 .get_frame = dwc3_gadget_get_frame,
1571 .wakeup = dwc3_gadget_wakeup,
1572 .set_selfpowered = dwc3_gadget_set_selfpowered,
1573 .pullup = dwc3_gadget_pullup,
1574 .udc_start = dwc3_gadget_start,
1575 .udc_stop = dwc3_gadget_stop,
1578 /* -------------------------------------------------------------------------- */
1580 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1582 struct dwc3_ep *dep;
1585 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1587 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1588 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1590 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1596 dep->number = epnum;
1597 dwc->eps[epnum] = dep;
1599 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1600 (epnum & 1) ? "in" : "out");
1601 dep->endpoint.name = dep->name;
1602 dep->direction = (epnum & 1);
1604 if (epnum == 0 || epnum == 1) {
1605 dep->endpoint.maxpacket = 512;
1606 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1608 dwc->gadget.ep0 = &dep->endpoint;
1612 dep->endpoint.maxpacket = 1024;
1613 dep->endpoint.max_streams = 15;
1614 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1615 list_add_tail(&dep->endpoint.ep_list,
1616 &dwc->gadget.ep_list);
1618 ret = dwc3_alloc_trb_pool(dep);
1623 INIT_LIST_HEAD(&dep->request_list);
1624 INIT_LIST_HEAD(&dep->req_queued);
1630 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1632 struct dwc3_ep *dep;
1635 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1636 dep = dwc->eps[epnum];
1637 dwc3_free_trb_pool(dep);
1639 if (epnum != 0 && epnum != 1)
1640 list_del(&dep->endpoint.ep_list);
1646 static void dwc3_gadget_release(struct device *dev)
1648 dev_dbg(dev, "%s\n", __func__);
1651 /* -------------------------------------------------------------------------- */
1652 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1653 const struct dwc3_event_depevt *event, int status)
1655 struct dwc3_request *req;
1656 struct dwc3_trb *trb;
1658 unsigned int s_pkt = 0;
1659 unsigned int trb_status;
1662 req = next_request(&dep->req_queued);
1670 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1672 * We continue despite the error. There is not much we
1673 * can do. If we don't clean it up we loop forever. If
1674 * we skip the TRB then it gets overwritten after a
1675 * while since we use them in a ring buffer. A BUG()
1676 * would help. Lets hope that if this occurs, someone
1677 * fixes the root cause instead of looking away :)
1679 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1680 dep->name, req->trb);
1681 count = trb->size & DWC3_TRB_SIZE_MASK;
1683 if (dep->direction) {
1685 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1686 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1687 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1689 dep->current_uf = event->parameters &
1690 ~(dep->interval - 1);
1691 dep->flags |= DWC3_EP_MISSED_ISOC;
1693 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1695 status = -ECONNRESET;
1699 if (count && (event->status & DEPEVT_STATUS_SHORT))
1704 * We assume here we will always receive the entire data block
1705 * which we should receive. Meaning, if we program RX to
1706 * receive 4K but we receive only 2K, we assume that's all we
1707 * should receive and we simply bounce the request back to the
1708 * gadget driver for further processing.
1710 req->request.actual += req->request.length - count;
1711 dwc3_gadget_giveback(dep, req, status);
1714 if ((event->status & DEPEVT_STATUS_LST) &&
1715 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1716 DWC3_TRB_CTRL_HWO)))
1718 if ((event->status & DEPEVT_STATUS_IOC) &&
1719 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1723 if ((event->status & DEPEVT_STATUS_IOC) &&
1724 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1729 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1730 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1733 unsigned status = 0;
1736 if (event->status & DEPEVT_STATUS_BUSERR)
1737 status = -ECONNRESET;
1739 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1741 dep->flags &= ~DWC3_EP_BUSY;
1744 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1745 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1747 if (dwc->revision < DWC3_REVISION_183A) {
1751 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1754 if (!(dep->flags & DWC3_EP_ENABLED))
1757 if (!list_empty(&dep->req_queued))
1761 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1763 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1769 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1770 const struct dwc3_event_depevt *event)
1772 struct dwc3_ep *dep;
1773 u8 epnum = event->endpoint_number;
1775 dep = dwc->eps[epnum];
1777 if (!(dep->flags & DWC3_EP_ENABLED))
1780 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1781 dwc3_ep_event_string(event->endpoint_event));
1783 if (epnum == 0 || epnum == 1) {
1784 dwc3_ep0_interrupt(dwc, event);
1788 switch (event->endpoint_event) {
1789 case DWC3_DEPEVT_XFERCOMPLETE:
1790 dep->resource_index = 0;
1792 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1793 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1798 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1800 case DWC3_DEPEVT_XFERINPROGRESS:
1801 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1802 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1807 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1809 case DWC3_DEPEVT_XFERNOTREADY:
1810 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1811 dwc3_gadget_start_isoc(dwc, dep, event);
1815 dev_vdbg(dwc->dev, "%s: reason %s\n",
1816 dep->name, event->status &
1817 DEPEVT_STATUS_TRANSFER_ACTIVE
1819 : "Transfer Not Active");
1821 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1822 if (!ret || ret == -EBUSY)
1825 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1830 case DWC3_DEPEVT_STREAMEVT:
1831 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1832 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1837 switch (event->status) {
1838 case DEPEVT_STREAMEVT_FOUND:
1839 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1843 case DEPEVT_STREAMEVT_NOTFOUND:
1846 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1849 case DWC3_DEPEVT_RXTXFIFOEVT:
1850 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1852 case DWC3_DEPEVT_EPCMDCMPLT:
1853 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1858 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1860 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1861 spin_unlock(&dwc->lock);
1862 dwc->gadget_driver->disconnect(&dwc->gadget);
1863 spin_lock(&dwc->lock);
1867 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1869 struct dwc3_ep *dep;
1870 struct dwc3_gadget_ep_cmd_params params;
1874 dep = dwc->eps[epnum];
1876 if (!dep->resource_index)
1880 * NOTICE: We are violating what the Databook says about the
1881 * EndTransfer command. Ideally we would _always_ wait for the
1882 * EndTransfer Command Completion IRQ, but that's causing too
1883 * much trouble synchronizing between us and gadget driver.
1885 * We have discussed this with the IP Provider and it was
1886 * suggested to giveback all requests here, but give HW some
1887 * extra time to synchronize with the interconnect. We're using
1888 * an arbitraty 100us delay for that.
1890 * Note also that a similar handling was tested by Synopsys
1891 * (thanks a lot Paul) and nothing bad has come out of it.
1892 * In short, what we're doing is:
1894 * - Issue EndTransfer WITH CMDIOC bit set
1898 cmd = DWC3_DEPCMD_ENDTRANSFER;
1899 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1900 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1901 memset(¶ms, 0, sizeof(params));
1902 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1904 dep->resource_index = 0;
1905 dep->flags &= ~DWC3_EP_BUSY;
1909 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1913 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1914 struct dwc3_ep *dep;
1916 dep = dwc->eps[epnum];
1917 if (!(dep->flags & DWC3_EP_ENABLED))
1920 dwc3_remove_requests(dwc, dep);
1924 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1928 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1929 struct dwc3_ep *dep;
1930 struct dwc3_gadget_ep_cmd_params params;
1933 dep = dwc->eps[epnum];
1935 if (!(dep->flags & DWC3_EP_STALL))
1938 dep->flags &= ~DWC3_EP_STALL;
1940 memset(¶ms, 0, sizeof(params));
1941 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1942 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1947 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1951 dev_vdbg(dwc->dev, "%s\n", __func__);
1953 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1954 reg &= ~DWC3_DCTL_INITU1ENA;
1955 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1957 reg &= ~DWC3_DCTL_INITU2ENA;
1958 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1960 dwc3_disconnect_gadget(dwc);
1961 dwc->start_config_issued = false;
1963 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1964 dwc->setup_packet_pending = false;
1967 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
1971 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1974 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1976 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1978 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1981 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
1985 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1988 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1990 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1992 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1995 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1999 dev_vdbg(dwc->dev, "%s\n", __func__);
2002 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2003 * would cause a missing Disconnect Event if there's a
2004 * pending Setup Packet in the FIFO.
2006 * There's no suggested workaround on the official Bug
2007 * report, which states that "unless the driver/application
2008 * is doing any special handling of a disconnect event,
2009 * there is no functional issue".
2011 * Unfortunately, it turns out that we _do_ some special
2012 * handling of a disconnect event, namely complete all
2013 * pending transfers, notify gadget driver of the
2014 * disconnection, and so on.
2016 * Our suggested workaround is to follow the Disconnect
2017 * Event steps here, instead, based on a setup_packet_pending
2018 * flag. Such flag gets set whenever we have a XferNotReady
2019 * event on EP0 and gets cleared on XferComplete for the
2024 * STAR#9000466709: RTL: Device : Disconnect event not
2025 * generated if setup packet pending in FIFO
2027 if (dwc->revision < DWC3_REVISION_188A) {
2028 if (dwc->setup_packet_pending)
2029 dwc3_gadget_disconnect_interrupt(dwc);
2032 /* after reset -> Default State */
2033 dwc->dev_state = DWC3_DEFAULT_STATE;
2035 /* Recent versions support automatic phy suspend and don't need this */
2036 if (dwc->revision < DWC3_REVISION_194A) {
2038 dwc3_gadget_usb2_phy_suspend(dwc, false);
2039 dwc3_gadget_usb3_phy_suspend(dwc, false);
2042 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2043 dwc3_disconnect_gadget(dwc);
2045 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2046 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2047 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2048 dwc->test_mode = false;
2050 dwc3_stop_active_transfers(dwc);
2051 dwc3_clear_stall_all_ep(dwc);
2052 dwc->start_config_issued = false;
2054 /* Reset device address to zero */
2055 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2056 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2057 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2060 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2063 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2066 * We change the clock only at SS but I dunno why I would want to do
2067 * this. Maybe it becomes part of the power saving plan.
2070 if (speed != DWC3_DSTS_SUPERSPEED)
2074 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2075 * each time on Connect Done.
2080 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2081 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2082 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2085 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2088 case USB_SPEED_SUPER:
2089 dwc3_gadget_usb2_phy_suspend(dwc, true);
2091 case USB_SPEED_HIGH:
2092 case USB_SPEED_FULL:
2094 dwc3_gadget_usb3_phy_suspend(dwc, true);
2099 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2101 struct dwc3_gadget_ep_cmd_params params;
2102 struct dwc3_ep *dep;
2107 dev_vdbg(dwc->dev, "%s\n", __func__);
2109 memset(¶ms, 0x00, sizeof(params));
2111 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2112 speed = reg & DWC3_DSTS_CONNECTSPD;
2115 dwc3_update_ram_clk_sel(dwc, speed);
2118 case DWC3_DCFG_SUPERSPEED:
2120 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2121 * would cause a missing USB3 Reset event.
2123 * In such situations, we should force a USB3 Reset
2124 * event by calling our dwc3_gadget_reset_interrupt()
2129 * STAR#9000483510: RTL: SS : USB3 reset event may
2130 * not be generated always when the link enters poll
2132 if (dwc->revision < DWC3_REVISION_190A)
2133 dwc3_gadget_reset_interrupt(dwc);
2135 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2136 dwc->gadget.ep0->maxpacket = 512;
2137 dwc->gadget.speed = USB_SPEED_SUPER;
2139 case DWC3_DCFG_HIGHSPEED:
2140 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2141 dwc->gadget.ep0->maxpacket = 64;
2142 dwc->gadget.speed = USB_SPEED_HIGH;
2144 case DWC3_DCFG_FULLSPEED2:
2145 case DWC3_DCFG_FULLSPEED1:
2146 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2147 dwc->gadget.ep0->maxpacket = 64;
2148 dwc->gadget.speed = USB_SPEED_FULL;
2150 case DWC3_DCFG_LOWSPEED:
2151 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2152 dwc->gadget.ep0->maxpacket = 8;
2153 dwc->gadget.speed = USB_SPEED_LOW;
2157 /* Recent versions support automatic phy suspend and don't need this */
2158 if (dwc->revision < DWC3_REVISION_194A) {
2159 /* Suspend unneeded PHY */
2160 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2164 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2166 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2171 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2173 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2178 * Configure PHY via GUSB3PIPECTLn if required.
2180 * Update GTXFIFOSIZn
2182 * In both cases reset values should be sufficient.
2186 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2188 dev_vdbg(dwc->dev, "%s\n", __func__);
2191 * TODO take core out of low power mode when that's
2195 dwc->gadget_driver->resume(&dwc->gadget);
2198 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2199 unsigned int evtinfo)
2201 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2204 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2205 * on the link partner, the USB session might do multiple entry/exit
2206 * of low power states before a transfer takes place.
2208 * Due to this problem, we might experience lower throughput. The
2209 * suggested workaround is to disable DCTL[12:9] bits if we're
2210 * transitioning from U1/U2 to U0 and enable those bits again
2211 * after a transfer completes and there are no pending transfers
2212 * on any of the enabled endpoints.
2214 * This is the first half of that workaround.
2218 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2219 * core send LGO_Ux entering U0
2221 if (dwc->revision < DWC3_REVISION_183A) {
2222 if (next == DWC3_LINK_STATE_U0) {
2226 switch (dwc->link_state) {
2227 case DWC3_LINK_STATE_U1:
2228 case DWC3_LINK_STATE_U2:
2229 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2230 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2231 | DWC3_DCTL_ACCEPTU2ENA
2232 | DWC3_DCTL_INITU1ENA
2233 | DWC3_DCTL_ACCEPTU1ENA);
2236 dwc->u1u2 = reg & u1u2;
2240 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2249 dwc->link_state = next;
2251 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2254 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2255 const struct dwc3_event_devt *event)
2257 switch (event->type) {
2258 case DWC3_DEVICE_EVENT_DISCONNECT:
2259 dwc3_gadget_disconnect_interrupt(dwc);
2261 case DWC3_DEVICE_EVENT_RESET:
2262 dwc3_gadget_reset_interrupt(dwc);
2264 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2265 dwc3_gadget_conndone_interrupt(dwc);
2267 case DWC3_DEVICE_EVENT_WAKEUP:
2268 dwc3_gadget_wakeup_interrupt(dwc);
2270 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2271 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2273 case DWC3_DEVICE_EVENT_EOPF:
2274 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2276 case DWC3_DEVICE_EVENT_SOF:
2277 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2279 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2280 dev_vdbg(dwc->dev, "Erratic Error\n");
2282 case DWC3_DEVICE_EVENT_CMD_CMPL:
2283 dev_vdbg(dwc->dev, "Command Complete\n");
2285 case DWC3_DEVICE_EVENT_OVERFLOW:
2286 dev_vdbg(dwc->dev, "Overflow\n");
2289 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2293 static void dwc3_process_event_entry(struct dwc3 *dwc,
2294 const union dwc3_event *event)
2296 /* Endpoint IRQ, handle it and return early */
2297 if (event->type.is_devspec == 0) {
2299 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2302 switch (event->type.type) {
2303 case DWC3_EVENT_TYPE_DEV:
2304 dwc3_gadget_interrupt(dwc, &event->devt);
2306 /* REVISIT what to do with Carkit and I2C events ? */
2308 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2312 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2314 struct dwc3_event_buffer *evt;
2318 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2319 count &= DWC3_GEVNTCOUNT_MASK;
2323 evt = dwc->ev_buffs[buf];
2327 union dwc3_event event;
2329 event.raw = *(u32 *) (evt->buf + evt->lpos);
2331 dwc3_process_event_entry(dwc, &event);
2333 * XXX we wrap around correctly to the next entry as almost all
2334 * entries are 4 bytes in size. There is one entry which has 12
2335 * bytes which is a regular entry followed by 8 bytes data. ATM
2336 * I don't know how things are organized if were get next to the
2337 * a boundary so I worry about that once we try to handle that.
2339 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2342 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2348 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2350 struct dwc3 *dwc = _dwc;
2352 irqreturn_t ret = IRQ_NONE;
2354 spin_lock(&dwc->lock);
2356 for (i = 0; i < dwc->num_event_buffers; i++) {
2359 status = dwc3_process_event_buf(dwc, i);
2360 if (status == IRQ_HANDLED)
2364 spin_unlock(&dwc->lock);
2370 * dwc3_gadget_init - Initializes gadget related registers
2371 * @dwc: pointer to our controller context structure
2373 * Returns 0 on success otherwise negative errno.
2375 int dwc3_gadget_init(struct dwc3 *dwc)
2381 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2382 &dwc->ctrl_req_addr, GFP_KERNEL);
2383 if (!dwc->ctrl_req) {
2384 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2389 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2390 &dwc->ep0_trb_addr, GFP_KERNEL);
2391 if (!dwc->ep0_trb) {
2392 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2397 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2398 if (!dwc->setup_buf) {
2399 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2404 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2405 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2407 if (!dwc->ep0_bounce) {
2408 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2413 dev_set_name(&dwc->gadget.dev, "gadget");
2415 dwc->gadget.ops = &dwc3_gadget_ops;
2416 dwc->gadget.max_speed = USB_SPEED_SUPER;
2417 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2418 dwc->gadget.dev.parent = dwc->dev;
2419 dwc->gadget.sg_supported = true;
2421 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2423 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2424 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2425 dwc->gadget.dev.release = dwc3_gadget_release;
2426 dwc->gadget.name = "dwc3-gadget";
2429 * REVISIT: Here we should clear all pending IRQs to be
2430 * sure we're starting from a well known location.
2433 ret = dwc3_gadget_init_endpoints(dwc);
2437 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2439 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2442 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2447 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2448 reg |= DWC3_DCFG_LPM_CAP;
2449 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2451 /* Enable all but Start and End of Frame IRQs */
2452 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2453 DWC3_DEVTEN_EVNTOVERFLOWEN |
2454 DWC3_DEVTEN_CMDCMPLTEN |
2455 DWC3_DEVTEN_ERRTICERREN |
2456 DWC3_DEVTEN_WKUPEVTEN |
2457 DWC3_DEVTEN_ULSTCNGEN |
2458 DWC3_DEVTEN_CONNECTDONEEN |
2459 DWC3_DEVTEN_USBRSTEN |
2460 DWC3_DEVTEN_DISCONNEVTEN);
2461 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2463 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2464 if (dwc->revision >= DWC3_REVISION_194A) {
2465 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2466 reg |= DWC3_DCFG_LPM_CAP;
2467 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2469 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2470 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2472 /* TODO: This should be configurable */
2473 reg |= DWC3_DCTL_HIRD_THRES(28);
2475 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2477 dwc3_gadget_usb2_phy_suspend(dwc, false);
2478 dwc3_gadget_usb3_phy_suspend(dwc, false);
2481 ret = device_register(&dwc->gadget.dev);
2483 dev_err(dwc->dev, "failed to register gadget device\n");
2484 put_device(&dwc->gadget.dev);
2488 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2490 dev_err(dwc->dev, "failed to register udc\n");
2497 device_unregister(&dwc->gadget.dev);
2500 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2504 dwc3_gadget_free_endpoints(dwc);
2507 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2508 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2511 kfree(dwc->setup_buf);
2514 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2515 dwc->ep0_trb, dwc->ep0_trb_addr);
2518 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2519 dwc->ctrl_req, dwc->ctrl_req_addr);
2525 void dwc3_gadget_exit(struct dwc3 *dwc)
2529 usb_del_gadget_udc(&dwc->gadget);
2530 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2532 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2535 dwc3_gadget_free_endpoints(dwc);
2537 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2538 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2540 kfree(dwc->setup_buf);
2542 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2543 dwc->ep0_trb, dwc->ep0_trb_addr);
2545 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2546 dwc->ctrl_req, dwc->ctrl_req_addr);
2548 device_unregister(&dwc->gadget.dev);