2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
71 * dwc3_gadget_get_link_state - Gets current state of USB Link
72 * @dwc: pointer to our context structure
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83 return DWC3_DSTS_USBLNKST(reg);
87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
100 * Wait until device controller is ready. Only applies to 1.94a and
103 if (dwc->revision >= DWC3_REVISION_194A) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
127 if (dwc->revision >= DWC3_REVISION_194A)
130 /* wait for a change in DSTS */
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135 if (DWC3_DSTS_USBLNKST(reg) == state)
141 dev_vdbg(dwc->dev, "link state change request timed out\n");
147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
148 * @dwc: pointer to our context structure
150 * This function will a best effort FIFO allocation in order
151 * to improve FIFO usage and throughput, while still allowing
152 * us to enable as many endpoints as possible.
154 * Keep in mind that this operation will be highly dependent
155 * on the configured size for RAM1 - which contains TxFifo -,
156 * the amount of endpoints enabled on coreConsultant tool, and
157 * the width of the Master Bus.
159 * In the ideal world, we would always be able to satisfy the
160 * following equation:
162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
165 * Unfortunately, due to many variables that's not always the case.
167 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
169 int last_fifo_depth = 0;
175 if (!dwc->needs_fifo_resize)
178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
181 /* MDWIDTH is represented in bits, we need it in bytes */
185 * FIXME For now we will only allocate 1 wMaxPacketSize space
186 * for each enabled endpoint, later patches will come to
187 * improve this algorithm so that we better use the internal
190 for (num = 0; num < dwc->num_in_eps; num++) {
191 /* bit0 indicates direction; 1 means IN ep */
192 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
196 if (!(dep->flags & DWC3_EP_ENABLED))
199 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
200 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
204 * REVISIT: the following assumes we will always have enough
205 * space available on the FIFO RAM for all possible use cases.
206 * Make sure that's true somehow and change FIFO allocation
209 * If we have Bulk or Isochronous endpoints, we want
210 * them to be able to be very, very fast. So we're giving
211 * those endpoints a fifo_size which is enough for 3 full
214 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
217 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
219 fifo_size |= (last_fifo_depth << 16);
221 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
222 dep->name, last_fifo_depth, fifo_size & 0xffff);
224 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
226 last_fifo_depth += (fifo_size & 0xffff);
232 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 struct dwc3 *dwc = dep->dwc;
243 * Skip LINK TRB. We can't use req->trb and check for
244 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
245 * just completed (not the LINK TRB).
247 if (((dep->busy_slot & DWC3_TRB_MASK) ==
249 usb_endpoint_xfer_isoc(dep->endpoint.desc))
251 } while(++i < req->request.num_mapped_sgs);
254 list_del(&req->list);
257 if (req->request.status == -EINPROGRESS)
258 req->request.status = status;
260 if (dwc->ep0_bounced && dep->number == 0)
261 dwc->ep0_bounced = false;
263 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
267 req, dep->name, req->request.actual,
268 req->request.length, status);
270 spin_unlock(&dwc->lock);
271 req->request.complete(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
275 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
278 case DWC3_DEPCMD_DEPSTARTCFG:
279 return "Start New Configuration";
280 case DWC3_DEPCMD_ENDTRANSFER:
281 return "End Transfer";
282 case DWC3_DEPCMD_UPDATETRANSFER:
283 return "Update Transfer";
284 case DWC3_DEPCMD_STARTTRANSFER:
285 return "Start Transfer";
286 case DWC3_DEPCMD_CLEARSTALL:
287 return "Clear Stall";
288 case DWC3_DEPCMD_SETSTALL:
290 case DWC3_DEPCMD_GETEPSTATE:
291 return "Get Endpoint State";
292 case DWC3_DEPCMD_SETTRANSFRESOURCE:
293 return "Set Endpoint Transfer Resource";
294 case DWC3_DEPCMD_SETEPCONFIG:
295 return "Set Endpoint Configuration";
297 return "UNKNOWN command";
301 static const char *dwc3_gadget_generic_cmd_string(u8 cmd)
304 case DWC3_DGCMD_SET_LMP:
306 case DWC3_DGCMD_SET_PERIODIC_PAR:
307 return "Set Periodic Parameters";
308 case DWC3_DGCMD_XMIT_FUNCTION:
309 return "Transmit Function Wake Device Notification";
310 case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO:
311 return "Set Scratchpad Buffer Array Address Lo";
312 case DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI:
313 return "Set Scratchpad Buffer Array Address Hi";
314 case DWC3_DGCMD_SELECTED_FIFO_FLUSH:
315 return "Selected FIFO Flush";
316 case DWC3_DGCMD_ALL_FIFO_FLUSH:
317 return "All FIFO Flush";
318 case DWC3_DGCMD_SET_ENDPOINT_NRDY:
319 return "Set Endpoint NRDY";
320 case DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK:
321 return "Run SoC Bus Loopback Test";
327 static const char *dwc3_gadget_link_string(enum dwc3_link_state link_state)
329 switch (link_state) {
330 case DWC3_LINK_STATE_U0:
332 case DWC3_LINK_STATE_U1:
334 case DWC3_LINK_STATE_U2:
336 case DWC3_LINK_STATE_U3:
338 case DWC3_LINK_STATE_SS_DIS:
339 return "SS.Disabled";
340 case DWC3_LINK_STATE_RX_DET:
342 case DWC3_LINK_STATE_SS_INACT:
343 return "SS.Inactive";
344 case DWC3_LINK_STATE_POLL:
346 case DWC3_LINK_STATE_RECOV:
348 case DWC3_LINK_STATE_HRESET:
350 case DWC3_LINK_STATE_CMPLY:
352 case DWC3_LINK_STATE_LPBK:
354 case DWC3_LINK_STATE_RESET:
356 case DWC3_LINK_STATE_RESUME:
359 return "UNKNOWN link state\n";
363 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
368 dev_vdbg(dwc->dev, "generic cmd '%s' [%d] param %08x\n",
369 dwc3_gadget_generic_cmd_string(cmd), cmd, param);
371 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
372 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
375 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
376 if (!(reg & DWC3_DGCMD_CMDACT)) {
377 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
378 DWC3_DGCMD_STATUS(reg));
383 * We can't sleep here, because it's also called from
393 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
394 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
396 struct dwc3_ep *dep = dwc->eps[ep];
400 dev_vdbg(dwc->dev, "%s: cmd '%s' [%d] params %08x %08x %08x\n",
402 dwc3_gadget_ep_cmd_string(cmd), cmd, params->param0,
403 params->param1, params->param2);
405 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
406 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
407 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
409 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
411 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
412 if (!(reg & DWC3_DEPCMD_CMDACT)) {
413 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
414 DWC3_DEPCMD_STATUS(reg));
419 * We can't sleep here, because it is also called from
430 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
431 struct dwc3_trb *trb)
433 u32 offset = (char *) trb - (char *) dep->trb_pool;
435 return dep->trb_pool_dma + offset;
438 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
440 struct dwc3 *dwc = dep->dwc;
445 if (dep->number == 0 || dep->number == 1)
448 dep->trb_pool = dma_alloc_coherent(dwc->dev,
449 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450 &dep->trb_pool_dma, GFP_KERNEL);
451 if (!dep->trb_pool) {
452 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
462 struct dwc3 *dwc = dep->dwc;
464 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465 dep->trb_pool, dep->trb_pool_dma);
467 dep->trb_pool = NULL;
468 dep->trb_pool_dma = 0;
471 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
473 struct dwc3_gadget_ep_cmd_params params;
476 memset(¶ms, 0x00, sizeof(params));
478 if (dep->number != 1) {
479 cmd = DWC3_DEPCMD_DEPSTARTCFG;
480 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
481 if (dep->number > 1) {
482 if (dwc->start_config_issued)
484 dwc->start_config_issued = true;
485 cmd |= DWC3_DEPCMD_PARAM(2);
488 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
494 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
495 const struct usb_endpoint_descriptor *desc,
496 const struct usb_ss_ep_comp_descriptor *comp_desc,
497 bool ignore, bool restore)
499 struct dwc3_gadget_ep_cmd_params params;
501 memset(¶ms, 0x00, sizeof(params));
503 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
506 /* Burst size is only needed in SuperSpeed mode */
507 if (dwc->gadget.speed == USB_SPEED_SUPER) {
508 u32 burst = dep->endpoint.maxburst - 1;
510 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
514 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
517 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
518 params.param2 |= dep->saved_state;
521 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
522 | DWC3_DEPCFG_XFER_NOT_READY_EN;
524 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
525 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
526 | DWC3_DEPCFG_STREAM_EVENT_EN;
527 dep->stream_capable = true;
530 if (usb_endpoint_xfer_isoc(desc))
531 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
534 * We are doing 1:1 mapping for endpoints, meaning
535 * Physical Endpoints 2 maps to Logical Endpoint 2 and
536 * so on. We consider the direction bit as part of the physical
537 * endpoint number. So USB endpoint 0x81 is 0x03.
539 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
542 * We must use the lower 16 TX FIFOs even though
546 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
548 if (desc->bInterval) {
549 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
550 dep->interval = 1 << (desc->bInterval - 1);
553 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
554 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
557 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
559 struct dwc3_gadget_ep_cmd_params params;
561 memset(¶ms, 0x00, sizeof(params));
563 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
565 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
566 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
570 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
571 * @dep: endpoint to be initialized
572 * @desc: USB Endpoint Descriptor
574 * Caller should take care of locking
576 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
577 const struct usb_endpoint_descriptor *desc,
578 const struct usb_ss_ep_comp_descriptor *comp_desc,
579 bool ignore, bool restore)
581 struct dwc3 *dwc = dep->dwc;
585 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
587 if (!(dep->flags & DWC3_EP_ENABLED)) {
588 ret = dwc3_gadget_start_config(dwc, dep);
593 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
598 if (!(dep->flags & DWC3_EP_ENABLED)) {
599 struct dwc3_trb *trb_st_hw;
600 struct dwc3_trb *trb_link;
602 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
606 dep->endpoint.desc = desc;
607 dep->comp_desc = comp_desc;
608 dep->type = usb_endpoint_type(desc);
609 dep->flags |= DWC3_EP_ENABLED;
611 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
612 reg |= DWC3_DALEPENA_EP(dep->number);
613 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
615 if (!usb_endpoint_xfer_isoc(desc))
618 memset(&trb_link, 0, sizeof(trb_link));
620 /* Link TRB for ISOC. The HWO bit is never reset */
621 trb_st_hw = &dep->trb_pool[0];
623 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
625 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
626 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
627 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
628 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
634 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
635 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
637 struct dwc3_request *req;
639 if (!list_empty(&dep->req_queued)) {
640 dwc3_stop_active_transfer(dwc, dep->number, true);
642 /* - giveback all requests to gadget driver */
643 while (!list_empty(&dep->req_queued)) {
644 req = next_request(&dep->req_queued);
646 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
650 while (!list_empty(&dep->request_list)) {
651 req = next_request(&dep->request_list);
653 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
658 * __dwc3_gadget_ep_disable - Disables a HW endpoint
659 * @dep: the endpoint to disable
661 * This function also removes requests which are currently processed ny the
662 * hardware and those which are not yet scheduled.
663 * Caller should take care of locking.
665 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
667 struct dwc3 *dwc = dep->dwc;
670 dwc3_remove_requests(dwc, dep);
672 /* make sure HW endpoint isn't stalled */
673 if (dep->flags & DWC3_EP_STALL)
674 __dwc3_gadget_ep_set_halt(dep, 0);
676 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
677 reg &= ~DWC3_DALEPENA_EP(dep->number);
678 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
680 dep->stream_capable = false;
681 dep->endpoint.desc = NULL;
682 dep->comp_desc = NULL;
689 /* -------------------------------------------------------------------------- */
691 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
692 const struct usb_endpoint_descriptor *desc)
697 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
702 /* -------------------------------------------------------------------------- */
704 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
705 const struct usb_endpoint_descriptor *desc)
712 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
713 pr_debug("dwc3: invalid parameters\n");
717 if (!desc->wMaxPacketSize) {
718 pr_debug("dwc3: missing wMaxPacketSize\n");
722 dep = to_dwc3_ep(ep);
725 if (dep->flags & DWC3_EP_ENABLED) {
726 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
731 switch (usb_endpoint_type(desc)) {
732 case USB_ENDPOINT_XFER_CONTROL:
733 strlcat(dep->name, "-control", sizeof(dep->name));
735 case USB_ENDPOINT_XFER_ISOC:
736 strlcat(dep->name, "-isoc", sizeof(dep->name));
738 case USB_ENDPOINT_XFER_BULK:
739 strlcat(dep->name, "-bulk", sizeof(dep->name));
741 case USB_ENDPOINT_XFER_INT:
742 strlcat(dep->name, "-int", sizeof(dep->name));
745 dev_err(dwc->dev, "invalid endpoint transfer type\n");
748 spin_lock_irqsave(&dwc->lock, flags);
749 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
750 spin_unlock_irqrestore(&dwc->lock, flags);
755 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
763 pr_debug("dwc3: invalid parameters\n");
767 dep = to_dwc3_ep(ep);
770 if (!(dep->flags & DWC3_EP_ENABLED)) {
771 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
776 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
778 (dep->number & 1) ? "in" : "out");
780 spin_lock_irqsave(&dwc->lock, flags);
781 ret = __dwc3_gadget_ep_disable(dep);
782 spin_unlock_irqrestore(&dwc->lock, flags);
787 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
790 struct dwc3_request *req;
791 struct dwc3_ep *dep = to_dwc3_ep(ep);
792 struct dwc3 *dwc = dep->dwc;
794 req = kzalloc(sizeof(*req), gfp_flags);
796 dev_err(dwc->dev, "not enough memory\n");
800 req->epnum = dep->number;
803 return &req->request;
806 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
807 struct usb_request *request)
809 struct dwc3_request *req = to_dwc3_request(request);
815 * dwc3_prepare_one_trb - setup one TRB from one request
816 * @dep: endpoint for which this request is prepared
817 * @req: dwc3_request pointer
819 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
820 struct dwc3_request *req, dma_addr_t dma,
821 unsigned length, unsigned last, unsigned chain, unsigned node)
823 struct dwc3 *dwc = dep->dwc;
824 struct dwc3_trb *trb;
826 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
827 dep->name, req, (unsigned long long) dma,
828 length, last ? " last" : "",
829 chain ? " chain" : "");
831 /* Skip the LINK-TRB on ISOC */
832 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
833 usb_endpoint_xfer_isoc(dep->endpoint.desc))
836 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
839 dwc3_gadget_move_request_queued(req);
841 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
842 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
847 trb->size = DWC3_TRB_SIZE_LENGTH(length);
848 trb->bpl = lower_32_bits(dma);
849 trb->bph = upper_32_bits(dma);
851 switch (usb_endpoint_type(dep->endpoint.desc)) {
852 case USB_ENDPOINT_XFER_CONTROL:
853 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
856 case USB_ENDPOINT_XFER_ISOC:
858 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
860 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
863 case USB_ENDPOINT_XFER_BULK:
864 case USB_ENDPOINT_XFER_INT:
865 trb->ctrl = DWC3_TRBCTL_NORMAL;
869 * This is only possible with faulty memory because we
870 * checked it already :)
875 if (!req->request.no_interrupt && !chain)
876 trb->ctrl |= DWC3_TRB_CTRL_IOC;
878 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
879 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
880 trb->ctrl |= DWC3_TRB_CTRL_CSP;
882 trb->ctrl |= DWC3_TRB_CTRL_LST;
886 trb->ctrl |= DWC3_TRB_CTRL_CHN;
888 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
889 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
891 trb->ctrl |= DWC3_TRB_CTRL_HWO;
895 * dwc3_prepare_trbs - setup TRBs from requests
896 * @dep: endpoint for which requests are being prepared
897 * @starting: true if the endpoint is idle and no requests are queued.
899 * The function goes through the requests list and sets up TRBs for the
900 * transfers. The function returns once there are no more TRBs available or
901 * it runs out of requests.
903 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
905 struct dwc3_request *req, *n;
908 unsigned int last_one = 0;
910 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
912 /* the first request must not be queued */
913 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
915 /* Can't wrap around on a non-isoc EP since there's no link TRB */
916 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
917 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
923 * If busy & slot are equal than it is either full or empty. If we are
924 * starting to process requests then we are empty. Otherwise we are
925 * full and don't do anything
930 trbs_left = DWC3_TRB_NUM;
932 * In case we start from scratch, we queue the ISOC requests
933 * starting from slot 1. This is done because we use ring
934 * buffer and have no LST bit to stop us. Instead, we place
935 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
936 * after the first request so we start at slot 1 and have
937 * 7 requests proceed before we hit the first IOC.
938 * Other transfer types don't use the ring buffer and are
939 * processed from the first TRB until the last one. Since we
940 * don't wrap around we have to start at the beginning.
942 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
951 /* The last TRB is a link TRB, not used for xfer */
952 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
955 list_for_each_entry_safe(req, n, &dep->request_list, list) {
960 if (req->request.num_mapped_sgs > 0) {
961 struct usb_request *request = &req->request;
962 struct scatterlist *sg = request->sg;
963 struct scatterlist *s;
966 for_each_sg(sg, s, request->num_mapped_sgs, i) {
967 unsigned chain = true;
969 length = sg_dma_len(s);
970 dma = sg_dma_address(s);
972 if (i == (request->num_mapped_sgs - 1) ||
974 if (list_is_last(&req->list,
987 dwc3_prepare_one_trb(dep, req, dma, length,
994 dma = req->request.dma;
995 length = req->request.length;
1001 /* Is this the last request? */
1002 if (list_is_last(&req->list, &dep->request_list))
1005 dwc3_prepare_one_trb(dep, req, dma, length,
1006 last_one, false, 0);
1014 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
1017 struct dwc3_gadget_ep_cmd_params params;
1018 struct dwc3_request *req;
1019 struct dwc3 *dwc = dep->dwc;
1023 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
1024 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
1027 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1030 * If we are getting here after a short-out-packet we don't enqueue any
1031 * new requests as we try to set the IOC bit only on the last request.
1034 if (list_empty(&dep->req_queued))
1035 dwc3_prepare_trbs(dep, start_new);
1037 /* req points to the first request which will be sent */
1038 req = next_request(&dep->req_queued);
1040 dwc3_prepare_trbs(dep, start_new);
1043 * req points to the first request where HWO changed from 0 to 1
1045 req = next_request(&dep->req_queued);
1048 dep->flags |= DWC3_EP_PENDING_REQUEST;
1052 memset(¶ms, 0, sizeof(params));
1055 params.param0 = upper_32_bits(req->trb_dma);
1056 params.param1 = lower_32_bits(req->trb_dma);
1057 cmd = DWC3_DEPCMD_STARTTRANSFER;
1059 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1062 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1063 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1065 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1068 * FIXME we need to iterate over the list of requests
1069 * here and stop, unmap, free and del each of the linked
1070 * requests instead of what we do now.
1072 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1074 list_del(&req->list);
1078 dep->flags |= DWC3_EP_BUSY;
1081 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1083 WARN_ON_ONCE(!dep->resource_index);
1089 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1090 struct dwc3_ep *dep, u32 cur_uf)
1094 if (list_empty(&dep->request_list)) {
1095 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1097 dep->flags |= DWC3_EP_PENDING_REQUEST;
1101 /* 4 micro frames in the future */
1102 uf = cur_uf + dep->interval * 4;
1104 __dwc3_gadget_kick_transfer(dep, uf, 1);
1107 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1108 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1112 mask = ~(dep->interval - 1);
1113 cur_uf = event->parameters & mask;
1115 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1118 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1120 struct dwc3 *dwc = dep->dwc;
1123 req->request.actual = 0;
1124 req->request.status = -EINPROGRESS;
1125 req->direction = dep->direction;
1126 req->epnum = dep->number;
1129 * We only add to our list of requests now and
1130 * start consuming the list once we get XferNotReady
1133 * That way, we avoid doing anything that we don't need
1134 * to do now and defer it until the point we receive a
1135 * particular token from the Host side.
1137 * This will also avoid Host cancelling URBs due to too
1140 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1145 list_add_tail(&req->list, &dep->request_list);
1148 * There are a few special cases:
1150 * 1. XferNotReady with empty list of requests. We need to kick the
1151 * transfer here in that situation, otherwise we will be NAKing
1152 * forever. If we get XferNotReady before gadget driver has a
1153 * chance to queue a request, we will ACK the IRQ but won't be
1154 * able to receive the data until the next request is queued.
1155 * The following code is handling exactly that.
1158 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1160 * If xfernotready is already elapsed and it is a case
1161 * of isoc transfer, then issue END TRANSFER, so that
1162 * you can receive xfernotready again and can have
1163 * notion of current microframe.
1165 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1166 if (list_empty(&dep->req_queued)) {
1167 dwc3_stop_active_transfer(dwc, dep->number, true);
1168 dep->flags = DWC3_EP_ENABLED;
1173 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1174 if (ret && ret != -EBUSY)
1175 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1181 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1182 * kick the transfer here after queuing a request, otherwise the
1183 * core may not see the modified TRB(s).
1185 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1186 (dep->flags & DWC3_EP_BUSY) &&
1187 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1188 WARN_ON_ONCE(!dep->resource_index);
1189 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1191 if (ret && ret != -EBUSY)
1192 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1198 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1199 * right away, otherwise host will not know we have streams to be
1202 if (dep->stream_capable) {
1205 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1206 if (ret && ret != -EBUSY) {
1207 struct dwc3 *dwc = dep->dwc;
1209 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1217 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1220 struct dwc3_request *req = to_dwc3_request(request);
1221 struct dwc3_ep *dep = to_dwc3_ep(ep);
1222 struct dwc3 *dwc = dep->dwc;
1224 unsigned long flags;
1228 if (!dep->endpoint.desc) {
1229 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1234 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1235 request, ep->name, request->length);
1237 spin_lock_irqsave(&dwc->lock, flags);
1238 ret = __dwc3_gadget_ep_queue(dep, req);
1239 spin_unlock_irqrestore(&dwc->lock, flags);
1244 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1245 struct usb_request *request)
1247 struct dwc3_request *req = to_dwc3_request(request);
1248 struct dwc3_request *r = NULL;
1250 struct dwc3_ep *dep = to_dwc3_ep(ep);
1251 struct dwc3 *dwc = dep->dwc;
1253 unsigned long flags;
1256 spin_lock_irqsave(&dwc->lock, flags);
1258 list_for_each_entry(r, &dep->request_list, list) {
1264 list_for_each_entry(r, &dep->req_queued, list) {
1269 /* wait until it is processed */
1270 dwc3_stop_active_transfer(dwc, dep->number, true);
1273 dev_err(dwc->dev, "request %p was not queued to %s\n",
1280 /* giveback the request */
1281 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1284 spin_unlock_irqrestore(&dwc->lock, flags);
1289 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1291 struct dwc3_gadget_ep_cmd_params params;
1292 struct dwc3 *dwc = dep->dwc;
1295 memset(¶ms, 0x00, sizeof(params));
1298 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1299 DWC3_DEPCMD_SETSTALL, ¶ms);
1301 dev_err(dwc->dev, "failed to set STALL on %s\n",
1304 dep->flags |= DWC3_EP_STALL;
1306 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1307 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1309 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1312 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1318 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1320 struct dwc3_ep *dep = to_dwc3_ep(ep);
1321 struct dwc3 *dwc = dep->dwc;
1323 unsigned long flags;
1327 spin_lock_irqsave(&dwc->lock, flags);
1329 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1330 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1335 ret = __dwc3_gadget_ep_set_halt(dep, value);
1337 spin_unlock_irqrestore(&dwc->lock, flags);
1342 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1344 struct dwc3_ep *dep = to_dwc3_ep(ep);
1345 struct dwc3 *dwc = dep->dwc;
1346 unsigned long flags;
1348 spin_lock_irqsave(&dwc->lock, flags);
1349 dep->flags |= DWC3_EP_WEDGE;
1350 spin_unlock_irqrestore(&dwc->lock, flags);
1352 if (dep->number == 0 || dep->number == 1)
1353 return dwc3_gadget_ep0_set_halt(ep, 1);
1355 return dwc3_gadget_ep_set_halt(ep, 1);
1358 /* -------------------------------------------------------------------------- */
1360 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1361 .bLength = USB_DT_ENDPOINT_SIZE,
1362 .bDescriptorType = USB_DT_ENDPOINT,
1363 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1366 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1367 .enable = dwc3_gadget_ep0_enable,
1368 .disable = dwc3_gadget_ep0_disable,
1369 .alloc_request = dwc3_gadget_ep_alloc_request,
1370 .free_request = dwc3_gadget_ep_free_request,
1371 .queue = dwc3_gadget_ep0_queue,
1372 .dequeue = dwc3_gadget_ep_dequeue,
1373 .set_halt = dwc3_gadget_ep0_set_halt,
1374 .set_wedge = dwc3_gadget_ep_set_wedge,
1377 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1378 .enable = dwc3_gadget_ep_enable,
1379 .disable = dwc3_gadget_ep_disable,
1380 .alloc_request = dwc3_gadget_ep_alloc_request,
1381 .free_request = dwc3_gadget_ep_free_request,
1382 .queue = dwc3_gadget_ep_queue,
1383 .dequeue = dwc3_gadget_ep_dequeue,
1384 .set_halt = dwc3_gadget_ep_set_halt,
1385 .set_wedge = dwc3_gadget_ep_set_wedge,
1388 /* -------------------------------------------------------------------------- */
1390 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1392 struct dwc3 *dwc = gadget_to_dwc(g);
1395 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1396 return DWC3_DSTS_SOFFN(reg);
1399 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1401 struct dwc3 *dwc = gadget_to_dwc(g);
1403 unsigned long timeout;
1404 unsigned long flags;
1413 spin_lock_irqsave(&dwc->lock, flags);
1416 * According to the Databook Remote wakeup request should
1417 * be issued only when the device is in early suspend state.
1419 * We can check that via USB Link State bits in DSTS register.
1421 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1423 speed = reg & DWC3_DSTS_CONNECTSPD;
1424 if (speed == DWC3_DSTS_SUPERSPEED) {
1425 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1430 link_state = DWC3_DSTS_USBLNKST(reg);
1432 switch (link_state) {
1433 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1434 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1437 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1443 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1445 dev_err(dwc->dev, "failed to put link in Recovery\n");
1449 /* Recent versions do this automatically */
1450 if (dwc->revision < DWC3_REVISION_194A) {
1451 /* write zeroes to Link Change Request */
1452 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1453 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1454 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1457 /* poll until Link State changes to ON */
1458 timeout = jiffies + msecs_to_jiffies(100);
1460 while (!time_after(jiffies, timeout)) {
1461 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1463 /* in HS, means ON */
1464 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1468 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1469 dev_err(dwc->dev, "failed to send remote wakeup\n");
1474 spin_unlock_irqrestore(&dwc->lock, flags);
1479 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1482 struct dwc3 *dwc = gadget_to_dwc(g);
1483 unsigned long flags;
1485 spin_lock_irqsave(&dwc->lock, flags);
1486 dwc->is_selfpowered = !!is_selfpowered;
1487 spin_unlock_irqrestore(&dwc->lock, flags);
1492 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1497 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1499 if (dwc->revision <= DWC3_REVISION_187A) {
1500 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1501 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1504 if (dwc->revision >= DWC3_REVISION_194A)
1505 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1506 reg |= DWC3_DCTL_RUN_STOP;
1508 if (dwc->has_hibernation)
1509 reg |= DWC3_DCTL_KEEP_CONNECT;
1511 dwc->pullups_connected = true;
1513 reg &= ~DWC3_DCTL_RUN_STOP;
1515 if (dwc->has_hibernation && !suspend)
1516 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1518 dwc->pullups_connected = false;
1521 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1524 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1526 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1529 if (reg & DWC3_DSTS_DEVCTRLHLT)
1538 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1540 ? dwc->gadget_driver->function : "no-function",
1541 is_on ? "connect" : "disconnect");
1546 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1548 struct dwc3 *dwc = gadget_to_dwc(g);
1549 unsigned long flags;
1554 spin_lock_irqsave(&dwc->lock, flags);
1555 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1556 spin_unlock_irqrestore(&dwc->lock, flags);
1561 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1565 /* Enable all but Start and End of Frame IRQs */
1566 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1567 DWC3_DEVTEN_EVNTOVERFLOWEN |
1568 DWC3_DEVTEN_CMDCMPLTEN |
1569 DWC3_DEVTEN_ERRTICERREN |
1570 DWC3_DEVTEN_WKUPEVTEN |
1571 DWC3_DEVTEN_ULSTCNGEN |
1572 DWC3_DEVTEN_CONNECTDONEEN |
1573 DWC3_DEVTEN_USBRSTEN |
1574 DWC3_DEVTEN_DISCONNEVTEN);
1576 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1579 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1581 /* mask all interrupts */
1582 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1585 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1586 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1588 static int dwc3_gadget_start(struct usb_gadget *g,
1589 struct usb_gadget_driver *driver)
1591 struct dwc3 *dwc = gadget_to_dwc(g);
1592 struct dwc3_ep *dep;
1593 unsigned long flags;
1598 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1599 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1600 IRQF_SHARED, "dwc3", dwc);
1602 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1607 spin_lock_irqsave(&dwc->lock, flags);
1609 if (dwc->gadget_driver) {
1610 dev_err(dwc->dev, "%s is already bound to %s\n",
1612 dwc->gadget_driver->driver.name);
1617 dwc->gadget_driver = driver;
1619 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1620 reg &= ~(DWC3_DCFG_SPEED_MASK);
1623 * WORKAROUND: DWC3 revision < 2.20a have an issue
1624 * which would cause metastability state on Run/Stop
1625 * bit if we try to force the IP to USB2-only mode.
1627 * Because of that, we cannot configure the IP to any
1628 * speed other than the SuperSpeed
1632 * STAR#9000525659: Clock Domain Crossing on DCTL in
1635 if (dwc->revision < DWC3_REVISION_220A) {
1636 reg |= DWC3_DCFG_SUPERSPEED;
1638 switch (dwc->maximum_speed) {
1640 reg |= DWC3_DSTS_LOWSPEED;
1642 case USB_SPEED_FULL:
1643 reg |= DWC3_DSTS_FULLSPEED1;
1645 case USB_SPEED_HIGH:
1646 reg |= DWC3_DSTS_HIGHSPEED;
1648 case USB_SPEED_SUPER: /* FALLTHROUGH */
1649 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1651 reg |= DWC3_DSTS_SUPERSPEED;
1654 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1656 dwc->start_config_issued = false;
1658 /* Start with SuperSpeed Default */
1659 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1662 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1665 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1670 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1673 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1677 /* begin to receive SETUP packets */
1678 dwc->ep0state = EP0_SETUP_PHASE;
1679 dwc3_ep0_out_start(dwc);
1681 dwc3_gadget_enable_irq(dwc);
1683 spin_unlock_irqrestore(&dwc->lock, flags);
1688 __dwc3_gadget_ep_disable(dwc->eps[0]);
1691 dwc->gadget_driver = NULL;
1694 spin_unlock_irqrestore(&dwc->lock, flags);
1702 static int dwc3_gadget_stop(struct usb_gadget *g,
1703 struct usb_gadget_driver *driver)
1705 struct dwc3 *dwc = gadget_to_dwc(g);
1706 unsigned long flags;
1709 spin_lock_irqsave(&dwc->lock, flags);
1711 dwc3_gadget_disable_irq(dwc);
1712 __dwc3_gadget_ep_disable(dwc->eps[0]);
1713 __dwc3_gadget_ep_disable(dwc->eps[1]);
1715 dwc->gadget_driver = NULL;
1717 spin_unlock_irqrestore(&dwc->lock, flags);
1719 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1725 static const struct usb_gadget_ops dwc3_gadget_ops = {
1726 .get_frame = dwc3_gadget_get_frame,
1727 .wakeup = dwc3_gadget_wakeup,
1728 .set_selfpowered = dwc3_gadget_set_selfpowered,
1729 .pullup = dwc3_gadget_pullup,
1730 .udc_start = dwc3_gadget_start,
1731 .udc_stop = dwc3_gadget_stop,
1734 /* -------------------------------------------------------------------------- */
1736 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1737 u8 num, u32 direction)
1739 struct dwc3_ep *dep;
1742 for (i = 0; i < num; i++) {
1743 u8 epnum = (i << 1) | (!!direction);
1745 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1747 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1753 dep->number = epnum;
1754 dep->direction = !!direction;
1755 dwc->eps[epnum] = dep;
1757 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1758 (epnum & 1) ? "in" : "out");
1760 dep->endpoint.name = dep->name;
1762 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1764 if (epnum == 0 || epnum == 1) {
1765 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1766 dep->endpoint.maxburst = 1;
1767 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1769 dwc->gadget.ep0 = &dep->endpoint;
1773 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1774 dep->endpoint.max_streams = 15;
1775 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1776 list_add_tail(&dep->endpoint.ep_list,
1777 &dwc->gadget.ep_list);
1779 ret = dwc3_alloc_trb_pool(dep);
1784 INIT_LIST_HEAD(&dep->request_list);
1785 INIT_LIST_HEAD(&dep->req_queued);
1791 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1795 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1797 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1799 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1803 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1805 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1812 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1814 struct dwc3_ep *dep;
1817 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1818 dep = dwc->eps[epnum];
1822 * Physical endpoints 0 and 1 are special; they form the
1823 * bi-directional USB endpoint 0.
1825 * For those two physical endpoints, we don't allocate a TRB
1826 * pool nor do we add them the endpoints list. Due to that, we
1827 * shouldn't do these two operations otherwise we would end up
1828 * with all sorts of bugs when removing dwc3.ko.
1830 if (epnum != 0 && epnum != 1) {
1831 dwc3_free_trb_pool(dep);
1832 list_del(&dep->endpoint.ep_list);
1839 /* -------------------------------------------------------------------------- */
1841 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1842 struct dwc3_request *req, struct dwc3_trb *trb,
1843 const struct dwc3_event_depevt *event, int status)
1846 unsigned int s_pkt = 0;
1847 unsigned int trb_status;
1849 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1851 * We continue despite the error. There is not much we
1852 * can do. If we don't clean it up we loop forever. If
1853 * we skip the TRB then it gets overwritten after a
1854 * while since we use them in a ring buffer. A BUG()
1855 * would help. Lets hope that if this occurs, someone
1856 * fixes the root cause instead of looking away :)
1858 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1860 count = trb->size & DWC3_TRB_SIZE_MASK;
1862 if (dep->direction) {
1864 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1865 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1866 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1869 * If missed isoc occurred and there is
1870 * no request queued then issue END
1871 * TRANSFER, so that core generates
1872 * next xfernotready and we will issue
1873 * a fresh START TRANSFER.
1874 * If there are still queued request
1875 * then wait, do not issue either END
1876 * or UPDATE TRANSFER, just attach next
1877 * request in request_list during
1878 * giveback.If any future queued request
1879 * is successfully transferred then we
1880 * will issue UPDATE TRANSFER for all
1881 * request in the request_list.
1883 dep->flags |= DWC3_EP_MISSED_ISOC;
1885 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1887 status = -ECONNRESET;
1890 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1893 if (count && (event->status & DEPEVT_STATUS_SHORT))
1898 * We assume here we will always receive the entire data block
1899 * which we should receive. Meaning, if we program RX to
1900 * receive 4K but we receive only 2K, we assume that's all we
1901 * should receive and we simply bounce the request back to the
1902 * gadget driver for further processing.
1904 req->request.actual += req->request.length - count;
1907 if ((event->status & DEPEVT_STATUS_LST) &&
1908 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1909 DWC3_TRB_CTRL_HWO)))
1911 if ((event->status & DEPEVT_STATUS_IOC) &&
1912 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1917 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1918 const struct dwc3_event_depevt *event, int status)
1920 struct dwc3_request *req;
1921 struct dwc3_trb *trb;
1927 req = next_request(&dep->req_queued);
1934 slot = req->start_slot + i;
1935 if ((slot == DWC3_TRB_NUM - 1) &&
1936 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1938 slot %= DWC3_TRB_NUM;
1939 trb = &dep->trb_pool[slot];
1941 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1945 }while (++i < req->request.num_mapped_sgs);
1947 dwc3_gadget_giveback(dep, req, status);
1953 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1954 list_empty(&dep->req_queued)) {
1955 if (list_empty(&dep->request_list)) {
1957 * If there is no entry in request list then do
1958 * not issue END TRANSFER now. Just set PENDING
1959 * flag, so that END TRANSFER is issued when an
1960 * entry is added into request list.
1962 dep->flags = DWC3_EP_PENDING_REQUEST;
1964 dwc3_stop_active_transfer(dwc, dep->number, true);
1965 dep->flags = DWC3_EP_ENABLED;
1973 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1974 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1977 unsigned status = 0;
1980 if (event->status & DEPEVT_STATUS_BUSERR)
1981 status = -ECONNRESET;
1983 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1985 dep->flags &= ~DWC3_EP_BUSY;
1988 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1989 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1991 if (dwc->revision < DWC3_REVISION_183A) {
1995 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1998 if (!(dep->flags & DWC3_EP_ENABLED))
2001 if (!list_empty(&dep->req_queued))
2005 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2007 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2013 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2014 const struct dwc3_event_depevt *event)
2016 struct dwc3_ep *dep;
2017 u8 epnum = event->endpoint_number;
2019 dep = dwc->eps[epnum];
2021 if (!(dep->flags & DWC3_EP_ENABLED))
2024 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
2025 dwc3_ep_event_string(event->endpoint_event));
2027 if (epnum == 0 || epnum == 1) {
2028 dwc3_ep0_interrupt(dwc, event);
2032 switch (event->endpoint_event) {
2033 case DWC3_DEPEVT_XFERCOMPLETE:
2034 dep->resource_index = 0;
2036 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2037 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
2042 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
2044 case DWC3_DEPEVT_XFERINPROGRESS:
2045 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2046 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
2051 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
2053 case DWC3_DEPEVT_XFERNOTREADY:
2054 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2055 dwc3_gadget_start_isoc(dwc, dep, event);
2059 dev_vdbg(dwc->dev, "%s: reason %s\n",
2060 dep->name, event->status &
2061 DEPEVT_STATUS_TRANSFER_ACTIVE
2063 : "Transfer Not Active");
2065 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
2066 if (!ret || ret == -EBUSY)
2069 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2074 case DWC3_DEPEVT_STREAMEVT:
2075 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2076 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2081 switch (event->status) {
2082 case DEPEVT_STREAMEVT_FOUND:
2083 dev_vdbg(dwc->dev, "Stream %d found and started\n",
2087 case DEPEVT_STREAMEVT_NOTFOUND:
2090 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2093 case DWC3_DEPEVT_RXTXFIFOEVT:
2094 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2096 case DWC3_DEPEVT_EPCMDCMPLT:
2097 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2102 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2104 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2105 spin_unlock(&dwc->lock);
2106 dwc->gadget_driver->disconnect(&dwc->gadget);
2107 spin_lock(&dwc->lock);
2111 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2113 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2114 spin_unlock(&dwc->lock);
2115 dwc->gadget_driver->suspend(&dwc->gadget);
2116 spin_lock(&dwc->lock);
2120 static void dwc3_resume_gadget(struct dwc3 *dwc)
2122 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2123 spin_unlock(&dwc->lock);
2124 dwc->gadget_driver->resume(&dwc->gadget);
2125 spin_lock(&dwc->lock);
2129 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2131 struct dwc3_ep *dep;
2132 struct dwc3_gadget_ep_cmd_params params;
2136 dep = dwc->eps[epnum];
2138 if (!dep->resource_index)
2142 * NOTICE: We are violating what the Databook says about the
2143 * EndTransfer command. Ideally we would _always_ wait for the
2144 * EndTransfer Command Completion IRQ, but that's causing too
2145 * much trouble synchronizing between us and gadget driver.
2147 * We have discussed this with the IP Provider and it was
2148 * suggested to giveback all requests here, but give HW some
2149 * extra time to synchronize with the interconnect. We're using
2150 * an arbitraty 100us delay for that.
2152 * Note also that a similar handling was tested by Synopsys
2153 * (thanks a lot Paul) and nothing bad has come out of it.
2154 * In short, what we're doing is:
2156 * - Issue EndTransfer WITH CMDIOC bit set
2160 cmd = DWC3_DEPCMD_ENDTRANSFER;
2161 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2162 cmd |= DWC3_DEPCMD_CMDIOC;
2163 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2164 memset(¶ms, 0, sizeof(params));
2165 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2167 dep->resource_index = 0;
2168 dep->flags &= ~DWC3_EP_BUSY;
2172 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2176 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2177 struct dwc3_ep *dep;
2179 dep = dwc->eps[epnum];
2183 if (!(dep->flags & DWC3_EP_ENABLED))
2186 dwc3_remove_requests(dwc, dep);
2190 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2194 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2195 struct dwc3_ep *dep;
2196 struct dwc3_gadget_ep_cmd_params params;
2199 dep = dwc->eps[epnum];
2203 if (!(dep->flags & DWC3_EP_STALL))
2206 dep->flags &= ~DWC3_EP_STALL;
2208 memset(¶ms, 0, sizeof(params));
2209 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2210 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2215 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2219 dev_vdbg(dwc->dev, "%s\n", __func__);
2221 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2222 reg &= ~DWC3_DCTL_INITU1ENA;
2223 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2225 reg &= ~DWC3_DCTL_INITU2ENA;
2226 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2228 dwc3_disconnect_gadget(dwc);
2229 dwc->start_config_issued = false;
2231 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2232 dwc->setup_packet_pending = false;
2235 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2239 dev_vdbg(dwc->dev, "%s\n", __func__);
2242 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2243 * would cause a missing Disconnect Event if there's a
2244 * pending Setup Packet in the FIFO.
2246 * There's no suggested workaround on the official Bug
2247 * report, which states that "unless the driver/application
2248 * is doing any special handling of a disconnect event,
2249 * there is no functional issue".
2251 * Unfortunately, it turns out that we _do_ some special
2252 * handling of a disconnect event, namely complete all
2253 * pending transfers, notify gadget driver of the
2254 * disconnection, and so on.
2256 * Our suggested workaround is to follow the Disconnect
2257 * Event steps here, instead, based on a setup_packet_pending
2258 * flag. Such flag gets set whenever we have a XferNotReady
2259 * event on EP0 and gets cleared on XferComplete for the
2264 * STAR#9000466709: RTL: Device : Disconnect event not
2265 * generated if setup packet pending in FIFO
2267 if (dwc->revision < DWC3_REVISION_188A) {
2268 if (dwc->setup_packet_pending)
2269 dwc3_gadget_disconnect_interrupt(dwc);
2272 /* after reset -> Default State */
2273 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2275 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2276 dwc3_disconnect_gadget(dwc);
2278 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2279 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2280 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2281 dwc->test_mode = false;
2283 dwc3_stop_active_transfers(dwc);
2284 dwc3_clear_stall_all_ep(dwc);
2285 dwc->start_config_issued = false;
2287 /* Reset device address to zero */
2288 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2289 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2290 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2293 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2296 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2299 * We change the clock only at SS but I dunno why I would want to do
2300 * this. Maybe it becomes part of the power saving plan.
2303 if (speed != DWC3_DSTS_SUPERSPEED)
2307 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2308 * each time on Connect Done.
2313 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2314 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2315 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2318 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2320 struct dwc3_ep *dep;
2325 dev_vdbg(dwc->dev, "%s\n", __func__);
2327 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2328 speed = reg & DWC3_DSTS_CONNECTSPD;
2331 dwc3_update_ram_clk_sel(dwc, speed);
2334 case DWC3_DCFG_SUPERSPEED:
2336 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2337 * would cause a missing USB3 Reset event.
2339 * In such situations, we should force a USB3 Reset
2340 * event by calling our dwc3_gadget_reset_interrupt()
2345 * STAR#9000483510: RTL: SS : USB3 reset event may
2346 * not be generated always when the link enters poll
2348 if (dwc->revision < DWC3_REVISION_190A)
2349 dwc3_gadget_reset_interrupt(dwc);
2351 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2352 dwc->gadget.ep0->maxpacket = 512;
2353 dwc->gadget.speed = USB_SPEED_SUPER;
2355 case DWC3_DCFG_HIGHSPEED:
2356 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2357 dwc->gadget.ep0->maxpacket = 64;
2358 dwc->gadget.speed = USB_SPEED_HIGH;
2360 case DWC3_DCFG_FULLSPEED2:
2361 case DWC3_DCFG_FULLSPEED1:
2362 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2363 dwc->gadget.ep0->maxpacket = 64;
2364 dwc->gadget.speed = USB_SPEED_FULL;
2366 case DWC3_DCFG_LOWSPEED:
2367 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2368 dwc->gadget.ep0->maxpacket = 8;
2369 dwc->gadget.speed = USB_SPEED_LOW;
2373 /* Enable USB2 LPM Capability */
2375 if ((dwc->revision > DWC3_REVISION_194A)
2376 && (speed != DWC3_DCFG_SUPERSPEED)) {
2377 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2378 reg |= DWC3_DCFG_LPM_CAP;
2379 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2381 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2382 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2385 * TODO: This should be configurable. For now using
2386 * maximum allowed HIRD threshold value of 0b1100
2388 reg |= DWC3_DCTL_HIRD_THRES(12);
2390 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2392 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2393 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2394 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2398 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2401 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2406 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2409 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2414 * Configure PHY via GUSB3PIPECTLn if required.
2416 * Update GTXFIFOSIZn
2418 * In both cases reset values should be sufficient.
2422 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2424 dev_vdbg(dwc->dev, "%s\n", __func__);
2427 * TODO take core out of low power mode when that's
2431 dwc->gadget_driver->resume(&dwc->gadget);
2434 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2435 unsigned int evtinfo)
2437 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2438 unsigned int pwropt;
2441 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2442 * Hibernation mode enabled which would show up when device detects
2443 * host-initiated U3 exit.
2445 * In that case, device will generate a Link State Change Interrupt
2446 * from U3 to RESUME which is only necessary if Hibernation is
2449 * There are no functional changes due to such spurious event and we
2450 * just need to ignore it.
2454 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2457 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2458 if ((dwc->revision < DWC3_REVISION_250A) &&
2459 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2460 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2461 (next == DWC3_LINK_STATE_RESUME)) {
2462 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2468 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2469 * on the link partner, the USB session might do multiple entry/exit
2470 * of low power states before a transfer takes place.
2472 * Due to this problem, we might experience lower throughput. The
2473 * suggested workaround is to disable DCTL[12:9] bits if we're
2474 * transitioning from U1/U2 to U0 and enable those bits again
2475 * after a transfer completes and there are no pending transfers
2476 * on any of the enabled endpoints.
2478 * This is the first half of that workaround.
2482 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2483 * core send LGO_Ux entering U0
2485 if (dwc->revision < DWC3_REVISION_183A) {
2486 if (next == DWC3_LINK_STATE_U0) {
2490 switch (dwc->link_state) {
2491 case DWC3_LINK_STATE_U1:
2492 case DWC3_LINK_STATE_U2:
2493 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2494 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2495 | DWC3_DCTL_ACCEPTU2ENA
2496 | DWC3_DCTL_INITU1ENA
2497 | DWC3_DCTL_ACCEPTU1ENA);
2500 dwc->u1u2 = reg & u1u2;
2504 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2514 case DWC3_LINK_STATE_U1:
2515 if (dwc->speed == USB_SPEED_SUPER)
2516 dwc3_suspend_gadget(dwc);
2518 case DWC3_LINK_STATE_U2:
2519 case DWC3_LINK_STATE_U3:
2520 dwc3_suspend_gadget(dwc);
2522 case DWC3_LINK_STATE_RESUME:
2523 dwc3_resume_gadget(dwc);
2530 dev_vdbg(dwc->dev, "link change: %s [%d] -> %s [%d]\n",
2531 dwc3_gadget_link_string(dwc->link_state),
2532 dwc->link_state, dwc3_gadget_link_string(next), next);
2534 dwc->link_state = next;
2537 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2538 unsigned int evtinfo)
2540 unsigned int is_ss = evtinfo & BIT(4);
2543 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2544 * have a known issue which can cause USB CV TD.9.23 to fail
2547 * Because of this issue, core could generate bogus hibernation
2548 * events which SW needs to ignore.
2552 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2553 * Device Fallback from SuperSpeed
2555 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2558 /* enter hibernation here */
2561 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2562 const struct dwc3_event_devt *event)
2564 switch (event->type) {
2565 case DWC3_DEVICE_EVENT_DISCONNECT:
2566 dwc3_gadget_disconnect_interrupt(dwc);
2568 case DWC3_DEVICE_EVENT_RESET:
2569 dwc3_gadget_reset_interrupt(dwc);
2571 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2572 dwc3_gadget_conndone_interrupt(dwc);
2574 case DWC3_DEVICE_EVENT_WAKEUP:
2575 dwc3_gadget_wakeup_interrupt(dwc);
2577 case DWC3_DEVICE_EVENT_HIBER_REQ:
2578 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2579 "unexpected hibernation event\n"))
2582 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2584 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2585 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2587 case DWC3_DEVICE_EVENT_EOPF:
2588 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2590 case DWC3_DEVICE_EVENT_SOF:
2591 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2593 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2594 dev_vdbg(dwc->dev, "Erratic Error\n");
2596 case DWC3_DEVICE_EVENT_CMD_CMPL:
2597 dev_vdbg(dwc->dev, "Command Complete\n");
2599 case DWC3_DEVICE_EVENT_OVERFLOW:
2600 dev_vdbg(dwc->dev, "Overflow\n");
2603 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2607 static void dwc3_process_event_entry(struct dwc3 *dwc,
2608 const union dwc3_event *event)
2610 /* Endpoint IRQ, handle it and return early */
2611 if (event->type.is_devspec == 0) {
2613 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2616 switch (event->type.type) {
2617 case DWC3_EVENT_TYPE_DEV:
2618 dwc3_gadget_interrupt(dwc, &event->devt);
2620 /* REVISIT what to do with Carkit and I2C events ? */
2622 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2626 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2628 struct dwc3_event_buffer *evt;
2629 irqreturn_t ret = IRQ_NONE;
2633 evt = dwc->ev_buffs[buf];
2636 if (!(evt->flags & DWC3_EVENT_PENDING))
2640 union dwc3_event event;
2642 event.raw = *(u32 *) (evt->buf + evt->lpos);
2644 dwc3_process_event_entry(dwc, &event);
2647 * FIXME we wrap around correctly to the next entry as
2648 * almost all entries are 4 bytes in size. There is one
2649 * entry which has 12 bytes which is a regular entry
2650 * followed by 8 bytes data. ATM I don't know how
2651 * things are organized if we get next to the a
2652 * boundary so I worry about that once we try to handle
2655 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2658 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2662 evt->flags &= ~DWC3_EVENT_PENDING;
2665 /* Unmask interrupt */
2666 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2667 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2668 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2673 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2675 struct dwc3 *dwc = _dwc;
2676 unsigned long flags;
2677 irqreturn_t ret = IRQ_NONE;
2680 spin_lock_irqsave(&dwc->lock, flags);
2682 for (i = 0; i < dwc->num_event_buffers; i++)
2683 ret |= dwc3_process_event_buf(dwc, i);
2685 spin_unlock_irqrestore(&dwc->lock, flags);
2690 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2692 struct dwc3_event_buffer *evt;
2696 evt = dwc->ev_buffs[buf];
2698 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2699 count &= DWC3_GEVNTCOUNT_MASK;
2704 evt->flags |= DWC3_EVENT_PENDING;
2706 /* Mask interrupt */
2707 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2708 reg |= DWC3_GEVNTSIZ_INTMASK;
2709 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2711 return IRQ_WAKE_THREAD;
2714 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2716 struct dwc3 *dwc = _dwc;
2718 irqreturn_t ret = IRQ_NONE;
2720 spin_lock(&dwc->lock);
2722 for (i = 0; i < dwc->num_event_buffers; i++) {
2725 status = dwc3_check_event_buf(dwc, i);
2726 if (status == IRQ_WAKE_THREAD)
2730 spin_unlock(&dwc->lock);
2736 * dwc3_gadget_init - Initializes gadget related registers
2737 * @dwc: pointer to our controller context structure
2739 * Returns 0 on success otherwise negative errno.
2741 int dwc3_gadget_init(struct dwc3 *dwc)
2745 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2746 &dwc->ctrl_req_addr, GFP_KERNEL);
2747 if (!dwc->ctrl_req) {
2748 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2753 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2754 &dwc->ep0_trb_addr, GFP_KERNEL);
2755 if (!dwc->ep0_trb) {
2756 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2761 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2762 if (!dwc->setup_buf) {
2763 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2768 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2769 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2771 if (!dwc->ep0_bounce) {
2772 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2777 dwc->gadget.ops = &dwc3_gadget_ops;
2778 dwc->gadget.max_speed = USB_SPEED_SUPER;
2779 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2780 dwc->gadget.sg_supported = true;
2781 dwc->gadget.name = "dwc3-gadget";
2784 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2787 dwc->gadget.quirk_ep_out_aligned_size = true;
2790 * REVISIT: Here we should clear all pending IRQs to be
2791 * sure we're starting from a well known location.
2794 ret = dwc3_gadget_init_endpoints(dwc);
2798 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2800 dev_err(dwc->dev, "failed to register udc\n");
2807 dwc3_gadget_free_endpoints(dwc);
2808 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2809 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2812 kfree(dwc->setup_buf);
2815 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2816 dwc->ep0_trb, dwc->ep0_trb_addr);
2819 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2820 dwc->ctrl_req, dwc->ctrl_req_addr);
2826 /* -------------------------------------------------------------------------- */
2828 void dwc3_gadget_exit(struct dwc3 *dwc)
2830 usb_del_gadget_udc(&dwc->gadget);
2832 dwc3_gadget_free_endpoints(dwc);
2834 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2835 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2837 kfree(dwc->setup_buf);
2839 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2840 dwc->ep0_trb, dwc->ep0_trb_addr);
2842 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2843 dwc->ctrl_req, dwc->ctrl_req_addr);
2846 int dwc3_gadget_prepare(struct dwc3 *dwc)
2848 if (dwc->pullups_connected) {
2849 dwc3_gadget_disable_irq(dwc);
2850 dwc3_gadget_run_stop(dwc, true, true);
2856 void dwc3_gadget_complete(struct dwc3 *dwc)
2858 if (dwc->pullups_connected) {
2859 dwc3_gadget_enable_irq(dwc);
2860 dwc3_gadget_run_stop(dwc, true, false);
2864 int dwc3_gadget_suspend(struct dwc3 *dwc)
2866 __dwc3_gadget_ep_disable(dwc->eps[0]);
2867 __dwc3_gadget_ep_disable(dwc->eps[1]);
2869 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2874 int dwc3_gadget_resume(struct dwc3 *dwc)
2876 struct dwc3_ep *dep;
2879 /* Start with SuperSpeed Default */
2880 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2883 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2889 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2894 /* begin to receive SETUP packets */
2895 dwc->ep0state = EP0_SETUP_PHASE;
2896 dwc3_ep0_out_start(dwc);
2898 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2903 __dwc3_gadget_ep_disable(dwc->eps[0]);